1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Chelsio Communications.
6 #ifndef _T4FW_INTERFACE_H_
7 #define _T4FW_INTERFACE_H_
9 /******************************************************************************
10 * R E T U R N V A L U E S
11 ********************************/
14 FW_SUCCESS = 0, /* completed successfully */
15 FW_EPERM = 1, /* operation not permitted */
16 FW_ENOENT = 2, /* no such file or directory */
17 FW_EIO = 5, /* input/output error; hw bad */
18 FW_ENOEXEC = 8, /* exec format error; inv microcode */
19 FW_EAGAIN = 11, /* try again */
20 FW_ENOMEM = 12, /* out of memory */
21 FW_EFAULT = 14, /* bad address; fw bad */
22 FW_EBUSY = 16, /* resource busy */
23 FW_EEXIST = 17, /* file exists */
24 FW_ENODEV = 19, /* no such device */
25 FW_EINVAL = 22, /* invalid argument */
26 FW_ENOSPC = 28, /* no space left on device */
27 FW_ENOSYS = 38, /* functionality not implemented */
28 FW_ENODATA = 61, /* no data available */
29 FW_EPROTO = 71, /* protocol error */
30 FW_EADDRINUSE = 98, /* address already in use */
31 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */
32 FW_ENETDOWN = 100, /* network is down */
33 FW_ENETUNREACH = 101, /* network is unreachable */
34 FW_ENOBUFS = 105, /* no buffer space available */
35 FW_ETIMEDOUT = 110, /* timeout */
36 FW_EINPROGRESS = 115, /* fw internal */
39 /******************************************************************************
40 * M E M O R Y T Y P E s
41 ******************************/
44 FW_MEMTYPE_EDC0 = 0x0,
45 FW_MEMTYPE_EDC1 = 0x1,
46 FW_MEMTYPE_EXTMEM = 0x2,
47 FW_MEMTYPE_FLASH = 0x4,
48 FW_MEMTYPE_INTERNAL = 0x5,
49 FW_MEMTYPE_EXTMEM1 = 0x6,
52 /******************************************************************************
53 * W O R K R E Q U E S T s
54 ********************************/
60 FW_ETH_TX_PKT_WR = 0x08,
61 FW_ETH_TX_PKTS_WR = 0x09,
62 FW_ETH_TX_PKT_VM_WR = 0x11,
63 FW_ETH_TX_PKTS_VM_WR = 0x12,
65 FW_ETH_TX_PKTS2_WR = 0x78,
69 * Generic work request header flit0
76 /* work request opcode (hi)
79 #define M_FW_WR_OP 0xff
80 #define V_FW_WR_OP(x) ((x) << S_FW_WR_OP)
81 #define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP)
83 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER
85 #define S_FW_WR_ATOMIC 23
86 #define V_FW_WR_ATOMIC(x) ((x) << S_FW_WR_ATOMIC)
88 /* work request immediate data length (hi)
90 #define S_FW_WR_IMMDLEN 0
91 #define M_FW_WR_IMMDLEN 0xff
92 #define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN)
93 #define G_FW_WR_IMMDLEN(x) \
94 (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN)
96 /* egress queue status update to egress queue status entry (lo)
98 #define S_FW_WR_EQUEQ 30
99 #define M_FW_WR_EQUEQ 0x1
100 #define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ)
101 #define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ)
102 #define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U)
104 /* flow context identifier (lo)
106 #define S_FW_WR_FLOWID 8
107 #define V_FW_WR_FLOWID(x) ((x) << S_FW_WR_FLOWID)
109 /* length in units of 16-bytes (lo)
111 #define S_FW_WR_LEN16 0
112 #define M_FW_WR_LEN16 0xff
113 #define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16)
114 #define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16)
116 struct fw_eth_tx_pkt_wr {
118 __be32 equiq_to_len16;
122 #define S_FW_ETH_TX_PKT_WR_IMMDLEN 0
123 #define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff
124 #define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN)
125 #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \
126 (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN)
128 struct fw_eth_tx_pkts_wr {
130 __be32 equiq_to_len16;
137 struct fw_eth_tx_pkt_vm_wr {
139 __be32 equiq_to_len16;
147 struct fw_eth_tx_pkts_vm_wr {
149 __be32 equiq_to_len16;
160 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */
161 enum fw_filter_wr_cookie {
162 FW_FILTER_WR_SUCCESS,
163 FW_FILTER_WR_FLT_ADDED,
164 FW_FILTER_WR_FLT_DELETED,
165 FW_FILTER_WR_SMT_TBL_FULL,
169 struct fw_filter2_wr {
174 __be32 del_filter_to_l2tix;
177 __u8 frag_to_ovlan_vldm;
179 __be16 rx_chan_rx_rpl_iq;
180 __be32 maci_to_matchtypem;
200 __u8 filter_type_swapmac;
201 __u8 natmode_to_ulp_type;
214 #define S_FW_FILTER_WR_TID 12
215 #define V_FW_FILTER_WR_TID(x) ((x) << S_FW_FILTER_WR_TID)
217 #define S_FW_FILTER_WR_RQTYPE 11
218 #define V_FW_FILTER_WR_RQTYPE(x) ((x) << S_FW_FILTER_WR_RQTYPE)
220 #define S_FW_FILTER_WR_NOREPLY 10
221 #define V_FW_FILTER_WR_NOREPLY(x) ((x) << S_FW_FILTER_WR_NOREPLY)
223 #define S_FW_FILTER_WR_IQ 0
224 #define V_FW_FILTER_WR_IQ(x) ((x) << S_FW_FILTER_WR_IQ)
226 #define S_FW_FILTER_WR_DEL_FILTER 31
227 #define V_FW_FILTER_WR_DEL_FILTER(x) ((x) << S_FW_FILTER_WR_DEL_FILTER)
228 #define F_FW_FILTER_WR_DEL_FILTER V_FW_FILTER_WR_DEL_FILTER(1U)
230 #define S_FW_FILTER_WR_RPTTID 25
231 #define V_FW_FILTER_WR_RPTTID(x) ((x) << S_FW_FILTER_WR_RPTTID)
233 #define S_FW_FILTER_WR_DROP 24
234 #define V_FW_FILTER_WR_DROP(x) ((x) << S_FW_FILTER_WR_DROP)
236 #define S_FW_FILTER_WR_DIRSTEER 23
237 #define V_FW_FILTER_WR_DIRSTEER(x) ((x) << S_FW_FILTER_WR_DIRSTEER)
239 #define S_FW_FILTER_WR_MASKHASH 22
240 #define V_FW_FILTER_WR_MASKHASH(x) ((x) << S_FW_FILTER_WR_MASKHASH)
242 #define S_FW_FILTER_WR_DIRSTEERHASH 21
243 #define V_FW_FILTER_WR_DIRSTEERHASH(x) ((x) << S_FW_FILTER_WR_DIRSTEERHASH)
245 #define S_FW_FILTER_WR_LPBK 20
246 #define V_FW_FILTER_WR_LPBK(x) ((x) << S_FW_FILTER_WR_LPBK)
248 #define S_FW_FILTER_WR_DMAC 19
249 #define V_FW_FILTER_WR_DMAC(x) ((x) << S_FW_FILTER_WR_DMAC)
251 #define S_FW_FILTER_WR_INSVLAN 17
252 #define V_FW_FILTER_WR_INSVLAN(x) ((x) << S_FW_FILTER_WR_INSVLAN)
254 #define S_FW_FILTER_WR_RMVLAN 16
255 #define V_FW_FILTER_WR_RMVLAN(x) ((x) << S_FW_FILTER_WR_RMVLAN)
257 #define S_FW_FILTER_WR_HITCNTS 15
258 #define V_FW_FILTER_WR_HITCNTS(x) ((x) << S_FW_FILTER_WR_HITCNTS)
260 #define S_FW_FILTER_WR_TXCHAN 13
261 #define V_FW_FILTER_WR_TXCHAN(x) ((x) << S_FW_FILTER_WR_TXCHAN)
263 #define S_FW_FILTER_WR_PRIO 12
264 #define V_FW_FILTER_WR_PRIO(x) ((x) << S_FW_FILTER_WR_PRIO)
266 #define S_FW_FILTER_WR_L2TIX 0
267 #define V_FW_FILTER_WR_L2TIX(x) ((x) << S_FW_FILTER_WR_L2TIX)
269 #define S_FW_FILTER_WR_FRAG 7
270 #define V_FW_FILTER_WR_FRAG(x) ((x) << S_FW_FILTER_WR_FRAG)
272 #define S_FW_FILTER_WR_FRAGM 6
273 #define V_FW_FILTER_WR_FRAGM(x) ((x) << S_FW_FILTER_WR_FRAGM)
275 #define S_FW_FILTER_WR_IVLAN_VLD 5
276 #define V_FW_FILTER_WR_IVLAN_VLD(x) ((x) << S_FW_FILTER_WR_IVLAN_VLD)
278 #define S_FW_FILTER_WR_OVLAN_VLD 4
279 #define V_FW_FILTER_WR_OVLAN_VLD(x) ((x) << S_FW_FILTER_WR_OVLAN_VLD)
281 #define S_FW_FILTER_WR_IVLAN_VLDM 3
282 #define V_FW_FILTER_WR_IVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_IVLAN_VLDM)
284 #define S_FW_FILTER_WR_OVLAN_VLDM 2
285 #define V_FW_FILTER_WR_OVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_OVLAN_VLDM)
287 #define S_FW_FILTER_WR_RX_CHAN 15
288 #define V_FW_FILTER_WR_RX_CHAN(x) ((x) << S_FW_FILTER_WR_RX_CHAN)
290 #define S_FW_FILTER_WR_RX_RPL_IQ 0
291 #define V_FW_FILTER_WR_RX_RPL_IQ(x) ((x) << S_FW_FILTER_WR_RX_RPL_IQ)
293 #define S_FW_FILTER_WR_MACI 23
294 #define V_FW_FILTER_WR_MACI(x) ((x) << S_FW_FILTER_WR_MACI)
296 #define S_FW_FILTER_WR_MACIM 14
297 #define V_FW_FILTER_WR_MACIM(x) ((x) << S_FW_FILTER_WR_MACIM)
299 #define S_FW_FILTER_WR_FCOE 13
300 #define V_FW_FILTER_WR_FCOE(x) ((x) << S_FW_FILTER_WR_FCOE)
302 #define S_FW_FILTER_WR_FCOEM 12
303 #define V_FW_FILTER_WR_FCOEM(x) ((x) << S_FW_FILTER_WR_FCOEM)
305 #define S_FW_FILTER_WR_PORT 9
306 #define V_FW_FILTER_WR_PORT(x) ((x) << S_FW_FILTER_WR_PORT)
308 #define S_FW_FILTER_WR_PORTM 6
309 #define V_FW_FILTER_WR_PORTM(x) ((x) << S_FW_FILTER_WR_PORTM)
311 #define S_FW_FILTER_WR_MATCHTYPE 3
312 #define V_FW_FILTER_WR_MATCHTYPE(x) ((x) << S_FW_FILTER_WR_MATCHTYPE)
314 #define S_FW_FILTER_WR_MATCHTYPEM 0
315 #define V_FW_FILTER_WR_MATCHTYPEM(x) ((x) << S_FW_FILTER_WR_MATCHTYPEM)
317 #define S_FW_FILTER2_WR_SWAPMAC 0
318 #define V_FW_FILTER2_WR_SWAPMAC(x) ((x) << S_FW_FILTER2_WR_SWAPMAC)
320 #define S_FW_FILTER2_WR_NATMODE 5
321 #define V_FW_FILTER2_WR_NATMODE(x) ((x) << S_FW_FILTER2_WR_NATMODE)
323 #define S_FW_FILTER2_WR_ULP_TYPE 0
324 #define V_FW_FILTER2_WR_ULP_TYPE(x) ((x) << S_FW_FILTER2_WR_ULP_TYPE)
326 /******************************************************************************
328 *********************/
331 * The maximum length of time, in miliseconds, that we expect any firmware
332 * command to take to execute and return a reply to the host. The RESET
333 * and INITIALIZE commands can take a fair amount of time to execute but
334 * most execute in far less time than this maximum. This constant is used
335 * by host software to determine how long to wait for a firmware command
336 * reply before declaring the firmware as dead/unreachable ...
338 #define FW_CMD_MAX_TIMEOUT 10000
341 * If a host driver does a HELLO and discovers that there's already a MASTER
342 * selected, we may have to wait for that MASTER to finish issuing RESET,
343 * configuration and INITIALIZE commands. Also, there's a possibility that
344 * our own HELLO may get lost if it happens right as the MASTER is issuign a
345 * RESET command, so we need to be willing to make a few retries of our HELLO.
347 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT)
348 #define FW_CMD_HELLO_RETRIES 3
350 enum fw_cmd_opcodes {
355 FW_INITIALIZE_CMD = 0x06,
356 FW_CAPS_CONFIG_CMD = 0x07,
357 FW_PARAMS_CMD = 0x08,
360 FW_EQ_ETH_CMD = 0x12,
361 FW_EQ_CTRL_CMD = 0x13,
363 FW_VI_MAC_CMD = 0x15,
364 FW_VI_RXMODE_CMD = 0x16,
365 FW_VI_ENABLE_CMD = 0x17,
366 FW_VI_STATS_CMD = 0x1a,
368 FW_RSS_IND_TBL_CMD = 0x20,
369 FW_RSS_GLB_CONFIG_CMD = 0x22,
370 FW_RSS_VI_CONFIG_CMD = 0x23,
376 FW_CMD_CAP_PORT = 0x04,
380 * Generic command header flit0
387 #define S_FW_CMD_OP 24
388 #define M_FW_CMD_OP 0xff
389 #define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP)
390 #define G_FW_CMD_OP(x) (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP)
392 #define S_FW_CMD_REQUEST 23
393 #define M_FW_CMD_REQUEST 0x1
394 #define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST)
395 #define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST)
396 #define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U)
398 #define S_FW_CMD_READ 22
399 #define M_FW_CMD_READ 0x1
400 #define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ)
401 #define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ)
402 #define F_FW_CMD_READ V_FW_CMD_READ(1U)
404 #define S_FW_CMD_WRITE 21
405 #define M_FW_CMD_WRITE 0x1
406 #define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE)
407 #define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE)
408 #define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U)
410 #define S_FW_CMD_EXEC 20
411 #define M_FW_CMD_EXEC 0x1
412 #define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC)
413 #define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC)
414 #define F_FW_CMD_EXEC V_FW_CMD_EXEC(1U)
416 #define S_FW_CMD_RETVAL 8
417 #define M_FW_CMD_RETVAL 0xff
418 #define V_FW_CMD_RETVAL(x) ((x) << S_FW_CMD_RETVAL)
419 #define G_FW_CMD_RETVAL(x) (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL)
421 #define S_FW_CMD_LEN16 0
422 #define M_FW_CMD_LEN16 0xff
423 #define V_FW_CMD_LEN16(x) ((x) << S_FW_CMD_LEN16)
424 #define G_FW_CMD_LEN16(x) (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16)
426 #define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16)
430 enum fw_ldst_addrspc {
431 FW_LDST_ADDRSPC_TP_PIO = 0x0010,
435 __be32 op_to_addrspace;
436 __be32 cycles_to_len16;
438 struct fw_ldst_addrval {
442 struct fw_ldst_idctxt {
444 __be32 msg_ctxtflush;
454 struct fw_ldst_mdio {
470 struct fw_ldst_func {
478 struct fw_ldst_pcie {
488 struct fw_ldst_i2c_deprecated {
512 #define S_FW_LDST_CMD_ADDRSPACE 0
513 #define M_FW_LDST_CMD_ADDRSPACE 0xff
514 #define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE)
516 struct fw_reset_cmd {
523 #define S_FW_RESET_CMD_HALT 31
524 #define M_FW_RESET_CMD_HALT 0x1
525 #define V_FW_RESET_CMD_HALT(x) ((x) << S_FW_RESET_CMD_HALT)
526 #define G_FW_RESET_CMD_HALT(x) \
527 (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT)
528 #define F_FW_RESET_CMD_HALT V_FW_RESET_CMD_HALT(1U)
531 FW_HELLO_CMD_STAGE_OS = 0,
534 struct fw_hello_cmd {
537 __be32 err_to_clearinit;
541 #define S_FW_HELLO_CMD_ERR 31
542 #define M_FW_HELLO_CMD_ERR 0x1
543 #define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR)
544 #define G_FW_HELLO_CMD_ERR(x) \
545 (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR)
546 #define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U)
548 #define S_FW_HELLO_CMD_INIT 30
549 #define M_FW_HELLO_CMD_INIT 0x1
550 #define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT)
551 #define G_FW_HELLO_CMD_INIT(x) \
552 (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT)
553 #define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U)
555 #define S_FW_HELLO_CMD_MASTERDIS 29
556 #define M_FW_HELLO_CMD_MASTERDIS 0x1
557 #define V_FW_HELLO_CMD_MASTERDIS(x) ((x) << S_FW_HELLO_CMD_MASTERDIS)
558 #define G_FW_HELLO_CMD_MASTERDIS(x) \
559 (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS)
560 #define F_FW_HELLO_CMD_MASTERDIS V_FW_HELLO_CMD_MASTERDIS(1U)
562 #define S_FW_HELLO_CMD_MASTERFORCE 28
563 #define M_FW_HELLO_CMD_MASTERFORCE 0x1
564 #define V_FW_HELLO_CMD_MASTERFORCE(x) ((x) << S_FW_HELLO_CMD_MASTERFORCE)
565 #define G_FW_HELLO_CMD_MASTERFORCE(x) \
566 (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE)
567 #define F_FW_HELLO_CMD_MASTERFORCE V_FW_HELLO_CMD_MASTERFORCE(1U)
569 #define S_FW_HELLO_CMD_MBMASTER 24
570 #define M_FW_HELLO_CMD_MBMASTER 0xf
571 #define V_FW_HELLO_CMD_MBMASTER(x) ((x) << S_FW_HELLO_CMD_MBMASTER)
572 #define G_FW_HELLO_CMD_MBMASTER(x) \
573 (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER)
575 #define S_FW_HELLO_CMD_MBASYNCNOT 20
576 #define M_FW_HELLO_CMD_MBASYNCNOT 0x7
577 #define V_FW_HELLO_CMD_MBASYNCNOT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOT)
578 #define G_FW_HELLO_CMD_MBASYNCNOT(x) \
579 (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT)
581 #define S_FW_HELLO_CMD_STAGE 17
582 #define M_FW_HELLO_CMD_STAGE 0x7
583 #define V_FW_HELLO_CMD_STAGE(x) ((x) << S_FW_HELLO_CMD_STAGE)
584 #define G_FW_HELLO_CMD_STAGE(x) \
585 (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE)
587 #define S_FW_HELLO_CMD_CLEARINIT 16
588 #define M_FW_HELLO_CMD_CLEARINIT 0x1
589 #define V_FW_HELLO_CMD_CLEARINIT(x) ((x) << S_FW_HELLO_CMD_CLEARINIT)
590 #define G_FW_HELLO_CMD_CLEARINIT(x) \
591 (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT)
592 #define F_FW_HELLO_CMD_CLEARINIT V_FW_HELLO_CMD_CLEARINIT(1U)
600 struct fw_initialize_cmd {
606 enum fw_caps_config_nic {
607 FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020,
608 FW_CAPS_CONFIG_NIC_ETHOFLD = 0x00000040,
612 FW_MEMTYPE_CF_FLASH = FW_MEMTYPE_FLASH,
615 struct fw_caps_config_cmd {
617 __be32 cfvalid_to_len16;
635 #define S_FW_CAPS_CONFIG_CMD_CFVALID 27
636 #define M_FW_CAPS_CONFIG_CMD_CFVALID 0x1
637 #define V_FW_CAPS_CONFIG_CMD_CFVALID(x) ((x) << S_FW_CAPS_CONFIG_CMD_CFVALID)
638 #define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \
639 (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID)
640 #define F_FW_CAPS_CONFIG_CMD_CFVALID V_FW_CAPS_CONFIG_CMD_CFVALID(1U)
642 #define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24
643 #define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7
644 #define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \
645 ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
646 #define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \
647 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \
648 M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
650 #define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16
651 #define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff
652 #define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \
653 ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
654 #define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \
655 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \
656 M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
659 * params command mnemonics
661 enum fw_params_mnem {
662 FW_PARAMS_MNEM_DEV = 1, /* device params */
663 FW_PARAMS_MNEM_PFVF = 2, /* function params */
664 FW_PARAMS_MNEM_REG = 3, /* limited register access */
665 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */
671 enum fw_params_param_dev {
672 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */
673 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */
674 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs
675 * allocated by the device's
678 FW_PARAMS_PARAM_DEV_FWREV = 0x0B, /* fw version */
679 FW_PARAMS_PARAM_DEV_TPREV = 0x0C, /* tp version */
680 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
681 FW_PARAMS_PARAM_DEV_FILTER2_WR = 0x1D,
682 FW_PARAMS_PARAM_DEV_OPAQUE_VIID_SMT_EXTN = 0x27,
686 * physical and virtual function parameters
688 enum fw_params_param_pfvf {
689 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03,
690 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04,
691 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05,
692 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06,
693 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13,
694 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14,
695 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31,
696 FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A,
697 FW_PARAMS_PARAM_PFVF_MAX_PKTS_PER_ETH_TX_PKTS_WR = 0x3D,
698 FW_PARAMS_PARAM_PFVF_GET_SMT_START = 0x3E,
699 FW_PARAMS_PARAM_PFVF_GET_SMT_SIZE = 0x3F,
703 * dma queue parameters
705 enum fw_params_param_dmaq {
706 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
707 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20,
710 #define S_FW_PARAMS_MNEM 24
711 #define M_FW_PARAMS_MNEM 0xff
712 #define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM)
713 #define G_FW_PARAMS_MNEM(x) \
714 (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM)
716 #define S_FW_PARAMS_PARAM_X 16
717 #define M_FW_PARAMS_PARAM_X 0xff
718 #define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X)
719 #define G_FW_PARAMS_PARAM_X(x) \
720 (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X)
722 #define S_FW_PARAMS_PARAM_Y 8
723 #define M_FW_PARAMS_PARAM_Y 0xff
724 #define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y)
725 #define G_FW_PARAMS_PARAM_Y(x) \
726 (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y)
728 #define S_FW_PARAMS_PARAM_Z 0
729 #define M_FW_PARAMS_PARAM_Z 0xff
730 #define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z)
731 #define G_FW_PARAMS_PARAM_Z(x) \
732 (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z)
734 #define S_FW_PARAMS_PARAM_YZ 0
735 #define M_FW_PARAMS_PARAM_YZ 0xffff
736 #define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ)
737 #define G_FW_PARAMS_PARAM_YZ(x) \
738 (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ)
740 #define S_FW_PARAMS_PARAM_XYZ 0
741 #define M_FW_PARAMS_PARAM_XYZ 0xffffff
742 #define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ)
744 struct fw_params_cmd {
747 struct fw_params_param {
753 #define S_FW_PARAMS_CMD_PFN 8
754 #define M_FW_PARAMS_CMD_PFN 0x7
755 #define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN)
756 #define G_FW_PARAMS_CMD_PFN(x) \
757 (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN)
759 #define S_FW_PARAMS_CMD_VFN 0
760 #define M_FW_PARAMS_CMD_VFN 0xff
761 #define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN)
762 #define G_FW_PARAMS_CMD_VFN(x) \
763 (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN)
770 __be32 tc_to_nexactf;
771 __be32 r_caps_to_nethctrl;
777 #define S_FW_PFVF_CMD_PFN 8
778 #define V_FW_PFVF_CMD_PFN(x) ((x) << S_FW_PFVF_CMD_PFN)
780 #define S_FW_PFVF_CMD_VFN 0
781 #define V_FW_PFVF_CMD_VFN(x) ((x) << S_FW_PFVF_CMD_VFN)
783 #define S_FW_PFVF_CMD_NIQFLINT 20
784 #define M_FW_PFVF_CMD_NIQFLINT 0xfff
785 #define G_FW_PFVF_CMD_NIQFLINT(x) \
786 (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT)
788 #define S_FW_PFVF_CMD_NIQ 0
789 #define M_FW_PFVF_CMD_NIQ 0xfffff
790 #define G_FW_PFVF_CMD_NIQ(x) \
791 (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ)
793 #define S_FW_PFVF_CMD_PMASK 20
794 #define M_FW_PFVF_CMD_PMASK 0xf
795 #define G_FW_PFVF_CMD_PMASK(x) \
796 (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK)
798 #define S_FW_PFVF_CMD_NEQ 0
799 #define M_FW_PFVF_CMD_NEQ 0xfffff
800 #define G_FW_PFVF_CMD_NEQ(x) \
801 (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ)
803 #define S_FW_PFVF_CMD_TC 24
804 #define M_FW_PFVF_CMD_TC 0xff
805 #define G_FW_PFVF_CMD_TC(x) \
806 (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC)
808 #define S_FW_PFVF_CMD_NVI 16
809 #define M_FW_PFVF_CMD_NVI 0xff
810 #define G_FW_PFVF_CMD_NVI(x) \
811 (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI)
813 #define S_FW_PFVF_CMD_NEXACTF 0
814 #define M_FW_PFVF_CMD_NEXACTF 0xffff
815 #define G_FW_PFVF_CMD_NEXACTF(x) \
816 (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF)
818 #define S_FW_PFVF_CMD_R_CAPS 24
819 #define M_FW_PFVF_CMD_R_CAPS 0xff
820 #define G_FW_PFVF_CMD_R_CAPS(x) \
821 (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS)
823 #define S_FW_PFVF_CMD_WX_CAPS 16
824 #define M_FW_PFVF_CMD_WX_CAPS 0xff
825 #define G_FW_PFVF_CMD_WX_CAPS(x) \
826 (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS)
828 #define S_FW_PFVF_CMD_NETHCTRL 0
829 #define M_FW_PFVF_CMD_NETHCTRL 0xffff
830 #define G_FW_PFVF_CMD_NETHCTRL(x) \
831 (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL)
834 * ingress queue type; the first 1K ingress queues can have associated 0,
835 * 1 or 2 free lists and an interrupt, all other ingress queues lack these
839 FW_IQ_TYPE_FL_INT_CAP,
843 FW_IQ_IQTYPE_NIC = 1,
849 __be32 alloc_to_len16;
854 __be32 type_to_iqandstindex;
855 __be16 iqdroprss_to_iqesize;
858 __be32 iqns_to_fl0congen;
859 __be16 fl0dcaen_to_fl0cidxfthresh;
862 __be32 fl1cngchmap_to_fl1congen;
863 __be16 fl1dcaen_to_fl1cidxfthresh;
868 #define S_FW_IQ_CMD_PFN 8
869 #define M_FW_IQ_CMD_PFN 0x7
870 #define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN)
871 #define G_FW_IQ_CMD_PFN(x) (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN)
873 #define S_FW_IQ_CMD_VFN 0
874 #define M_FW_IQ_CMD_VFN 0xff
875 #define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN)
876 #define G_FW_IQ_CMD_VFN(x) (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN)
878 #define S_FW_IQ_CMD_ALLOC 31
879 #define M_FW_IQ_CMD_ALLOC 0x1
880 #define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC)
881 #define G_FW_IQ_CMD_ALLOC(x) \
882 (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC)
883 #define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U)
885 #define S_FW_IQ_CMD_FREE 30
886 #define M_FW_IQ_CMD_FREE 0x1
887 #define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE)
888 #define G_FW_IQ_CMD_FREE(x) (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE)
889 #define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U)
891 #define S_FW_IQ_CMD_IQSTART 28
892 #define M_FW_IQ_CMD_IQSTART 0x1
893 #define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART)
894 #define G_FW_IQ_CMD_IQSTART(x) \
895 (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART)
896 #define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U)
898 #define S_FW_IQ_CMD_IQSTOP 27
899 #define M_FW_IQ_CMD_IQSTOP 0x1
900 #define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP)
901 #define G_FW_IQ_CMD_IQSTOP(x) \
902 (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP)
903 #define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U)
905 #define S_FW_IQ_CMD_TYPE 29
906 #define M_FW_IQ_CMD_TYPE 0x7
907 #define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE)
908 #define G_FW_IQ_CMD_TYPE(x) (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE)
910 #define S_FW_IQ_CMD_IQASYNCH 28
911 #define M_FW_IQ_CMD_IQASYNCH 0x1
912 #define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH)
913 #define G_FW_IQ_CMD_IQASYNCH(x) \
914 (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH)
915 #define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U)
917 #define S_FW_IQ_CMD_VIID 16
918 #define M_FW_IQ_CMD_VIID 0xfff
919 #define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID)
920 #define G_FW_IQ_CMD_VIID(x) (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID)
922 #define S_FW_IQ_CMD_IQANDST 15
923 #define M_FW_IQ_CMD_IQANDST 0x1
924 #define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST)
925 #define G_FW_IQ_CMD_IQANDST(x) \
926 (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST)
927 #define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U)
929 #define S_FW_IQ_CMD_IQANUD 12
930 #define M_FW_IQ_CMD_IQANUD 0x3
931 #define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD)
932 #define G_FW_IQ_CMD_IQANUD(x) \
933 (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD)
935 #define S_FW_IQ_CMD_IQANDSTINDEX 0
936 #define M_FW_IQ_CMD_IQANDSTINDEX 0xfff
937 #define V_FW_IQ_CMD_IQANDSTINDEX(x) ((x) << S_FW_IQ_CMD_IQANDSTINDEX)
938 #define G_FW_IQ_CMD_IQANDSTINDEX(x) \
939 (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX)
941 #define S_FW_IQ_CMD_IQGTSMODE 14
942 #define M_FW_IQ_CMD_IQGTSMODE 0x1
943 #define V_FW_IQ_CMD_IQGTSMODE(x) ((x) << S_FW_IQ_CMD_IQGTSMODE)
944 #define G_FW_IQ_CMD_IQGTSMODE(x) \
945 (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE)
946 #define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U)
948 #define S_FW_IQ_CMD_IQPCIECH 12
949 #define M_FW_IQ_CMD_IQPCIECH 0x3
950 #define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH)
951 #define G_FW_IQ_CMD_IQPCIECH(x) \
952 (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH)
954 #define S_FW_IQ_CMD_IQINTCNTTHRESH 4
955 #define M_FW_IQ_CMD_IQINTCNTTHRESH 0x3
956 #define V_FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << S_FW_IQ_CMD_IQINTCNTTHRESH)
957 #define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \
958 (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH)
960 #define S_FW_IQ_CMD_IQESIZE 0
961 #define M_FW_IQ_CMD_IQESIZE 0x3
962 #define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE)
963 #define G_FW_IQ_CMD_IQESIZE(x) \
964 (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE)
966 #define S_FW_IQ_CMD_IQRO 30
967 #define M_FW_IQ_CMD_IQRO 0x1
968 #define V_FW_IQ_CMD_IQRO(x) ((x) << S_FW_IQ_CMD_IQRO)
969 #define G_FW_IQ_CMD_IQRO(x) \
970 (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO)
971 #define F_FW_IQ_CMD_IQRO V_FW_IQ_CMD_IQRO(1U)
973 #define S_FW_IQ_CMD_IQFLINTCONGEN 27
974 #define M_FW_IQ_CMD_IQFLINTCONGEN 0x1
975 #define V_FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << S_FW_IQ_CMD_IQFLINTCONGEN)
976 #define G_FW_IQ_CMD_IQFLINTCONGEN(x) \
977 (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN)
978 #define F_FW_IQ_CMD_IQFLINTCONGEN V_FW_IQ_CMD_IQFLINTCONGEN(1U)
980 #define S_FW_IQ_CMD_IQTYPE 24
981 #define V_FW_IQ_CMD_IQTYPE(x) ((x) << S_FW_IQ_CMD_IQTYPE)
983 #define S_FW_IQ_CMD_FL0CNGCHMAP 20
984 #define M_FW_IQ_CMD_FL0CNGCHMAP 0xf
985 #define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP)
986 #define G_FW_IQ_CMD_FL0CNGCHMAP(x) \
987 (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP)
989 #define S_FW_IQ_CMD_FL0DATARO 12
990 #define M_FW_IQ_CMD_FL0DATARO 0x1
991 #define V_FW_IQ_CMD_FL0DATARO(x) ((x) << S_FW_IQ_CMD_FL0DATARO)
992 #define G_FW_IQ_CMD_FL0DATARO(x) \
993 (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO)
994 #define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U)
996 #define S_FW_IQ_CMD_FL0CONGCIF 11
997 #define M_FW_IQ_CMD_FL0CONGCIF 0x1
998 #define V_FW_IQ_CMD_FL0CONGCIF(x) ((x) << S_FW_IQ_CMD_FL0CONGCIF)
999 #define G_FW_IQ_CMD_FL0CONGCIF(x) \
1000 (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF)
1001 #define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U)
1003 #define S_FW_IQ_CMD_FL0FETCHRO 6
1004 #define M_FW_IQ_CMD_FL0FETCHRO 0x1
1005 #define V_FW_IQ_CMD_FL0FETCHRO(x) ((x) << S_FW_IQ_CMD_FL0FETCHRO)
1006 #define G_FW_IQ_CMD_FL0FETCHRO(x) \
1007 (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO)
1008 #define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U)
1010 #define S_FW_IQ_CMD_FL0HOSTFCMODE 4
1011 #define M_FW_IQ_CMD_FL0HOSTFCMODE 0x3
1012 #define V_FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL0HOSTFCMODE)
1013 #define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \
1014 (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE)
1016 #define S_FW_IQ_CMD_FL0PADEN 2
1017 #define M_FW_IQ_CMD_FL0PADEN 0x1
1018 #define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN)
1019 #define G_FW_IQ_CMD_FL0PADEN(x) \
1020 (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN)
1021 #define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U)
1023 #define S_FW_IQ_CMD_FL0PACKEN 1
1024 #define M_FW_IQ_CMD_FL0PACKEN 0x1
1025 #define V_FW_IQ_CMD_FL0PACKEN(x) ((x) << S_FW_IQ_CMD_FL0PACKEN)
1026 #define G_FW_IQ_CMD_FL0PACKEN(x) \
1027 (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN)
1028 #define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U)
1030 #define S_FW_IQ_CMD_FL0CONGEN 0
1031 #define M_FW_IQ_CMD_FL0CONGEN 0x1
1032 #define V_FW_IQ_CMD_FL0CONGEN(x) ((x) << S_FW_IQ_CMD_FL0CONGEN)
1033 #define G_FW_IQ_CMD_FL0CONGEN(x) \
1034 (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN)
1035 #define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U)
1037 #define S_FW_IQ_CMD_FL0FBMIN 7
1038 #define M_FW_IQ_CMD_FL0FBMIN 0x7
1039 #define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN)
1040 #define G_FW_IQ_CMD_FL0FBMIN(x) \
1041 (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN)
1043 #define S_FW_IQ_CMD_FL0FBMAX 4
1044 #define M_FW_IQ_CMD_FL0FBMAX 0x7
1045 #define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX)
1046 #define G_FW_IQ_CMD_FL0FBMAX(x) \
1047 (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX)
1049 struct fw_eq_eth_cmd {
1051 __be32 alloc_to_len16;
1053 __be32 physeqid_pkd;
1054 __be32 fetchszm_to_iqid;
1055 __be32 dcaen_to_eqsize;
1057 __be32 autoequiqe_to_viid;
1062 #define S_FW_EQ_ETH_CMD_PFN 8
1063 #define M_FW_EQ_ETH_CMD_PFN 0x7
1064 #define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN)
1065 #define G_FW_EQ_ETH_CMD_PFN(x) \
1066 (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN)
1068 #define S_FW_EQ_ETH_CMD_VFN 0
1069 #define M_FW_EQ_ETH_CMD_VFN 0xff
1070 #define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN)
1071 #define G_FW_EQ_ETH_CMD_VFN(x) \
1072 (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN)
1074 #define S_FW_EQ_ETH_CMD_ALLOC 31
1075 #define M_FW_EQ_ETH_CMD_ALLOC 0x1
1076 #define V_FW_EQ_ETH_CMD_ALLOC(x) ((x) << S_FW_EQ_ETH_CMD_ALLOC)
1077 #define G_FW_EQ_ETH_CMD_ALLOC(x) \
1078 (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC)
1079 #define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U)
1081 #define S_FW_EQ_ETH_CMD_FREE 30
1082 #define M_FW_EQ_ETH_CMD_FREE 0x1
1083 #define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE)
1084 #define G_FW_EQ_ETH_CMD_FREE(x) \
1085 (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE)
1086 #define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U)
1088 #define S_FW_EQ_ETH_CMD_EQSTART 28
1089 #define M_FW_EQ_ETH_CMD_EQSTART 0x1
1090 #define V_FW_EQ_ETH_CMD_EQSTART(x) ((x) << S_FW_EQ_ETH_CMD_EQSTART)
1091 #define G_FW_EQ_ETH_CMD_EQSTART(x) \
1092 (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART)
1093 #define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U)
1095 #define S_FW_EQ_ETH_CMD_EQID 0
1096 #define M_FW_EQ_ETH_CMD_EQID 0xfffff
1097 #define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID)
1098 #define G_FW_EQ_ETH_CMD_EQID(x) \
1099 (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID)
1101 #define S_FW_EQ_ETH_CMD_PHYSEQID 0
1102 #define M_FW_EQ_ETH_CMD_PHYSEQID 0xfffff
1103 #define G_FW_EQ_ETH_CMD_PHYSEQID(x) \
1104 (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID)
1106 #define S_FW_EQ_ETH_CMD_FETCHRO 22
1107 #define M_FW_EQ_ETH_CMD_FETCHRO 0x1
1108 #define V_FW_EQ_ETH_CMD_FETCHRO(x) ((x) << S_FW_EQ_ETH_CMD_FETCHRO)
1109 #define G_FW_EQ_ETH_CMD_FETCHRO(x) \
1110 (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO)
1111 #define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U)
1113 #define S_FW_EQ_ETH_CMD_HOSTFCMODE 20
1114 #define M_FW_EQ_ETH_CMD_HOSTFCMODE 0x3
1115 #define V_FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE)
1116 #define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \
1117 (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE)
1119 #define S_FW_EQ_ETH_CMD_PCIECHN 16
1120 #define M_FW_EQ_ETH_CMD_PCIECHN 0x3
1121 #define V_FW_EQ_ETH_CMD_PCIECHN(x) ((x) << S_FW_EQ_ETH_CMD_PCIECHN)
1122 #define G_FW_EQ_ETH_CMD_PCIECHN(x) \
1123 (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN)
1125 #define S_FW_EQ_ETH_CMD_IQID 0
1126 #define M_FW_EQ_ETH_CMD_IQID 0xffff
1127 #define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID)
1128 #define G_FW_EQ_ETH_CMD_IQID(x) \
1129 (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID)
1131 #define S_FW_EQ_ETH_CMD_FBMIN 23
1132 #define M_FW_EQ_ETH_CMD_FBMIN 0x7
1133 #define V_FW_EQ_ETH_CMD_FBMIN(x) ((x) << S_FW_EQ_ETH_CMD_FBMIN)
1134 #define G_FW_EQ_ETH_CMD_FBMIN(x) \
1135 (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN)
1137 #define S_FW_EQ_ETH_CMD_FBMAX 20
1138 #define M_FW_EQ_ETH_CMD_FBMAX 0x7
1139 #define V_FW_EQ_ETH_CMD_FBMAX(x) ((x) << S_FW_EQ_ETH_CMD_FBMAX)
1140 #define G_FW_EQ_ETH_CMD_FBMAX(x) \
1141 (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX)
1143 #define S_FW_EQ_ETH_CMD_CIDXFTHRESH 16
1144 #define M_FW_EQ_ETH_CMD_CIDXFTHRESH 0x7
1145 #define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH)
1146 #define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \
1147 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH)
1149 #define S_FW_EQ_ETH_CMD_EQSIZE 0
1150 #define M_FW_EQ_ETH_CMD_EQSIZE 0xffff
1151 #define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE)
1152 #define G_FW_EQ_ETH_CMD_EQSIZE(x) \
1153 (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE)
1155 #define S_FW_EQ_ETH_CMD_AUTOEQUEQE 30
1156 #define M_FW_EQ_ETH_CMD_AUTOEQUEQE 0x1
1157 #define V_FW_EQ_ETH_CMD_AUTOEQUEQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUEQE)
1158 #define G_FW_EQ_ETH_CMD_AUTOEQUEQE(x) \
1159 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUEQE) & M_FW_EQ_ETH_CMD_AUTOEQUEQE)
1160 #define F_FW_EQ_ETH_CMD_AUTOEQUEQE V_FW_EQ_ETH_CMD_AUTOEQUEQE(1U)
1162 #define S_FW_EQ_ETH_CMD_VIID 16
1163 #define M_FW_EQ_ETH_CMD_VIID 0xfff
1164 #define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID)
1165 #define G_FW_EQ_ETH_CMD_VIID(x) \
1166 (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID)
1168 struct fw_eq_ctrl_cmd {
1170 __be32 alloc_to_len16;
1171 __be32 cmpliqid_eqid;
1172 __be32 physeqid_pkd;
1173 __be32 fetchszm_to_iqid;
1174 __be32 dcaen_to_eqsize;
1178 #define S_FW_EQ_CTRL_CMD_PFN 8
1179 #define V_FW_EQ_CTRL_CMD_PFN(x) ((x) << S_FW_EQ_CTRL_CMD_PFN)
1181 #define S_FW_EQ_CTRL_CMD_VFN 0
1182 #define V_FW_EQ_CTRL_CMD_VFN(x) ((x) << S_FW_EQ_CTRL_CMD_VFN)
1184 #define S_FW_EQ_CTRL_CMD_ALLOC 31
1185 #define V_FW_EQ_CTRL_CMD_ALLOC(x) ((x) << S_FW_EQ_CTRL_CMD_ALLOC)
1186 #define F_FW_EQ_CTRL_CMD_ALLOC V_FW_EQ_CTRL_CMD_ALLOC(1U)
1188 #define S_FW_EQ_CTRL_CMD_FREE 30
1189 #define V_FW_EQ_CTRL_CMD_FREE(x) ((x) << S_FW_EQ_CTRL_CMD_FREE)
1190 #define F_FW_EQ_CTRL_CMD_FREE V_FW_EQ_CTRL_CMD_FREE(1U)
1192 #define S_FW_EQ_CTRL_CMD_EQSTART 28
1193 #define V_FW_EQ_CTRL_CMD_EQSTART(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTART)
1194 #define F_FW_EQ_CTRL_CMD_EQSTART V_FW_EQ_CTRL_CMD_EQSTART(1U)
1196 #define S_FW_EQ_CTRL_CMD_CMPLIQID 20
1197 #define V_FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << S_FW_EQ_CTRL_CMD_CMPLIQID)
1199 #define S_FW_EQ_CTRL_CMD_EQID 0
1200 #define M_FW_EQ_CTRL_CMD_EQID 0xfffff
1201 #define V_FW_EQ_CTRL_CMD_EQID(x) ((x) << S_FW_EQ_CTRL_CMD_EQID)
1202 #define G_FW_EQ_CTRL_CMD_EQID(x) \
1203 (((x) >> S_FW_EQ_CTRL_CMD_EQID) & M_FW_EQ_CTRL_CMD_EQID)
1205 #define S_FW_EQ_CTRL_CMD_PHYSEQID 0
1206 #define M_FW_EQ_CTRL_CMD_PHYSEQID 0xfffff
1207 #define V_FW_EQ_CTRL_CMD_PHYSEQID(x) ((x) << S_FW_EQ_CTRL_CMD_PHYSEQID)
1208 #define G_FW_EQ_CTRL_CMD_PHYSEQID(x) \
1209 (((x) >> S_FW_EQ_CTRL_CMD_PHYSEQID) & M_FW_EQ_CTRL_CMD_PHYSEQID)
1211 #define S_FW_EQ_CTRL_CMD_FETCHRO 22
1212 #define V_FW_EQ_CTRL_CMD_FETCHRO(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHRO)
1213 #define F_FW_EQ_CTRL_CMD_FETCHRO V_FW_EQ_CTRL_CMD_FETCHRO(1U)
1215 #define S_FW_EQ_CTRL_CMD_HOSTFCMODE 20
1216 #define M_FW_EQ_CTRL_CMD_HOSTFCMODE 0x3
1217 #define V_FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_CTRL_CMD_HOSTFCMODE)
1219 #define S_FW_EQ_CTRL_CMD_PCIECHN 16
1220 #define V_FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << S_FW_EQ_CTRL_CMD_PCIECHN)
1222 #define S_FW_EQ_CTRL_CMD_IQID 0
1223 #define V_FW_EQ_CTRL_CMD_IQID(x) ((x) << S_FW_EQ_CTRL_CMD_IQID)
1225 #define S_FW_EQ_CTRL_CMD_FBMIN 23
1226 #define V_FW_EQ_CTRL_CMD_FBMIN(x) ((x) << S_FW_EQ_CTRL_CMD_FBMIN)
1228 #define S_FW_EQ_CTRL_CMD_FBMAX 20
1229 #define V_FW_EQ_CTRL_CMD_FBMAX(x) ((x) << S_FW_EQ_CTRL_CMD_FBMAX)
1231 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESH 16
1232 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESH)
1234 #define S_FW_EQ_CTRL_CMD_EQSIZE 0
1235 #define V_FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << S_FW_EQ_CTRL_CMD_EQSIZE)
1241 /* Macros for VIID parsing:
1242 * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number
1245 #define S_FW_VIID_VIVLD 7
1246 #define M_FW_VIID_VIVLD 0x1
1247 #define G_FW_VIID_VIVLD(x) (((x) >> S_FW_VIID_VIVLD) & M_FW_VIID_VIVLD)
1249 #define S_FW_VIID_VIN 0
1250 #define M_FW_VIID_VIN 0x7F
1251 #define G_FW_VIID_VIN(x) (((x) >> S_FW_VIID_VIN) & M_FW_VIID_VIN)
1255 __be32 alloc_to_len16;
1256 __be16 type_to_viid;
1261 __be16 norss_rsssize;
1271 #define S_FW_VI_CMD_PFN 8
1272 #define M_FW_VI_CMD_PFN 0x7
1273 #define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN)
1274 #define G_FW_VI_CMD_PFN(x) (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN)
1276 #define S_FW_VI_CMD_VFN 0
1277 #define M_FW_VI_CMD_VFN 0xff
1278 #define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN)
1279 #define G_FW_VI_CMD_VFN(x) (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN)
1281 #define S_FW_VI_CMD_ALLOC 31
1282 #define M_FW_VI_CMD_ALLOC 0x1
1283 #define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC)
1284 #define G_FW_VI_CMD_ALLOC(x) \
1285 (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC)
1286 #define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U)
1288 #define S_FW_VI_CMD_FREE 30
1289 #define M_FW_VI_CMD_FREE 0x1
1290 #define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE)
1291 #define G_FW_VI_CMD_FREE(x) (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE)
1292 #define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U)
1294 #define S_FW_VI_CMD_VFVLD 24
1295 #define M_FW_VI_CMD_VFVLD 0x1
1296 #define G_FW_VI_CMD_VFVLD(x) \
1297 (((x) >> S_FW_VI_CMD_VFVLD) & M_FW_VI_CMD_VFVLD)
1299 #define S_FW_VI_CMD_VIN 16
1300 #define M_FW_VI_CMD_VIN 0xff
1301 #define G_FW_VI_CMD_VIN(x) \
1302 (((x) >> S_FW_VI_CMD_VIN) & M_FW_VI_CMD_VIN)
1304 #define S_FW_VI_CMD_TYPE 15
1305 #define M_FW_VI_CMD_TYPE 0x1
1306 #define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE)
1307 #define G_FW_VI_CMD_TYPE(x) (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE)
1308 #define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U)
1310 #define S_FW_VI_CMD_FUNC 12
1311 #define M_FW_VI_CMD_FUNC 0x7
1312 #define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC)
1313 #define G_FW_VI_CMD_FUNC(x) (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC)
1315 #define S_FW_VI_CMD_VIID 0
1316 #define M_FW_VI_CMD_VIID 0xfff
1317 #define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID)
1318 #define G_FW_VI_CMD_VIID(x) (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID)
1320 #define S_FW_VI_CMD_PORTID 4
1321 #define M_FW_VI_CMD_PORTID 0xf
1322 #define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID)
1323 #define G_FW_VI_CMD_PORTID(x) \
1324 (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID)
1326 #define S_FW_VI_CMD_RSSSIZE 0
1327 #define M_FW_VI_CMD_RSSSIZE 0x7ff
1328 #define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE)
1329 #define G_FW_VI_CMD_RSSSIZE(x) \
1330 (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE)
1332 /* Special VI_MAC command index ids */
1333 #define FW_VI_MAC_ADD_MAC 0x3FF
1334 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE
1335 #define FW_VI_MAC_ID_BASED_FREE 0x3FC
1337 enum fw_vi_mac_smac {
1338 FW_VI_MAC_MPS_TCAM_ENTRY,
1339 FW_VI_MAC_SMT_AND_MPSTCAM
1342 enum fw_vi_mac_entry_types {
1343 FW_VI_MAC_TYPE_RAW = 0x2,
1346 struct fw_vi_mac_cmd {
1348 __be32 freemacs_to_len16;
1350 struct fw_vi_mac_exact {
1351 __be16 valid_to_idx;
1354 struct fw_vi_mac_hash {
1357 struct fw_vi_mac_raw {
1367 #define S_FW_VI_MAC_CMD_VIID 0
1368 #define M_FW_VI_MAC_CMD_VIID 0xfff
1369 #define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID)
1370 #define G_FW_VI_MAC_CMD_VIID(x) \
1371 (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID)
1373 #define S_FW_VI_MAC_CMD_FREEMACS 31
1374 #define V_FW_VI_MAC_CMD_FREEMACS(x) ((x) << S_FW_VI_MAC_CMD_FREEMACS)
1376 #define S_FW_VI_MAC_CMD_ENTRY_TYPE 23
1377 #define V_FW_VI_MAC_CMD_ENTRY_TYPE(x) ((x) << S_FW_VI_MAC_CMD_ENTRY_TYPE)
1379 #define S_FW_VI_MAC_CMD_VALID 15
1380 #define M_FW_VI_MAC_CMD_VALID 0x1
1381 #define V_FW_VI_MAC_CMD_VALID(x) ((x) << S_FW_VI_MAC_CMD_VALID)
1382 #define G_FW_VI_MAC_CMD_VALID(x) \
1383 (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID)
1384 #define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U)
1386 #define S_FW_VI_MAC_CMD_SMAC_RESULT 10
1387 #define M_FW_VI_MAC_CMD_SMAC_RESULT 0x3
1388 #define V_FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << S_FW_VI_MAC_CMD_SMAC_RESULT)
1389 #define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \
1390 (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT)
1392 #define S_FW_VI_MAC_CMD_IDX 0
1393 #define M_FW_VI_MAC_CMD_IDX 0x3ff
1394 #define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX)
1395 #define G_FW_VI_MAC_CMD_IDX(x) \
1396 (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX)
1398 #define S_FW_VI_MAC_CMD_RAW_IDX 16
1399 #define M_FW_VI_MAC_CMD_RAW_IDX 0xffff
1400 #define V_FW_VI_MAC_CMD_RAW_IDX(x) ((x) << S_FW_VI_MAC_CMD_RAW_IDX)
1401 #define G_FW_VI_MAC_CMD_RAW_IDX(x) \
1402 (((x) >> S_FW_VI_MAC_CMD_RAW_IDX) & M_FW_VI_MAC_CMD_RAW_IDX)
1404 struct fw_vi_rxmode_cmd {
1406 __be32 retval_len16;
1407 __be32 mtu_to_vlanexen;
1411 #define S_FW_VI_RXMODE_CMD_VIID 0
1412 #define M_FW_VI_RXMODE_CMD_VIID 0xfff
1413 #define V_FW_VI_RXMODE_CMD_VIID(x) ((x) << S_FW_VI_RXMODE_CMD_VIID)
1414 #define G_FW_VI_RXMODE_CMD_VIID(x) \
1415 (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID)
1417 #define S_FW_VI_RXMODE_CMD_MTU 16
1418 #define M_FW_VI_RXMODE_CMD_MTU 0xffff
1419 #define V_FW_VI_RXMODE_CMD_MTU(x) ((x) << S_FW_VI_RXMODE_CMD_MTU)
1420 #define G_FW_VI_RXMODE_CMD_MTU(x) \
1421 (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU)
1423 #define S_FW_VI_RXMODE_CMD_PROMISCEN 14
1424 #define M_FW_VI_RXMODE_CMD_PROMISCEN 0x3
1425 #define V_FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << S_FW_VI_RXMODE_CMD_PROMISCEN)
1426 #define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \
1427 (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN)
1429 #define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12
1430 #define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3
1431 #define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \
1432 ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN)
1433 #define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \
1434 (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN)
1436 #define S_FW_VI_RXMODE_CMD_BROADCASTEN 10
1437 #define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3
1438 #define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \
1439 ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN)
1440 #define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \
1441 (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & \
1442 M_FW_VI_RXMODE_CMD_BROADCASTEN)
1444 #define S_FW_VI_RXMODE_CMD_VLANEXEN 8
1445 #define M_FW_VI_RXMODE_CMD_VLANEXEN 0x3
1446 #define V_FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << S_FW_VI_RXMODE_CMD_VLANEXEN)
1447 #define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \
1448 (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN)
1450 struct fw_vi_enable_cmd {
1452 __be32 ien_to_len16;
1458 #define S_FW_VI_ENABLE_CMD_VIID 0
1459 #define M_FW_VI_ENABLE_CMD_VIID 0xfff
1460 #define V_FW_VI_ENABLE_CMD_VIID(x) ((x) << S_FW_VI_ENABLE_CMD_VIID)
1461 #define G_FW_VI_ENABLE_CMD_VIID(x) \
1462 (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID)
1464 #define S_FW_VI_ENABLE_CMD_IEN 31
1465 #define M_FW_VI_ENABLE_CMD_IEN 0x1
1466 #define V_FW_VI_ENABLE_CMD_IEN(x) ((x) << S_FW_VI_ENABLE_CMD_IEN)
1467 #define G_FW_VI_ENABLE_CMD_IEN(x) \
1468 (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN)
1469 #define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U)
1471 #define S_FW_VI_ENABLE_CMD_EEN 30
1472 #define M_FW_VI_ENABLE_CMD_EEN 0x1
1473 #define V_FW_VI_ENABLE_CMD_EEN(x) ((x) << S_FW_VI_ENABLE_CMD_EEN)
1474 #define G_FW_VI_ENABLE_CMD_EEN(x) \
1475 (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN)
1476 #define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U)
1478 #define S_FW_VI_ENABLE_CMD_DCB_INFO 28
1479 #define M_FW_VI_ENABLE_CMD_DCB_INFO 0x1
1480 #define V_FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << S_FW_VI_ENABLE_CMD_DCB_INFO)
1481 #define G_FW_VI_ENABLE_CMD_DCB_INFO(x) \
1482 (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO)
1483 #define F_FW_VI_ENABLE_CMD_DCB_INFO V_FW_VI_ENABLE_CMD_DCB_INFO(1U)
1485 /* VI VF stats offset definitions */
1486 #define VI_VF_NUM_STATS 16
1488 /* VI PF stats offset definitions */
1489 #define VI_PF_NUM_STATS 17
1490 enum fw_vi_stats_pf_index {
1491 FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
1492 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
1493 FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
1494 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
1495 FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
1496 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
1497 FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
1498 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
1499 FW_VI_PF_STAT_RX_BYTES_IX,
1500 FW_VI_PF_STAT_RX_FRAMES_IX,
1501 FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
1502 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
1503 FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
1504 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
1505 FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
1506 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
1507 FW_VI_PF_STAT_RX_ERR_FRAMES_IX
1510 struct fw_vi_stats_cmd {
1512 __be32 retval_len16;
1514 struct fw_vi_stats_ctl {
1525 struct fw_vi_stats_pf {
1526 __be64 tx_bcast_bytes;
1527 __be64 tx_bcast_frames;
1528 __be64 tx_mcast_bytes;
1529 __be64 tx_mcast_frames;
1530 __be64 tx_ucast_bytes;
1531 __be64 tx_ucast_frames;
1532 __be64 tx_offload_bytes;
1533 __be64 tx_offload_frames;
1535 __be64 rx_pf_frames;
1536 __be64 rx_bcast_bytes;
1537 __be64 rx_bcast_frames;
1538 __be64 rx_mcast_bytes;
1539 __be64 rx_mcast_frames;
1540 __be64 rx_ucast_bytes;
1541 __be64 rx_ucast_frames;
1542 __be64 rx_err_frames;
1544 struct fw_vi_stats_vf {
1545 __be64 tx_bcast_bytes;
1546 __be64 tx_bcast_frames;
1547 __be64 tx_mcast_bytes;
1548 __be64 tx_mcast_frames;
1549 __be64 tx_ucast_bytes;
1550 __be64 tx_ucast_frames;
1551 __be64 tx_drop_frames;
1552 __be64 tx_offload_bytes;
1553 __be64 tx_offload_frames;
1554 __be64 rx_bcast_bytes;
1555 __be64 rx_bcast_frames;
1556 __be64 rx_mcast_bytes;
1557 __be64 rx_mcast_frames;
1558 __be64 rx_ucast_bytes;
1559 __be64 rx_ucast_frames;
1560 __be64 rx_err_frames;
1565 #define S_FW_VI_STATS_CMD_VIID 0
1566 #define V_FW_VI_STATS_CMD_VIID(x) ((x) << S_FW_VI_STATS_CMD_VIID)
1568 #define S_FW_VI_STATS_CMD_NSTATS 12
1569 #define V_FW_VI_STATS_CMD_NSTATS(x) ((x) << S_FW_VI_STATS_CMD_NSTATS)
1571 #define S_FW_VI_STATS_CMD_IX 0
1572 #define V_FW_VI_STATS_CMD_IX(x) ((x) << S_FW_VI_STATS_CMD_IX)
1574 /* old 16-bit port capabilities bitmap */
1576 FW_PORT_CAP_SPEED_100M = 0x0001,
1577 FW_PORT_CAP_SPEED_1G = 0x0002,
1578 FW_PORT_CAP_SPEED_25G = 0x0004,
1579 FW_PORT_CAP_SPEED_10G = 0x0008,
1580 FW_PORT_CAP_SPEED_40G = 0x0010,
1581 FW_PORT_CAP_SPEED_100G = 0x0020,
1582 FW_PORT_CAP_FC_RX = 0x0040,
1583 FW_PORT_CAP_FC_TX = 0x0080,
1584 FW_PORT_CAP_ANEG = 0x0100,
1585 FW_PORT_CAP_MDIX = 0x0200,
1586 FW_PORT_CAP_MDIAUTO = 0x0400,
1587 FW_PORT_CAP_FEC_RS = 0x0800,
1588 FW_PORT_CAP_FEC_BASER_RS = 0x1000,
1589 FW_PORT_CAP_FEC_RESERVED = 0x2000,
1590 FW_PORT_CAP_802_3_PAUSE = 0x4000,
1591 FW_PORT_CAP_802_3_ASM_DIR = 0x8000,
1594 #define S_FW_PORT_CAP_SPEED 0
1595 #define M_FW_PORT_CAP_SPEED 0x3f
1596 #define V_FW_PORT_CAP_SPEED(x) ((x) << S_FW_PORT_CAP_SPEED)
1597 #define G_FW_PORT_CAP_SPEED(x) \
1598 (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED)
1601 FW_PORT_CAP_MDI_AUTO,
1604 #define S_FW_PORT_CAP_MDI 9
1605 #define M_FW_PORT_CAP_MDI 3
1606 #define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI)
1607 #define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI)
1609 /* new 32-bit port capabilities bitmap (fw_port_cap32_t) */
1610 #define FW_PORT_CAP32_SPEED_100M 0x00000001UL
1611 #define FW_PORT_CAP32_SPEED_1G 0x00000002UL
1612 #define FW_PORT_CAP32_SPEED_10G 0x00000004UL
1613 #define FW_PORT_CAP32_SPEED_25G 0x00000008UL
1614 #define FW_PORT_CAP32_SPEED_40G 0x00000010UL
1615 #define FW_PORT_CAP32_SPEED_50G 0x00000020UL
1616 #define FW_PORT_CAP32_SPEED_100G 0x00000040UL
1617 #define FW_PORT_CAP32_FC_RX 0x00010000UL
1618 #define FW_PORT_CAP32_FC_TX 0x00020000UL
1619 #define FW_PORT_CAP32_802_3_PAUSE 0x00040000UL
1620 #define FW_PORT_CAP32_802_3_ASM_DIR 0x00080000UL
1621 #define FW_PORT_CAP32_ANEG 0x00100000UL
1622 #define FW_PORT_CAP32_MDIX 0x00200000UL
1623 #define FW_PORT_CAP32_MDIAUTO 0x00400000UL
1624 #define FW_PORT_CAP32_FEC_RS 0x00800000UL
1625 #define FW_PORT_CAP32_FEC_BASER_RS 0x01000000UL
1627 #define S_FW_PORT_CAP32_SPEED 0
1628 #define M_FW_PORT_CAP32_SPEED 0xfff
1629 #define V_FW_PORT_CAP32_SPEED(x) ((x) << S_FW_PORT_CAP32_SPEED)
1630 #define G_FW_PORT_CAP32_SPEED(x) \
1631 (((x) >> S_FW_PORT_CAP32_SPEED) & M_FW_PORT_CAP32_SPEED)
1633 enum fw_port_mdi32 {
1634 FW_PORT_CAP32_MDI_AUTO,
1637 #define S_FW_PORT_CAP32_MDI 21
1638 #define M_FW_PORT_CAP32_MDI 3
1639 #define V_FW_PORT_CAP32_MDI(x) ((x) << S_FW_PORT_CAP32_MDI)
1640 #define G_FW_PORT_CAP32_MDI(x) \
1641 (((x) >> S_FW_PORT_CAP32_MDI) & M_FW_PORT_CAP32_MDI)
1643 enum fw_port_action {
1644 FW_PORT_ACTION_L1_CFG = 0x0001,
1645 FW_PORT_ACTION_GET_PORT_INFO = 0x0003,
1646 FW_PORT_ACTION_L1_CFG32 = 0x0009,
1647 FW_PORT_ACTION_GET_PORT_INFO32 = 0x000a,
1650 struct fw_port_cmd {
1651 __be32 op_to_portid;
1652 __be32 action_to_len16;
1654 struct fw_port_l1cfg {
1658 struct fw_port_l2cfg {
1660 __u8 ovlan3_to_ivlan0;
1662 __be16 txipg_force_pinfo;
1673 struct fw_port_info {
1674 __be32 lstatus_to_modtype;
1685 struct fw_port_diags {
1691 struct fw_port_dcb_pgid {
1698 struct fw_port_dcb_pgrate {
1702 __u8 num_tcs_supported;
1706 struct fw_port_dcb_priorate {
1710 __u8 strict_priorate[8];
1712 struct fw_port_dcb_pfc {
1719 struct fw_port_app_priority {
1728 struct fw_port_dcb_control {
1731 __be16 dcb_version_to_app_state;
1736 struct fw_port_l1cfg32 {
1740 struct fw_port_info32 {
1741 __be32 lstatus32_to_cbllen32;
1742 __be32 auxlinfo32_mtu32;
1751 #define S_FW_PORT_CMD_PORTID 0
1752 #define M_FW_PORT_CMD_PORTID 0xf
1753 #define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID)
1754 #define G_FW_PORT_CMD_PORTID(x) \
1755 (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID)
1757 #define S_FW_PORT_CMD_ACTION 16
1758 #define M_FW_PORT_CMD_ACTION 0xffff
1759 #define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION)
1760 #define G_FW_PORT_CMD_ACTION(x) \
1761 (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION)
1763 #define S_FW_PORT_CMD_LSTATUS 31
1764 #define M_FW_PORT_CMD_LSTATUS 0x1
1765 #define V_FW_PORT_CMD_LSTATUS(x) ((x) << S_FW_PORT_CMD_LSTATUS)
1766 #define G_FW_PORT_CMD_LSTATUS(x) \
1767 (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS)
1768 #define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U)
1770 #define S_FW_PORT_CMD_LSPEED 24
1771 #define M_FW_PORT_CMD_LSPEED 0x3f
1772 #define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED)
1773 #define G_FW_PORT_CMD_LSPEED(x) \
1774 (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED)
1776 #define S_FW_PORT_CMD_TXPAUSE 23
1777 #define M_FW_PORT_CMD_TXPAUSE 0x1
1778 #define V_FW_PORT_CMD_TXPAUSE(x) ((x) << S_FW_PORT_CMD_TXPAUSE)
1779 #define G_FW_PORT_CMD_TXPAUSE(x) \
1780 (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE)
1781 #define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U)
1783 #define S_FW_PORT_CMD_RXPAUSE 22
1784 #define M_FW_PORT_CMD_RXPAUSE 0x1
1785 #define V_FW_PORT_CMD_RXPAUSE(x) ((x) << S_FW_PORT_CMD_RXPAUSE)
1786 #define G_FW_PORT_CMD_RXPAUSE(x) \
1787 (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE)
1788 #define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U)
1790 #define S_FW_PORT_CMD_MDIOCAP 21
1791 #define M_FW_PORT_CMD_MDIOCAP 0x1
1792 #define V_FW_PORT_CMD_MDIOCAP(x) ((x) << S_FW_PORT_CMD_MDIOCAP)
1793 #define G_FW_PORT_CMD_MDIOCAP(x) \
1794 (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP)
1795 #define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U)
1797 #define S_FW_PORT_CMD_MDIOADDR 16
1798 #define M_FW_PORT_CMD_MDIOADDR 0x1f
1799 #define V_FW_PORT_CMD_MDIOADDR(x) ((x) << S_FW_PORT_CMD_MDIOADDR)
1800 #define G_FW_PORT_CMD_MDIOADDR(x) \
1801 (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR)
1803 #define S_FW_PORT_CMD_PTYPE 8
1804 #define M_FW_PORT_CMD_PTYPE 0x1f
1805 #define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE)
1806 #define G_FW_PORT_CMD_PTYPE(x) \
1807 (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE)
1809 #define S_FW_PORT_CMD_LINKDNRC 5
1810 #define M_FW_PORT_CMD_LINKDNRC 0x7
1811 #define V_FW_PORT_CMD_LINKDNRC(x) ((x) << S_FW_PORT_CMD_LINKDNRC)
1812 #define G_FW_PORT_CMD_LINKDNRC(x) \
1813 (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC)
1815 #define S_FW_PORT_CMD_MODTYPE 0
1816 #define M_FW_PORT_CMD_MODTYPE 0x1f
1817 #define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE)
1818 #define G_FW_PORT_CMD_MODTYPE(x) \
1819 (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE)
1821 #define S_FW_PORT_CMD_LSTATUS32 31
1822 #define M_FW_PORT_CMD_LSTATUS32 0x1
1823 #define V_FW_PORT_CMD_LSTATUS32(x) ((x) << S_FW_PORT_CMD_LSTATUS32)
1824 #define F_FW_PORT_CMD_LSTATUS32 V_FW_PORT_CMD_LSTATUS32(1U)
1826 #define S_FW_PORT_CMD_LINKDNRC32 28
1827 #define M_FW_PORT_CMD_LINKDNRC32 0x7
1828 #define G_FW_PORT_CMD_LINKDNRC32(x) \
1829 (((x) >> S_FW_PORT_CMD_LINKDNRC32) & M_FW_PORT_CMD_LINKDNRC32)
1831 #define S_FW_PORT_CMD_MDIOCAP32 26
1832 #define M_FW_PORT_CMD_MDIOCAP32 0x1
1833 #define V_FW_PORT_CMD_MDIOCAP32(x) ((x) << S_FW_PORT_CMD_MDIOCAP32)
1834 #define F_FW_PORT_CMD_MDIOCAP32 V_FW_PORT_CMD_MDIOCAP32(1U)
1836 #define S_FW_PORT_CMD_MDIOADDR32 21
1837 #define M_FW_PORT_CMD_MDIOADDR32 0x1f
1838 #define G_FW_PORT_CMD_MDIOADDR32(x) \
1839 (((x) >> S_FW_PORT_CMD_MDIOADDR32) & M_FW_PORT_CMD_MDIOADDR32)
1841 #define S_FW_PORT_CMD_PORTTYPE32 13
1842 #define M_FW_PORT_CMD_PORTTYPE32 0xff
1843 #define G_FW_PORT_CMD_PORTTYPE32(x) \
1844 (((x) >> S_FW_PORT_CMD_PORTTYPE32) & M_FW_PORT_CMD_PORTTYPE32)
1846 #define S_FW_PORT_CMD_MODTYPE32 8
1847 #define M_FW_PORT_CMD_MODTYPE32 0x1f
1848 #define G_FW_PORT_CMD_MODTYPE32(x) \
1849 (((x) >> S_FW_PORT_CMD_MODTYPE32) & M_FW_PORT_CMD_MODTYPE32)
1852 * These are configured into the VPD and hence tools that generate
1853 * VPD may use this enumeration.
1854 * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed
1857 * Update the Common Code t4_hw.c:t4_get_port_type_description()
1858 * with any new Firmware Port Technology Types!
1861 FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */
1862 FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */
1863 FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */
1864 FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G */
1865 FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M? */
1866 FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */
1867 FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */
1868 FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */
1869 FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G */
1870 FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */
1871 FW_PORT_TYPE_BP_AP = 10,
1872 /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */
1873 FW_PORT_TYPE_BP4_AP = 11,
1874 /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */
1875 FW_PORT_TYPE_QSFP_10G = 12, /* No, 1, Yes, No, No, No, 10G */
1876 FW_PORT_TYPE_QSA = 13, /* No, 1, Yes, No, No, No, 10G */
1877 FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */
1878 FW_PORT_TYPE_BP40_BA = 15,
1879 /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */
1880 FW_PORT_TYPE_KR4_100G = 16, /* No, 4, 100G/40G/25G, Backplane */
1881 FW_PORT_TYPE_CR4_QSFP = 17, /* No, 4, 100G/40G/25G */
1882 FW_PORT_TYPE_CR_QSFP = 18, /* No, 1, 25G Spider cable */
1883 FW_PORT_TYPE_CR2_QSFP = 19, /* No, 2, 50G */
1884 FW_PORT_TYPE_SFP28 = 20, /* No, 1, 25G/10G/1G */
1885 FW_PORT_TYPE_KR_SFP28 = 21, /* No, 1, 25G/10G/1G using Backplane */
1886 FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE
1889 /* These are read from module's EEPROM and determined once the
1890 * module is inserted.
1892 enum fw_port_module_type {
1893 FW_PORT_MOD_TYPE_NA = 0x0,
1894 FW_PORT_MOD_TYPE_LR = 0x1,
1895 FW_PORT_MOD_TYPE_SR = 0x2,
1896 FW_PORT_MOD_TYPE_ER = 0x3,
1897 FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4,
1898 FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5,
1899 FW_PORT_MOD_TYPE_LRM = 0x6,
1900 FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE - 3,
1901 FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE - 2,
1902 FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1,
1903 FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE
1906 /* used by FW and tools may use this to generate VPD */
1907 enum fw_port_mod_sub_type {
1908 FW_PORT_MOD_SUB_TYPE_NA,
1909 FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1,
1910 FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2,
1911 FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3,
1912 FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4,
1913 FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5,
1914 FW_PORT_MOD_SUB_TYPE_BCM5482 = 0x6,
1915 FW_PORT_MOD_SUB_TYPE_BCM84856 = 0x7,
1916 FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8,
1919 * The following will never been in the VPD. They are TWINAX cable
1920 * lengths decoded from SFP+ module i2c PROMs. These should almost
1921 * certainly go somewhere else ...
1923 FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9,
1924 FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA,
1925 FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB,
1926 FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC,
1929 /* link down reason codes (3b) */
1930 enum fw_port_link_dn_rc {
1931 FW_PORT_LINK_DN_RC_NONE,
1932 FW_PORT_LINK_DN_RC_REMFLT, /* Remote fault detected */
1933 FW_PORT_LINK_DN_ANEG_F, /* Auto-negotiation fault */
1934 FW_PORT_LINK_DN_RESERVED3,
1935 FW_PORT_LINK_DN_OVERHEAT, /* Port overheated */
1936 FW_PORT_LINK_DN_UNKNOWN, /* Unable to determine reason */
1937 FW_PORT_LINK_DN_RX_LOS, /* No RX signal detected */
1938 FW_PORT_LINK_DN_RESERVED7
1942 #define FW_NUM_PORT_STATS 50
1943 #define FW_NUM_PORT_TX_STATS 23
1944 #define FW_NUM_PORT_RX_STATS 27
1946 enum fw_port_stats_tx_index {
1947 FW_STAT_TX_PORT_BYTES_IX,
1948 FW_STAT_TX_PORT_FRAMES_IX,
1949 FW_STAT_TX_PORT_BCAST_IX,
1950 FW_STAT_TX_PORT_MCAST_IX,
1951 FW_STAT_TX_PORT_UCAST_IX,
1952 FW_STAT_TX_PORT_ERROR_IX,
1953 FW_STAT_TX_PORT_64B_IX,
1954 FW_STAT_TX_PORT_65B_127B_IX,
1955 FW_STAT_TX_PORT_128B_255B_IX,
1956 FW_STAT_TX_PORT_256B_511B_IX,
1957 FW_STAT_TX_PORT_512B_1023B_IX,
1958 FW_STAT_TX_PORT_1024B_1518B_IX,
1959 FW_STAT_TX_PORT_1519B_MAX_IX,
1960 FW_STAT_TX_PORT_DROP_IX,
1961 FW_STAT_TX_PORT_PAUSE_IX,
1962 FW_STAT_TX_PORT_PPP0_IX,
1963 FW_STAT_TX_PORT_PPP1_IX,
1964 FW_STAT_TX_PORT_PPP2_IX,
1965 FW_STAT_TX_PORT_PPP3_IX,
1966 FW_STAT_TX_PORT_PPP4_IX,
1967 FW_STAT_TX_PORT_PPP5_IX,
1968 FW_STAT_TX_PORT_PPP6_IX,
1969 FW_STAT_TX_PORT_PPP7_IX
1972 enum fw_port_stat_rx_index {
1973 FW_STAT_RX_PORT_BYTES_IX,
1974 FW_STAT_RX_PORT_FRAMES_IX,
1975 FW_STAT_RX_PORT_BCAST_IX,
1976 FW_STAT_RX_PORT_MCAST_IX,
1977 FW_STAT_RX_PORT_UCAST_IX,
1978 FW_STAT_RX_PORT_MTU_ERROR_IX,
1979 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
1980 FW_STAT_RX_PORT_CRC_ERROR_IX,
1981 FW_STAT_RX_PORT_LEN_ERROR_IX,
1982 FW_STAT_RX_PORT_SYM_ERROR_IX,
1983 FW_STAT_RX_PORT_64B_IX,
1984 FW_STAT_RX_PORT_65B_127B_IX,
1985 FW_STAT_RX_PORT_128B_255B_IX,
1986 FW_STAT_RX_PORT_256B_511B_IX,
1987 FW_STAT_RX_PORT_512B_1023B_IX,
1988 FW_STAT_RX_PORT_1024B_1518B_IX,
1989 FW_STAT_RX_PORT_1519B_MAX_IX,
1990 FW_STAT_RX_PORT_PAUSE_IX,
1991 FW_STAT_RX_PORT_PPP0_IX,
1992 FW_STAT_RX_PORT_PPP1_IX,
1993 FW_STAT_RX_PORT_PPP2_IX,
1994 FW_STAT_RX_PORT_PPP3_IX,
1995 FW_STAT_RX_PORT_PPP4_IX,
1996 FW_STAT_RX_PORT_PPP5_IX,
1997 FW_STAT_RX_PORT_PPP6_IX,
1998 FW_STAT_RX_PORT_PPP7_IX,
1999 FW_STAT_RX_PORT_LESS_64B_IX
2002 struct fw_port_stats_cmd {
2003 __be32 op_to_portid;
2004 __be32 retval_len16;
2005 union fw_port_stats {
2006 struct fw_port_stats_ctl {
2018 struct fw_port_stats_all {
2027 __be64 tx_128b_255b;
2028 __be64 tx_256b_511b;
2029 __be64 tx_512b_1023b;
2030 __be64 tx_1024b_1518b;
2031 __be64 tx_1519b_max;
2047 __be64 rx_mtu_error;
2048 __be64 rx_mtu_crc_error;
2049 __be64 rx_crc_error;
2050 __be64 rx_len_error;
2051 __be64 rx_sym_error;
2054 __be64 rx_128b_255b;
2055 __be64 rx_256b_511b;
2056 __be64 rx_512b_1023b;
2057 __be64 rx_1024b_1518b;
2058 __be64 rx_1519b_max;
2075 struct fw_rss_ind_tbl_cmd {
2077 __be32 retval_len16;
2085 __be32 iq12_to_iq14;
2086 __be32 iq15_to_iq17;
2087 __be32 iq18_to_iq20;
2088 __be32 iq21_to_iq23;
2089 __be32 iq24_to_iq26;
2090 __be32 iq27_to_iq29;
2095 #define S_FW_RSS_IND_TBL_CMD_VIID 0
2096 #define M_FW_RSS_IND_TBL_CMD_VIID 0xfff
2097 #define V_FW_RSS_IND_TBL_CMD_VIID(x) ((x) << S_FW_RSS_IND_TBL_CMD_VIID)
2098 #define G_FW_RSS_IND_TBL_CMD_VIID(x) \
2099 (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID)
2101 #define S_FW_RSS_IND_TBL_CMD_IQ0 20
2102 #define M_FW_RSS_IND_TBL_CMD_IQ0 0x3ff
2103 #define V_FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ0)
2104 #define G_FW_RSS_IND_TBL_CMD_IQ0(x) \
2105 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0)
2107 #define S_FW_RSS_IND_TBL_CMD_IQ1 10
2108 #define M_FW_RSS_IND_TBL_CMD_IQ1 0x3ff
2109 #define V_FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ1)
2110 #define G_FW_RSS_IND_TBL_CMD_IQ1(x) \
2111 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1)
2113 #define S_FW_RSS_IND_TBL_CMD_IQ2 0
2114 #define M_FW_RSS_IND_TBL_CMD_IQ2 0x3ff
2115 #define V_FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ2)
2116 #define G_FW_RSS_IND_TBL_CMD_IQ2(x) \
2117 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2)
2119 struct fw_rss_glb_config_cmd {
2121 __be32 retval_len16;
2122 union fw_rss_glb_config {
2123 struct fw_rss_glb_config_manual {
2129 struct fw_rss_glb_config_basicvirtual {
2130 __be32 mode_keymode;
2131 __be32 synmapen_to_hashtoeplitz;
2138 #define S_FW_RSS_GLB_CONFIG_CMD_MODE 28
2139 #define M_FW_RSS_GLB_CONFIG_CMD_MODE 0xf
2140 #define G_FW_RSS_GLB_CONFIG_CMD_MODE(x) \
2141 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE)
2143 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1
2145 #define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8
2146 #define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \
2147 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN)
2148 #define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U)
2150 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7
2151 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \
2152 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6)
2153 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \
2154 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U)
2156 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6
2157 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \
2158 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6)
2159 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \
2160 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U)
2162 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5
2163 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \
2164 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4)
2165 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \
2166 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U)
2168 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4
2169 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \
2170 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4)
2171 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \
2172 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U)
2174 #define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3
2175 #define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \
2176 ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN)
2177 #define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U)
2179 #define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2
2180 #define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \
2181 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN)
2182 #define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U)
2184 #define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1
2185 #define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \
2186 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP)
2187 #define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \
2188 V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U)
2190 #define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0
2191 #define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \
2192 ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ)
2193 #define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \
2194 V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U)
2196 struct fw_rss_vi_config_cmd {
2198 __be32 retval_len16;
2199 union fw_rss_vi_config {
2200 struct fw_rss_vi_config_manual {
2205 struct fw_rss_vi_config_basicvirtual {
2207 __be32 defaultq_to_udpen;
2214 #define S_FW_RSS_VI_CONFIG_CMD_VIID 0
2215 #define M_FW_RSS_VI_CONFIG_CMD_VIID 0xfff
2216 #define V_FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_VIID)
2217 #define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \
2218 (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID)
2220 #define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16
2221 #define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff
2222 #define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \
2223 ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
2224 #define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \
2225 (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \
2226 M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
2228 #define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4
2229 #define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1
2230 #define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \
2231 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
2232 #define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \
2233 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \
2234 M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
2235 #define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \
2236 V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U)
2238 #define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3
2239 #define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1
2240 #define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \
2241 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
2242 #define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \
2243 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \
2244 M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
2245 #define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \
2246 V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U)
2248 #define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2
2249 #define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1
2250 #define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \
2251 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
2252 #define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \
2253 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \
2254 M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
2255 #define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \
2256 V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U)
2258 #define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1
2259 #define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1
2260 #define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \
2261 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
2262 #define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \
2263 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \
2264 M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
2265 #define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \
2266 V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U)
2268 #define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0
2269 #define M_FW_RSS_VI_CONFIG_CMD_UDPEN 0x1
2270 #define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN)
2271 #define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \
2272 (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN)
2273 #define F_FW_RSS_VI_CONFIG_CMD_UDPEN V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U)
2275 struct fw_clip_cmd {
2277 __be32 alloc_to_len16;
2283 #define S_FW_CLIP_CMD_ALLOC 31
2284 #define V_FW_CLIP_CMD_ALLOC(x) ((x) << S_FW_CLIP_CMD_ALLOC)
2285 #define F_FW_CLIP_CMD_ALLOC V_FW_CLIP_CMD_ALLOC(1U)
2287 #define S_FW_CLIP_CMD_FREE 30
2288 #define V_FW_CLIP_CMD_FREE(x) ((x) << S_FW_CLIP_CMD_FREE)
2289 #define F_FW_CLIP_CMD_FREE V_FW_CLIP_CMD_FREE(1U)
2291 /******************************************************************************
2292 * D E B U G C O M M A N D s
2293 ******************************************************/
2295 struct fw_debug_cmd {
2299 struct fw_debug_assert {
2304 __u8 filename_0_7[8];
2305 __u8 filename_8_15[8];
2308 struct fw_debug_prt {
2311 __be32 dprtstrparam0;
2312 __be32 dprtstrparam1;
2313 __be32 dprtstrparam2;
2314 __be32 dprtstrparam3;
2319 #define S_FW_DEBUG_CMD_TYPE 0
2320 #define M_FW_DEBUG_CMD_TYPE 0xff
2321 #define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE)
2322 #define G_FW_DEBUG_CMD_TYPE(x) \
2323 (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE)
2325 /******************************************************************************
2326 * P C I E F W R E G I S T E R
2327 **************************************/
2330 * Register definitions for the PCIE_FW register which the firmware uses
2331 * to retain status across RESETs. This register should be considered
2332 * as a READ-ONLY register for Host Software and only to be used to
2333 * track firmware initialization/error state, etc.
2335 #define S_PCIE_FW_ERR 31
2336 #define M_PCIE_FW_ERR 0x1
2337 #define V_PCIE_FW_ERR(x) ((x) << S_PCIE_FW_ERR)
2338 #define G_PCIE_FW_ERR(x) (((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR)
2339 #define F_PCIE_FW_ERR V_PCIE_FW_ERR(1U)
2341 #define S_PCIE_FW_INIT 30
2342 #define M_PCIE_FW_INIT 0x1
2343 #define V_PCIE_FW_INIT(x) ((x) << S_PCIE_FW_INIT)
2344 #define G_PCIE_FW_INIT(x) (((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT)
2345 #define F_PCIE_FW_INIT V_PCIE_FW_INIT(1U)
2347 #define S_PCIE_FW_HALT 29
2348 #define M_PCIE_FW_HALT 0x1
2349 #define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT)
2350 #define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT)
2351 #define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U)
2353 #define S_PCIE_FW_EVAL 24
2354 #define M_PCIE_FW_EVAL 0x7
2355 #define V_PCIE_FW_EVAL(x) ((x) << S_PCIE_FW_EVAL)
2356 #define G_PCIE_FW_EVAL(x) (((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL)
2358 #define S_PCIE_FW_MASTER_VLD 15
2359 #define M_PCIE_FW_MASTER_VLD 0x1
2360 #define V_PCIE_FW_MASTER_VLD(x) ((x) << S_PCIE_FW_MASTER_VLD)
2361 #define G_PCIE_FW_MASTER_VLD(x) \
2362 (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD)
2363 #define F_PCIE_FW_MASTER_VLD V_PCIE_FW_MASTER_VLD(1U)
2365 #define S_PCIE_FW_MASTER 12
2366 #define M_PCIE_FW_MASTER 0x7
2367 #define V_PCIE_FW_MASTER(x) ((x) << S_PCIE_FW_MASTER)
2368 #define G_PCIE_FW_MASTER(x) (((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER)
2370 /******************************************************************************
2371 * B I N A R Y H E A D E R F O R M A T
2372 **********************************************/
2375 * firmware binary header format
2379 __u8 chip; /* terminator chip family */
2380 __be16 len512; /* bin length in units of 512-bytes */
2381 __be32 fw_ver; /* firmware version */
2382 __be32 tp_microcode_ver; /* tcp processor microcode version */
2387 __u8 intfver_iscsipdu;
2389 __u8 intfver_fcoepdu;
2393 __u32 magic; /* runtime or bootstrap fw */
2395 __be32 reserved6[23];
2398 #define S_FW_HDR_FW_VER_MAJOR 24
2399 #define M_FW_HDR_FW_VER_MAJOR 0xff
2400 #define V_FW_HDR_FW_VER_MAJOR(x) \
2401 ((x) << S_FW_HDR_FW_VER_MAJOR)
2402 #define G_FW_HDR_FW_VER_MAJOR(x) \
2403 (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR)
2405 #define S_FW_HDR_FW_VER_MINOR 16
2406 #define M_FW_HDR_FW_VER_MINOR 0xff
2407 #define V_FW_HDR_FW_VER_MINOR(x) \
2408 ((x) << S_FW_HDR_FW_VER_MINOR)
2409 #define G_FW_HDR_FW_VER_MINOR(x) \
2410 (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR)
2412 #define S_FW_HDR_FW_VER_MICRO 8
2413 #define M_FW_HDR_FW_VER_MICRO 0xff
2414 #define V_FW_HDR_FW_VER_MICRO(x) \
2415 ((x) << S_FW_HDR_FW_VER_MICRO)
2416 #define G_FW_HDR_FW_VER_MICRO(x) \
2417 (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO)
2419 #define S_FW_HDR_FW_VER_BUILD 0
2420 #define M_FW_HDR_FW_VER_BUILD 0xff
2421 #define V_FW_HDR_FW_VER_BUILD(x) \
2422 ((x) << S_FW_HDR_FW_VER_BUILD)
2423 #define G_FW_HDR_FW_VER_BUILD(x) \
2424 (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD)
2426 #endif /* _T4FW_INTERFACE_H_ */