4 * Copyright(c) 2014-2017 Chelsio Communications.
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8 * modification, are permitted provided that the following conditions
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12 * notice, this list of conditions and the following disclaimer.
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15 * the documentation and/or other materials provided with the
17 * * Neither the name of Chelsio Communications nor the names of its
18 * contributors may be used to endorse or promote products derived
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
42 #include <netinet/in.h>
44 #include <rte_byteorder.h>
45 #include <rte_common.h>
46 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_bus_pci.h>
52 #include <rte_atomic.h>
53 #include <rte_branch_prediction.h>
54 #include <rte_memory.h>
55 #include <rte_tailq.h>
57 #include <rte_alarm.h>
58 #include <rte_ether.h>
59 #include <rte_ethdev_driver.h>
60 #include <rte_ethdev_pci.h>
61 #include <rte_malloc.h>
62 #include <rte_random.h>
66 #include "cxgbe_pfvf.h"
69 * Macros needed to support the PCI Device ID Table ...
71 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
72 static const struct rte_pci_id cxgb4_pci_tbl[] = {
73 #define CH_PCI_DEVICE_ID_FUNCTION 0x4
75 #define PCI_VENDOR_ID_CHELSIO 0x1425
77 #define CH_PCI_ID_TABLE_ENTRY(devid) \
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CHELSIO, (devid)) }
80 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
85 *... and the PCI ID Table itself ...
87 #include "t4_pci_id_tbl.h"
89 uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
92 struct sge_eth_txq *txq = (struct sge_eth_txq *)tx_queue;
93 uint16_t pkts_sent, pkts_remain;
94 uint16_t total_sent = 0;
97 CXGBE_DEBUG_TX(adapter, "%s: txq = %p; tx_pkts = %p; nb_pkts = %d\n",
98 __func__, txq, tx_pkts, nb_pkts);
100 t4_os_lock(&txq->txq_lock);
101 /* free up desc from already completed tx */
102 reclaim_completed_tx(&txq->q);
103 while (total_sent < nb_pkts) {
104 pkts_remain = nb_pkts - total_sent;
106 for (pkts_sent = 0; pkts_sent < pkts_remain; pkts_sent++) {
107 ret = t4_eth_xmit(txq, tx_pkts[total_sent + pkts_sent],
114 total_sent += pkts_sent;
115 /* reclaim as much as possible */
116 reclaim_completed_tx(&txq->q);
119 t4_os_unlock(&txq->txq_lock);
123 uint16_t cxgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
126 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)rx_queue;
127 unsigned int work_done;
129 CXGBE_DEBUG_RX(adapter, "%s: rxq->rspq.cntxt_id = %u; nb_pkts = %d\n",
130 __func__, rxq->rspq.cntxt_id, nb_pkts);
132 if (cxgbe_poll(&rxq->rspq, rx_pkts, (unsigned int)nb_pkts, &work_done))
133 dev_err(adapter, "error in cxgbe poll\n");
135 CXGBE_DEBUG_RX(adapter, "%s: work_done = %u\n", __func__, work_done);
139 void cxgbe_dev_info_get(struct rte_eth_dev *eth_dev,
140 struct rte_eth_dev_info *device_info)
142 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
143 struct adapter *adapter = pi->adapter;
144 int max_queues = adapter->sge.max_ethqsets / adapter->params.nports;
146 static const struct rte_eth_desc_lim cxgbe_desc_lim = {
147 .nb_max = CXGBE_MAX_RING_DESC_SIZE,
148 .nb_min = CXGBE_MIN_RING_DESC_SIZE,
152 device_info->pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
154 device_info->min_rx_bufsize = CXGBE_MIN_RX_BUFSIZE;
155 device_info->max_rx_pktlen = CXGBE_MAX_RX_PKTLEN;
156 device_info->max_rx_queues = max_queues;
157 device_info->max_tx_queues = max_queues;
158 device_info->max_mac_addrs = 1;
159 /* XXX: For now we support one MAC/port */
160 device_info->max_vfs = adapter->params.arch.vfcount;
161 device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */
163 device_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
164 DEV_RX_OFFLOAD_IPV4_CKSUM |
165 DEV_RX_OFFLOAD_UDP_CKSUM |
166 DEV_RX_OFFLOAD_TCP_CKSUM;
168 device_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
169 DEV_TX_OFFLOAD_IPV4_CKSUM |
170 DEV_TX_OFFLOAD_UDP_CKSUM |
171 DEV_TX_OFFLOAD_TCP_CKSUM |
172 DEV_TX_OFFLOAD_TCP_TSO;
174 device_info->reta_size = pi->rss_size;
175 device_info->hash_key_size = CXGBE_DEFAULT_RSS_KEY_LEN;
176 device_info->flow_type_rss_offloads = CXGBE_RSS_HF_ALL;
178 device_info->rx_desc_lim = cxgbe_desc_lim;
179 device_info->tx_desc_lim = cxgbe_desc_lim;
180 cxgbe_get_speed_caps(pi, &device_info->speed_capa);
183 void cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
185 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
186 struct adapter *adapter = pi->adapter;
188 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
189 1, -1, 1, -1, false);
192 void cxgbe_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
194 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
195 struct adapter *adapter = pi->adapter;
197 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
198 0, -1, 1, -1, false);
201 void cxgbe_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
203 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
204 struct adapter *adapter = pi->adapter;
206 /* TODO: address filters ?? */
208 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
209 -1, 1, 1, -1, false);
212 void cxgbe_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
214 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
215 struct adapter *adapter = pi->adapter;
217 /* TODO: address filters ?? */
219 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
220 -1, 0, 1, -1, false);
223 int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev,
224 __rte_unused int wait_to_complete)
226 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
227 struct adapter *adapter = pi->adapter;
228 struct sge *s = &adapter->sge;
229 struct rte_eth_link *old_link = ð_dev->data->dev_link;
230 unsigned int work_done, budget = 4;
232 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
233 if (old_link->link_status == pi->link_cfg.link_ok)
234 return -1; /* link not changed */
236 eth_dev->data->dev_link.link_status = pi->link_cfg.link_ok;
237 eth_dev->data->dev_link.link_duplex = ETH_LINK_FULL_DUPLEX;
238 eth_dev->data->dev_link.link_speed = pi->link_cfg.speed;
240 /* link has changed */
244 int cxgbe_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
246 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
247 struct adapter *adapter = pi->adapter;
248 struct rte_eth_dev_info dev_info;
250 uint16_t new_mtu = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
252 cxgbe_dev_info_get(eth_dev, &dev_info);
254 /* Must accommodate at least ETHER_MIN_MTU */
255 if ((new_mtu < ETHER_MIN_MTU) || (new_mtu > dev_info.max_rx_pktlen))
258 /* set to jumbo mode if needed */
259 if (new_mtu > ETHER_MAX_LEN)
260 eth_dev->data->dev_conf.rxmode.jumbo_frame = 1;
262 eth_dev->data->dev_conf.rxmode.jumbo_frame = 0;
264 err = t4_set_rxmode(adapter, adapter->mbox, pi->viid, new_mtu, -1, -1,
267 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_mtu;
275 void cxgbe_dev_close(struct rte_eth_dev *eth_dev)
277 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
278 struct adapter *adapter = pi->adapter;
283 if (!(adapter->flags & FULL_INIT_DONE))
289 * We clear queues only if both tx and rx path of the port
292 t4_sge_eth_clear_queues(pi);
294 /* See if all ports are down */
295 for_each_port(adapter, i) {
296 pi = adap2pinfo(adapter, i);
298 * Skip first port of the adapter since it will be closed
303 dev_down += (pi->eth_dev->data->dev_started == 0) ? 1 : 0;
306 /* If rest of the ports are stopped, then free up resources */
307 if (dev_down == (adapter->params.nports - 1))
308 cxgbe_close(adapter);
312 * It returns 0 on success.
314 int cxgbe_dev_start(struct rte_eth_dev *eth_dev)
316 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
317 struct adapter *adapter = pi->adapter;
323 * If we don't have a connection to the firmware there's nothing we
326 if (!(adapter->flags & FW_OK)) {
331 if (!(adapter->flags & FULL_INIT_DONE)) {
332 err = cxgbe_up(adapter);
337 cxgbe_enable_rx_queues(pi);
343 for (i = 0; i < pi->n_tx_qsets; i++) {
344 err = cxgbe_dev_tx_queue_start(eth_dev, i);
349 for (i = 0; i < pi->n_rx_qsets; i++) {
350 err = cxgbe_dev_rx_queue_start(eth_dev, i);
355 err = link_start(pi);
364 * Stop device: disable rx and tx functions to allow for reconfiguring.
366 void cxgbe_dev_stop(struct rte_eth_dev *eth_dev)
368 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
369 struct adapter *adapter = pi->adapter;
373 if (!(adapter->flags & FULL_INIT_DONE))
379 * We clear queues only if both tx and rx path of the port
382 t4_sge_eth_clear_queues(pi);
385 int cxgbe_dev_configure(struct rte_eth_dev *eth_dev)
387 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
388 struct adapter *adapter = pi->adapter;
393 if (!(adapter->flags & FW_QUEUE_BOUND)) {
394 err = setup_sge_fwevtq(adapter);
397 adapter->flags |= FW_QUEUE_BOUND;
400 err = cfg_queue_count(eth_dev);
407 int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
410 struct sge_eth_txq *txq = (struct sge_eth_txq *)
411 (eth_dev->data->tx_queues[tx_queue_id]);
413 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
415 ret = t4_sge_eth_txq_start(txq);
417 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
422 int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
425 struct sge_eth_txq *txq = (struct sge_eth_txq *)
426 (eth_dev->data->tx_queues[tx_queue_id]);
428 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
430 ret = t4_sge_eth_txq_stop(txq);
432 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
437 int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev,
438 uint16_t queue_idx, uint16_t nb_desc,
439 unsigned int socket_id,
440 const struct rte_eth_txconf *tx_conf)
442 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
443 struct adapter *adapter = pi->adapter;
444 struct sge *s = &adapter->sge;
445 struct sge_eth_txq *txq = &s->ethtxq[pi->first_qset + queue_idx];
447 unsigned int temp_nb_desc;
449 RTE_SET_USED(tx_conf);
451 dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n",
452 __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc,
453 socket_id, pi->first_qset);
455 /* Free up the existing queue */
456 if (eth_dev->data->tx_queues[queue_idx]) {
457 cxgbe_dev_tx_queue_release(eth_dev->data->tx_queues[queue_idx]);
458 eth_dev->data->tx_queues[queue_idx] = NULL;
461 eth_dev->data->tx_queues[queue_idx] = (void *)txq;
465 * nb_desc should be > 1023 and <= CXGBE_MAX_RING_DESC_SIZE
467 temp_nb_desc = nb_desc;
468 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
469 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
470 __func__, CXGBE_MIN_RING_DESC_SIZE,
471 CXGBE_DEFAULT_TX_DESC_SIZE);
472 temp_nb_desc = CXGBE_DEFAULT_TX_DESC_SIZE;
473 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
474 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
475 __func__, CXGBE_MIN_RING_DESC_SIZE,
476 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_TX_DESC_SIZE);
480 txq->q.size = temp_nb_desc;
482 err = t4_sge_alloc_eth_txq(adapter, txq, eth_dev, queue_idx,
483 s->fw_evtq.cntxt_id, socket_id);
485 dev_debug(adapter, "%s: txq->q.cntxt_id= %u txq->q.abs_id= %u err = %d\n",
486 __func__, txq->q.cntxt_id, txq->q.abs_id, err);
490 void cxgbe_dev_tx_queue_release(void *q)
492 struct sge_eth_txq *txq = (struct sge_eth_txq *)q;
495 struct port_info *pi = (struct port_info *)
496 (txq->eth_dev->data->dev_private);
497 struct adapter *adap = pi->adapter;
499 dev_debug(adapter, "%s: pi->port_id = %d; tx_queue_id = %d\n",
500 __func__, pi->port_id, txq->q.cntxt_id);
502 t4_sge_eth_txq_release(adap, txq);
506 int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
509 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
510 struct adapter *adap = pi->adapter;
513 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
514 __func__, pi->port_id, rx_queue_id);
516 q = eth_dev->data->rx_queues[rx_queue_id];
518 ret = t4_sge_eth_rxq_start(adap, q);
520 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
525 int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
528 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
529 struct adapter *adap = pi->adapter;
532 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
533 __func__, pi->port_id, rx_queue_id);
535 q = eth_dev->data->rx_queues[rx_queue_id];
536 ret = t4_sge_eth_rxq_stop(adap, q);
538 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
543 int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev,
544 uint16_t queue_idx, uint16_t nb_desc,
545 unsigned int socket_id,
546 const struct rte_eth_rxconf *rx_conf,
547 struct rte_mempool *mp)
549 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
550 struct adapter *adapter = pi->adapter;
551 struct sge *s = &adapter->sge;
552 struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_qset + queue_idx];
555 unsigned int temp_nb_desc;
556 struct rte_eth_dev_info dev_info;
557 unsigned int pkt_len = eth_dev->data->dev_conf.rxmode.max_rx_pkt_len;
559 RTE_SET_USED(rx_conf);
561 dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n",
562 __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc,
565 cxgbe_dev_info_get(eth_dev, &dev_info);
567 /* Must accommodate at least ETHER_MIN_MTU */
568 if ((pkt_len < dev_info.min_rx_bufsize) ||
569 (pkt_len > dev_info.max_rx_pktlen)) {
570 dev_err(adap, "%s: max pkt len must be > %d and <= %d\n",
571 __func__, dev_info.min_rx_bufsize,
572 dev_info.max_rx_pktlen);
576 /* Free up the existing queue */
577 if (eth_dev->data->rx_queues[queue_idx]) {
578 cxgbe_dev_rx_queue_release(eth_dev->data->rx_queues[queue_idx]);
579 eth_dev->data->rx_queues[queue_idx] = NULL;
582 eth_dev->data->rx_queues[queue_idx] = (void *)rxq;
586 * nb_desc should be > 0 and <= CXGBE_MAX_RING_DESC_SIZE
588 temp_nb_desc = nb_desc;
589 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
590 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
591 __func__, CXGBE_MIN_RING_DESC_SIZE,
592 CXGBE_DEFAULT_RX_DESC_SIZE);
593 temp_nb_desc = CXGBE_DEFAULT_RX_DESC_SIZE;
594 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
595 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
596 __func__, CXGBE_MIN_RING_DESC_SIZE,
597 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_RX_DESC_SIZE);
601 rxq->rspq.size = temp_nb_desc;
602 if ((&rxq->fl) != NULL)
603 rxq->fl.size = temp_nb_desc;
605 /* Set to jumbo mode if necessary */
606 if (pkt_len > ETHER_MAX_LEN)
607 eth_dev->data->dev_conf.rxmode.jumbo_frame = 1;
609 eth_dev->data->dev_conf.rxmode.jumbo_frame = 0;
611 err = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx,
612 &rxq->fl, t4_ethrx_handler,
614 t4_get_tp_ch_map(adapter, pi->tx_chan) : 0, mp,
615 queue_idx, socket_id);
617 dev_debug(adapter, "%s: err = %d; port_id = %d; cntxt_id = %u; abs_id = %u\n",
618 __func__, err, pi->port_id, rxq->rspq.cntxt_id,
623 void cxgbe_dev_rx_queue_release(void *q)
625 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)q;
626 struct sge_rspq *rq = &rxq->rspq;
629 struct port_info *pi = (struct port_info *)
630 (rq->eth_dev->data->dev_private);
631 struct adapter *adap = pi->adapter;
633 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
634 __func__, pi->port_id, rxq->rspq.cntxt_id);
636 t4_sge_eth_rxq_release(adap, rxq);
641 * Get port statistics.
643 static int cxgbe_dev_stats_get(struct rte_eth_dev *eth_dev,
644 struct rte_eth_stats *eth_stats)
646 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
647 struct adapter *adapter = pi->adapter;
648 struct sge *s = &adapter->sge;
649 struct port_stats ps;
652 cxgbe_stats_get(pi, &ps);
655 eth_stats->imissed = ps.rx_ovflow0 + ps.rx_ovflow1 +
656 ps.rx_ovflow2 + ps.rx_ovflow3 +
657 ps.rx_trunc0 + ps.rx_trunc1 +
658 ps.rx_trunc2 + ps.rx_trunc3;
659 eth_stats->ierrors = ps.rx_symbol_err + ps.rx_fcs_err +
660 ps.rx_jabber + ps.rx_too_long + ps.rx_runt +
664 eth_stats->opackets = ps.tx_frames;
665 eth_stats->obytes = ps.tx_octets;
666 eth_stats->oerrors = ps.tx_error_frames;
668 for (i = 0; i < pi->n_rx_qsets; i++) {
669 struct sge_eth_rxq *rxq =
670 &s->ethrxq[pi->first_qset + i];
672 eth_stats->q_ipackets[i] = rxq->stats.pkts;
673 eth_stats->q_ibytes[i] = rxq->stats.rx_bytes;
674 eth_stats->ipackets += eth_stats->q_ipackets[i];
675 eth_stats->ibytes += eth_stats->q_ibytes[i];
678 for (i = 0; i < pi->n_tx_qsets; i++) {
679 struct sge_eth_txq *txq =
680 &s->ethtxq[pi->first_qset + i];
682 eth_stats->q_opackets[i] = txq->stats.pkts;
683 eth_stats->q_obytes[i] = txq->stats.tx_bytes;
684 eth_stats->q_errors[i] = txq->stats.mapping_err;
690 * Reset port statistics.
692 static void cxgbe_dev_stats_reset(struct rte_eth_dev *eth_dev)
694 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
695 struct adapter *adapter = pi->adapter;
696 struct sge *s = &adapter->sge;
699 cxgbe_stats_reset(pi);
700 for (i = 0; i < pi->n_rx_qsets; i++) {
701 struct sge_eth_rxq *rxq =
702 &s->ethrxq[pi->first_qset + i];
705 rxq->stats.rx_bytes = 0;
707 for (i = 0; i < pi->n_tx_qsets; i++) {
708 struct sge_eth_txq *txq =
709 &s->ethtxq[pi->first_qset + i];
712 txq->stats.tx_bytes = 0;
713 txq->stats.mapping_err = 0;
717 static int cxgbe_flow_ctrl_get(struct rte_eth_dev *eth_dev,
718 struct rte_eth_fc_conf *fc_conf)
720 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
721 struct link_config *lc = &pi->link_cfg;
722 int rx_pause, tx_pause;
724 fc_conf->autoneg = lc->fc & PAUSE_AUTONEG;
725 rx_pause = lc->fc & PAUSE_RX;
726 tx_pause = lc->fc & PAUSE_TX;
728 if (rx_pause && tx_pause)
729 fc_conf->mode = RTE_FC_FULL;
731 fc_conf->mode = RTE_FC_RX_PAUSE;
733 fc_conf->mode = RTE_FC_TX_PAUSE;
735 fc_conf->mode = RTE_FC_NONE;
739 static int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev,
740 struct rte_eth_fc_conf *fc_conf)
742 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
743 struct adapter *adapter = pi->adapter;
744 struct link_config *lc = &pi->link_cfg;
746 if (lc->pcaps & FW_PORT_CAP32_ANEG) {
747 if (fc_conf->autoneg)
748 lc->requested_fc |= PAUSE_AUTONEG;
750 lc->requested_fc &= ~PAUSE_AUTONEG;
753 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
754 (fc_conf->mode & RTE_FC_RX_PAUSE))
755 lc->requested_fc |= PAUSE_RX;
757 lc->requested_fc &= ~PAUSE_RX;
759 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
760 (fc_conf->mode & RTE_FC_TX_PAUSE))
761 lc->requested_fc |= PAUSE_TX;
763 lc->requested_fc &= ~PAUSE_TX;
765 return t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,
770 cxgbe_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
772 static const uint32_t ptypes[] = {
778 if (eth_dev->rx_pkt_burst == cxgbe_recv_pkts)
783 /* Update RSS hash configuration
785 static int cxgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
786 struct rte_eth_rss_conf *rss_conf)
788 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
789 struct adapter *adapter = pi->adapter;
792 err = cxgbe_write_rss_conf(pi, rss_conf->rss_hf);
796 pi->rss_hf = rss_conf->rss_hf;
798 if (rss_conf->rss_key) {
799 u32 key[10], mod_key[10];
802 memcpy(key, rss_conf->rss_key, CXGBE_DEFAULT_RSS_KEY_LEN);
804 for (i = 9, j = 0; i >= 0; i--, j++)
805 mod_key[j] = cpu_to_be32(key[i]);
807 t4_write_rss_key(adapter, mod_key, -1);
813 /* Get RSS hash configuration
815 static int cxgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
816 struct rte_eth_rss_conf *rss_conf)
818 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
819 struct adapter *adapter = pi->adapter;
824 err = t4_read_config_vi_rss(adapter, adapter->mbox, pi->viid,
830 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) {
831 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
832 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
833 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
836 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
837 rss_hf |= ETH_RSS_IPV6;
839 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) {
840 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
841 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
842 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
845 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
846 rss_hf |= ETH_RSS_IPV4;
848 rss_conf->rss_hf = rss_hf;
850 if (rss_conf->rss_key) {
851 u32 key[10], mod_key[10];
854 t4_read_rss_key(adapter, key);
856 for (i = 9, j = 0; i >= 0; i--, j++)
857 mod_key[j] = be32_to_cpu(key[i]);
859 memcpy(rss_conf->rss_key, mod_key, CXGBE_DEFAULT_RSS_KEY_LEN);
865 static int cxgbe_get_eeprom_length(struct rte_eth_dev *dev)
872 * eeprom_ptov - translate a physical EEPROM address to virtual
873 * @phys_addr: the physical EEPROM address
874 * @fn: the PCI function number
875 * @sz: size of function-specific area
877 * Translate a physical EEPROM address to virtual. The first 1K is
878 * accessed through virtual addresses starting at 31K, the rest is
879 * accessed through virtual addresses starting at 0.
881 * The mapping is as follows:
882 * [0..1K) -> [31K..32K)
883 * [1K..1K+A) -> [31K-A..31K)
884 * [1K+A..ES) -> [0..ES-A-1K)
886 * where A = @fn * @sz, and ES = EEPROM size.
888 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
891 if (phys_addr < 1024)
892 return phys_addr + (31 << 10);
893 if (phys_addr < 1024 + fn)
894 return fn + phys_addr - 1024;
895 if (phys_addr < EEPROMSIZE)
896 return phys_addr - 1024 - fn;
897 if (phys_addr < EEPROMVSIZE)
898 return phys_addr - 1024;
902 /* The next two routines implement eeprom read/write from physical addresses.
904 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v)
906 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
909 vaddr = t4_seeprom_read(adap, vaddr, v);
910 return vaddr < 0 ? vaddr : 0;
913 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v)
915 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
918 vaddr = t4_seeprom_write(adap, vaddr, v);
919 return vaddr < 0 ? vaddr : 0;
922 #define EEPROM_MAGIC 0x38E2F10C
924 static int cxgbe_get_eeprom(struct rte_eth_dev *dev,
925 struct rte_dev_eeprom_info *e)
927 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
928 struct adapter *adapter = pi->adapter;
930 u8 *buf = rte_zmalloc(NULL, EEPROMSIZE, 0);
935 e->magic = EEPROM_MAGIC;
936 for (i = e->offset & ~3; !err && i < e->offset + e->length; i += 4)
937 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]);
940 rte_memcpy(e->data, buf + e->offset, e->length);
945 static int cxgbe_set_eeprom(struct rte_eth_dev *dev,
946 struct rte_dev_eeprom_info *eeprom)
948 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
949 struct adapter *adapter = pi->adapter;
952 u32 aligned_offset, aligned_len, *p;
954 if (eeprom->magic != EEPROM_MAGIC)
957 aligned_offset = eeprom->offset & ~3;
958 aligned_len = (eeprom->length + (eeprom->offset & 3) + 3) & ~3;
960 if (adapter->pf > 0) {
961 u32 start = 1024 + adapter->pf * EEPROMPFSIZE;
963 if (aligned_offset < start ||
964 aligned_offset + aligned_len > start + EEPROMPFSIZE)
968 if (aligned_offset != eeprom->offset || aligned_len != eeprom->length) {
969 /* RMW possibly needed for first or last words.
971 buf = rte_zmalloc(NULL, aligned_len, 0);
974 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf);
975 if (!err && aligned_len > 4)
976 err = eeprom_rd_phys(adapter,
977 aligned_offset + aligned_len - 4,
978 (u32 *)&buf[aligned_len - 4]);
981 rte_memcpy(buf + (eeprom->offset & 3), eeprom->data,
987 err = t4_seeprom_wp(adapter, false);
991 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
992 err = eeprom_wr_phys(adapter, aligned_offset, *p);
997 err = t4_seeprom_wp(adapter, true);
999 if (buf != eeprom->data)
1004 static int cxgbe_get_regs_len(struct rte_eth_dev *eth_dev)
1006 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
1007 struct adapter *adapter = pi->adapter;
1009 return t4_get_regs_len(adapter) / sizeof(uint32_t);
1012 static int cxgbe_get_regs(struct rte_eth_dev *eth_dev,
1013 struct rte_dev_reg_info *regs)
1015 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
1016 struct adapter *adapter = pi->adapter;
1018 regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) |
1019 (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) |
1022 if (regs->data == NULL) {
1023 regs->length = cxgbe_get_regs_len(eth_dev);
1024 regs->width = sizeof(uint32_t);
1029 t4_get_regs(adapter, regs->data, (regs->length * sizeof(uint32_t)));
1034 void cxgbe_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
1036 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
1037 struct adapter *adapter = pi->adapter;
1040 ret = t4_change_mac(adapter, adapter->mbox, pi->viid,
1041 pi->xact_addr_filt, (u8 *)addr, true, true);
1043 dev_err(adapter, "failed to set mac addr; err = %d\n",
1047 pi->xact_addr_filt = ret;
1050 static const struct eth_dev_ops cxgbe_eth_dev_ops = {
1051 .dev_start = cxgbe_dev_start,
1052 .dev_stop = cxgbe_dev_stop,
1053 .dev_close = cxgbe_dev_close,
1054 .promiscuous_enable = cxgbe_dev_promiscuous_enable,
1055 .promiscuous_disable = cxgbe_dev_promiscuous_disable,
1056 .allmulticast_enable = cxgbe_dev_allmulticast_enable,
1057 .allmulticast_disable = cxgbe_dev_allmulticast_disable,
1058 .dev_configure = cxgbe_dev_configure,
1059 .dev_infos_get = cxgbe_dev_info_get,
1060 .dev_supported_ptypes_get = cxgbe_dev_supported_ptypes_get,
1061 .link_update = cxgbe_dev_link_update,
1062 .mtu_set = cxgbe_dev_mtu_set,
1063 .tx_queue_setup = cxgbe_dev_tx_queue_setup,
1064 .tx_queue_start = cxgbe_dev_tx_queue_start,
1065 .tx_queue_stop = cxgbe_dev_tx_queue_stop,
1066 .tx_queue_release = cxgbe_dev_tx_queue_release,
1067 .rx_queue_setup = cxgbe_dev_rx_queue_setup,
1068 .rx_queue_start = cxgbe_dev_rx_queue_start,
1069 .rx_queue_stop = cxgbe_dev_rx_queue_stop,
1070 .rx_queue_release = cxgbe_dev_rx_queue_release,
1071 .stats_get = cxgbe_dev_stats_get,
1072 .stats_reset = cxgbe_dev_stats_reset,
1073 .flow_ctrl_get = cxgbe_flow_ctrl_get,
1074 .flow_ctrl_set = cxgbe_flow_ctrl_set,
1075 .get_eeprom_length = cxgbe_get_eeprom_length,
1076 .get_eeprom = cxgbe_get_eeprom,
1077 .set_eeprom = cxgbe_set_eeprom,
1078 .get_reg = cxgbe_get_regs,
1079 .rss_hash_update = cxgbe_dev_rss_hash_update,
1080 .rss_hash_conf_get = cxgbe_dev_rss_hash_conf_get,
1081 .mac_addr_set = cxgbe_mac_addr_set,
1086 * It returns 0 on success.
1088 static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev)
1090 struct rte_pci_device *pci_dev;
1091 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
1092 struct adapter *adapter = NULL;
1093 char name[RTE_ETH_NAME_MAX_LEN];
1098 eth_dev->dev_ops = &cxgbe_eth_dev_ops;
1099 eth_dev->rx_pkt_burst = &cxgbe_recv_pkts;
1100 eth_dev->tx_pkt_burst = &cxgbe_xmit_pkts;
1101 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1103 /* for secondary processes, we attach to ethdevs allocated by primary
1104 * and do minimal initialization.
1106 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1109 for (i = 1; i < MAX_NPORTS; i++) {
1110 struct rte_eth_dev *rest_eth_dev;
1111 char namei[RTE_ETH_NAME_MAX_LEN];
1113 snprintf(namei, sizeof(namei), "%s_%d",
1114 pci_dev->device.name, i);
1115 rest_eth_dev = rte_eth_dev_attach_secondary(namei);
1117 rest_eth_dev->device = &pci_dev->device;
1118 rest_eth_dev->dev_ops =
1120 rest_eth_dev->rx_pkt_burst =
1121 eth_dev->rx_pkt_burst;
1122 rest_eth_dev->tx_pkt_burst =
1123 eth_dev->tx_pkt_burst;
1129 snprintf(name, sizeof(name), "cxgbeadapter%d", eth_dev->data->port_id);
1130 adapter = rte_zmalloc(name, sizeof(*adapter), 0);
1134 adapter->use_unpacked_mode = 1;
1135 adapter->regs = (void *)pci_dev->mem_resource[0].addr;
1136 if (!adapter->regs) {
1137 dev_err(adapter, "%s: cannot map device registers\n", __func__);
1139 goto out_free_adapter;
1141 adapter->pdev = pci_dev;
1142 adapter->eth_dev = eth_dev;
1143 pi->adapter = adapter;
1145 err = cxgbe_probe(adapter);
1147 dev_err(adapter, "%s: cxgbe probe failed with err %d\n",
1149 goto out_free_adapter;
1159 static int eth_cxgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1160 struct rte_pci_device *pci_dev)
1162 return rte_eth_dev_pci_generic_probe(pci_dev,
1163 sizeof(struct port_info), eth_cxgbe_dev_init);
1166 static int eth_cxgbe_pci_remove(struct rte_pci_device *pci_dev)
1168 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
1171 static struct rte_pci_driver rte_cxgbe_pmd = {
1172 .id_table = cxgb4_pci_tbl,
1173 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1174 .probe = eth_cxgbe_pci_probe,
1175 .remove = eth_cxgbe_pci_remove,
1178 RTE_PMD_REGISTER_PCI(net_cxgbe, rte_cxgbe_pmd);
1179 RTE_PMD_REGISTER_PCI_TABLE(net_cxgbe, cxgb4_pci_tbl);
1180 RTE_PMD_REGISTER_KMOD_DEP(net_cxgbe, "* igb_uio | uio_pci_generic | vfio-pci");