2610d62efcaaff3ac804899972c76aae0fadcd26
[dpdk.git] / drivers / net / cxgbe / cxgbe_ethdev.c
1 /*-
2  *   BSD LICENSE
3  *
4  *   Copyright(c) 2014-2017 Chelsio Communications.
5  *   All rights reserved.
6  *
7  *   Redistribution and use in source and binary forms, with or without
8  *   modification, are permitted provided that the following conditions
9  *   are met:
10  *
11  *     * Redistributions of source code must retain the above copyright
12  *       notice, this list of conditions and the following disclaimer.
13  *     * Redistributions in binary form must reproduce the above copyright
14  *       notice, this list of conditions and the following disclaimer in
15  *       the documentation and/or other materials provided with the
16  *       distribution.
17  *     * Neither the name of Chelsio Communications nor the names of its
18  *       contributors may be used to endorse or promote products derived
19  *       from this software without specific prior written permission.
20  *
21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32  */
33
34 #include <sys/queue.h>
35 #include <stdio.h>
36 #include <errno.h>
37 #include <stdint.h>
38 #include <string.h>
39 #include <unistd.h>
40 #include <stdarg.h>
41 #include <inttypes.h>
42 #include <netinet/in.h>
43
44 #include <rte_byteorder.h>
45 #include <rte_common.h>
46 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
48 #include <rte_log.h>
49 #include <rte_debug.h>
50 #include <rte_pci.h>
51 #include <rte_bus_pci.h>
52 #include <rte_atomic.h>
53 #include <rte_branch_prediction.h>
54 #include <rte_memory.h>
55 #include <rte_tailq.h>
56 #include <rte_eal.h>
57 #include <rte_alarm.h>
58 #include <rte_ether.h>
59 #include <rte_ethdev_driver.h>
60 #include <rte_ethdev_pci.h>
61 #include <rte_malloc.h>
62 #include <rte_random.h>
63 #include <rte_dev.h>
64
65 #include "cxgbe.h"
66 #include "cxgbe_pfvf.h"
67
68 /*
69  * Macros needed to support the PCI Device ID Table ...
70  */
71 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
72         static const struct rte_pci_id cxgb4_pci_tbl[] = {
73 #define CH_PCI_DEVICE_ID_FUNCTION 0x4
74
75 #define PCI_VENDOR_ID_CHELSIO 0x1425
76
77 #define CH_PCI_ID_TABLE_ENTRY(devid) \
78                 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CHELSIO, (devid)) }
79
80 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
81                 { .vendor_id = 0, } \
82         }
83
84 /*
85  *... and the PCI ID Table itself ...
86  */
87 #include "t4_pci_id_tbl.h"
88
89 uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
90                          uint16_t nb_pkts)
91 {
92         struct sge_eth_txq *txq = (struct sge_eth_txq *)tx_queue;
93         uint16_t pkts_sent, pkts_remain;
94         uint16_t total_sent = 0;
95         int ret = 0;
96
97         CXGBE_DEBUG_TX(adapter, "%s: txq = %p; tx_pkts = %p; nb_pkts = %d\n",
98                        __func__, txq, tx_pkts, nb_pkts);
99
100         t4_os_lock(&txq->txq_lock);
101         /* free up desc from already completed tx */
102         reclaim_completed_tx(&txq->q);
103         while (total_sent < nb_pkts) {
104                 pkts_remain = nb_pkts - total_sent;
105
106                 for (pkts_sent = 0; pkts_sent < pkts_remain; pkts_sent++) {
107                         ret = t4_eth_xmit(txq, tx_pkts[total_sent + pkts_sent],
108                                           nb_pkts);
109                         if (ret < 0)
110                                 break;
111                 }
112                 if (!pkts_sent)
113                         break;
114                 total_sent += pkts_sent;
115                 /* reclaim as much as possible */
116                 reclaim_completed_tx(&txq->q);
117         }
118
119         t4_os_unlock(&txq->txq_lock);
120         return total_sent;
121 }
122
123 uint16_t cxgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
124                          uint16_t nb_pkts)
125 {
126         struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)rx_queue;
127         unsigned int work_done;
128
129         CXGBE_DEBUG_RX(adapter, "%s: rxq->rspq.cntxt_id = %u; nb_pkts = %d\n",
130                        __func__, rxq->rspq.cntxt_id, nb_pkts);
131
132         if (cxgbe_poll(&rxq->rspq, rx_pkts, (unsigned int)nb_pkts, &work_done))
133                 dev_err(adapter, "error in cxgbe poll\n");
134
135         CXGBE_DEBUG_RX(adapter, "%s: work_done = %u\n", __func__, work_done);
136         return work_done;
137 }
138
139 void cxgbe_dev_info_get(struct rte_eth_dev *eth_dev,
140                         struct rte_eth_dev_info *device_info)
141 {
142         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
143         struct adapter *adapter = pi->adapter;
144         int max_queues = adapter->sge.max_ethqsets / adapter->params.nports;
145
146         static const struct rte_eth_desc_lim cxgbe_desc_lim = {
147                 .nb_max = CXGBE_MAX_RING_DESC_SIZE,
148                 .nb_min = CXGBE_MIN_RING_DESC_SIZE,
149                 .nb_align = 1,
150         };
151
152         device_info->pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
153
154         device_info->min_rx_bufsize = CXGBE_MIN_RX_BUFSIZE;
155         device_info->max_rx_pktlen = CXGBE_MAX_RX_PKTLEN;
156         device_info->max_rx_queues = max_queues;
157         device_info->max_tx_queues = max_queues;
158         device_info->max_mac_addrs = 1;
159         /* XXX: For now we support one MAC/port */
160         device_info->max_vfs = adapter->params.arch.vfcount;
161         device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */
162
163         device_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
164                                        DEV_RX_OFFLOAD_IPV4_CKSUM |
165                                        DEV_RX_OFFLOAD_UDP_CKSUM |
166                                        DEV_RX_OFFLOAD_TCP_CKSUM;
167
168         device_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
169                                        DEV_TX_OFFLOAD_IPV4_CKSUM |
170                                        DEV_TX_OFFLOAD_UDP_CKSUM |
171                                        DEV_TX_OFFLOAD_TCP_CKSUM |
172                                        DEV_TX_OFFLOAD_TCP_TSO;
173
174         device_info->reta_size = pi->rss_size;
175         device_info->hash_key_size = CXGBE_DEFAULT_RSS_KEY_LEN;
176         device_info->flow_type_rss_offloads = CXGBE_RSS_HF_ALL;
177
178         device_info->rx_desc_lim = cxgbe_desc_lim;
179         device_info->tx_desc_lim = cxgbe_desc_lim;
180         cxgbe_get_speed_caps(pi, &device_info->speed_capa);
181 }
182
183 void cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
184 {
185         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
186         struct adapter *adapter = pi->adapter;
187
188         t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
189                       1, -1, 1, -1, false);
190 }
191
192 void cxgbe_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
193 {
194         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
195         struct adapter *adapter = pi->adapter;
196
197         t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
198                       0, -1, 1, -1, false);
199 }
200
201 void cxgbe_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
202 {
203         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
204         struct adapter *adapter = pi->adapter;
205
206         /* TODO: address filters ?? */
207
208         t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
209                       -1, 1, 1, -1, false);
210 }
211
212 void cxgbe_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
213 {
214         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
215         struct adapter *adapter = pi->adapter;
216
217         /* TODO: address filters ?? */
218
219         t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
220                       -1, 0, 1, -1, false);
221 }
222
223 int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev,
224                           __rte_unused int wait_to_complete)
225 {
226         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
227         struct adapter *adapter = pi->adapter;
228         struct sge *s = &adapter->sge;
229         struct rte_eth_link *old_link = &eth_dev->data->dev_link;
230         unsigned int work_done, budget = 4;
231
232         cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
233         if (old_link->link_status == pi->link_cfg.link_ok)
234                 return -1;  /* link not changed */
235
236         eth_dev->data->dev_link.link_status = pi->link_cfg.link_ok;
237         eth_dev->data->dev_link.link_duplex = ETH_LINK_FULL_DUPLEX;
238         eth_dev->data->dev_link.link_speed = pi->link_cfg.speed;
239
240         /* link has changed */
241         return 0;
242 }
243
244 int cxgbe_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
245 {
246         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
247         struct adapter *adapter = pi->adapter;
248         struct rte_eth_dev_info dev_info;
249         int err;
250         uint16_t new_mtu = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
251
252         cxgbe_dev_info_get(eth_dev, &dev_info);
253
254         /* Must accommodate at least ETHER_MIN_MTU */
255         if ((new_mtu < ETHER_MIN_MTU) || (new_mtu > dev_info.max_rx_pktlen))
256                 return -EINVAL;
257
258         /* set to jumbo mode if needed */
259         if (new_mtu > ETHER_MAX_LEN)
260                 eth_dev->data->dev_conf.rxmode.jumbo_frame = 1;
261         else
262                 eth_dev->data->dev_conf.rxmode.jumbo_frame = 0;
263
264         err = t4_set_rxmode(adapter, adapter->mbox, pi->viid, new_mtu, -1, -1,
265                             -1, -1, true);
266         if (!err)
267                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_mtu;
268
269         return err;
270 }
271
272 /*
273  * Stop device.
274  */
275 void cxgbe_dev_close(struct rte_eth_dev *eth_dev)
276 {
277         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
278         struct adapter *adapter = pi->adapter;
279         int i, dev_down = 0;
280
281         CXGBE_FUNC_TRACE();
282
283         if (!(adapter->flags & FULL_INIT_DONE))
284                 return;
285
286         cxgbe_down(pi);
287
288         /*
289          *  We clear queues only if both tx and rx path of the port
290          *  have been disabled
291          */
292         t4_sge_eth_clear_queues(pi);
293
294         /*  See if all ports are down */
295         for_each_port(adapter, i) {
296                 pi = adap2pinfo(adapter, i);
297                 /*
298                  * Skip first port of the adapter since it will be closed
299                  * by DPDK
300                  */
301                 if (i == 0)
302                         continue;
303                 dev_down += (pi->eth_dev->data->dev_started == 0) ? 1 : 0;
304         }
305
306         /* If rest of the ports are stopped, then free up resources */
307         if (dev_down == (adapter->params.nports - 1))
308                 cxgbe_close(adapter);
309 }
310
311 /* Start the device.
312  * It returns 0 on success.
313  */
314 int cxgbe_dev_start(struct rte_eth_dev *eth_dev)
315 {
316         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
317         struct adapter *adapter = pi->adapter;
318         int err = 0, i;
319
320         CXGBE_FUNC_TRACE();
321
322         /*
323          * If we don't have a connection to the firmware there's nothing we
324          * can do.
325          */
326         if (!(adapter->flags & FW_OK)) {
327                 err = -ENXIO;
328                 goto out;
329         }
330
331         if (!(adapter->flags & FULL_INIT_DONE)) {
332                 err = cxgbe_up(adapter);
333                 if (err < 0)
334                         goto out;
335         }
336
337         cxgbe_enable_rx_queues(pi);
338
339         err = setup_rss(pi);
340         if (err)
341                 goto out;
342
343         for (i = 0; i < pi->n_tx_qsets; i++) {
344                 err = cxgbe_dev_tx_queue_start(eth_dev, i);
345                 if (err)
346                         goto out;
347         }
348
349         for (i = 0; i < pi->n_rx_qsets; i++) {
350                 err = cxgbe_dev_rx_queue_start(eth_dev, i);
351                 if (err)
352                         goto out;
353         }
354
355         err = link_start(pi);
356         if (err)
357                 goto out;
358
359 out:
360         return err;
361 }
362
363 /*
364  * Stop device: disable rx and tx functions to allow for reconfiguring.
365  */
366 void cxgbe_dev_stop(struct rte_eth_dev *eth_dev)
367 {
368         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
369         struct adapter *adapter = pi->adapter;
370
371         CXGBE_FUNC_TRACE();
372
373         if (!(adapter->flags & FULL_INIT_DONE))
374                 return;
375
376         cxgbe_down(pi);
377
378         /*
379          *  We clear queues only if both tx and rx path of the port
380          *  have been disabled
381          */
382         t4_sge_eth_clear_queues(pi);
383 }
384
385 int cxgbe_dev_configure(struct rte_eth_dev *eth_dev)
386 {
387         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
388         struct adapter *adapter = pi->adapter;
389         int err;
390
391         CXGBE_FUNC_TRACE();
392
393         if (!(adapter->flags & FW_QUEUE_BOUND)) {
394                 err = setup_sge_fwevtq(adapter);
395                 if (err)
396                         return err;
397                 adapter->flags |= FW_QUEUE_BOUND;
398         }
399
400         err = cfg_queue_count(eth_dev);
401         if (err)
402                 return err;
403
404         return 0;
405 }
406
407 int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
408 {
409         int ret;
410         struct sge_eth_txq *txq = (struct sge_eth_txq *)
411                                   (eth_dev->data->tx_queues[tx_queue_id]);
412
413         dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
414
415         ret = t4_sge_eth_txq_start(txq);
416         if (ret == 0)
417                 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
418
419         return ret;
420 }
421
422 int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
423 {
424         int ret;
425         struct sge_eth_txq *txq = (struct sge_eth_txq *)
426                                   (eth_dev->data->tx_queues[tx_queue_id]);
427
428         dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
429
430         ret = t4_sge_eth_txq_stop(txq);
431         if (ret == 0)
432                 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
433
434         return ret;
435 }
436
437 int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev,
438                              uint16_t queue_idx, uint16_t nb_desc,
439                              unsigned int socket_id,
440                              const struct rte_eth_txconf *tx_conf)
441 {
442         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
443         struct adapter *adapter = pi->adapter;
444         struct sge *s = &adapter->sge;
445         struct sge_eth_txq *txq = &s->ethtxq[pi->first_qset + queue_idx];
446         int err = 0;
447         unsigned int temp_nb_desc;
448
449         RTE_SET_USED(tx_conf);
450
451         dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n",
452                   __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc,
453                   socket_id, pi->first_qset);
454
455         /*  Free up the existing queue  */
456         if (eth_dev->data->tx_queues[queue_idx]) {
457                 cxgbe_dev_tx_queue_release(eth_dev->data->tx_queues[queue_idx]);
458                 eth_dev->data->tx_queues[queue_idx] = NULL;
459         }
460
461         eth_dev->data->tx_queues[queue_idx] = (void *)txq;
462
463         /* Sanity Checking
464          *
465          * nb_desc should be > 1023 and <= CXGBE_MAX_RING_DESC_SIZE
466          */
467         temp_nb_desc = nb_desc;
468         if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
469                 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
470                          __func__, CXGBE_MIN_RING_DESC_SIZE,
471                          CXGBE_DEFAULT_TX_DESC_SIZE);
472                 temp_nb_desc = CXGBE_DEFAULT_TX_DESC_SIZE;
473         } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
474                 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
475                         __func__, CXGBE_MIN_RING_DESC_SIZE,
476                         CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_TX_DESC_SIZE);
477                 return -(EINVAL);
478         }
479
480         txq->q.size = temp_nb_desc;
481
482         err = t4_sge_alloc_eth_txq(adapter, txq, eth_dev, queue_idx,
483                                    s->fw_evtq.cntxt_id, socket_id);
484
485         dev_debug(adapter, "%s: txq->q.cntxt_id= %u txq->q.abs_id= %u err = %d\n",
486                   __func__, txq->q.cntxt_id, txq->q.abs_id, err);
487         return err;
488 }
489
490 void cxgbe_dev_tx_queue_release(void *q)
491 {
492         struct sge_eth_txq *txq = (struct sge_eth_txq *)q;
493
494         if (txq) {
495                 struct port_info *pi = (struct port_info *)
496                                        (txq->eth_dev->data->dev_private);
497                 struct adapter *adap = pi->adapter;
498
499                 dev_debug(adapter, "%s: pi->port_id = %d; tx_queue_id = %d\n",
500                           __func__, pi->port_id, txq->q.cntxt_id);
501
502                 t4_sge_eth_txq_release(adap, txq);
503         }
504 }
505
506 int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
507 {
508         int ret;
509         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
510         struct adapter *adap = pi->adapter;
511         struct sge_rspq *q;
512
513         dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
514                   __func__, pi->port_id, rx_queue_id);
515
516         q = eth_dev->data->rx_queues[rx_queue_id];
517
518         ret = t4_sge_eth_rxq_start(adap, q);
519         if (ret == 0)
520                 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
521
522         return ret;
523 }
524
525 int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
526 {
527         int ret;
528         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
529         struct adapter *adap = pi->adapter;
530         struct sge_rspq *q;
531
532         dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
533                   __func__, pi->port_id, rx_queue_id);
534
535         q = eth_dev->data->rx_queues[rx_queue_id];
536         ret = t4_sge_eth_rxq_stop(adap, q);
537         if (ret == 0)
538                 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
539
540         return ret;
541 }
542
543 int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev,
544                              uint16_t queue_idx, uint16_t nb_desc,
545                              unsigned int socket_id,
546                              const struct rte_eth_rxconf *rx_conf,
547                              struct rte_mempool *mp)
548 {
549         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
550         struct adapter *adapter = pi->adapter;
551         struct sge *s = &adapter->sge;
552         struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_qset + queue_idx];
553         int err = 0;
554         int msi_idx = 0;
555         unsigned int temp_nb_desc;
556         struct rte_eth_dev_info dev_info;
557         unsigned int pkt_len = eth_dev->data->dev_conf.rxmode.max_rx_pkt_len;
558
559         RTE_SET_USED(rx_conf);
560
561         dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n",
562                   __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc,
563                   socket_id, mp);
564
565         cxgbe_dev_info_get(eth_dev, &dev_info);
566
567         /* Must accommodate at least ETHER_MIN_MTU */
568         if ((pkt_len < dev_info.min_rx_bufsize) ||
569             (pkt_len > dev_info.max_rx_pktlen)) {
570                 dev_err(adap, "%s: max pkt len must be > %d and <= %d\n",
571                         __func__, dev_info.min_rx_bufsize,
572                         dev_info.max_rx_pktlen);
573                 return -EINVAL;
574         }
575
576         /*  Free up the existing queue  */
577         if (eth_dev->data->rx_queues[queue_idx]) {
578                 cxgbe_dev_rx_queue_release(eth_dev->data->rx_queues[queue_idx]);
579                 eth_dev->data->rx_queues[queue_idx] = NULL;
580         }
581
582         eth_dev->data->rx_queues[queue_idx] = (void *)rxq;
583
584         /* Sanity Checking
585          *
586          * nb_desc should be > 0 and <= CXGBE_MAX_RING_DESC_SIZE
587          */
588         temp_nb_desc = nb_desc;
589         if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
590                 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
591                          __func__, CXGBE_MIN_RING_DESC_SIZE,
592                          CXGBE_DEFAULT_RX_DESC_SIZE);
593                 temp_nb_desc = CXGBE_DEFAULT_RX_DESC_SIZE;
594         } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
595                 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
596                         __func__, CXGBE_MIN_RING_DESC_SIZE,
597                         CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_RX_DESC_SIZE);
598                 return -(EINVAL);
599         }
600
601         rxq->rspq.size = temp_nb_desc;
602         if ((&rxq->fl) != NULL)
603                 rxq->fl.size = temp_nb_desc;
604
605         /* Set to jumbo mode if necessary */
606         if (pkt_len > ETHER_MAX_LEN)
607                 eth_dev->data->dev_conf.rxmode.jumbo_frame = 1;
608         else
609                 eth_dev->data->dev_conf.rxmode.jumbo_frame = 0;
610
611         err = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx,
612                                &rxq->fl, t4_ethrx_handler,
613                                is_pf4(adapter) ?
614                                t4_get_tp_ch_map(adapter, pi->tx_chan) : 0, mp,
615                                queue_idx, socket_id);
616
617         dev_debug(adapter, "%s: err = %d; port_id = %d; cntxt_id = %u; abs_id = %u\n",
618                   __func__, err, pi->port_id, rxq->rspq.cntxt_id,
619                   rxq->rspq.abs_id);
620         return err;
621 }
622
623 void cxgbe_dev_rx_queue_release(void *q)
624 {
625         struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)q;
626         struct sge_rspq *rq = &rxq->rspq;
627
628         if (rq) {
629                 struct port_info *pi = (struct port_info *)
630                                        (rq->eth_dev->data->dev_private);
631                 struct adapter *adap = pi->adapter;
632
633                 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
634                           __func__, pi->port_id, rxq->rspq.cntxt_id);
635
636                 t4_sge_eth_rxq_release(adap, rxq);
637         }
638 }
639
640 /*
641  * Get port statistics.
642  */
643 static int cxgbe_dev_stats_get(struct rte_eth_dev *eth_dev,
644                                 struct rte_eth_stats *eth_stats)
645 {
646         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
647         struct adapter *adapter = pi->adapter;
648         struct sge *s = &adapter->sge;
649         struct port_stats ps;
650         unsigned int i;
651
652         cxgbe_stats_get(pi, &ps);
653
654         /* RX Stats */
655         eth_stats->imissed  = ps.rx_ovflow0 + ps.rx_ovflow1 +
656                               ps.rx_ovflow2 + ps.rx_ovflow3 +
657                               ps.rx_trunc0 + ps.rx_trunc1 +
658                               ps.rx_trunc2 + ps.rx_trunc3;
659         eth_stats->ierrors  = ps.rx_symbol_err + ps.rx_fcs_err +
660                               ps.rx_jabber + ps.rx_too_long + ps.rx_runt +
661                               ps.rx_len_err;
662
663         /* TX Stats */
664         eth_stats->opackets = ps.tx_frames;
665         eth_stats->obytes   = ps.tx_octets;
666         eth_stats->oerrors  = ps.tx_error_frames;
667
668         for (i = 0; i < pi->n_rx_qsets; i++) {
669                 struct sge_eth_rxq *rxq =
670                         &s->ethrxq[pi->first_qset + i];
671
672                 eth_stats->q_ipackets[i] = rxq->stats.pkts;
673                 eth_stats->q_ibytes[i] = rxq->stats.rx_bytes;
674                 eth_stats->ipackets += eth_stats->q_ipackets[i];
675                 eth_stats->ibytes += eth_stats->q_ibytes[i];
676         }
677
678         for (i = 0; i < pi->n_tx_qsets; i++) {
679                 struct sge_eth_txq *txq =
680                         &s->ethtxq[pi->first_qset + i];
681
682                 eth_stats->q_opackets[i] = txq->stats.pkts;
683                 eth_stats->q_obytes[i] = txq->stats.tx_bytes;
684                 eth_stats->q_errors[i] = txq->stats.mapping_err;
685         }
686         return 0;
687 }
688
689 /*
690  * Reset port statistics.
691  */
692 static void cxgbe_dev_stats_reset(struct rte_eth_dev *eth_dev)
693 {
694         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
695         struct adapter *adapter = pi->adapter;
696         struct sge *s = &adapter->sge;
697         unsigned int i;
698
699         cxgbe_stats_reset(pi);
700         for (i = 0; i < pi->n_rx_qsets; i++) {
701                 struct sge_eth_rxq *rxq =
702                         &s->ethrxq[pi->first_qset + i];
703
704                 rxq->stats.pkts = 0;
705                 rxq->stats.rx_bytes = 0;
706         }
707         for (i = 0; i < pi->n_tx_qsets; i++) {
708                 struct sge_eth_txq *txq =
709                         &s->ethtxq[pi->first_qset + i];
710
711                 txq->stats.pkts = 0;
712                 txq->stats.tx_bytes = 0;
713                 txq->stats.mapping_err = 0;
714         }
715 }
716
717 static int cxgbe_flow_ctrl_get(struct rte_eth_dev *eth_dev,
718                                struct rte_eth_fc_conf *fc_conf)
719 {
720         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
721         struct link_config *lc = &pi->link_cfg;
722         int rx_pause, tx_pause;
723
724         fc_conf->autoneg = lc->fc & PAUSE_AUTONEG;
725         rx_pause = lc->fc & PAUSE_RX;
726         tx_pause = lc->fc & PAUSE_TX;
727
728         if (rx_pause && tx_pause)
729                 fc_conf->mode = RTE_FC_FULL;
730         else if (rx_pause)
731                 fc_conf->mode = RTE_FC_RX_PAUSE;
732         else if (tx_pause)
733                 fc_conf->mode = RTE_FC_TX_PAUSE;
734         else
735                 fc_conf->mode = RTE_FC_NONE;
736         return 0;
737 }
738
739 static int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev,
740                                struct rte_eth_fc_conf *fc_conf)
741 {
742         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
743         struct adapter *adapter = pi->adapter;
744         struct link_config *lc = &pi->link_cfg;
745
746         if (lc->pcaps & FW_PORT_CAP32_ANEG) {
747                 if (fc_conf->autoneg)
748                         lc->requested_fc |= PAUSE_AUTONEG;
749                 else
750                         lc->requested_fc &= ~PAUSE_AUTONEG;
751         }
752
753         if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
754             (fc_conf->mode & RTE_FC_RX_PAUSE))
755                 lc->requested_fc |= PAUSE_RX;
756         else
757                 lc->requested_fc &= ~PAUSE_RX;
758
759         if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
760             (fc_conf->mode & RTE_FC_TX_PAUSE))
761                 lc->requested_fc |= PAUSE_TX;
762         else
763                 lc->requested_fc &= ~PAUSE_TX;
764
765         return t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,
766                              &pi->link_cfg);
767 }
768
769 const uint32_t *
770 cxgbe_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
771 {
772         static const uint32_t ptypes[] = {
773                 RTE_PTYPE_L3_IPV4,
774                 RTE_PTYPE_L3_IPV6,
775                 RTE_PTYPE_UNKNOWN
776         };
777
778         if (eth_dev->rx_pkt_burst == cxgbe_recv_pkts)
779                 return ptypes;
780         return NULL;
781 }
782
783 /* Update RSS hash configuration
784  */
785 static int cxgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
786                                      struct rte_eth_rss_conf *rss_conf)
787 {
788         struct port_info *pi = (struct port_info *)(dev->data->dev_private);
789         struct adapter *adapter = pi->adapter;
790         int err;
791
792         err = cxgbe_write_rss_conf(pi, rss_conf->rss_hf);
793         if (err)
794                 return err;
795
796         pi->rss_hf = rss_conf->rss_hf;
797
798         if (rss_conf->rss_key) {
799                 u32 key[10], mod_key[10];
800                 int i, j;
801
802                 memcpy(key, rss_conf->rss_key, CXGBE_DEFAULT_RSS_KEY_LEN);
803
804                 for (i = 9, j = 0; i >= 0; i--, j++)
805                         mod_key[j] = cpu_to_be32(key[i]);
806
807                 t4_write_rss_key(adapter, mod_key, -1);
808         }
809
810         return 0;
811 }
812
813 /* Get RSS hash configuration
814  */
815 static int cxgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
816                                        struct rte_eth_rss_conf *rss_conf)
817 {
818         struct port_info *pi = (struct port_info *)(dev->data->dev_private);
819         struct adapter *adapter = pi->adapter;
820         u64 rss_hf = 0;
821         u64 flags = 0;
822         int err;
823
824         err = t4_read_config_vi_rss(adapter, adapter->mbox, pi->viid,
825                                     &flags, NULL);
826
827         if (err)
828                 return err;
829
830         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) {
831                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
832                 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
833                         rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
834         }
835
836         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
837                 rss_hf |= ETH_RSS_IPV6;
838
839         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) {
840                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
841                 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
842                         rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
843         }
844
845         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
846                 rss_hf |= ETH_RSS_IPV4;
847
848         rss_conf->rss_hf = rss_hf;
849
850         if (rss_conf->rss_key) {
851                 u32 key[10], mod_key[10];
852                 int i, j;
853
854                 t4_read_rss_key(adapter, key);
855
856                 for (i = 9, j = 0; i >= 0; i--, j++)
857                         mod_key[j] = be32_to_cpu(key[i]);
858
859                 memcpy(rss_conf->rss_key, mod_key, CXGBE_DEFAULT_RSS_KEY_LEN);
860         }
861
862         return 0;
863 }
864
865 static int cxgbe_get_eeprom_length(struct rte_eth_dev *dev)
866 {
867         RTE_SET_USED(dev);
868         return EEPROMSIZE;
869 }
870
871 /**
872  * eeprom_ptov - translate a physical EEPROM address to virtual
873  * @phys_addr: the physical EEPROM address
874  * @fn: the PCI function number
875  * @sz: size of function-specific area
876  *
877  * Translate a physical EEPROM address to virtual.  The first 1K is
878  * accessed through virtual addresses starting at 31K, the rest is
879  * accessed through virtual addresses starting at 0.
880  *
881  * The mapping is as follows:
882  * [0..1K) -> [31K..32K)
883  * [1K..1K+A) -> [31K-A..31K)
884  * [1K+A..ES) -> [0..ES-A-1K)
885  *
886  * where A = @fn * @sz, and ES = EEPROM size.
887  */
888 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
889 {
890         fn *= sz;
891         if (phys_addr < 1024)
892                 return phys_addr + (31 << 10);
893         if (phys_addr < 1024 + fn)
894                 return fn + phys_addr - 1024;
895         if (phys_addr < EEPROMSIZE)
896                 return phys_addr - 1024 - fn;
897         if (phys_addr < EEPROMVSIZE)
898                 return phys_addr - 1024;
899         return -EINVAL;
900 }
901
902 /* The next two routines implement eeprom read/write from physical addresses.
903  */
904 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v)
905 {
906         int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
907
908         if (vaddr >= 0)
909                 vaddr = t4_seeprom_read(adap, vaddr, v);
910         return vaddr < 0 ? vaddr : 0;
911 }
912
913 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v)
914 {
915         int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
916
917         if (vaddr >= 0)
918                 vaddr = t4_seeprom_write(adap, vaddr, v);
919         return vaddr < 0 ? vaddr : 0;
920 }
921
922 #define EEPROM_MAGIC 0x38E2F10C
923
924 static int cxgbe_get_eeprom(struct rte_eth_dev *dev,
925                             struct rte_dev_eeprom_info *e)
926 {
927         struct port_info *pi = (struct port_info *)(dev->data->dev_private);
928         struct adapter *adapter = pi->adapter;
929         u32 i, err = 0;
930         u8 *buf = rte_zmalloc(NULL, EEPROMSIZE, 0);
931
932         if (!buf)
933                 return -ENOMEM;
934
935         e->magic = EEPROM_MAGIC;
936         for (i = e->offset & ~3; !err && i < e->offset + e->length; i += 4)
937                 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]);
938
939         if (!err)
940                 rte_memcpy(e->data, buf + e->offset, e->length);
941         rte_free(buf);
942         return err;
943 }
944
945 static int cxgbe_set_eeprom(struct rte_eth_dev *dev,
946                             struct rte_dev_eeprom_info *eeprom)
947 {
948         struct port_info *pi = (struct port_info *)(dev->data->dev_private);
949         struct adapter *adapter = pi->adapter;
950         u8 *buf;
951         int err = 0;
952         u32 aligned_offset, aligned_len, *p;
953
954         if (eeprom->magic != EEPROM_MAGIC)
955                 return -EINVAL;
956
957         aligned_offset = eeprom->offset & ~3;
958         aligned_len = (eeprom->length + (eeprom->offset & 3) + 3) & ~3;
959
960         if (adapter->pf > 0) {
961                 u32 start = 1024 + adapter->pf * EEPROMPFSIZE;
962
963                 if (aligned_offset < start ||
964                     aligned_offset + aligned_len > start + EEPROMPFSIZE)
965                         return -EPERM;
966         }
967
968         if (aligned_offset != eeprom->offset || aligned_len != eeprom->length) {
969                 /* RMW possibly needed for first or last words.
970                  */
971                 buf = rte_zmalloc(NULL, aligned_len, 0);
972                 if (!buf)
973                         return -ENOMEM;
974                 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf);
975                 if (!err && aligned_len > 4)
976                         err = eeprom_rd_phys(adapter,
977                                              aligned_offset + aligned_len - 4,
978                                              (u32 *)&buf[aligned_len - 4]);
979                 if (err)
980                         goto out;
981                 rte_memcpy(buf + (eeprom->offset & 3), eeprom->data,
982                            eeprom->length);
983         } else {
984                 buf = eeprom->data;
985         }
986
987         err = t4_seeprom_wp(adapter, false);
988         if (err)
989                 goto out;
990
991         for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
992                 err = eeprom_wr_phys(adapter, aligned_offset, *p);
993                 aligned_offset += 4;
994         }
995
996         if (!err)
997                 err = t4_seeprom_wp(adapter, true);
998 out:
999         if (buf != eeprom->data)
1000                 rte_free(buf);
1001         return err;
1002 }
1003
1004 static int cxgbe_get_regs_len(struct rte_eth_dev *eth_dev)
1005 {
1006         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
1007         struct adapter *adapter = pi->adapter;
1008
1009         return t4_get_regs_len(adapter) / sizeof(uint32_t);
1010 }
1011
1012 static int cxgbe_get_regs(struct rte_eth_dev *eth_dev,
1013                           struct rte_dev_reg_info *regs)
1014 {
1015         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
1016         struct adapter *adapter = pi->adapter;
1017
1018         regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) |
1019                 (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) |
1020                 (1 << 16);
1021
1022         if (regs->data == NULL) {
1023                 regs->length = cxgbe_get_regs_len(eth_dev);
1024                 regs->width = sizeof(uint32_t);
1025
1026                 return 0;
1027         }
1028
1029         t4_get_regs(adapter, regs->data, (regs->length * sizeof(uint32_t)));
1030
1031         return 0;
1032 }
1033
1034 void cxgbe_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
1035 {
1036         struct port_info *pi = (struct port_info *)(dev->data->dev_private);
1037         struct adapter *adapter = pi->adapter;
1038         int ret;
1039
1040         ret = t4_change_mac(adapter, adapter->mbox, pi->viid,
1041                             pi->xact_addr_filt, (u8 *)addr, true, true);
1042         if (ret < 0) {
1043                 dev_err(adapter, "failed to set mac addr; err = %d\n",
1044                         ret);
1045                 return;
1046         }
1047         pi->xact_addr_filt = ret;
1048 }
1049
1050 static const struct eth_dev_ops cxgbe_eth_dev_ops = {
1051         .dev_start              = cxgbe_dev_start,
1052         .dev_stop               = cxgbe_dev_stop,
1053         .dev_close              = cxgbe_dev_close,
1054         .promiscuous_enable     = cxgbe_dev_promiscuous_enable,
1055         .promiscuous_disable    = cxgbe_dev_promiscuous_disable,
1056         .allmulticast_enable    = cxgbe_dev_allmulticast_enable,
1057         .allmulticast_disable   = cxgbe_dev_allmulticast_disable,
1058         .dev_configure          = cxgbe_dev_configure,
1059         .dev_infos_get          = cxgbe_dev_info_get,
1060         .dev_supported_ptypes_get = cxgbe_dev_supported_ptypes_get,
1061         .link_update            = cxgbe_dev_link_update,
1062         .mtu_set                = cxgbe_dev_mtu_set,
1063         .tx_queue_setup         = cxgbe_dev_tx_queue_setup,
1064         .tx_queue_start         = cxgbe_dev_tx_queue_start,
1065         .tx_queue_stop          = cxgbe_dev_tx_queue_stop,
1066         .tx_queue_release       = cxgbe_dev_tx_queue_release,
1067         .rx_queue_setup         = cxgbe_dev_rx_queue_setup,
1068         .rx_queue_start         = cxgbe_dev_rx_queue_start,
1069         .rx_queue_stop          = cxgbe_dev_rx_queue_stop,
1070         .rx_queue_release       = cxgbe_dev_rx_queue_release,
1071         .stats_get              = cxgbe_dev_stats_get,
1072         .stats_reset            = cxgbe_dev_stats_reset,
1073         .flow_ctrl_get          = cxgbe_flow_ctrl_get,
1074         .flow_ctrl_set          = cxgbe_flow_ctrl_set,
1075         .get_eeprom_length      = cxgbe_get_eeprom_length,
1076         .get_eeprom             = cxgbe_get_eeprom,
1077         .set_eeprom             = cxgbe_set_eeprom,
1078         .get_reg                = cxgbe_get_regs,
1079         .rss_hash_update        = cxgbe_dev_rss_hash_update,
1080         .rss_hash_conf_get      = cxgbe_dev_rss_hash_conf_get,
1081         .mac_addr_set           = cxgbe_mac_addr_set,
1082 };
1083
1084 /*
1085  * Initialize driver
1086  * It returns 0 on success.
1087  */
1088 static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev)
1089 {
1090         struct rte_pci_device *pci_dev;
1091         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
1092         struct adapter *adapter = NULL;
1093         char name[RTE_ETH_NAME_MAX_LEN];
1094         int err = 0;
1095
1096         CXGBE_FUNC_TRACE();
1097
1098         eth_dev->dev_ops = &cxgbe_eth_dev_ops;
1099         eth_dev->rx_pkt_burst = &cxgbe_recv_pkts;
1100         eth_dev->tx_pkt_burst = &cxgbe_xmit_pkts;
1101         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1102
1103         /* for secondary processes, we attach to ethdevs allocated by primary
1104          * and do minimal initialization.
1105          */
1106         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1107                 int i;
1108
1109                 for (i = 1; i < MAX_NPORTS; i++) {
1110                         struct rte_eth_dev *rest_eth_dev;
1111                         char namei[RTE_ETH_NAME_MAX_LEN];
1112
1113                         snprintf(namei, sizeof(namei), "%s_%d",
1114                                  pci_dev->device.name, i);
1115                         rest_eth_dev = rte_eth_dev_attach_secondary(namei);
1116                         if (rest_eth_dev) {
1117                                 rest_eth_dev->device = &pci_dev->device;
1118                                 rest_eth_dev->dev_ops =
1119                                         eth_dev->dev_ops;
1120                                 rest_eth_dev->rx_pkt_burst =
1121                                         eth_dev->rx_pkt_burst;
1122                                 rest_eth_dev->tx_pkt_burst =
1123                                         eth_dev->tx_pkt_burst;
1124                         }
1125                 }
1126                 return 0;
1127         }
1128
1129         snprintf(name, sizeof(name), "cxgbeadapter%d", eth_dev->data->port_id);
1130         adapter = rte_zmalloc(name, sizeof(*adapter), 0);
1131         if (!adapter)
1132                 return -1;
1133
1134         adapter->use_unpacked_mode = 1;
1135         adapter->regs = (void *)pci_dev->mem_resource[0].addr;
1136         if (!adapter->regs) {
1137                 dev_err(adapter, "%s: cannot map device registers\n", __func__);
1138                 err = -ENOMEM;
1139                 goto out_free_adapter;
1140         }
1141         adapter->pdev = pci_dev;
1142         adapter->eth_dev = eth_dev;
1143         pi->adapter = adapter;
1144
1145         err = cxgbe_probe(adapter);
1146         if (err) {
1147                 dev_err(adapter, "%s: cxgbe probe failed with err %d\n",
1148                         __func__, err);
1149                 goto out_free_adapter;
1150         }
1151
1152         return 0;
1153
1154 out_free_adapter:
1155         rte_free(adapter);
1156         return err;
1157 }
1158
1159 static int eth_cxgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1160         struct rte_pci_device *pci_dev)
1161 {
1162         return rte_eth_dev_pci_generic_probe(pci_dev,
1163                 sizeof(struct port_info), eth_cxgbe_dev_init);
1164 }
1165
1166 static int eth_cxgbe_pci_remove(struct rte_pci_device *pci_dev)
1167 {
1168         return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
1169 }
1170
1171 static struct rte_pci_driver rte_cxgbe_pmd = {
1172         .id_table = cxgb4_pci_tbl,
1173         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1174         .probe = eth_cxgbe_pci_probe,
1175         .remove = eth_cxgbe_pci_remove,
1176 };
1177
1178 RTE_PMD_REGISTER_PCI(net_cxgbe, rte_cxgbe_pmd);
1179 RTE_PMD_REGISTER_PCI_TABLE(net_cxgbe, cxgb4_pci_tbl);
1180 RTE_PMD_REGISTER_KMOD_DEP(net_cxgbe, "* igb_uio | uio_pci_generic | vfio-pci");