drivers/net/cxgbe/cxgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2014-2017 Chelsio Communications.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Chelsio Communications nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43
  44 #include <rte_byteorder.h>
  45 #include <rte_common.h>
  46 #include <rte_cycles.h>
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_bus_pci.h>
  52 #include <rte_atomic.h>
  53 #include <rte_branch_prediction.h>
  54 #include <rte_memory.h>
  55 #include <rte_tailq.h>
  56 #include <rte_eal.h>
  57 #include <rte_alarm.h>
  58 #include <rte_ether.h>
  59 #include <rte_ethdev_driver.h>
  60 #include <rte_ethdev_pci.h>
  61 #include <rte_malloc.h>
  62 #include <rte_random.h>
  63 #include <rte_dev.h>
  64
  65 #include "cxgbe.h"
  66 #include "cxgbe_pfvf.h"
  67
  68 /*
  69  * Macros needed to support the PCI Device ID Table ...
  70  */
  71 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
  72         static const struct rte_pci_id cxgb4_pci_tbl[] = {
  73 #define CH_PCI_DEVICE_ID_FUNCTION 0x4
  74
  75 #define PCI_VENDOR_ID_CHELSIO 0x1425
  76
  77 #define CH_PCI_ID_TABLE_ENTRY(devid) \
  78                 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CHELSIO, (devid)) }
  79
  80 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
  81                 { .vendor_id = 0, } \
  82         }
  83
  84 /*
  85  *... and the PCI ID Table itself ...
  86  */
  87 #include "t4_pci_id_tbl.h"
  88
  89 static uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
  90                                 uint16_t nb_pkts)
  91 {
  92         struct sge_eth_txq *txq = (struct sge_eth_txq *)tx_queue;
  93         uint16_t pkts_sent, pkts_remain;
  94         uint16_t total_sent = 0;
  95         int ret = 0;
  96
  97         CXGBE_DEBUG_TX(adapter, "%s: txq = %p; tx_pkts = %p; nb_pkts = %d\n",
  98                        __func__, txq, tx_pkts, nb_pkts);
  99
 100         t4_os_lock(&txq->txq_lock);
 101         /* free up desc from already completed tx */
 102         reclaim_completed_tx(&txq->q);
 103         while (total_sent < nb_pkts) {
 104                 pkts_remain = nb_pkts - total_sent;
 105
 106                 for (pkts_sent = 0; pkts_sent < pkts_remain; pkts_sent++) {
 107                         ret = t4_eth_xmit(txq, tx_pkts[total_sent + pkts_sent],
 108                                           nb_pkts);
 109                         if (ret < 0)
 110                                 break;
 111                 }
 112                 if (!pkts_sent)
 113                         break;
 114                 total_sent += pkts_sent;
 115                 /* reclaim as much as possible */
 116                 reclaim_completed_tx(&txq->q);
 117         }
 118
 119         t4_os_unlock(&txq->txq_lock);
 120         return total_sent;
 121 }
 122
 123 static uint16_t cxgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
 124                                 uint16_t nb_pkts)
 125 {
 126         struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)rx_queue;
 127         unsigned int work_done;
 128
 129         CXGBE_DEBUG_RX(adapter, "%s: rxq->rspq.cntxt_id = %u; nb_pkts = %d\n",
 130                        __func__, rxq->rspq.cntxt_id, nb_pkts);
 131
 132         if (cxgbe_poll(&rxq->rspq, rx_pkts, (unsigned int)nb_pkts, &work_done))
 133                 dev_err(adapter, "error in cxgbe poll\n");
 134
 135         CXGBE_DEBUG_RX(adapter, "%s: work_done = %u\n", __func__, work_done);
 136         return work_done;
 137 }
 138
 139 void cxgbe_dev_info_get(struct rte_eth_dev *eth_dev,
 140                         struct rte_eth_dev_info *device_info)
 141 {
 142         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 143         struct adapter *adapter = pi->adapter;
 144         int max_queues = adapter->sge.max_ethqsets / adapter->params.nports;
 145
 146         static const struct rte_eth_desc_lim cxgbe_desc_lim = {
 147                 .nb_max = CXGBE_MAX_RING_DESC_SIZE,
 148                 .nb_min = CXGBE_MIN_RING_DESC_SIZE,
 149                 .nb_align = 1,
 150         };
 151
 152         device_info->pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 153
 154         device_info->min_rx_bufsize = CXGBE_MIN_RX_BUFSIZE;
 155         device_info->max_rx_pktlen = CXGBE_MAX_RX_PKTLEN;
 156         device_info->max_rx_queues = max_queues;
 157         device_info->max_tx_queues = max_queues;
 158         device_info->max_mac_addrs = 1;
 159         /* XXX: For now we support one MAC/port */
 160         device_info->max_vfs = adapter->params.arch.vfcount;
 161         device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */
 162
 163         device_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
 164                                        DEV_RX_OFFLOAD_IPV4_CKSUM |
 165                                        DEV_RX_OFFLOAD_UDP_CKSUM |
 166                                        DEV_RX_OFFLOAD_TCP_CKSUM;
 167
 168         device_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
 169                                        DEV_TX_OFFLOAD_IPV4_CKSUM |
 170                                        DEV_TX_OFFLOAD_UDP_CKSUM |
 171                                        DEV_TX_OFFLOAD_TCP_CKSUM |
 172                                        DEV_TX_OFFLOAD_TCP_TSO;
 173
 174         device_info->reta_size = pi->rss_size;
 175         device_info->hash_key_size = CXGBE_DEFAULT_RSS_KEY_LEN;
 176         device_info->flow_type_rss_offloads = CXGBE_RSS_HF_ALL;
 177
 178         device_info->rx_desc_lim = cxgbe_desc_lim;
 179         device_info->tx_desc_lim = cxgbe_desc_lim;
 180         cxgbe_get_speed_caps(pi, &device_info->speed_capa);
 181 }
 182
 183 void cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
 184 {
 185         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 186         struct adapter *adapter = pi->adapter;
 187
 188         t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 189                       1, -1, 1, -1, false);
 190 }
 191
 192 void cxgbe_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
 193 {
 194         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 195         struct adapter *adapter = pi->adapter;
 196
 197         t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 198                       0, -1, 1, -1, false);
 199 }
 200
 201 void cxgbe_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
 202 {
 203         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 204         struct adapter *adapter = pi->adapter;
 205
 206         /* TODO: address filters ?? */
 207
 208         t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 209                       -1, 1, 1, -1, false);
 210 }
 211
 212 void cxgbe_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
 213 {
 214         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 215         struct adapter *adapter = pi->adapter;
 216
 217         /* TODO: address filters ?? */
 218
 219         t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 220                       -1, 0, 1, -1, false);
 221 }
 222
 223 int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev,
 224                           __rte_unused int wait_to_complete)
 225 {
 226         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 227         struct adapter *adapter = pi->adapter;
 228         struct sge *s = &adapter->sge;
 229         struct rte_eth_link *old_link = &eth_dev->data->dev_link;
 230         unsigned int work_done, budget = 4;
 231
 232         cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
 233         if (old_link->link_status == pi->link_cfg.link_ok)
 234                 return -1;  /* link not changed */
 235
 236         eth_dev->data->dev_link.link_status = pi->link_cfg.link_ok;
 237         eth_dev->data->dev_link.link_duplex = ETH_LINK_FULL_DUPLEX;
 238         eth_dev->data->dev_link.link_speed = pi->link_cfg.speed;
 239
 240         /* link has changed */
 241         return 0;
 242 }
 243
 244 int cxgbe_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
 245 {
 246         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 247         struct adapter *adapter = pi->adapter;
 248         struct rte_eth_dev_info dev_info;
 249         int err;
 250         uint16_t new_mtu = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
 251
 252         cxgbe_dev_info_get(eth_dev, &dev_info);
 253
 254         /* Must accommodate at least ETHER_MIN_MTU */
 255         if ((new_mtu < ETHER_MIN_MTU) || (new_mtu > dev_info.max_rx_pktlen))
 256                 return -EINVAL;
 257
 258         /* set to jumbo mode if needed */
 259         if (new_mtu > ETHER_MAX_LEN)
 260                 eth_dev->data->dev_conf.rxmode.jumbo_frame = 1;
 261         else
 262                 eth_dev->data->dev_conf.rxmode.jumbo_frame = 0;
 263
 264         err = t4_set_rxmode(adapter, adapter->mbox, pi->viid, new_mtu, -1, -1,
 265                             -1, -1, true);
 266         if (!err)
 267                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_mtu;
 268
 269         return err;
 270 }
 271
 272 /*
 273  * Stop device.
 274  */
 275 void cxgbe_dev_close(struct rte_eth_dev *eth_dev)
 276 {
 277         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 278         struct adapter *adapter = pi->adapter;
 279         int i, dev_down = 0;
 280
 281         CXGBE_FUNC_TRACE();
 282
 283         if (!(adapter->flags & FULL_INIT_DONE))
 284                 return;
 285
 286         cxgbe_down(pi);
 287
 288         /*
 289          *  We clear queues only if both tx and rx path of the port
 290          *  have been disabled
 291          */
 292         t4_sge_eth_clear_queues(pi);
 293
 294         /*  See if all ports are down */
 295         for_each_port(adapter, i) {
 296                 pi = adap2pinfo(adapter, i);
 297                 /*
 298                  * Skip first port of the adapter since it will be closed
 299                  * by DPDK
 300                  */
 301                 if (i == 0)
 302                         continue;
 303                 dev_down += (pi->eth_dev->data->dev_started == 0) ? 1 : 0;
 304         }
 305
 306         /* If rest of the ports are stopped, then free up resources */
 307         if (dev_down == (adapter->params.nports - 1))
 308                 cxgbe_close(adapter);
 309 }
 310
 311 /* Start the device.
 312  * It returns 0 on success.
 313  */
 314 int cxgbe_dev_start(struct rte_eth_dev *eth_dev)
 315 {
 316         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 317         struct adapter *adapter = pi->adapter;
 318         int err = 0, i;
 319
 320         CXGBE_FUNC_TRACE();
 321
 322         /*
 323          * If we don't have a connection to the firmware there's nothing we
 324          * can do.
 325          */
 326         if (!(adapter->flags & FW_OK)) {
 327                 err = -ENXIO;
 328                 goto out;
 329         }
 330
 331         if (!(adapter->flags & FULL_INIT_DONE)) {
 332                 err = cxgbe_up(adapter);
 333                 if (err < 0)
 334                         goto out;
 335         }
 336
 337         cxgbe_enable_rx_queues(pi);
 338
 339         err = setup_rss(pi);
 340         if (err)
 341                 goto out;
 342
 343         for (i = 0; i < pi->n_tx_qsets; i++) {
 344                 err = cxgbe_dev_tx_queue_start(eth_dev, i);
 345                 if (err)
 346                         goto out;
 347         }
 348
 349         for (i = 0; i < pi->n_rx_qsets; i++) {
 350                 err = cxgbe_dev_rx_queue_start(eth_dev, i);
 351                 if (err)
 352                         goto out;
 353         }
 354
 355         err = link_start(pi);
 356         if (err)
 357                 goto out;
 358
 359 out:
 360         return err;
 361 }
 362
 363 /*
 364  * Stop device: disable rx and tx functions to allow for reconfiguring.
 365  */
 366 void cxgbe_dev_stop(struct rte_eth_dev *eth_dev)
 367 {
 368         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 369         struct adapter *adapter = pi->adapter;
 370
 371         CXGBE_FUNC_TRACE();
 372
 373         if (!(adapter->flags & FULL_INIT_DONE))
 374                 return;
 375
 376         cxgbe_down(pi);
 377
 378         /*
 379          *  We clear queues only if both tx and rx path of the port
 380          *  have been disabled
 381          */
 382         t4_sge_eth_clear_queues(pi);
 383 }
 384
 385 int cxgbe_dev_configure(struct rte_eth_dev *eth_dev)
 386 {
 387         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 388         struct adapter *adapter = pi->adapter;
 389         int err;
 390
 391         CXGBE_FUNC_TRACE();
 392
 393         if (!(adapter->flags & FW_QUEUE_BOUND)) {
 394                 err = setup_sge_fwevtq(adapter);
 395                 if (err)
 396                         return err;
 397                 adapter->flags |= FW_QUEUE_BOUND;
 398         }
 399
 400         err = cfg_queue_count(eth_dev);
 401         if (err)
 402                 return err;
 403
 404         return 0;
 405 }
 406
 407 int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
 408 {
 409         int ret;
 410         struct sge_eth_txq *txq = (struct sge_eth_txq *)
 411                                   (eth_dev->data->tx_queues[tx_queue_id]);
 412
 413         dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
 414
 415         ret = t4_sge_eth_txq_start(txq);
 416         if (ret == 0)
 417                 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 418
 419         return ret;
 420 }
 421
 422 int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
 423 {
 424         int ret;
 425         struct sge_eth_txq *txq = (struct sge_eth_txq *)
 426                                   (eth_dev->data->tx_queues[tx_queue_id]);
 427
 428         dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
 429
 430         ret = t4_sge_eth_txq_stop(txq);
 431         if (ret == 0)
 432                 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 433
 434         return ret;
 435 }
 436
 437 int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev,
 438                              uint16_t queue_idx, uint16_t nb_desc,
 439                              unsigned int socket_id,
 440                              const struct rte_eth_txconf *tx_conf)
 441 {
 442         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 443         struct adapter *adapter = pi->adapter;
 444         struct sge *s = &adapter->sge;
 445         struct sge_eth_txq *txq = &s->ethtxq[pi->first_qset + queue_idx];
 446         int err = 0;
 447         unsigned int temp_nb_desc;
 448
 449         RTE_SET_USED(tx_conf);
 450
 451         dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n",
 452                   __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc,
 453                   socket_id, pi->first_qset);
 454
 455         /*  Free up the existing queue  */
 456         if (eth_dev->data->tx_queues[queue_idx]) {
 457                 cxgbe_dev_tx_queue_release(eth_dev->data->tx_queues[queue_idx]);
 458                 eth_dev->data->tx_queues[queue_idx] = NULL;
 459         }
 460
 461         eth_dev->data->tx_queues[queue_idx] = (void *)txq;
 462
 463         /* Sanity Checking
 464          *
 465          * nb_desc should be > 1023 and <= CXGBE_MAX_RING_DESC_SIZE
 466          */
 467         temp_nb_desc = nb_desc;
 468         if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
 469                 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
 470                          __func__, CXGBE_MIN_RING_DESC_SIZE,
 471                          CXGBE_DEFAULT_TX_DESC_SIZE);
 472                 temp_nb_desc = CXGBE_DEFAULT_TX_DESC_SIZE;
 473         } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
 474                 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
 475                         __func__, CXGBE_MIN_RING_DESC_SIZE,
 476                         CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_TX_DESC_SIZE);
 477                 return -(EINVAL);
 478         }
 479
 480         txq->q.size = temp_nb_desc;
 481
 482         err = t4_sge_alloc_eth_txq(adapter, txq, eth_dev, queue_idx,
 483                                    s->fw_evtq.cntxt_id, socket_id);
 484
 485         dev_debug(adapter, "%s: txq->q.cntxt_id= %d err = %d\n",
 486                   __func__, txq->q.cntxt_id, err);
 487
 488         return err;
 489 }
 490
 491 void cxgbe_dev_tx_queue_release(void *q)
 492 {
 493         struct sge_eth_txq *txq = (struct sge_eth_txq *)q;
 494
 495         if (txq) {
 496                 struct port_info *pi = (struct port_info *)
 497                                        (txq->eth_dev->data->dev_private);
 498                 struct adapter *adap = pi->adapter;
 499
 500                 dev_debug(adapter, "%s: pi->port_id = %d; tx_queue_id = %d\n",
 501                           __func__, pi->port_id, txq->q.cntxt_id);
 502
 503                 t4_sge_eth_txq_release(adap, txq);
 504         }
 505 }
 506
 507 int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
 508 {
 509         int ret;
 510         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 511         struct adapter *adap = pi->adapter;
 512         struct sge_rspq *q;
 513
 514         dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
 515                   __func__, pi->port_id, rx_queue_id);
 516
 517         q = eth_dev->data->rx_queues[rx_queue_id];
 518
 519         ret = t4_sge_eth_rxq_start(adap, q);
 520         if (ret == 0)
 521                 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 522
 523         return ret;
 524 }
 525
 526 int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
 527 {
 528         int ret;
 529         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 530         struct adapter *adap = pi->adapter;
 531         struct sge_rspq *q;
 532
 533         dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
 534                   __func__, pi->port_id, rx_queue_id);
 535
 536         q = eth_dev->data->rx_queues[rx_queue_id];
 537         ret = t4_sge_eth_rxq_stop(adap, q);
 538         if (ret == 0)
 539                 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 540
 541         return ret;
 542 }
 543
 544 int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev,
 545                              uint16_t queue_idx, uint16_t nb_desc,
 546                              unsigned int socket_id,
 547                              const struct rte_eth_rxconf *rx_conf,
 548                              struct rte_mempool *mp)
 549 {
 550         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 551         struct adapter *adapter = pi->adapter;
 552         struct sge *s = &adapter->sge;
 553         struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_qset + queue_idx];
 554         int err = 0;
 555         int msi_idx = 0;
 556         unsigned int temp_nb_desc;
 557         struct rte_eth_dev_info dev_info;
 558         unsigned int pkt_len = eth_dev->data->dev_conf.rxmode.max_rx_pkt_len;
 559
 560         RTE_SET_USED(rx_conf);
 561
 562         dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n",
 563                   __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc,
 564                   socket_id, mp);
 565
 566         cxgbe_dev_info_get(eth_dev, &dev_info);
 567
 568         /* Must accommodate at least ETHER_MIN_MTU */
 569         if ((pkt_len < dev_info.min_rx_bufsize) ||
 570             (pkt_len > dev_info.max_rx_pktlen)) {
 571                 dev_err(adap, "%s: max pkt len must be > %d and <= %d\n",
 572                         __func__, dev_info.min_rx_bufsize,
 573                         dev_info.max_rx_pktlen);
 574                 return -EINVAL;
 575         }
 576
 577         /*  Free up the existing queue  */
 578         if (eth_dev->data->rx_queues[queue_idx]) {
 579                 cxgbe_dev_rx_queue_release(eth_dev->data->rx_queues[queue_idx]);
 580                 eth_dev->data->rx_queues[queue_idx] = NULL;
 581         }
 582
 583         eth_dev->data->rx_queues[queue_idx] = (void *)rxq;
 584
 585         /* Sanity Checking
 586          *
 587          * nb_desc should be > 0 and <= CXGBE_MAX_RING_DESC_SIZE
 588          */
 589         temp_nb_desc = nb_desc;
 590         if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
 591                 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
 592                          __func__, CXGBE_MIN_RING_DESC_SIZE,
 593                          CXGBE_DEFAULT_RX_DESC_SIZE);
 594                 temp_nb_desc = CXGBE_DEFAULT_RX_DESC_SIZE;
 595         } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
 596                 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
 597                         __func__, CXGBE_MIN_RING_DESC_SIZE,
 598                         CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_RX_DESC_SIZE);
 599                 return -(EINVAL);
 600         }
 601
 602         rxq->rspq.size = temp_nb_desc;
 603         if ((&rxq->fl) != NULL)
 604                 rxq->fl.size = temp_nb_desc;
 605
 606         /* Set to jumbo mode if necessary */
 607         if (pkt_len > ETHER_MAX_LEN)
 608                 eth_dev->data->dev_conf.rxmode.jumbo_frame = 1;
 609         else
 610                 eth_dev->data->dev_conf.rxmode.jumbo_frame = 0;
 611
 612         err = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx,
 613                                &rxq->fl, t4_ethrx_handler,
 614                                t4_get_tp_ch_map(adapter, pi->tx_chan), mp,
 615                                queue_idx, socket_id);
 616
 617         dev_debug(adapter, "%s: err = %d; port_id = %d; cntxt_id = %u\n",
 618                   __func__, err, pi->port_id, rxq->rspq.cntxt_id);
 619         return err;
 620 }
 621
 622 void cxgbe_dev_rx_queue_release(void *q)
 623 {
 624         struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)q;
 625         struct sge_rspq *rq = &rxq->rspq;
 626
 627         if (rq) {
 628                 struct port_info *pi = (struct port_info *)
 629                                        (rq->eth_dev->data->dev_private);
 630                 struct adapter *adap = pi->adapter;
 631
 632                 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
 633                           __func__, pi->port_id, rxq->rspq.cntxt_id);
 634
 635                 t4_sge_eth_rxq_release(adap, rxq);
 636         }
 637 }
 638
 639 /*
 640  * Get port statistics.
 641  */
 642 static int cxgbe_dev_stats_get(struct rte_eth_dev *eth_dev,
 643                                 struct rte_eth_stats *eth_stats)
 644 {
 645         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 646         struct adapter *adapter = pi->adapter;
 647         struct sge *s = &adapter->sge;
 648         struct port_stats ps;
 649         unsigned int i;
 650
 651         cxgbe_stats_get(pi, &ps);
 652
 653         /* RX Stats */
 654         eth_stats->imissed  = ps.rx_ovflow0 + ps.rx_ovflow1 +
 655                               ps.rx_ovflow2 + ps.rx_ovflow3 +
 656                               ps.rx_trunc0 + ps.rx_trunc1 +
 657                               ps.rx_trunc2 + ps.rx_trunc3;
 658         eth_stats->ierrors  = ps.rx_symbol_err + ps.rx_fcs_err +
 659                               ps.rx_jabber + ps.rx_too_long + ps.rx_runt +
 660                               ps.rx_len_err;
 661
 662         /* TX Stats */
 663         eth_stats->opackets = ps.tx_frames;
 664         eth_stats->obytes   = ps.tx_octets;
 665         eth_stats->oerrors  = ps.tx_error_frames;
 666
 667         for (i = 0; i < pi->n_rx_qsets; i++) {
 668                 struct sge_eth_rxq *rxq =
 669                         &s->ethrxq[pi->first_qset + i];
 670
 671                 eth_stats->q_ipackets[i] = rxq->stats.pkts;
 672                 eth_stats->q_ibytes[i] = rxq->stats.rx_bytes;
 673                 eth_stats->ipackets += eth_stats->q_ipackets[i];
 674                 eth_stats->ibytes += eth_stats->q_ibytes[i];
 675         }
 676
 677         for (i = 0; i < pi->n_tx_qsets; i++) {
 678                 struct sge_eth_txq *txq =
 679                         &s->ethtxq[pi->first_qset + i];
 680
 681                 eth_stats->q_opackets[i] = txq->stats.pkts;
 682                 eth_stats->q_obytes[i] = txq->stats.tx_bytes;
 683                 eth_stats->q_errors[i] = txq->stats.mapping_err;
 684         }
 685         return 0;
 686 }
 687
 688 /*
 689  * Reset port statistics.
 690  */
 691 static void cxgbe_dev_stats_reset(struct rte_eth_dev *eth_dev)
 692 {
 693         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 694         struct adapter *adapter = pi->adapter;
 695         struct sge *s = &adapter->sge;
 696         unsigned int i;
 697
 698         cxgbe_stats_reset(pi);
 699         for (i = 0; i < pi->n_rx_qsets; i++) {
 700                 struct sge_eth_rxq *rxq =
 701                         &s->ethrxq[pi->first_qset + i];
 702
 703                 rxq->stats.pkts = 0;
 704                 rxq->stats.rx_bytes = 0;
 705         }
 706         for (i = 0; i < pi->n_tx_qsets; i++) {
 707                 struct sge_eth_txq *txq =
 708                         &s->ethtxq[pi->first_qset + i];
 709
 710                 txq->stats.pkts = 0;
 711                 txq->stats.tx_bytes = 0;
 712                 txq->stats.mapping_err = 0;
 713         }
 714 }
 715
 716 static int cxgbe_flow_ctrl_get(struct rte_eth_dev *eth_dev,
 717                                struct rte_eth_fc_conf *fc_conf)
 718 {
 719         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 720         struct link_config *lc = &pi->link_cfg;
 721         int rx_pause, tx_pause;
 722
 723         fc_conf->autoneg = lc->fc & PAUSE_AUTONEG;
 724         rx_pause = lc->fc & PAUSE_RX;
 725         tx_pause = lc->fc & PAUSE_TX;
 726
 727         if (rx_pause && tx_pause)
 728                 fc_conf->mode = RTE_FC_FULL;
 729         else if (rx_pause)
 730                 fc_conf->mode = RTE_FC_RX_PAUSE;
 731         else if (tx_pause)
 732                 fc_conf->mode = RTE_FC_TX_PAUSE;
 733         else
 734                 fc_conf->mode = RTE_FC_NONE;
 735         return 0;
 736 }
 737
 738 static int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev,
 739                                struct rte_eth_fc_conf *fc_conf)
 740 {
 741         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 742         struct adapter *adapter = pi->adapter;
 743         struct link_config *lc = &pi->link_cfg;
 744
 745         if (lc->pcaps & FW_PORT_CAP32_ANEG) {
 746                 if (fc_conf->autoneg)
 747                         lc->requested_fc |= PAUSE_AUTONEG;
 748                 else
 749                         lc->requested_fc &= ~PAUSE_AUTONEG;
 750         }
 751
 752         if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
 753             (fc_conf->mode & RTE_FC_RX_PAUSE))
 754                 lc->requested_fc |= PAUSE_RX;
 755         else
 756                 lc->requested_fc &= ~PAUSE_RX;
 757
 758         if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
 759             (fc_conf->mode & RTE_FC_TX_PAUSE))
 760                 lc->requested_fc |= PAUSE_TX;
 761         else
 762                 lc->requested_fc &= ~PAUSE_TX;
 763
 764         return t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,
 765                              &pi->link_cfg);
 766 }
 767
 768 const uint32_t *
 769 cxgbe_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
 770 {
 771         static const uint32_t ptypes[] = {
 772                 RTE_PTYPE_L3_IPV4,
 773                 RTE_PTYPE_L3_IPV6,
 774                 RTE_PTYPE_UNKNOWN
 775         };
 776
 777         if (eth_dev->rx_pkt_burst == cxgbe_recv_pkts)
 778                 return ptypes;
 779         return NULL;
 780 }
 781
 782 /* Update RSS hash configuration
 783  */
 784 static int cxgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
 785                                      struct rte_eth_rss_conf *rss_conf)
 786 {
 787         struct port_info *pi = (struct port_info *)(dev->data->dev_private);
 788         struct adapter *adapter = pi->adapter;
 789         int err;
 790
 791         err = cxgbe_write_rss_conf(pi, rss_conf->rss_hf);
 792         if (err)
 793                 return err;
 794
 795         pi->rss_hf = rss_conf->rss_hf;
 796
 797         if (rss_conf->rss_key) {
 798                 u32 key[10], mod_key[10];
 799                 int i, j;
 800
 801                 memcpy(key, rss_conf->rss_key, CXGBE_DEFAULT_RSS_KEY_LEN);
 802
 803                 for (i = 9, j = 0; i >= 0; i--, j++)
 804                         mod_key[j] = cpu_to_be32(key[i]);
 805
 806                 t4_write_rss_key(adapter, mod_key, -1);
 807         }
 808
 809         return 0;
 810 }
 811
 812 /* Get RSS hash configuration
 813  */
 814 static int cxgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 815                                        struct rte_eth_rss_conf *rss_conf)
 816 {
 817         struct port_info *pi = (struct port_info *)(dev->data->dev_private);
 818         struct adapter *adapter = pi->adapter;
 819         u64 rss_hf = 0;
 820         u64 flags = 0;
 821         int err;
 822
 823         err = t4_read_config_vi_rss(adapter, adapter->mbox, pi->viid,
 824                                     &flags, NULL);
 825
 826         if (err)
 827                 return err;
 828
 829         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) {
 830                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
 831                 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
 832                         rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
 833         }
 834
 835         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
 836                 rss_hf |= ETH_RSS_IPV6;
 837
 838         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) {
 839                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
 840                 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
 841                         rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
 842         }
 843
 844         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
 845                 rss_hf |= ETH_RSS_IPV4;
 846
 847         rss_conf->rss_hf = rss_hf;
 848
 849         if (rss_conf->rss_key) {
 850                 u32 key[10], mod_key[10];
 851                 int i, j;
 852
 853                 t4_read_rss_key(adapter, key);
 854
 855                 for (i = 9, j = 0; i >= 0; i--, j++)
 856                         mod_key[j] = be32_to_cpu(key[i]);
 857
 858                 memcpy(rss_conf->rss_key, mod_key, CXGBE_DEFAULT_RSS_KEY_LEN);
 859         }
 860
 861         return 0;
 862 }
 863
 864 static int cxgbe_get_eeprom_length(struct rte_eth_dev *dev)
 865 {
 866         RTE_SET_USED(dev);
 867         return EEPROMSIZE;
 868 }
 869
 870 /**
 871  * eeprom_ptov - translate a physical EEPROM address to virtual
 872  * @phys_addr: the physical EEPROM address
 873  * @fn: the PCI function number
 874  * @sz: size of function-specific area
 875  *
 876  * Translate a physical EEPROM address to virtual.  The first 1K is
 877  * accessed through virtual addresses starting at 31K, the rest is
 878  * accessed through virtual addresses starting at 0.
 879  *
 880  * The mapping is as follows:
 881  * [0..1K) -> [31K..32K)
 882  * [1K..1K+A) -> [31K-A..31K)
 883  * [1K+A..ES) -> [0..ES-A-1K)
 884  *
 885  * where A = @fn * @sz, and ES = EEPROM size.
 886  */
 887 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
 888 {
 889         fn *= sz;
 890         if (phys_addr < 1024)
 891                 return phys_addr + (31 << 10);
 892         if (phys_addr < 1024 + fn)
 893                 return fn + phys_addr - 1024;
 894         if (phys_addr < EEPROMSIZE)
 895                 return phys_addr - 1024 - fn;
 896         if (phys_addr < EEPROMVSIZE)
 897                 return phys_addr - 1024;
 898         return -EINVAL;
 899 }
 900
 901 /* The next two routines implement eeprom read/write from physical addresses.
 902  */
 903 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v)
 904 {
 905         int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
 906
 907         if (vaddr >= 0)
 908                 vaddr = t4_seeprom_read(adap, vaddr, v);
 909         return vaddr < 0 ? vaddr : 0;
 910 }
 911
 912 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v)
 913 {
 914         int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
 915
 916         if (vaddr >= 0)
 917                 vaddr = t4_seeprom_write(adap, vaddr, v);
 918         return vaddr < 0 ? vaddr : 0;
 919 }
 920
 921 #define EEPROM_MAGIC 0x38E2F10C
 922
 923 static int cxgbe_get_eeprom(struct rte_eth_dev *dev,
 924                             struct rte_dev_eeprom_info *e)
 925 {
 926         struct port_info *pi = (struct port_info *)(dev->data->dev_private);
 927         struct adapter *adapter = pi->adapter;
 928         u32 i, err = 0;
 929         u8 *buf = rte_zmalloc(NULL, EEPROMSIZE, 0);
 930
 931         if (!buf)
 932                 return -ENOMEM;
 933
 934         e->magic = EEPROM_MAGIC;
 935         for (i = e->offset & ~3; !err && i < e->offset + e->length; i += 4)
 936                 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]);
 937
 938         if (!err)
 939                 rte_memcpy(e->data, buf + e->offset, e->length);
 940         rte_free(buf);
 941         return err;
 942 }
 943
 944 static int cxgbe_set_eeprom(struct rte_eth_dev *dev,
 945                             struct rte_dev_eeprom_info *eeprom)
 946 {
 947         struct port_info *pi = (struct port_info *)(dev->data->dev_private);
 948         struct adapter *adapter = pi->adapter;
 949         u8 *buf;
 950         int err = 0;
 951         u32 aligned_offset, aligned_len, *p;
 952
 953         if (eeprom->magic != EEPROM_MAGIC)
 954                 return -EINVAL;
 955
 956         aligned_offset = eeprom->offset & ~3;
 957         aligned_len = (eeprom->length + (eeprom->offset & 3) + 3) & ~3;
 958
 959         if (adapter->pf > 0) {
 960                 u32 start = 1024 + adapter->pf * EEPROMPFSIZE;
 961
 962                 if (aligned_offset < start ||
 963                     aligned_offset + aligned_len > start + EEPROMPFSIZE)
 964                         return -EPERM;
 965         }
 966
 967         if (aligned_offset != eeprom->offset || aligned_len != eeprom->length) {
 968                 /* RMW possibly needed for first or last words.
 969                  */
 970                 buf = rte_zmalloc(NULL, aligned_len, 0);
 971                 if (!buf)
 972                         return -ENOMEM;
 973                 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf);
 974                 if (!err && aligned_len > 4)
 975                         err = eeprom_rd_phys(adapter,
 976                                              aligned_offset + aligned_len - 4,
 977                                              (u32 *)&buf[aligned_len - 4]);
 978                 if (err)
 979                         goto out;
 980                 rte_memcpy(buf + (eeprom->offset & 3), eeprom->data,
 981                            eeprom->length);
 982         } else {
 983                 buf = eeprom->data;
 984         }
 985
 986         err = t4_seeprom_wp(adapter, false);
 987         if (err)
 988                 goto out;
 989
 990         for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
 991                 err = eeprom_wr_phys(adapter, aligned_offset, *p);
 992                 aligned_offset += 4;
 993         }
 994
 995         if (!err)
 996                 err = t4_seeprom_wp(adapter, true);
 997 out:
 998         if (buf != eeprom->data)
 999                 rte_free(buf);
1000         return err;
1001 }
1002
1003 static int cxgbe_get_regs_len(struct rte_eth_dev *eth_dev)
1004 {
1005         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
1006         struct adapter *adapter = pi->adapter;
1007
1008         return t4_get_regs_len(adapter) / sizeof(uint32_t);
1009 }
1010
1011 static int cxgbe_get_regs(struct rte_eth_dev *eth_dev,
1012                           struct rte_dev_reg_info *regs)
1013 {
1014         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
1015         struct adapter *adapter = pi->adapter;
1016
1017         regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) |
1018                 (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) |
1019                 (1 << 16);
1020
1021         if (regs->data == NULL) {
1022                 regs->length = cxgbe_get_regs_len(eth_dev);
1023                 regs->width = sizeof(uint32_t);
1024
1025                 return 0;
1026         }
1027
1028         t4_get_regs(adapter, regs->data, (regs->length * sizeof(uint32_t)));
1029
1030         return 0;
1031 }
1032
1033 static const struct eth_dev_ops cxgbe_eth_dev_ops = {
1034         .dev_start              = cxgbe_dev_start,
1035         .dev_stop               = cxgbe_dev_stop,
1036         .dev_close              = cxgbe_dev_close,
1037         .promiscuous_enable     = cxgbe_dev_promiscuous_enable,
1038         .promiscuous_disable    = cxgbe_dev_promiscuous_disable,
1039         .allmulticast_enable    = cxgbe_dev_allmulticast_enable,
1040         .allmulticast_disable   = cxgbe_dev_allmulticast_disable,
1041         .dev_configure          = cxgbe_dev_configure,
1042         .dev_infos_get          = cxgbe_dev_info_get,
1043         .dev_supported_ptypes_get = cxgbe_dev_supported_ptypes_get,
1044         .link_update            = cxgbe_dev_link_update,
1045         .mtu_set                = cxgbe_dev_mtu_set,
1046         .tx_queue_setup         = cxgbe_dev_tx_queue_setup,
1047         .tx_queue_start         = cxgbe_dev_tx_queue_start,
1048         .tx_queue_stop          = cxgbe_dev_tx_queue_stop,
1049         .tx_queue_release       = cxgbe_dev_tx_queue_release,
1050         .rx_queue_setup         = cxgbe_dev_rx_queue_setup,
1051         .rx_queue_start         = cxgbe_dev_rx_queue_start,
1052         .rx_queue_stop          = cxgbe_dev_rx_queue_stop,
1053         .rx_queue_release       = cxgbe_dev_rx_queue_release,
1054         .stats_get              = cxgbe_dev_stats_get,
1055         .stats_reset            = cxgbe_dev_stats_reset,
1056         .flow_ctrl_get          = cxgbe_flow_ctrl_get,
1057         .flow_ctrl_set          = cxgbe_flow_ctrl_set,
1058         .get_eeprom_length      = cxgbe_get_eeprom_length,
1059         .get_eeprom             = cxgbe_get_eeprom,
1060         .set_eeprom             = cxgbe_set_eeprom,
1061         .get_reg                = cxgbe_get_regs,
1062         .rss_hash_update        = cxgbe_dev_rss_hash_update,
1063         .rss_hash_conf_get      = cxgbe_dev_rss_hash_conf_get,
1064 };
1065
1066 /*
1067  * Initialize driver
1068  * It returns 0 on success.
1069  */
1070 static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev)
1071 {
1072         struct rte_pci_device *pci_dev;
1073         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
1074         struct adapter *adapter = NULL;
1075         char name[RTE_ETH_NAME_MAX_LEN];
1076         int err = 0;
1077
1078         CXGBE_FUNC_TRACE();
1079
1080         eth_dev->dev_ops = &cxgbe_eth_dev_ops;
1081         eth_dev->rx_pkt_burst = &cxgbe_recv_pkts;
1082         eth_dev->tx_pkt_burst = &cxgbe_xmit_pkts;
1083         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1084
1085         /* for secondary processes, we attach to ethdevs allocated by primary
1086          * and do minimal initialization.
1087          */
1088         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1089                 int i;
1090
1091                 for (i = 1; i < MAX_NPORTS; i++) {
1092                         struct rte_eth_dev *rest_eth_dev;
1093                         char namei[RTE_ETH_NAME_MAX_LEN];
1094
1095                         snprintf(namei, sizeof(namei), "%s_%d",
1096                                  pci_dev->device.name, i);
1097                         rest_eth_dev = rte_eth_dev_attach_secondary(namei);
1098                         if (rest_eth_dev) {
1099                                 rest_eth_dev->device = &pci_dev->device;
1100                                 rest_eth_dev->dev_ops =
1101                                         eth_dev->dev_ops;
1102                                 rest_eth_dev->rx_pkt_burst =
1103                                         eth_dev->rx_pkt_burst;
1104                                 rest_eth_dev->tx_pkt_burst =
1105                                         eth_dev->tx_pkt_burst;
1106                         }
1107                 }
1108                 return 0;
1109         }
1110
1111         snprintf(name, sizeof(name), "cxgbeadapter%d", eth_dev->data->port_id);
1112         adapter = rte_zmalloc(name, sizeof(*adapter), 0);
1113         if (!adapter)
1114                 return -1;
1115
1116         adapter->use_unpacked_mode = 1;
1117         adapter->regs = (void *)pci_dev->mem_resource[0].addr;
1118         if (!adapter->regs) {
1119                 dev_err(adapter, "%s: cannot map device registers\n", __func__);
1120                 err = -ENOMEM;
1121                 goto out_free_adapter;
1122         }
1123         adapter->pdev = pci_dev;
1124         adapter->eth_dev = eth_dev;
1125         pi->adapter = adapter;
1126
1127         err = cxgbe_probe(adapter);
1128         if (err) {
1129                 dev_err(adapter, "%s: cxgbe probe failed with err %d\n",
1130                         __func__, err);
1131                 goto out_free_adapter;
1132         }
1133
1134         return 0;
1135
1136 out_free_adapter:
1137         rte_free(adapter);
1138         return err;
1139 }
1140
1141 static int eth_cxgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1142         struct rte_pci_device *pci_dev)
1143 {
1144         return rte_eth_dev_pci_generic_probe(pci_dev,
1145                 sizeof(struct port_info), eth_cxgbe_dev_init);
1146 }
1147
1148 static int eth_cxgbe_pci_remove(struct rte_pci_device *pci_dev)
1149 {
1150         return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
1151 }
1152
1153 static struct rte_pci_driver rte_cxgbe_pmd = {
1154         .id_table = cxgb4_pci_tbl,
1155         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1156         .probe = eth_cxgbe_pci_probe,
1157         .remove = eth_cxgbe_pci_remove,
1158 };
1159
1160 RTE_PMD_REGISTER_PCI(net_cxgbe, rte_cxgbe_pmd);
1161 RTE_PMD_REGISTER_PCI_TABLE(net_cxgbe, cxgb4_pci_tbl);
1162 RTE_PMD_REGISTER_KMOD_DEP(net_cxgbe, "* igb_uio | uio_pci_generic | vfio-pci");