4 * Copyright(c) 2014-2015 Chelsio Communications.
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8 * modification, are permitted provided that the following conditions
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12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Chelsio Communications nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
42 #include <netinet/in.h>
44 #include <rte_byteorder.h>
45 #include <rte_common.h>
46 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
55 #include <rte_tailq.h>
57 #include <rte_alarm.h>
58 #include <rte_ether.h>
59 #include <rte_ethdev.h>
60 #include <rte_atomic.h>
61 #include <rte_malloc.h>
62 #include <rte_random.h>
68 * Macros needed to support the PCI Device ID Table ...
70 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
71 static struct rte_pci_id cxgb4_pci_tbl[] = {
72 #define CH_PCI_DEVICE_ID_FUNCTION 0x4
74 #define PCI_VENDOR_ID_CHELSIO 0x1425
76 #define CH_PCI_ID_TABLE_ENTRY(devid) \
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CHELSIO, (devid)) }
79 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
84 *... and the PCI ID Table itself ...
86 #include "t4_pci_id_tbl.h"
88 static uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
91 struct sge_eth_txq *txq = (struct sge_eth_txq *)tx_queue;
92 uint16_t pkts_sent, pkts_remain;
93 uint16_t total_sent = 0;
96 CXGBE_DEBUG_TX(adapter, "%s: txq = %p; tx_pkts = %p; nb_pkts = %d\n",
97 __func__, txq, tx_pkts, nb_pkts);
99 t4_os_lock(&txq->txq_lock);
100 /* free up desc from already completed tx */
101 reclaim_completed_tx(&txq->q);
102 while (total_sent < nb_pkts) {
103 pkts_remain = nb_pkts - total_sent;
105 for (pkts_sent = 0; pkts_sent < pkts_remain; pkts_sent++) {
106 ret = t4_eth_xmit(txq, tx_pkts[total_sent + pkts_sent]);
112 total_sent += pkts_sent;
113 /* reclaim as much as possible */
114 reclaim_completed_tx(&txq->q);
117 t4_os_unlock(&txq->txq_lock);
121 static uint16_t cxgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
124 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)rx_queue;
125 unsigned int work_done;
127 CXGBE_DEBUG_RX(adapter, "%s: rxq->rspq.cntxt_id = %u; nb_pkts = %d\n",
128 __func__, rxq->rspq.cntxt_id, nb_pkts);
130 if (cxgbe_poll(&rxq->rspq, rx_pkts, (unsigned int)nb_pkts, &work_done))
131 dev_err(adapter, "error in cxgbe poll\n");
133 CXGBE_DEBUG_RX(adapter, "%s: work_done = %u\n", __func__, work_done);
137 static void cxgbe_dev_info_get(struct rte_eth_dev *eth_dev,
138 struct rte_eth_dev_info *device_info)
140 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
141 struct adapter *adapter = pi->adapter;
142 int max_queues = adapter->sge.max_ethqsets / adapter->params.nports;
144 static const struct rte_eth_desc_lim cxgbe_desc_lim = {
145 .nb_max = CXGBE_MAX_RING_DESC_SIZE,
146 .nb_min = CXGBE_MIN_RING_DESC_SIZE,
150 device_info->min_rx_bufsize = CXGBE_MIN_RX_BUFSIZE;
151 device_info->max_rx_pktlen = CXGBE_MAX_RX_PKTLEN;
152 device_info->max_rx_queues = max_queues;
153 device_info->max_tx_queues = max_queues;
154 device_info->max_mac_addrs = 1;
155 /* XXX: For now we support one MAC/port */
156 device_info->max_vfs = adapter->params.arch.vfcount;
157 device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */
159 device_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
160 DEV_RX_OFFLOAD_IPV4_CKSUM |
161 DEV_RX_OFFLOAD_UDP_CKSUM |
162 DEV_RX_OFFLOAD_TCP_CKSUM;
164 device_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
165 DEV_TX_OFFLOAD_IPV4_CKSUM |
166 DEV_TX_OFFLOAD_UDP_CKSUM |
167 DEV_TX_OFFLOAD_TCP_CKSUM |
168 DEV_TX_OFFLOAD_TCP_TSO;
170 device_info->reta_size = pi->rss_size;
172 device_info->rx_desc_lim = cxgbe_desc_lim;
173 device_info->tx_desc_lim = cxgbe_desc_lim;
176 static void cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
178 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
179 struct adapter *adapter = pi->adapter;
181 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
182 1, -1, 1, -1, false);
185 static void cxgbe_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
187 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
188 struct adapter *adapter = pi->adapter;
190 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
191 0, -1, 1, -1, false);
194 static void cxgbe_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
196 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
197 struct adapter *adapter = pi->adapter;
199 /* TODO: address filters ?? */
201 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
202 -1, 1, 1, -1, false);
205 static void cxgbe_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
207 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
208 struct adapter *adapter = pi->adapter;
210 /* TODO: address filters ?? */
212 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
213 -1, 0, 1, -1, false);
216 static int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev,
217 __rte_unused int wait_to_complete)
219 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
220 struct adapter *adapter = pi->adapter;
221 struct sge *s = &adapter->sge;
222 struct rte_eth_link *old_link = ð_dev->data->dev_link;
223 unsigned int work_done, budget = 4;
225 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
226 if (old_link->link_status == pi->link_cfg.link_ok)
227 return -1; /* link not changed */
229 eth_dev->data->dev_link.link_status = pi->link_cfg.link_ok;
230 eth_dev->data->dev_link.link_duplex = ETH_LINK_FULL_DUPLEX;
231 eth_dev->data->dev_link.link_speed = pi->link_cfg.speed;
233 /* link has changed */
237 static int cxgbe_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
239 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
240 struct adapter *adapter = pi->adapter;
241 struct rte_eth_dev_info dev_info;
243 uint16_t new_mtu = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
245 cxgbe_dev_info_get(eth_dev, &dev_info);
247 /* Must accommodate at least ETHER_MIN_MTU */
248 if ((new_mtu < ETHER_MIN_MTU) || (new_mtu > dev_info.max_rx_pktlen))
251 /* set to jumbo mode if needed */
252 if (new_mtu > ETHER_MAX_LEN)
253 eth_dev->data->dev_conf.rxmode.jumbo_frame = 1;
255 eth_dev->data->dev_conf.rxmode.jumbo_frame = 0;
257 err = t4_set_rxmode(adapter, adapter->mbox, pi->viid, new_mtu, -1, -1,
260 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_mtu;
265 static int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev,
266 uint16_t tx_queue_id);
267 static int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev,
268 uint16_t tx_queue_id);
269 static void cxgbe_dev_tx_queue_release(void *q);
270 static void cxgbe_dev_rx_queue_release(void *q);
275 static void cxgbe_dev_close(struct rte_eth_dev *eth_dev)
277 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
278 struct adapter *adapter = pi->adapter;
283 if (!(adapter->flags & FULL_INIT_DONE))
289 * We clear queues only if both tx and rx path of the port
292 t4_sge_eth_clear_queues(pi);
294 /* See if all ports are down */
295 for_each_port(adapter, i) {
296 pi = adap2pinfo(adapter, i);
298 * Skip first port of the adapter since it will be closed
303 dev_down += (pi->eth_dev->data->dev_started == 0) ? 1 : 0;
306 /* If rest of the ports are stopped, then free up resources */
307 if (dev_down == (adapter->params.nports - 1))
308 cxgbe_close(adapter);
312 * It returns 0 on success.
314 static int cxgbe_dev_start(struct rte_eth_dev *eth_dev)
316 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
317 struct adapter *adapter = pi->adapter;
323 * If we don't have a connection to the firmware there's nothing we
326 if (!(adapter->flags & FW_OK)) {
331 if (!(adapter->flags & FULL_INIT_DONE)) {
332 err = cxgbe_up(adapter);
341 for (i = 0; i < pi->n_tx_qsets; i++) {
342 err = cxgbe_dev_tx_queue_start(eth_dev, i);
347 for (i = 0; i < pi->n_rx_qsets; i++) {
348 err = cxgbe_dev_rx_queue_start(eth_dev, i);
353 err = link_start(pi);
362 * Stop device: disable rx and tx functions to allow for reconfiguring.
364 static void cxgbe_dev_stop(struct rte_eth_dev *eth_dev)
366 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
367 struct adapter *adapter = pi->adapter;
371 if (!(adapter->flags & FULL_INIT_DONE))
377 * We clear queues only if both tx and rx path of the port
380 t4_sge_eth_clear_queues(pi);
383 static int cxgbe_dev_configure(struct rte_eth_dev *eth_dev)
385 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
386 struct adapter *adapter = pi->adapter;
391 if (!(adapter->flags & FW_QUEUE_BOUND)) {
392 err = setup_sge_fwevtq(adapter);
395 adapter->flags |= FW_QUEUE_BOUND;
398 err = cfg_queue_count(eth_dev);
405 static int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev,
406 uint16_t tx_queue_id)
408 struct sge_eth_txq *txq = (struct sge_eth_txq *)
409 (eth_dev->data->tx_queues[tx_queue_id]);
411 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
413 return t4_sge_eth_txq_start(txq);
416 static int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev,
417 uint16_t tx_queue_id)
419 struct sge_eth_txq *txq = (struct sge_eth_txq *)
420 (eth_dev->data->tx_queues[tx_queue_id]);
422 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
424 return t4_sge_eth_txq_stop(txq);
427 static int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev,
428 uint16_t queue_idx, uint16_t nb_desc,
429 unsigned int socket_id,
430 const struct rte_eth_txconf *tx_conf)
432 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
433 struct adapter *adapter = pi->adapter;
434 struct sge *s = &adapter->sge;
435 struct sge_eth_txq *txq = &s->ethtxq[pi->first_qset + queue_idx];
437 unsigned int temp_nb_desc;
439 RTE_SET_USED(tx_conf);
441 dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n",
442 __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc,
443 socket_id, pi->first_qset);
445 /* Free up the existing queue */
446 if (eth_dev->data->tx_queues[queue_idx]) {
447 cxgbe_dev_tx_queue_release(eth_dev->data->tx_queues[queue_idx]);
448 eth_dev->data->tx_queues[queue_idx] = NULL;
451 eth_dev->data->tx_queues[queue_idx] = (void *)txq;
455 * nb_desc should be > 1023 and <= CXGBE_MAX_RING_DESC_SIZE
457 temp_nb_desc = nb_desc;
458 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
459 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
460 __func__, CXGBE_MIN_RING_DESC_SIZE,
461 CXGBE_DEFAULT_TX_DESC_SIZE);
462 temp_nb_desc = CXGBE_DEFAULT_TX_DESC_SIZE;
463 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
464 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
465 __func__, CXGBE_MIN_RING_DESC_SIZE,
466 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_TX_DESC_SIZE);
470 txq->q.size = temp_nb_desc;
472 err = t4_sge_alloc_eth_txq(adapter, txq, eth_dev, queue_idx,
473 s->fw_evtq.cntxt_id, socket_id);
475 dev_debug(adapter, "%s: txq->q.cntxt_id= %d err = %d\n",
476 __func__, txq->q.cntxt_id, err);
481 static void cxgbe_dev_tx_queue_release(void *q)
483 struct sge_eth_txq *txq = (struct sge_eth_txq *)q;
486 struct port_info *pi = (struct port_info *)
487 (txq->eth_dev->data->dev_private);
488 struct adapter *adap = pi->adapter;
490 dev_debug(adapter, "%s: pi->port_id = %d; tx_queue_id = %d\n",
491 __func__, pi->port_id, txq->q.cntxt_id);
493 t4_sge_eth_txq_release(adap, txq);
497 static int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev,
498 uint16_t rx_queue_id)
500 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
501 struct adapter *adap = pi->adapter;
504 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
505 __func__, pi->port_id, rx_queue_id);
507 q = eth_dev->data->rx_queues[rx_queue_id];
508 return t4_sge_eth_rxq_start(adap, q);
511 static int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev,
512 uint16_t rx_queue_id)
514 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
515 struct adapter *adap = pi->adapter;
518 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
519 __func__, pi->port_id, rx_queue_id);
521 q = eth_dev->data->rx_queues[rx_queue_id];
522 return t4_sge_eth_rxq_stop(adap, q);
525 static int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev,
526 uint16_t queue_idx, uint16_t nb_desc,
527 unsigned int socket_id,
528 const struct rte_eth_rxconf *rx_conf,
529 struct rte_mempool *mp)
531 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
532 struct adapter *adapter = pi->adapter;
533 struct sge *s = &adapter->sge;
534 struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_qset + queue_idx];
537 unsigned int temp_nb_desc;
538 struct rte_eth_dev_info dev_info;
539 unsigned int pkt_len = eth_dev->data->dev_conf.rxmode.max_rx_pkt_len;
541 RTE_SET_USED(rx_conf);
543 dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n",
544 __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc,
547 cxgbe_dev_info_get(eth_dev, &dev_info);
549 /* Must accommodate at least ETHER_MIN_MTU */
550 if ((pkt_len < dev_info.min_rx_bufsize) ||
551 (pkt_len > dev_info.max_rx_pktlen)) {
552 dev_err(adap, "%s: max pkt len must be > %d and <= %d\n",
553 __func__, dev_info.min_rx_bufsize,
554 dev_info.max_rx_pktlen);
558 /* Free up the existing queue */
559 if (eth_dev->data->rx_queues[queue_idx]) {
560 cxgbe_dev_rx_queue_release(eth_dev->data->rx_queues[queue_idx]);
561 eth_dev->data->rx_queues[queue_idx] = NULL;
564 eth_dev->data->rx_queues[queue_idx] = (void *)rxq;
568 * nb_desc should be > 0 and <= CXGBE_MAX_RING_DESC_SIZE
570 temp_nb_desc = nb_desc;
571 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
572 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
573 __func__, CXGBE_MIN_RING_DESC_SIZE,
574 CXGBE_DEFAULT_RX_DESC_SIZE);
575 temp_nb_desc = CXGBE_DEFAULT_RX_DESC_SIZE;
576 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
577 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
578 __func__, CXGBE_MIN_RING_DESC_SIZE,
579 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_RX_DESC_SIZE);
583 rxq->rspq.size = temp_nb_desc;
584 if ((&rxq->fl) != NULL)
585 rxq->fl.size = temp_nb_desc;
587 /* Set to jumbo mode if necessary */
588 if (pkt_len > ETHER_MAX_LEN)
589 eth_dev->data->dev_conf.rxmode.jumbo_frame = 1;
591 eth_dev->data->dev_conf.rxmode.jumbo_frame = 0;
593 err = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx,
594 &rxq->fl, t4_ethrx_handler,
595 t4_get_mps_bg_map(adapter, pi->tx_chan), mp,
596 queue_idx, socket_id);
598 dev_debug(adapter, "%s: err = %d; port_id = %d; cntxt_id = %u\n",
599 __func__, err, pi->port_id, rxq->rspq.cntxt_id);
603 static void cxgbe_dev_rx_queue_release(void *q)
605 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)q;
606 struct sge_rspq *rq = &rxq->rspq;
609 struct port_info *pi = (struct port_info *)
610 (rq->eth_dev->data->dev_private);
611 struct adapter *adap = pi->adapter;
613 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
614 __func__, pi->port_id, rxq->rspq.cntxt_id);
616 t4_sge_eth_rxq_release(adap, rxq);
621 * Get port statistics.
623 static void cxgbe_dev_stats_get(struct rte_eth_dev *eth_dev,
624 struct rte_eth_stats *eth_stats)
626 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
627 struct adapter *adapter = pi->adapter;
628 struct sge *s = &adapter->sge;
629 struct port_stats ps;
632 cxgbe_stats_get(pi, &ps);
635 eth_stats->ipackets = ps.rx_frames;
636 eth_stats->ibytes = ps.rx_octets;
637 eth_stats->imcasts = ps.rx_mcast_frames;
638 eth_stats->imissed = ps.rx_ovflow0 + ps.rx_ovflow1 +
639 ps.rx_ovflow2 + ps.rx_ovflow3 +
640 ps.rx_trunc0 + ps.rx_trunc1 +
641 ps.rx_trunc2 + ps.rx_trunc3;
642 eth_stats->ibadcrc = ps.rx_fcs_err;
643 eth_stats->ibadlen = ps.rx_jabber + ps.rx_too_long + ps.rx_runt;
644 eth_stats->ierrors = ps.rx_symbol_err + eth_stats->ibadcrc +
645 eth_stats->ibadlen + ps.rx_len_err +
647 eth_stats->rx_pause_xon = ps.rx_pause;
650 eth_stats->opackets = ps.tx_frames;
651 eth_stats->obytes = ps.tx_octets;
652 eth_stats->oerrors = ps.tx_error_frames;
653 eth_stats->tx_pause_xon = ps.tx_pause;
655 for (i = 0; i < pi->n_rx_qsets; i++) {
656 struct sge_eth_rxq *rxq =
657 &s->ethrxq[pi->first_qset + i];
659 eth_stats->q_ipackets[i] = rxq->stats.pkts;
660 eth_stats->q_ibytes[i] = rxq->stats.rx_bytes;
663 for (i = 0; i < pi->n_tx_qsets; i++) {
664 struct sge_eth_txq *txq =
665 &s->ethtxq[pi->first_qset + i];
667 eth_stats->q_opackets[i] = txq->stats.pkts;
668 eth_stats->q_obytes[i] = txq->stats.tx_bytes;
669 eth_stats->q_errors[i] = txq->stats.mapping_err;
674 * Reset port statistics.
676 static void cxgbe_dev_stats_reset(struct rte_eth_dev *eth_dev)
678 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
679 struct adapter *adapter = pi->adapter;
680 struct sge *s = &adapter->sge;
683 cxgbe_stats_reset(pi);
684 for (i = 0; i < pi->n_rx_qsets; i++) {
685 struct sge_eth_rxq *rxq =
686 &s->ethrxq[pi->first_qset + i];
689 rxq->stats.rx_bytes = 0;
691 for (i = 0; i < pi->n_tx_qsets; i++) {
692 struct sge_eth_txq *txq =
693 &s->ethtxq[pi->first_qset + i];
696 txq->stats.tx_bytes = 0;
697 txq->stats.mapping_err = 0;
701 static int cxgbe_flow_ctrl_get(struct rte_eth_dev *eth_dev,
702 struct rte_eth_fc_conf *fc_conf)
704 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
705 struct link_config *lc = &pi->link_cfg;
706 int rx_pause, tx_pause;
708 fc_conf->autoneg = lc->fc & PAUSE_AUTONEG;
709 rx_pause = lc->fc & PAUSE_RX;
710 tx_pause = lc->fc & PAUSE_TX;
712 if (rx_pause && tx_pause)
713 fc_conf->mode = RTE_FC_FULL;
715 fc_conf->mode = RTE_FC_RX_PAUSE;
717 fc_conf->mode = RTE_FC_TX_PAUSE;
719 fc_conf->mode = RTE_FC_NONE;
723 static int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev,
724 struct rte_eth_fc_conf *fc_conf)
726 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
727 struct adapter *adapter = pi->adapter;
728 struct link_config *lc = &pi->link_cfg;
730 if (lc->supported & FW_PORT_CAP_ANEG) {
731 if (fc_conf->autoneg)
732 lc->requested_fc |= PAUSE_AUTONEG;
734 lc->requested_fc &= ~PAUSE_AUTONEG;
737 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
738 (fc_conf->mode & RTE_FC_RX_PAUSE))
739 lc->requested_fc |= PAUSE_RX;
741 lc->requested_fc &= ~PAUSE_RX;
743 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
744 (fc_conf->mode & RTE_FC_TX_PAUSE))
745 lc->requested_fc |= PAUSE_TX;
747 lc->requested_fc &= ~PAUSE_TX;
749 return t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,
753 static struct eth_dev_ops cxgbe_eth_dev_ops = {
754 .dev_start = cxgbe_dev_start,
755 .dev_stop = cxgbe_dev_stop,
756 .dev_close = cxgbe_dev_close,
757 .promiscuous_enable = cxgbe_dev_promiscuous_enable,
758 .promiscuous_disable = cxgbe_dev_promiscuous_disable,
759 .allmulticast_enable = cxgbe_dev_allmulticast_enable,
760 .allmulticast_disable = cxgbe_dev_allmulticast_disable,
761 .dev_configure = cxgbe_dev_configure,
762 .dev_infos_get = cxgbe_dev_info_get,
763 .link_update = cxgbe_dev_link_update,
764 .mtu_set = cxgbe_dev_mtu_set,
765 .tx_queue_setup = cxgbe_dev_tx_queue_setup,
766 .tx_queue_start = cxgbe_dev_tx_queue_start,
767 .tx_queue_stop = cxgbe_dev_tx_queue_stop,
768 .tx_queue_release = cxgbe_dev_tx_queue_release,
769 .rx_queue_setup = cxgbe_dev_rx_queue_setup,
770 .rx_queue_start = cxgbe_dev_rx_queue_start,
771 .rx_queue_stop = cxgbe_dev_rx_queue_stop,
772 .rx_queue_release = cxgbe_dev_rx_queue_release,
773 .stats_get = cxgbe_dev_stats_get,
774 .stats_reset = cxgbe_dev_stats_reset,
775 .flow_ctrl_get = cxgbe_flow_ctrl_get,
776 .flow_ctrl_set = cxgbe_flow_ctrl_set,
781 * It returns 0 on success.
783 static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev)
785 struct rte_pci_device *pci_dev;
786 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
787 struct adapter *adapter = NULL;
788 char name[RTE_ETH_NAME_MAX_LEN];
793 eth_dev->dev_ops = &cxgbe_eth_dev_ops;
794 eth_dev->rx_pkt_burst = &cxgbe_recv_pkts;
795 eth_dev->tx_pkt_burst = &cxgbe_xmit_pkts;
797 /* for secondary processes, we don't initialise any further as primary
798 * has already done this work.
800 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
803 pci_dev = eth_dev->pci_dev;
805 rte_eth_copy_pci_info(eth_dev, pci_dev);
807 snprintf(name, sizeof(name), "cxgbeadapter%d", eth_dev->data->port_id);
808 adapter = rte_zmalloc(name, sizeof(*adapter), 0);
812 adapter->use_unpacked_mode = 1;
813 adapter->regs = (void *)pci_dev->mem_resource[0].addr;
814 if (!adapter->regs) {
815 dev_err(adapter, "%s: cannot map device registers\n", __func__);
817 goto out_free_adapter;
819 adapter->pdev = pci_dev;
820 adapter->eth_dev = eth_dev;
821 pi->adapter = adapter;
823 err = cxgbe_probe(adapter);
825 dev_err(adapter, "%s: cxgbe probe failed with err %d\n",
832 static struct eth_driver rte_cxgbe_pmd = {
834 .name = "rte_cxgbe_pmd",
835 .id_table = cxgb4_pci_tbl,
836 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
838 .eth_dev_init = eth_cxgbe_dev_init,
839 .dev_private_size = sizeof(struct port_info),
843 * Driver initialization routine.
844 * Invoked once at EAL init time.
845 * Register itself as the [Poll Mode] Driver of PCI CXGBE devices.
847 static int rte_cxgbe_pmd_init(const char *name __rte_unused,
848 const char *params __rte_unused)
852 rte_eth_driver_register(&rte_cxgbe_pmd);
856 static struct rte_driver rte_cxgbe_driver = {
857 .name = "cxgbe_driver",
859 .init = rte_cxgbe_pmd_init,
862 PMD_REGISTER_DRIVER(rte_cxgbe_driver);