4 * Copyright(c) 2014-2016 Chelsio Communications.
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8 * modification, are permitted provided that the following conditions
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12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Chelsio Communications nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
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22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
42 #include <netinet/in.h>
44 #include <rte_byteorder.h>
45 #include <rte_common.h>
46 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
55 #include <rte_tailq.h>
57 #include <rte_alarm.h>
58 #include <rte_ether.h>
59 #include <rte_ethdev.h>
60 #include <rte_atomic.h>
61 #include <rte_malloc.h>
62 #include <rte_random.h>
68 * Macros needed to support the PCI Device ID Table ...
70 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
71 static struct rte_pci_id cxgb4_pci_tbl[] = {
72 #define CH_PCI_DEVICE_ID_FUNCTION 0x4
74 #define PCI_VENDOR_ID_CHELSIO 0x1425
76 #define CH_PCI_ID_TABLE_ENTRY(devid) \
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CHELSIO, (devid)) }
79 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
84 *... and the PCI ID Table itself ...
86 #include "t4_pci_id_tbl.h"
88 static uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
91 struct sge_eth_txq *txq = (struct sge_eth_txq *)tx_queue;
92 uint16_t pkts_sent, pkts_remain;
93 uint16_t total_sent = 0;
96 CXGBE_DEBUG_TX(adapter, "%s: txq = %p; tx_pkts = %p; nb_pkts = %d\n",
97 __func__, txq, tx_pkts, nb_pkts);
99 t4_os_lock(&txq->txq_lock);
100 /* free up desc from already completed tx */
101 reclaim_completed_tx(&txq->q);
102 while (total_sent < nb_pkts) {
103 pkts_remain = nb_pkts - total_sent;
105 for (pkts_sent = 0; pkts_sent < pkts_remain; pkts_sent++) {
106 ret = t4_eth_xmit(txq, tx_pkts[total_sent + pkts_sent]);
112 total_sent += pkts_sent;
113 /* reclaim as much as possible */
114 reclaim_completed_tx(&txq->q);
117 t4_os_unlock(&txq->txq_lock);
121 static uint16_t cxgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
124 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)rx_queue;
125 unsigned int work_done;
127 CXGBE_DEBUG_RX(adapter, "%s: rxq->rspq.cntxt_id = %u; nb_pkts = %d\n",
128 __func__, rxq->rspq.cntxt_id, nb_pkts);
130 if (cxgbe_poll(&rxq->rspq, rx_pkts, (unsigned int)nb_pkts, &work_done))
131 dev_err(adapter, "error in cxgbe poll\n");
133 CXGBE_DEBUG_RX(adapter, "%s: work_done = %u\n", __func__, work_done);
137 static void cxgbe_dev_info_get(struct rte_eth_dev *eth_dev,
138 struct rte_eth_dev_info *device_info)
140 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
141 struct adapter *adapter = pi->adapter;
142 int max_queues = adapter->sge.max_ethqsets / adapter->params.nports;
144 static const struct rte_eth_desc_lim cxgbe_desc_lim = {
145 .nb_max = CXGBE_MAX_RING_DESC_SIZE,
146 .nb_min = CXGBE_MIN_RING_DESC_SIZE,
150 device_info->min_rx_bufsize = CXGBE_MIN_RX_BUFSIZE;
151 device_info->max_rx_pktlen = CXGBE_MAX_RX_PKTLEN;
152 device_info->max_rx_queues = max_queues;
153 device_info->max_tx_queues = max_queues;
154 device_info->max_mac_addrs = 1;
155 /* XXX: For now we support one MAC/port */
156 device_info->max_vfs = adapter->params.arch.vfcount;
157 device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */
159 device_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
160 DEV_RX_OFFLOAD_IPV4_CKSUM |
161 DEV_RX_OFFLOAD_UDP_CKSUM |
162 DEV_RX_OFFLOAD_TCP_CKSUM;
164 device_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
165 DEV_TX_OFFLOAD_IPV4_CKSUM |
166 DEV_TX_OFFLOAD_UDP_CKSUM |
167 DEV_TX_OFFLOAD_TCP_CKSUM |
168 DEV_TX_OFFLOAD_TCP_TSO;
170 device_info->reta_size = pi->rss_size;
172 device_info->rx_desc_lim = cxgbe_desc_lim;
173 device_info->tx_desc_lim = cxgbe_desc_lim;
174 device_info->speed_capa = ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G;
177 static void cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
179 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
180 struct adapter *adapter = pi->adapter;
182 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
183 1, -1, 1, -1, false);
186 static void cxgbe_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
188 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
189 struct adapter *adapter = pi->adapter;
191 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
192 0, -1, 1, -1, false);
195 static void cxgbe_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
197 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
198 struct adapter *adapter = pi->adapter;
200 /* TODO: address filters ?? */
202 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
203 -1, 1, 1, -1, false);
206 static void cxgbe_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
208 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
209 struct adapter *adapter = pi->adapter;
211 /* TODO: address filters ?? */
213 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
214 -1, 0, 1, -1, false);
217 static int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev,
218 __rte_unused int wait_to_complete)
220 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
221 struct adapter *adapter = pi->adapter;
222 struct sge *s = &adapter->sge;
223 struct rte_eth_link *old_link = ð_dev->data->dev_link;
224 unsigned int work_done, budget = 4;
226 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
227 if (old_link->link_status == pi->link_cfg.link_ok)
228 return -1; /* link not changed */
230 eth_dev->data->dev_link.link_status = pi->link_cfg.link_ok;
231 eth_dev->data->dev_link.link_duplex = ETH_LINK_FULL_DUPLEX;
232 eth_dev->data->dev_link.link_speed = pi->link_cfg.speed;
234 /* link has changed */
238 static int cxgbe_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
240 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
241 struct adapter *adapter = pi->adapter;
242 struct rte_eth_dev_info dev_info;
244 uint16_t new_mtu = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
246 cxgbe_dev_info_get(eth_dev, &dev_info);
248 /* Must accommodate at least ETHER_MIN_MTU */
249 if ((new_mtu < ETHER_MIN_MTU) || (new_mtu > dev_info.max_rx_pktlen))
252 /* set to jumbo mode if needed */
253 if (new_mtu > ETHER_MAX_LEN)
254 eth_dev->data->dev_conf.rxmode.jumbo_frame = 1;
256 eth_dev->data->dev_conf.rxmode.jumbo_frame = 0;
258 err = t4_set_rxmode(adapter, adapter->mbox, pi->viid, new_mtu, -1, -1,
261 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_mtu;
266 static int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev,
267 uint16_t tx_queue_id);
268 static int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev,
269 uint16_t tx_queue_id);
270 static void cxgbe_dev_tx_queue_release(void *q);
271 static void cxgbe_dev_rx_queue_release(void *q);
276 static void cxgbe_dev_close(struct rte_eth_dev *eth_dev)
278 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
279 struct adapter *adapter = pi->adapter;
284 if (!(adapter->flags & FULL_INIT_DONE))
290 * We clear queues only if both tx and rx path of the port
293 t4_sge_eth_clear_queues(pi);
295 /* See if all ports are down */
296 for_each_port(adapter, i) {
297 pi = adap2pinfo(adapter, i);
299 * Skip first port of the adapter since it will be closed
304 dev_down += (pi->eth_dev->data->dev_started == 0) ? 1 : 0;
307 /* If rest of the ports are stopped, then free up resources */
308 if (dev_down == (adapter->params.nports - 1))
309 cxgbe_close(adapter);
313 * It returns 0 on success.
315 static int cxgbe_dev_start(struct rte_eth_dev *eth_dev)
317 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
318 struct adapter *adapter = pi->adapter;
324 * If we don't have a connection to the firmware there's nothing we
327 if (!(adapter->flags & FW_OK)) {
332 if (!(adapter->flags & FULL_INIT_DONE)) {
333 err = cxgbe_up(adapter);
342 for (i = 0; i < pi->n_tx_qsets; i++) {
343 err = cxgbe_dev_tx_queue_start(eth_dev, i);
348 for (i = 0; i < pi->n_rx_qsets; i++) {
349 err = cxgbe_dev_rx_queue_start(eth_dev, i);
354 err = link_start(pi);
363 * Stop device: disable rx and tx functions to allow for reconfiguring.
365 static void cxgbe_dev_stop(struct rte_eth_dev *eth_dev)
367 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
368 struct adapter *adapter = pi->adapter;
372 if (!(adapter->flags & FULL_INIT_DONE))
378 * We clear queues only if both tx and rx path of the port
381 t4_sge_eth_clear_queues(pi);
384 static int cxgbe_dev_configure(struct rte_eth_dev *eth_dev)
386 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
387 struct adapter *adapter = pi->adapter;
392 if (!(adapter->flags & FW_QUEUE_BOUND)) {
393 err = setup_sge_fwevtq(adapter);
396 adapter->flags |= FW_QUEUE_BOUND;
399 err = cfg_queue_count(eth_dev);
406 static int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev,
407 uint16_t tx_queue_id)
410 struct sge_eth_txq *txq = (struct sge_eth_txq *)
411 (eth_dev->data->tx_queues[tx_queue_id]);
413 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
415 ret = t4_sge_eth_txq_start(txq);
417 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
422 static int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev,
423 uint16_t tx_queue_id)
426 struct sge_eth_txq *txq = (struct sge_eth_txq *)
427 (eth_dev->data->tx_queues[tx_queue_id]);
429 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
431 ret = t4_sge_eth_txq_stop(txq);
433 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
438 static int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev,
439 uint16_t queue_idx, uint16_t nb_desc,
440 unsigned int socket_id,
441 const struct rte_eth_txconf *tx_conf)
443 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
444 struct adapter *adapter = pi->adapter;
445 struct sge *s = &adapter->sge;
446 struct sge_eth_txq *txq = &s->ethtxq[pi->first_qset + queue_idx];
448 unsigned int temp_nb_desc;
450 RTE_SET_USED(tx_conf);
452 dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n",
453 __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc,
454 socket_id, pi->first_qset);
456 /* Free up the existing queue */
457 if (eth_dev->data->tx_queues[queue_idx]) {
458 cxgbe_dev_tx_queue_release(eth_dev->data->tx_queues[queue_idx]);
459 eth_dev->data->tx_queues[queue_idx] = NULL;
462 eth_dev->data->tx_queues[queue_idx] = (void *)txq;
466 * nb_desc should be > 1023 and <= CXGBE_MAX_RING_DESC_SIZE
468 temp_nb_desc = nb_desc;
469 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
470 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
471 __func__, CXGBE_MIN_RING_DESC_SIZE,
472 CXGBE_DEFAULT_TX_DESC_SIZE);
473 temp_nb_desc = CXGBE_DEFAULT_TX_DESC_SIZE;
474 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
475 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
476 __func__, CXGBE_MIN_RING_DESC_SIZE,
477 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_TX_DESC_SIZE);
481 txq->q.size = temp_nb_desc;
483 err = t4_sge_alloc_eth_txq(adapter, txq, eth_dev, queue_idx,
484 s->fw_evtq.cntxt_id, socket_id);
486 dev_debug(adapter, "%s: txq->q.cntxt_id= %d err = %d\n",
487 __func__, txq->q.cntxt_id, err);
492 static void cxgbe_dev_tx_queue_release(void *q)
494 struct sge_eth_txq *txq = (struct sge_eth_txq *)q;
497 struct port_info *pi = (struct port_info *)
498 (txq->eth_dev->data->dev_private);
499 struct adapter *adap = pi->adapter;
501 dev_debug(adapter, "%s: pi->port_id = %d; tx_queue_id = %d\n",
502 __func__, pi->port_id, txq->q.cntxt_id);
504 t4_sge_eth_txq_release(adap, txq);
508 static int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev,
509 uint16_t rx_queue_id)
512 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
513 struct adapter *adap = pi->adapter;
516 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
517 __func__, pi->port_id, rx_queue_id);
519 q = eth_dev->data->rx_queues[rx_queue_id];
521 ret = t4_sge_eth_rxq_start(adap, q);
523 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
528 static int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev,
529 uint16_t rx_queue_id)
532 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
533 struct adapter *adap = pi->adapter;
536 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
537 __func__, pi->port_id, rx_queue_id);
539 q = eth_dev->data->rx_queues[rx_queue_id];
540 ret = t4_sge_eth_rxq_stop(adap, q);
542 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
547 static int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev,
548 uint16_t queue_idx, uint16_t nb_desc,
549 unsigned int socket_id,
550 const struct rte_eth_rxconf *rx_conf,
551 struct rte_mempool *mp)
553 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
554 struct adapter *adapter = pi->adapter;
555 struct sge *s = &adapter->sge;
556 struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_qset + queue_idx];
559 unsigned int temp_nb_desc;
560 struct rte_eth_dev_info dev_info;
561 unsigned int pkt_len = eth_dev->data->dev_conf.rxmode.max_rx_pkt_len;
563 RTE_SET_USED(rx_conf);
565 dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n",
566 __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc,
569 cxgbe_dev_info_get(eth_dev, &dev_info);
571 /* Must accommodate at least ETHER_MIN_MTU */
572 if ((pkt_len < dev_info.min_rx_bufsize) ||
573 (pkt_len > dev_info.max_rx_pktlen)) {
574 dev_err(adap, "%s: max pkt len must be > %d and <= %d\n",
575 __func__, dev_info.min_rx_bufsize,
576 dev_info.max_rx_pktlen);
580 /* Free up the existing queue */
581 if (eth_dev->data->rx_queues[queue_idx]) {
582 cxgbe_dev_rx_queue_release(eth_dev->data->rx_queues[queue_idx]);
583 eth_dev->data->rx_queues[queue_idx] = NULL;
586 eth_dev->data->rx_queues[queue_idx] = (void *)rxq;
590 * nb_desc should be > 0 and <= CXGBE_MAX_RING_DESC_SIZE
592 temp_nb_desc = nb_desc;
593 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
594 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
595 __func__, CXGBE_MIN_RING_DESC_SIZE,
596 CXGBE_DEFAULT_RX_DESC_SIZE);
597 temp_nb_desc = CXGBE_DEFAULT_RX_DESC_SIZE;
598 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
599 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
600 __func__, CXGBE_MIN_RING_DESC_SIZE,
601 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_RX_DESC_SIZE);
605 rxq->rspq.size = temp_nb_desc;
606 if ((&rxq->fl) != NULL)
607 rxq->fl.size = temp_nb_desc;
609 /* Set to jumbo mode if necessary */
610 if (pkt_len > ETHER_MAX_LEN)
611 eth_dev->data->dev_conf.rxmode.jumbo_frame = 1;
613 eth_dev->data->dev_conf.rxmode.jumbo_frame = 0;
615 err = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx,
616 &rxq->fl, t4_ethrx_handler,
617 t4_get_mps_bg_map(adapter, pi->tx_chan), mp,
618 queue_idx, socket_id);
620 dev_debug(adapter, "%s: err = %d; port_id = %d; cntxt_id = %u\n",
621 __func__, err, pi->port_id, rxq->rspq.cntxt_id);
625 static void cxgbe_dev_rx_queue_release(void *q)
627 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)q;
628 struct sge_rspq *rq = &rxq->rspq;
631 struct port_info *pi = (struct port_info *)
632 (rq->eth_dev->data->dev_private);
633 struct adapter *adap = pi->adapter;
635 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
636 __func__, pi->port_id, rxq->rspq.cntxt_id);
638 t4_sge_eth_rxq_release(adap, rxq);
643 * Get port statistics.
645 static void cxgbe_dev_stats_get(struct rte_eth_dev *eth_dev,
646 struct rte_eth_stats *eth_stats)
648 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
649 struct adapter *adapter = pi->adapter;
650 struct sge *s = &adapter->sge;
651 struct port_stats ps;
654 cxgbe_stats_get(pi, &ps);
657 eth_stats->ipackets = ps.rx_frames;
658 eth_stats->ibytes = ps.rx_octets;
659 eth_stats->imissed = ps.rx_ovflow0 + ps.rx_ovflow1 +
660 ps.rx_ovflow2 + ps.rx_ovflow3 +
661 ps.rx_trunc0 + ps.rx_trunc1 +
662 ps.rx_trunc2 + ps.rx_trunc3;
663 eth_stats->ierrors = ps.rx_symbol_err + ps.rx_fcs_err +
664 ps.rx_jabber + ps.rx_too_long + ps.rx_runt +
668 eth_stats->opackets = ps.tx_frames;
669 eth_stats->obytes = ps.tx_octets;
670 eth_stats->oerrors = ps.tx_error_frames;
672 for (i = 0; i < pi->n_rx_qsets; i++) {
673 struct sge_eth_rxq *rxq =
674 &s->ethrxq[pi->first_qset + i];
676 eth_stats->q_ipackets[i] = rxq->stats.pkts;
677 eth_stats->q_ibytes[i] = rxq->stats.rx_bytes;
680 for (i = 0; i < pi->n_tx_qsets; i++) {
681 struct sge_eth_txq *txq =
682 &s->ethtxq[pi->first_qset + i];
684 eth_stats->q_opackets[i] = txq->stats.pkts;
685 eth_stats->q_obytes[i] = txq->stats.tx_bytes;
686 eth_stats->q_errors[i] = txq->stats.mapping_err;
691 * Reset port statistics.
693 static void cxgbe_dev_stats_reset(struct rte_eth_dev *eth_dev)
695 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
696 struct adapter *adapter = pi->adapter;
697 struct sge *s = &adapter->sge;
700 cxgbe_stats_reset(pi);
701 for (i = 0; i < pi->n_rx_qsets; i++) {
702 struct sge_eth_rxq *rxq =
703 &s->ethrxq[pi->first_qset + i];
706 rxq->stats.rx_bytes = 0;
708 for (i = 0; i < pi->n_tx_qsets; i++) {
709 struct sge_eth_txq *txq =
710 &s->ethtxq[pi->first_qset + i];
713 txq->stats.tx_bytes = 0;
714 txq->stats.mapping_err = 0;
718 static int cxgbe_flow_ctrl_get(struct rte_eth_dev *eth_dev,
719 struct rte_eth_fc_conf *fc_conf)
721 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
722 struct link_config *lc = &pi->link_cfg;
723 int rx_pause, tx_pause;
725 fc_conf->autoneg = lc->fc & PAUSE_AUTONEG;
726 rx_pause = lc->fc & PAUSE_RX;
727 tx_pause = lc->fc & PAUSE_TX;
729 if (rx_pause && tx_pause)
730 fc_conf->mode = RTE_FC_FULL;
732 fc_conf->mode = RTE_FC_RX_PAUSE;
734 fc_conf->mode = RTE_FC_TX_PAUSE;
736 fc_conf->mode = RTE_FC_NONE;
740 static int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev,
741 struct rte_eth_fc_conf *fc_conf)
743 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
744 struct adapter *adapter = pi->adapter;
745 struct link_config *lc = &pi->link_cfg;
747 if (lc->supported & FW_PORT_CAP_ANEG) {
748 if (fc_conf->autoneg)
749 lc->requested_fc |= PAUSE_AUTONEG;
751 lc->requested_fc &= ~PAUSE_AUTONEG;
754 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
755 (fc_conf->mode & RTE_FC_RX_PAUSE))
756 lc->requested_fc |= PAUSE_RX;
758 lc->requested_fc &= ~PAUSE_RX;
760 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
761 (fc_conf->mode & RTE_FC_TX_PAUSE))
762 lc->requested_fc |= PAUSE_TX;
764 lc->requested_fc &= ~PAUSE_TX;
766 return t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,
770 static const uint32_t *
771 cxgbe_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
773 static const uint32_t ptypes[] = {
779 if (eth_dev->rx_pkt_burst == cxgbe_recv_pkts)
784 static int cxgbe_get_eeprom_length(struct rte_eth_dev *dev)
791 * eeprom_ptov - translate a physical EEPROM address to virtual
792 * @phys_addr: the physical EEPROM address
793 * @fn: the PCI function number
794 * @sz: size of function-specific area
796 * Translate a physical EEPROM address to virtual. The first 1K is
797 * accessed through virtual addresses starting at 31K, the rest is
798 * accessed through virtual addresses starting at 0.
800 * The mapping is as follows:
801 * [0..1K) -> [31K..32K)
802 * [1K..1K+A) -> [31K-A..31K)
803 * [1K+A..ES) -> [0..ES-A-1K)
805 * where A = @fn * @sz, and ES = EEPROM size.
807 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
810 if (phys_addr < 1024)
811 return phys_addr + (31 << 10);
812 if (phys_addr < 1024 + fn)
813 return fn + phys_addr - 1024;
814 if (phys_addr < EEPROMSIZE)
815 return phys_addr - 1024 - fn;
816 if (phys_addr < EEPROMVSIZE)
817 return phys_addr - 1024;
821 /* The next two routines implement eeprom read/write from physical addresses.
823 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v)
825 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
828 vaddr = t4_seeprom_read(adap, vaddr, v);
829 return vaddr < 0 ? vaddr : 0;
832 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v)
834 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
837 vaddr = t4_seeprom_write(adap, vaddr, v);
838 return vaddr < 0 ? vaddr : 0;
841 #define EEPROM_MAGIC 0x38E2F10C
843 static int cxgbe_get_eeprom(struct rte_eth_dev *dev,
844 struct rte_dev_eeprom_info *e)
846 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
847 struct adapter *adapter = pi->adapter;
849 u8 *buf = rte_zmalloc(NULL, EEPROMSIZE, 0);
854 e->magic = EEPROM_MAGIC;
855 for (i = e->offset & ~3; !err && i < e->offset + e->length; i += 4)
856 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]);
859 rte_memcpy(e->data, buf + e->offset, e->length);
864 static int cxgbe_set_eeprom(struct rte_eth_dev *dev,
865 struct rte_dev_eeprom_info *eeprom)
867 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
868 struct adapter *adapter = pi->adapter;
871 u32 aligned_offset, aligned_len, *p;
873 if (eeprom->magic != EEPROM_MAGIC)
876 aligned_offset = eeprom->offset & ~3;
877 aligned_len = (eeprom->length + (eeprom->offset & 3) + 3) & ~3;
879 if (adapter->pf > 0) {
880 u32 start = 1024 + adapter->pf * EEPROMPFSIZE;
882 if (aligned_offset < start ||
883 aligned_offset + aligned_len > start + EEPROMPFSIZE)
887 if (aligned_offset != eeprom->offset || aligned_len != eeprom->length) {
888 /* RMW possibly needed for first or last words.
890 buf = rte_zmalloc(NULL, aligned_len, 0);
893 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf);
894 if (!err && aligned_len > 4)
895 err = eeprom_rd_phys(adapter,
896 aligned_offset + aligned_len - 4,
897 (u32 *)&buf[aligned_len - 4]);
900 rte_memcpy(buf + (eeprom->offset & 3), eeprom->data,
906 err = t4_seeprom_wp(adapter, false);
910 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
911 err = eeprom_wr_phys(adapter, aligned_offset, *p);
916 err = t4_seeprom_wp(adapter, true);
918 if (buf != eeprom->data)
923 static int cxgbe_get_regs_len(struct rte_eth_dev *eth_dev)
925 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
926 struct adapter *adapter = pi->adapter;
928 return t4_get_regs_len(adapter) / sizeof(uint32_t);
931 static int cxgbe_get_regs(struct rte_eth_dev *eth_dev,
932 struct rte_dev_reg_info *regs)
934 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
935 struct adapter *adapter = pi->adapter;
937 regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) |
938 (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) |
941 if (regs->data == NULL) {
942 regs->length = cxgbe_get_regs_len(eth_dev);
943 regs->width = sizeof(uint32_t);
948 t4_get_regs(adapter, regs->data, (regs->length * sizeof(uint32_t)));
953 static const struct eth_dev_ops cxgbe_eth_dev_ops = {
954 .dev_start = cxgbe_dev_start,
955 .dev_stop = cxgbe_dev_stop,
956 .dev_close = cxgbe_dev_close,
957 .promiscuous_enable = cxgbe_dev_promiscuous_enable,
958 .promiscuous_disable = cxgbe_dev_promiscuous_disable,
959 .allmulticast_enable = cxgbe_dev_allmulticast_enable,
960 .allmulticast_disable = cxgbe_dev_allmulticast_disable,
961 .dev_configure = cxgbe_dev_configure,
962 .dev_infos_get = cxgbe_dev_info_get,
963 .dev_supported_ptypes_get = cxgbe_dev_supported_ptypes_get,
964 .link_update = cxgbe_dev_link_update,
965 .mtu_set = cxgbe_dev_mtu_set,
966 .tx_queue_setup = cxgbe_dev_tx_queue_setup,
967 .tx_queue_start = cxgbe_dev_tx_queue_start,
968 .tx_queue_stop = cxgbe_dev_tx_queue_stop,
969 .tx_queue_release = cxgbe_dev_tx_queue_release,
970 .rx_queue_setup = cxgbe_dev_rx_queue_setup,
971 .rx_queue_start = cxgbe_dev_rx_queue_start,
972 .rx_queue_stop = cxgbe_dev_rx_queue_stop,
973 .rx_queue_release = cxgbe_dev_rx_queue_release,
974 .stats_get = cxgbe_dev_stats_get,
975 .stats_reset = cxgbe_dev_stats_reset,
976 .flow_ctrl_get = cxgbe_flow_ctrl_get,
977 .flow_ctrl_set = cxgbe_flow_ctrl_set,
978 .get_eeprom_length = cxgbe_get_eeprom_length,
979 .get_eeprom = cxgbe_get_eeprom,
980 .set_eeprom = cxgbe_set_eeprom,
981 .get_reg = cxgbe_get_regs,
986 * It returns 0 on success.
988 static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev)
990 struct rte_pci_device *pci_dev;
991 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
992 struct adapter *adapter = NULL;
993 char name[RTE_ETH_NAME_MAX_LEN];
998 eth_dev->dev_ops = &cxgbe_eth_dev_ops;
999 eth_dev->rx_pkt_burst = &cxgbe_recv_pkts;
1000 eth_dev->tx_pkt_burst = &cxgbe_xmit_pkts;
1002 /* for secondary processes, we don't initialise any further as primary
1003 * has already done this work.
1005 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1008 pci_dev = eth_dev->pci_dev;
1010 snprintf(name, sizeof(name), "cxgbeadapter%d", eth_dev->data->port_id);
1011 adapter = rte_zmalloc(name, sizeof(*adapter), 0);
1015 adapter->use_unpacked_mode = 1;
1016 adapter->regs = (void *)pci_dev->mem_resource[0].addr;
1017 if (!adapter->regs) {
1018 dev_err(adapter, "%s: cannot map device registers\n", __func__);
1020 goto out_free_adapter;
1022 adapter->pdev = pci_dev;
1023 adapter->eth_dev = eth_dev;
1024 pi->adapter = adapter;
1026 err = cxgbe_probe(adapter);
1028 dev_err(adapter, "%s: cxgbe probe failed with err %d\n",
1030 goto out_free_adapter;
1040 static struct eth_driver rte_cxgbe_pmd = {
1042 .id_table = cxgb4_pci_tbl,
1043 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1044 .probe = rte_eth_dev_pci_probe,
1045 .remove = rte_eth_dev_pci_remove,
1047 .eth_dev_init = eth_cxgbe_dev_init,
1048 .dev_private_size = sizeof(struct port_info),
1051 DRIVER_REGISTER_PCI(net_cxgbe, rte_cxgbe_pmd.pci_drv);
1052 DRIVER_REGISTER_PCI_TABLE(net_cxgbe, cxgb4_pci_tbl);