drivers/net/cxgbe/cxgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Chelsio Communications.
   3  * All rights reserved.
   4  */
   5
   6 #include <sys/queue.h>
   7 #include <stdio.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <string.h>
  11 #include <unistd.h>
  12 #include <stdarg.h>
  13 #include <inttypes.h>
  14 #include <netinet/in.h>
  15
  16 #include <rte_byteorder.h>
  17 #include <rte_common.h>
  18 #include <rte_cycles.h>
  19 #include <rte_interrupts.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_pci.h>
  23 #include <rte_bus_pci.h>
  24 #include <rte_atomic.h>
  25 #include <rte_branch_prediction.h>
  26 #include <rte_memory.h>
  27 #include <rte_tailq.h>
  28 #include <rte_eal.h>
  29 #include <rte_alarm.h>
  30 #include <rte_ether.h>
  31 #include <rte_ethdev_driver.h>
  32 #include <rte_ethdev_pci.h>
  33 #include <rte_malloc.h>
  34 #include <rte_random.h>
  35 #include <rte_dev.h>
  36
  37 #include "cxgbe.h"
  38 #include "cxgbe_pfvf.h"
  39 #include "cxgbe_flow.h"
  40
  41 /*
  42  * Macros needed to support the PCI Device ID Table ...
  43  */
  44 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
  45         static const struct rte_pci_id cxgb4_pci_tbl[] = {
  46 #define CH_PCI_DEVICE_ID_FUNCTION 0x4
  47
  48 #define PCI_VENDOR_ID_CHELSIO 0x1425
  49
  50 #define CH_PCI_ID_TABLE_ENTRY(devid) \
  51                 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CHELSIO, (devid)) }
  52
  53 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
  54                 { .vendor_id = 0, } \
  55         }
  56
  57 /*
  58  *... and the PCI ID Table itself ...
  59  */
  60 #include "base/t4_pci_id_tbl.h"
  61
  62 uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
  63                          uint16_t nb_pkts)
  64 {
  65         struct sge_eth_txq *txq = (struct sge_eth_txq *)tx_queue;
  66         uint16_t pkts_sent, pkts_remain;
  67         uint16_t total_sent = 0;
  68         uint16_t idx = 0;
  69         int ret = 0;
  70
  71         t4_os_lock(&txq->txq_lock);
  72         /* free up desc from already completed tx */
  73         reclaim_completed_tx(&txq->q);
  74         if (unlikely(!nb_pkts))
  75                 goto out_unlock;
  76
  77         rte_prefetch0(rte_pktmbuf_mtod(tx_pkts[0], volatile void *));
  78         while (total_sent < nb_pkts) {
  79                 pkts_remain = nb_pkts - total_sent;
  80
  81                 for (pkts_sent = 0; pkts_sent < pkts_remain; pkts_sent++) {
  82                         idx = total_sent + pkts_sent;
  83                         if ((idx + 1) < nb_pkts)
  84                                 rte_prefetch0(rte_pktmbuf_mtod(tx_pkts[idx + 1],
  85                                                         volatile void *));
  86                         ret = t4_eth_xmit(txq, tx_pkts[idx], nb_pkts);
  87                         if (ret < 0)
  88                                 break;
  89                 }
  90                 if (!pkts_sent)
  91                         break;
  92                 total_sent += pkts_sent;
  93                 /* reclaim as much as possible */
  94                 reclaim_completed_tx(&txq->q);
  95         }
  96
  97 out_unlock:
  98         t4_os_unlock(&txq->txq_lock);
  99         return total_sent;
 100 }
 101
 102 uint16_t cxgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
 103                          uint16_t nb_pkts)
 104 {
 105         struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)rx_queue;
 106         unsigned int work_done;
 107
 108         if (cxgbe_poll(&rxq->rspq, rx_pkts, (unsigned int)nb_pkts, &work_done))
 109                 dev_err(adapter, "error in cxgbe poll\n");
 110
 111         return work_done;
 112 }
 113
 114 int cxgbe_dev_info_get(struct rte_eth_dev *eth_dev,
 115                         struct rte_eth_dev_info *device_info)
 116 {
 117         struct port_info *pi = eth_dev->data->dev_private;
 118         struct adapter *adapter = pi->adapter;
 119
 120         static const struct rte_eth_desc_lim cxgbe_desc_lim = {
 121                 .nb_max = CXGBE_MAX_RING_DESC_SIZE,
 122                 .nb_min = CXGBE_MIN_RING_DESC_SIZE,
 123                 .nb_align = 1,
 124         };
 125
 126         device_info->min_rx_bufsize = CXGBE_MIN_RX_BUFSIZE;
 127         device_info->max_rx_pktlen = CXGBE_MAX_RX_PKTLEN;
 128         device_info->max_rx_queues = adapter->sge.max_ethqsets;
 129         device_info->max_tx_queues = adapter->sge.max_ethqsets;
 130         device_info->max_mac_addrs = 1;
 131         /* XXX: For now we support one MAC/port */
 132         device_info->max_vfs = adapter->params.arch.vfcount;
 133         device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */
 134
 135         device_info->rx_queue_offload_capa = 0UL;
 136         device_info->rx_offload_capa = CXGBE_RX_OFFLOADS;
 137
 138         device_info->tx_queue_offload_capa = 0UL;
 139         device_info->tx_offload_capa = CXGBE_TX_OFFLOADS;
 140
 141         device_info->reta_size = pi->rss_size;
 142         device_info->hash_key_size = CXGBE_DEFAULT_RSS_KEY_LEN;
 143         device_info->flow_type_rss_offloads = CXGBE_RSS_HF_ALL;
 144
 145         device_info->rx_desc_lim = cxgbe_desc_lim;
 146         device_info->tx_desc_lim = cxgbe_desc_lim;
 147         cxgbe_get_speed_caps(pi, &device_info->speed_capa);
 148
 149         return 0;
 150 }
 151
 152 int cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
 153 {
 154         struct port_info *pi = eth_dev->data->dev_private;
 155         struct adapter *adapter = pi->adapter;
 156
 157         return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 158                              1, -1, 1, -1, false);
 159 }
 160
 161 int cxgbe_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
 162 {
 163         struct port_info *pi = eth_dev->data->dev_private;
 164         struct adapter *adapter = pi->adapter;
 165
 166         return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 167                              0, -1, 1, -1, false);
 168 }
 169
 170 int cxgbe_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
 171 {
 172         struct port_info *pi = eth_dev->data->dev_private;
 173         struct adapter *adapter = pi->adapter;
 174
 175         /* TODO: address filters ?? */
 176
 177         return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 178                              -1, 1, 1, -1, false);
 179 }
 180
 181 int cxgbe_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
 182 {
 183         struct port_info *pi = eth_dev->data->dev_private;
 184         struct adapter *adapter = pi->adapter;
 185
 186         /* TODO: address filters ?? */
 187
 188         return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 189                              -1, 0, 1, -1, false);
 190 }
 191
 192 int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev,
 193                           int wait_to_complete)
 194 {
 195         struct port_info *pi = eth_dev->data->dev_private;
 196         struct adapter *adapter = pi->adapter;
 197         struct sge *s = &adapter->sge;
 198         struct rte_eth_link new_link = { 0 };
 199         unsigned int i, work_done, budget = 32;
 200         u8 old_link = pi->link_cfg.link_ok;
 201
 202         for (i = 0; i < CXGBE_LINK_STATUS_POLL_CNT; i++) {
 203                 if (!s->fw_evtq.desc)
 204                         break;
 205
 206                 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
 207
 208                 /* Exit if link status changed or always forced up */
 209                 if (pi->link_cfg.link_ok != old_link ||
 210                     cxgbe_force_linkup(adapter))
 211                         break;
 212
 213                 if (!wait_to_complete)
 214                         break;
 215
 216                 rte_delay_ms(CXGBE_LINK_STATUS_POLL_MS);
 217         }
 218
 219         new_link.link_status = cxgbe_force_linkup(adapter) ?
 220                                ETH_LINK_UP : pi->link_cfg.link_ok;
 221         new_link.link_autoneg = pi->link_cfg.autoneg;
 222         new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
 223         new_link.link_speed = pi->link_cfg.speed;
 224
 225         return rte_eth_linkstatus_set(eth_dev, &new_link);
 226 }
 227
 228 /**
 229  * Set device link up.
 230  */
 231 int cxgbe_dev_set_link_up(struct rte_eth_dev *dev)
 232 {
 233         struct port_info *pi = dev->data->dev_private;
 234         struct adapter *adapter = pi->adapter;
 235         unsigned int work_done, budget = 32;
 236         struct sge *s = &adapter->sge;
 237         int ret;
 238
 239         if (!s->fw_evtq.desc)
 240                 return -ENOMEM;
 241
 242         /* Flush all link events */
 243         cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
 244
 245         /* If link already up, nothing to do */
 246         if (pi->link_cfg.link_ok)
 247                 return 0;
 248
 249         ret = cxgbe_set_link_status(pi, true);
 250         if (ret)
 251                 return ret;
 252
 253         cxgbe_dev_link_update(dev, 1);
 254         return 0;
 255 }
 256
 257 /**
 258  * Set device link down.
 259  */
 260 int cxgbe_dev_set_link_down(struct rte_eth_dev *dev)
 261 {
 262         struct port_info *pi = dev->data->dev_private;
 263         struct adapter *adapter = pi->adapter;
 264         unsigned int work_done, budget = 32;
 265         struct sge *s = &adapter->sge;
 266         int ret;
 267
 268         if (!s->fw_evtq.desc)
 269                 return -ENOMEM;
 270
 271         /* Flush all link events */
 272         cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
 273
 274         /* If link already down, nothing to do */
 275         if (!pi->link_cfg.link_ok)
 276                 return 0;
 277
 278         ret = cxgbe_set_link_status(pi, false);
 279         if (ret)
 280                 return ret;
 281
 282         cxgbe_dev_link_update(dev, 0);
 283         return 0;
 284 }
 285
 286 int cxgbe_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
 287 {
 288         struct port_info *pi = eth_dev->data->dev_private;
 289         struct adapter *adapter = pi->adapter;
 290         struct rte_eth_dev_info dev_info;
 291         int err;
 292         uint16_t new_mtu = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN;
 293
 294         err = cxgbe_dev_info_get(eth_dev, &dev_info);
 295         if (err != 0)
 296                 return err;
 297
 298         /* Must accommodate at least RTE_ETHER_MIN_MTU */
 299         if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > dev_info.max_rx_pktlen)
 300                 return -EINVAL;
 301
 302         /* set to jumbo mode if needed */
 303         if (new_mtu > RTE_ETHER_MAX_LEN)
 304                 eth_dev->data->dev_conf.rxmode.offloads |=
 305                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 306         else
 307                 eth_dev->data->dev_conf.rxmode.offloads &=
 308                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 309
 310         err = t4_set_rxmode(adapter, adapter->mbox, pi->viid, new_mtu, -1, -1,
 311                             -1, -1, true);
 312         if (!err)
 313                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_mtu;
 314
 315         return err;
 316 }
 317
 318 /*
 319  * Stop device.
 320  */
 321 int cxgbe_dev_close(struct rte_eth_dev *eth_dev)
 322 {
 323         struct port_info *temp_pi, *pi = eth_dev->data->dev_private;
 324         struct adapter *adapter = pi->adapter;
 325         u8 i;
 326
 327         CXGBE_FUNC_TRACE();
 328
 329         if (!(adapter->flags & FULL_INIT_DONE))
 330                 return 0;
 331
 332         if (!pi->viid)
 333                 return 0;
 334
 335         cxgbe_down(pi);
 336         t4_sge_eth_release_queues(pi);
 337         t4_free_vi(adapter, adapter->mbox, adapter->pf, 0, pi->viid);
 338         pi->viid = 0;
 339
 340         /* Free up the adapter-wide resources only after all the ports
 341          * under this PF have been closed.
 342          */
 343         for_each_port(adapter, i) {
 344                 temp_pi = adap2pinfo(adapter, i);
 345                 if (temp_pi->viid)
 346                         return 0;
 347         }
 348
 349         cxgbe_close(adapter);
 350         rte_free(adapter);
 351
 352         return 0;
 353 }
 354
 355 /* Start the device.
 356  * It returns 0 on success.
 357  */
 358 int cxgbe_dev_start(struct rte_eth_dev *eth_dev)
 359 {
 360         struct port_info *pi = eth_dev->data->dev_private;
 361         struct rte_eth_rxmode *rx_conf = &eth_dev->data->dev_conf.rxmode;
 362         struct adapter *adapter = pi->adapter;
 363         int err = 0, i;
 364
 365         CXGBE_FUNC_TRACE();
 366
 367         /*
 368          * If we don't have a connection to the firmware there's nothing we
 369          * can do.
 370          */
 371         if (!(adapter->flags & FW_OK)) {
 372                 err = -ENXIO;
 373                 goto out;
 374         }
 375
 376         if (!(adapter->flags & FULL_INIT_DONE)) {
 377                 err = cxgbe_up(adapter);
 378                 if (err < 0)
 379                         goto out;
 380         }
 381
 382         if (rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER)
 383                 eth_dev->data->scattered_rx = 1;
 384         else
 385                 eth_dev->data->scattered_rx = 0;
 386
 387         cxgbe_enable_rx_queues(pi);
 388
 389         err = cxgbe_setup_rss(pi);
 390         if (err)
 391                 goto out;
 392
 393         for (i = 0; i < pi->n_tx_qsets; i++) {
 394                 err = cxgbe_dev_tx_queue_start(eth_dev, i);
 395                 if (err)
 396                         goto out;
 397         }
 398
 399         for (i = 0; i < pi->n_rx_qsets; i++) {
 400                 err = cxgbe_dev_rx_queue_start(eth_dev, i);
 401                 if (err)
 402                         goto out;
 403         }
 404
 405         err = cxgbe_link_start(pi);
 406         if (err)
 407                 goto out;
 408
 409 out:
 410         return err;
 411 }
 412
 413 /*
 414  * Stop device: disable rx and tx functions to allow for reconfiguring.
 415  */
 416 void cxgbe_dev_stop(struct rte_eth_dev *eth_dev)
 417 {
 418         struct port_info *pi = eth_dev->data->dev_private;
 419         struct adapter *adapter = pi->adapter;
 420
 421         CXGBE_FUNC_TRACE();
 422
 423         if (!(adapter->flags & FULL_INIT_DONE))
 424                 return;
 425
 426         cxgbe_down(pi);
 427
 428         /*
 429          *  We clear queues only if both tx and rx path of the port
 430          *  have been disabled
 431          */
 432         t4_sge_eth_clear_queues(pi);
 433         eth_dev->data->scattered_rx = 0;
 434 }
 435
 436 int cxgbe_dev_configure(struct rte_eth_dev *eth_dev)
 437 {
 438         struct port_info *pi = eth_dev->data->dev_private;
 439         struct adapter *adapter = pi->adapter;
 440         int err;
 441
 442         CXGBE_FUNC_TRACE();
 443
 444         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
 445                 eth_dev->data->dev_conf.rxmode.offloads |=
 446                         DEV_RX_OFFLOAD_RSS_HASH;
 447
 448         if (!(adapter->flags & FW_QUEUE_BOUND)) {
 449                 err = cxgbe_setup_sge_fwevtq(adapter);
 450                 if (err)
 451                         return err;
 452                 adapter->flags |= FW_QUEUE_BOUND;
 453                 if (is_pf4(adapter)) {
 454                         err = cxgbe_setup_sge_ctrl_txq(adapter);
 455                         if (err)
 456                                 return err;
 457                 }
 458         }
 459
 460         err = cxgbe_cfg_queue_count(eth_dev);
 461         if (err)
 462                 return err;
 463
 464         return 0;
 465 }
 466
 467 int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
 468 {
 469         int ret;
 470         struct sge_eth_txq *txq = (struct sge_eth_txq *)
 471                                   (eth_dev->data->tx_queues[tx_queue_id]);
 472
 473         dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
 474
 475         ret = t4_sge_eth_txq_start(txq);
 476         if (ret == 0)
 477                 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 478
 479         return ret;
 480 }
 481
 482 int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
 483 {
 484         int ret;
 485         struct sge_eth_txq *txq = (struct sge_eth_txq *)
 486                                   (eth_dev->data->tx_queues[tx_queue_id]);
 487
 488         dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
 489
 490         ret = t4_sge_eth_txq_stop(txq);
 491         if (ret == 0)
 492                 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 493
 494         return ret;
 495 }
 496
 497 int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev,
 498                              uint16_t queue_idx, uint16_t nb_desc,
 499                              unsigned int socket_id,
 500                              const struct rte_eth_txconf *tx_conf __rte_unused)
 501 {
 502         struct port_info *pi = eth_dev->data->dev_private;
 503         struct adapter *adapter = pi->adapter;
 504         struct sge *s = &adapter->sge;
 505         unsigned int temp_nb_desc;
 506         struct sge_eth_txq *txq;
 507         int err = 0;
 508
 509         txq = &s->ethtxq[pi->first_txqset + queue_idx];
 510         dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n",
 511                   __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc,
 512                   socket_id, pi->first_txqset);
 513
 514         /*  Free up the existing queue  */
 515         if (eth_dev->data->tx_queues[queue_idx]) {
 516                 cxgbe_dev_tx_queue_release(eth_dev->data->tx_queues[queue_idx]);
 517                 eth_dev->data->tx_queues[queue_idx] = NULL;
 518         }
 519
 520         eth_dev->data->tx_queues[queue_idx] = (void *)txq;
 521
 522         /* Sanity Checking
 523          *
 524          * nb_desc should be > 1023 and <= CXGBE_MAX_RING_DESC_SIZE
 525          */
 526         temp_nb_desc = nb_desc;
 527         if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
 528                 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
 529                          __func__, CXGBE_MIN_RING_DESC_SIZE,
 530                          CXGBE_DEFAULT_TX_DESC_SIZE);
 531                 temp_nb_desc = CXGBE_DEFAULT_TX_DESC_SIZE;
 532         } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
 533                 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
 534                         __func__, CXGBE_MIN_RING_DESC_SIZE,
 535                         CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_TX_DESC_SIZE);
 536                 return -(EINVAL);
 537         }
 538
 539         txq->q.size = temp_nb_desc;
 540
 541         err = t4_sge_alloc_eth_txq(adapter, txq, eth_dev, queue_idx,
 542                                    s->fw_evtq.cntxt_id, socket_id);
 543
 544         dev_debug(adapter, "%s: txq->q.cntxt_id= %u txq->q.abs_id= %u err = %d\n",
 545                   __func__, txq->q.cntxt_id, txq->q.abs_id, err);
 546         return err;
 547 }
 548
 549 void cxgbe_dev_tx_queue_release(void *q)
 550 {
 551         struct sge_eth_txq *txq = (struct sge_eth_txq *)q;
 552
 553         if (txq) {
 554                 struct port_info *pi = (struct port_info *)
 555                                        (txq->eth_dev->data->dev_private);
 556                 struct adapter *adap = pi->adapter;
 557
 558                 dev_debug(adapter, "%s: pi->port_id = %d; tx_queue_id = %d\n",
 559                           __func__, pi->port_id, txq->q.cntxt_id);
 560
 561                 t4_sge_eth_txq_release(adap, txq);
 562         }
 563 }
 564
 565 int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
 566 {
 567         struct port_info *pi = eth_dev->data->dev_private;
 568         struct adapter *adap = pi->adapter;
 569         struct sge_eth_rxq *rxq;
 570         int ret;
 571
 572         dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
 573                   __func__, pi->port_id, rx_queue_id);
 574
 575         rxq = eth_dev->data->rx_queues[rx_queue_id];
 576         ret = t4_sge_eth_rxq_start(adap, rxq);
 577         if (ret == 0)
 578                 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 579
 580         return ret;
 581 }
 582
 583 int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
 584 {
 585         struct port_info *pi = eth_dev->data->dev_private;
 586         struct adapter *adap = pi->adapter;
 587         struct sge_eth_rxq *rxq;
 588         int ret;
 589
 590         dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
 591                   __func__, pi->port_id, rx_queue_id);
 592
 593         rxq = eth_dev->data->rx_queues[rx_queue_id];
 594         ret = t4_sge_eth_rxq_stop(adap, rxq);
 595         if (ret == 0)
 596                 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 597
 598         return ret;
 599 }
 600
 601 int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev,
 602                              uint16_t queue_idx, uint16_t nb_desc,
 603                              unsigned int socket_id,
 604                              const struct rte_eth_rxconf *rx_conf __rte_unused,
 605                              struct rte_mempool *mp)
 606 {
 607         unsigned int pkt_len = eth_dev->data->dev_conf.rxmode.max_rx_pkt_len;
 608         struct port_info *pi = eth_dev->data->dev_private;
 609         struct adapter *adapter = pi->adapter;
 610         struct rte_eth_dev_info dev_info;
 611         struct sge *s = &adapter->sge;
 612         unsigned int temp_nb_desc;
 613         int err = 0, msi_idx = 0;
 614         struct sge_eth_rxq *rxq;
 615
 616         rxq = &s->ethrxq[pi->first_rxqset + queue_idx];
 617         dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n",
 618                   __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc,
 619                   socket_id, mp);
 620
 621         err = cxgbe_dev_info_get(eth_dev, &dev_info);
 622         if (err != 0) {
 623                 dev_err(adap, "%s: error during getting ethernet device info",
 624                         __func__);
 625                 return err;
 626         }
 627
 628         /* Must accommodate at least RTE_ETHER_MIN_MTU */
 629         if ((pkt_len < dev_info.min_rx_bufsize) ||
 630             (pkt_len > dev_info.max_rx_pktlen)) {
 631                 dev_err(adap, "%s: max pkt len must be > %d and <= %d\n",
 632                         __func__, dev_info.min_rx_bufsize,
 633                         dev_info.max_rx_pktlen);
 634                 return -EINVAL;
 635         }
 636
 637         /*  Free up the existing queue  */
 638         if (eth_dev->data->rx_queues[queue_idx]) {
 639                 cxgbe_dev_rx_queue_release(eth_dev->data->rx_queues[queue_idx]);
 640                 eth_dev->data->rx_queues[queue_idx] = NULL;
 641         }
 642
 643         eth_dev->data->rx_queues[queue_idx] = (void *)rxq;
 644
 645         /* Sanity Checking
 646          *
 647          * nb_desc should be > 0 and <= CXGBE_MAX_RING_DESC_SIZE
 648          */
 649         temp_nb_desc = nb_desc;
 650         if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
 651                 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
 652                          __func__, CXGBE_MIN_RING_DESC_SIZE,
 653                          CXGBE_DEFAULT_RX_DESC_SIZE);
 654                 temp_nb_desc = CXGBE_DEFAULT_RX_DESC_SIZE;
 655         } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
 656                 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
 657                         __func__, CXGBE_MIN_RING_DESC_SIZE,
 658                         CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_RX_DESC_SIZE);
 659                 return -(EINVAL);
 660         }
 661
 662         rxq->rspq.size = temp_nb_desc;
 663         if ((&rxq->fl) != NULL)
 664                 rxq->fl.size = temp_nb_desc;
 665
 666         /* Set to jumbo mode if necessary */
 667         if (pkt_len > RTE_ETHER_MAX_LEN)
 668                 eth_dev->data->dev_conf.rxmode.offloads |=
 669                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 670         else
 671                 eth_dev->data->dev_conf.rxmode.offloads &=
 672                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 673
 674         err = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx,
 675                                &rxq->fl, NULL,
 676                                is_pf4(adapter) ?
 677                                t4_get_tp_ch_map(adapter, pi->tx_chan) : 0, mp,
 678                                queue_idx, socket_id);
 679
 680         dev_debug(adapter, "%s: err = %d; port_id = %d; cntxt_id = %u; abs_id = %u\n",
 681                   __func__, err, pi->port_id, rxq->rspq.cntxt_id,
 682                   rxq->rspq.abs_id);
 683         return err;
 684 }
 685
 686 void cxgbe_dev_rx_queue_release(void *q)
 687 {
 688         struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)q;
 689
 690         if (rxq) {
 691                 struct port_info *pi = (struct port_info *)
 692                                        (rxq->rspq.eth_dev->data->dev_private);
 693                 struct adapter *adap = pi->adapter;
 694
 695                 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
 696                           __func__, pi->port_id, rxq->rspq.cntxt_id);
 697
 698                 t4_sge_eth_rxq_release(adap, rxq);
 699         }
 700 }
 701
 702 /*
 703  * Get port statistics.
 704  */
 705 static int cxgbe_dev_stats_get(struct rte_eth_dev *eth_dev,
 706                                 struct rte_eth_stats *eth_stats)
 707 {
 708         struct port_info *pi = eth_dev->data->dev_private;
 709         struct adapter *adapter = pi->adapter;
 710         struct sge *s = &adapter->sge;
 711         struct port_stats ps;
 712         unsigned int i;
 713
 714         cxgbe_stats_get(pi, &ps);
 715
 716         /* RX Stats */
 717         eth_stats->imissed  = ps.rx_ovflow0 + ps.rx_ovflow1 +
 718                               ps.rx_ovflow2 + ps.rx_ovflow3 +
 719                               ps.rx_trunc0 + ps.rx_trunc1 +
 720                               ps.rx_trunc2 + ps.rx_trunc3;
 721         eth_stats->ierrors  = ps.rx_symbol_err + ps.rx_fcs_err +
 722                               ps.rx_jabber + ps.rx_too_long + ps.rx_runt +
 723                               ps.rx_len_err;
 724
 725         /* TX Stats */
 726         eth_stats->opackets = ps.tx_frames;
 727         eth_stats->obytes   = ps.tx_octets;
 728         eth_stats->oerrors  = ps.tx_error_frames;
 729
 730         for (i = 0; i < pi->n_rx_qsets; i++) {
 731                 struct sge_eth_rxq *rxq =
 732                         &s->ethrxq[pi->first_rxqset + i];
 733
 734                 eth_stats->q_ipackets[i] = rxq->stats.pkts;
 735                 eth_stats->q_ibytes[i] = rxq->stats.rx_bytes;
 736                 eth_stats->ipackets += eth_stats->q_ipackets[i];
 737                 eth_stats->ibytes += eth_stats->q_ibytes[i];
 738         }
 739
 740         for (i = 0; i < pi->n_tx_qsets; i++) {
 741                 struct sge_eth_txq *txq =
 742                         &s->ethtxq[pi->first_txqset + i];
 743
 744                 eth_stats->q_opackets[i] = txq->stats.pkts;
 745                 eth_stats->q_obytes[i] = txq->stats.tx_bytes;
 746         }
 747         return 0;
 748 }
 749
 750 /*
 751  * Reset port statistics.
 752  */
 753 static int cxgbe_dev_stats_reset(struct rte_eth_dev *eth_dev)
 754 {
 755         struct port_info *pi = eth_dev->data->dev_private;
 756         struct adapter *adapter = pi->adapter;
 757         struct sge *s = &adapter->sge;
 758         unsigned int i;
 759
 760         cxgbe_stats_reset(pi);
 761         for (i = 0; i < pi->n_rx_qsets; i++) {
 762                 struct sge_eth_rxq *rxq =
 763                         &s->ethrxq[pi->first_rxqset + i];
 764
 765                 rxq->stats.pkts = 0;
 766                 rxq->stats.rx_bytes = 0;
 767         }
 768         for (i = 0; i < pi->n_tx_qsets; i++) {
 769                 struct sge_eth_txq *txq =
 770                         &s->ethtxq[pi->first_txqset + i];
 771
 772                 txq->stats.pkts = 0;
 773                 txq->stats.tx_bytes = 0;
 774                 txq->stats.mapping_err = 0;
 775         }
 776
 777         return 0;
 778 }
 779
 780 static int cxgbe_flow_ctrl_get(struct rte_eth_dev *eth_dev,
 781                                struct rte_eth_fc_conf *fc_conf)
 782 {
 783         struct port_info *pi = eth_dev->data->dev_private;
 784         struct link_config *lc = &pi->link_cfg;
 785         int rx_pause, tx_pause;
 786
 787         fc_conf->autoneg = lc->fc & PAUSE_AUTONEG;
 788         rx_pause = lc->fc & PAUSE_RX;
 789         tx_pause = lc->fc & PAUSE_TX;
 790
 791         if (rx_pause && tx_pause)
 792                 fc_conf->mode = RTE_FC_FULL;
 793         else if (rx_pause)
 794                 fc_conf->mode = RTE_FC_RX_PAUSE;
 795         else if (tx_pause)
 796                 fc_conf->mode = RTE_FC_TX_PAUSE;
 797         else
 798                 fc_conf->mode = RTE_FC_NONE;
 799         return 0;
 800 }
 801
 802 static int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev,
 803                                struct rte_eth_fc_conf *fc_conf)
 804 {
 805         struct port_info *pi = eth_dev->data->dev_private;
 806         struct adapter *adapter = pi->adapter;
 807         struct link_config *lc = &pi->link_cfg;
 808
 809         if (lc->pcaps & FW_PORT_CAP32_ANEG) {
 810                 if (fc_conf->autoneg)
 811                         lc->requested_fc |= PAUSE_AUTONEG;
 812                 else
 813                         lc->requested_fc &= ~PAUSE_AUTONEG;
 814         }
 815
 816         if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
 817             (fc_conf->mode & RTE_FC_RX_PAUSE))
 818                 lc->requested_fc |= PAUSE_RX;
 819         else
 820                 lc->requested_fc &= ~PAUSE_RX;
 821
 822         if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
 823             (fc_conf->mode & RTE_FC_TX_PAUSE))
 824                 lc->requested_fc |= PAUSE_TX;
 825         else
 826                 lc->requested_fc &= ~PAUSE_TX;
 827
 828         return t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,
 829                              &pi->link_cfg);
 830 }
 831
 832 const uint32_t *
 833 cxgbe_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
 834 {
 835         static const uint32_t ptypes[] = {
 836                 RTE_PTYPE_L3_IPV4,
 837                 RTE_PTYPE_L3_IPV6,
 838                 RTE_PTYPE_UNKNOWN
 839         };
 840
 841         if (eth_dev->rx_pkt_burst == cxgbe_recv_pkts)
 842                 return ptypes;
 843         return NULL;
 844 }
 845
 846 /* Update RSS hash configuration
 847  */
 848 static int cxgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
 849                                      struct rte_eth_rss_conf *rss_conf)
 850 {
 851         struct port_info *pi = dev->data->dev_private;
 852         struct adapter *adapter = pi->adapter;
 853         int err;
 854
 855         err = cxgbe_write_rss_conf(pi, rss_conf->rss_hf);
 856         if (err)
 857                 return err;
 858
 859         pi->rss_hf = rss_conf->rss_hf;
 860
 861         if (rss_conf->rss_key) {
 862                 u32 key[10], mod_key[10];
 863                 int i, j;
 864
 865                 memcpy(key, rss_conf->rss_key, CXGBE_DEFAULT_RSS_KEY_LEN);
 866
 867                 for (i = 9, j = 0; i >= 0; i--, j++)
 868                         mod_key[j] = cpu_to_be32(key[i]);
 869
 870                 t4_write_rss_key(adapter, mod_key, -1);
 871         }
 872
 873         return 0;
 874 }
 875
 876 /* Get RSS hash configuration
 877  */
 878 static int cxgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 879                                        struct rte_eth_rss_conf *rss_conf)
 880 {
 881         struct port_info *pi = dev->data->dev_private;
 882         struct adapter *adapter = pi->adapter;
 883         u64 rss_hf = 0;
 884         u64 flags = 0;
 885         int err;
 886
 887         err = t4_read_config_vi_rss(adapter, adapter->mbox, pi->viid,
 888                                     &flags, NULL);
 889
 890         if (err)
 891                 return err;
 892
 893         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) {
 894                 rss_hf |= CXGBE_RSS_HF_TCP_IPV6_MASK;
 895                 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
 896                         rss_hf |= CXGBE_RSS_HF_UDP_IPV6_MASK;
 897         }
 898
 899         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
 900                 rss_hf |= CXGBE_RSS_HF_IPV6_MASK;
 901
 902         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) {
 903                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
 904                 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
 905                         rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
 906         }
 907
 908         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
 909                 rss_hf |= CXGBE_RSS_HF_IPV4_MASK;
 910
 911         rss_conf->rss_hf = rss_hf;
 912
 913         if (rss_conf->rss_key) {
 914                 u32 key[10], mod_key[10];
 915                 int i, j;
 916
 917                 t4_read_rss_key(adapter, key);
 918
 919                 for (i = 9, j = 0; i >= 0; i--, j++)
 920                         mod_key[j] = be32_to_cpu(key[i]);
 921
 922                 memcpy(rss_conf->rss_key, mod_key, CXGBE_DEFAULT_RSS_KEY_LEN);
 923         }
 924
 925         return 0;
 926 }
 927
 928 static int cxgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 929                                      struct rte_eth_rss_reta_entry64 *reta_conf,
 930                                      uint16_t reta_size)
 931 {
 932         struct port_info *pi = dev->data->dev_private;
 933         struct adapter *adapter = pi->adapter;
 934         u16 i, idx, shift, *rss;
 935         int ret;
 936
 937         if (!(adapter->flags & FULL_INIT_DONE))
 938                 return -ENOMEM;
 939
 940         if (!reta_size || reta_size > pi->rss_size)
 941                 return -EINVAL;
 942
 943         rss = rte_calloc(NULL, pi->rss_size, sizeof(u16), 0);
 944         if (!rss)
 945                 return -ENOMEM;
 946
 947         rte_memcpy(rss, pi->rss, pi->rss_size * sizeof(u16));
 948         for (i = 0; i < reta_size; i++) {
 949                 idx = i / RTE_RETA_GROUP_SIZE;
 950                 shift = i % RTE_RETA_GROUP_SIZE;
 951                 if (!(reta_conf[idx].mask & (1ULL << shift)))
 952                         continue;
 953
 954                 rss[i] = reta_conf[idx].reta[shift];
 955         }
 956
 957         ret = cxgbe_write_rss(pi, rss);
 958         if (!ret)
 959                 rte_memcpy(pi->rss, rss, pi->rss_size * sizeof(u16));
 960
 961         rte_free(rss);
 962         return ret;
 963 }
 964
 965 static int cxgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 966                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 967                                     uint16_t reta_size)
 968 {
 969         struct port_info *pi = dev->data->dev_private;
 970         struct adapter *adapter = pi->adapter;
 971         u16 i, idx, shift;
 972
 973         if (!(adapter->flags & FULL_INIT_DONE))
 974                 return -ENOMEM;
 975
 976         if (!reta_size || reta_size > pi->rss_size)
 977                 return -EINVAL;
 978
 979         for (i = 0; i < reta_size; i++) {
 980                 idx = i / RTE_RETA_GROUP_SIZE;
 981                 shift = i % RTE_RETA_GROUP_SIZE;
 982                 if (!(reta_conf[idx].mask & (1ULL << shift)))
 983                         continue;
 984
 985                 reta_conf[idx].reta[shift] = pi->rss[i];
 986         }
 987
 988         return 0;
 989 }
 990
 991 static int cxgbe_get_eeprom_length(struct rte_eth_dev *dev)
 992 {
 993         RTE_SET_USED(dev);
 994         return EEPROMSIZE;
 995 }
 996
 997 /**
 998  * eeprom_ptov - translate a physical EEPROM address to virtual
 999  * @phys_addr: the physical EEPROM address
1000  * @fn: the PCI function number
1001  * @sz: size of function-specific area
1002  *
1003  * Translate a physical EEPROM address to virtual.  The first 1K is
1004  * accessed through virtual addresses starting at 31K, the rest is
1005  * accessed through virtual addresses starting at 0.
1006  *
1007  * The mapping is as follows:
1008  * [0..1K) -> [31K..32K)
1009  * [1K..1K+A) -> [31K-A..31K)
1010  * [1K+A..ES) -> [0..ES-A-1K)
1011  *
1012  * where A = @fn * @sz, and ES = EEPROM size.
1013  */
1014 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
1015 {
1016         fn *= sz;
1017         if (phys_addr < 1024)
1018                 return phys_addr + (31 << 10);
1019         if (phys_addr < 1024 + fn)
1020                 return fn + phys_addr - 1024;
1021         if (phys_addr < EEPROMSIZE)
1022                 return phys_addr - 1024 - fn;
1023         if (phys_addr < EEPROMVSIZE)
1024                 return phys_addr - 1024;
1025         return -EINVAL;
1026 }
1027
1028 /* The next two routines implement eeprom read/write from physical addresses.
1029  */
1030 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v)
1031 {
1032         int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
1033
1034         if (vaddr >= 0)
1035                 vaddr = t4_seeprom_read(adap, vaddr, v);
1036         return vaddr < 0 ? vaddr : 0;
1037 }
1038
1039 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v)
1040 {
1041         int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
1042
1043         if (vaddr >= 0)
1044                 vaddr = t4_seeprom_write(adap, vaddr, v);
1045         return vaddr < 0 ? vaddr : 0;
1046 }
1047
1048 #define EEPROM_MAGIC 0x38E2F10C
1049
1050 static int cxgbe_get_eeprom(struct rte_eth_dev *dev,
1051                             struct rte_dev_eeprom_info *e)
1052 {
1053         struct port_info *pi = dev->data->dev_private;
1054         struct adapter *adapter = pi->adapter;
1055         u32 i, err = 0;
1056         u8 *buf = rte_zmalloc(NULL, EEPROMSIZE, 0);
1057
1058         if (!buf)
1059                 return -ENOMEM;
1060
1061         e->magic = EEPROM_MAGIC;
1062         for (i = e->offset & ~3; !err && i < e->offset + e->length; i += 4)
1063                 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]);
1064
1065         if (!err)
1066                 rte_memcpy(e->data, buf + e->offset, e->length);
1067         rte_free(buf);
1068         return err;
1069 }
1070
1071 static int cxgbe_set_eeprom(struct rte_eth_dev *dev,
1072                             struct rte_dev_eeprom_info *eeprom)
1073 {
1074         struct port_info *pi = dev->data->dev_private;
1075         struct adapter *adapter = pi->adapter;
1076         u8 *buf;
1077         int err = 0;
1078         u32 aligned_offset, aligned_len, *p;
1079
1080         if (eeprom->magic != EEPROM_MAGIC)
1081                 return -EINVAL;
1082
1083         aligned_offset = eeprom->offset & ~3;
1084         aligned_len = (eeprom->length + (eeprom->offset & 3) + 3) & ~3;
1085
1086         if (adapter->pf > 0) {
1087                 u32 start = 1024 + adapter->pf * EEPROMPFSIZE;
1088
1089                 if (aligned_offset < start ||
1090                     aligned_offset + aligned_len > start + EEPROMPFSIZE)
1091                         return -EPERM;
1092         }
1093
1094         if (aligned_offset != eeprom->offset || aligned_len != eeprom->length) {
1095                 /* RMW possibly needed for first or last words.
1096                  */
1097                 buf = rte_zmalloc(NULL, aligned_len, 0);
1098                 if (!buf)
1099                         return -ENOMEM;
1100                 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf);
1101                 if (!err && aligned_len > 4)
1102                         err = eeprom_rd_phys(adapter,
1103                                              aligned_offset + aligned_len - 4,
1104                                              (u32 *)&buf[aligned_len - 4]);
1105                 if (err)
1106                         goto out;
1107                 rte_memcpy(buf + (eeprom->offset & 3), eeprom->data,
1108                            eeprom->length);
1109         } else {
1110                 buf = eeprom->data;
1111         }
1112
1113         err = t4_seeprom_wp(adapter, false);
1114         if (err)
1115                 goto out;
1116
1117         for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
1118                 err = eeprom_wr_phys(adapter, aligned_offset, *p);
1119                 aligned_offset += 4;
1120         }
1121
1122         if (!err)
1123                 err = t4_seeprom_wp(adapter, true);
1124 out:
1125         if (buf != eeprom->data)
1126                 rte_free(buf);
1127         return err;
1128 }
1129
1130 static int cxgbe_get_regs_len(struct rte_eth_dev *eth_dev)
1131 {
1132         struct port_info *pi = eth_dev->data->dev_private;
1133         struct adapter *adapter = pi->adapter;
1134
1135         return t4_get_regs_len(adapter) / sizeof(uint32_t);
1136 }
1137
1138 static int cxgbe_get_regs(struct rte_eth_dev *eth_dev,
1139                           struct rte_dev_reg_info *regs)
1140 {
1141         struct port_info *pi = eth_dev->data->dev_private;
1142         struct adapter *adapter = pi->adapter;
1143
1144         regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) |
1145                 (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) |
1146                 (1 << 16);
1147
1148         if (regs->data == NULL) {
1149                 regs->length = cxgbe_get_regs_len(eth_dev);
1150                 regs->width = sizeof(uint32_t);
1151
1152                 return 0;
1153         }
1154
1155         t4_get_regs(adapter, regs->data, (regs->length * sizeof(uint32_t)));
1156
1157         return 0;
1158 }
1159
1160 int cxgbe_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
1161 {
1162         struct port_info *pi = dev->data->dev_private;
1163         int ret;
1164
1165         ret = cxgbe_mpstcam_modify(pi, (int)pi->xact_addr_filt, (u8 *)addr);
1166         if (ret < 0) {
1167                 dev_err(adapter, "failed to set mac addr; err = %d\n",
1168                         ret);
1169                 return ret;
1170         }
1171         pi->xact_addr_filt = ret;
1172         return 0;
1173 }
1174
1175 static const struct eth_dev_ops cxgbe_eth_dev_ops = {
1176         .dev_start              = cxgbe_dev_start,
1177         .dev_stop               = cxgbe_dev_stop,
1178         .dev_close              = cxgbe_dev_close,
1179         .promiscuous_enable     = cxgbe_dev_promiscuous_enable,
1180         .promiscuous_disable    = cxgbe_dev_promiscuous_disable,
1181         .allmulticast_enable    = cxgbe_dev_allmulticast_enable,
1182         .allmulticast_disable   = cxgbe_dev_allmulticast_disable,
1183         .dev_configure          = cxgbe_dev_configure,
1184         .dev_infos_get          = cxgbe_dev_info_get,
1185         .dev_supported_ptypes_get = cxgbe_dev_supported_ptypes_get,
1186         .link_update            = cxgbe_dev_link_update,
1187         .dev_set_link_up        = cxgbe_dev_set_link_up,
1188         .dev_set_link_down      = cxgbe_dev_set_link_down,
1189         .mtu_set                = cxgbe_dev_mtu_set,
1190         .tx_queue_setup         = cxgbe_dev_tx_queue_setup,
1191         .tx_queue_start         = cxgbe_dev_tx_queue_start,
1192         .tx_queue_stop          = cxgbe_dev_tx_queue_stop,
1193         .tx_queue_release       = cxgbe_dev_tx_queue_release,
1194         .rx_queue_setup         = cxgbe_dev_rx_queue_setup,
1195         .rx_queue_start         = cxgbe_dev_rx_queue_start,
1196         .rx_queue_stop          = cxgbe_dev_rx_queue_stop,
1197         .rx_queue_release       = cxgbe_dev_rx_queue_release,
1198         .filter_ctrl            = cxgbe_dev_filter_ctrl,
1199         .stats_get              = cxgbe_dev_stats_get,
1200         .stats_reset            = cxgbe_dev_stats_reset,
1201         .flow_ctrl_get          = cxgbe_flow_ctrl_get,
1202         .flow_ctrl_set          = cxgbe_flow_ctrl_set,
1203         .get_eeprom_length      = cxgbe_get_eeprom_length,
1204         .get_eeprom             = cxgbe_get_eeprom,
1205         .set_eeprom             = cxgbe_set_eeprom,
1206         .get_reg                = cxgbe_get_regs,
1207         .rss_hash_update        = cxgbe_dev_rss_hash_update,
1208         .rss_hash_conf_get      = cxgbe_dev_rss_hash_conf_get,
1209         .mac_addr_set           = cxgbe_mac_addr_set,
1210         .reta_update            = cxgbe_dev_rss_reta_update,
1211         .reta_query             = cxgbe_dev_rss_reta_query,
1212 };
1213
1214 /*
1215  * Initialize driver
1216  * It returns 0 on success.
1217  */
1218 static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev)
1219 {
1220         struct rte_pci_device *pci_dev;
1221         struct port_info *pi = eth_dev->data->dev_private;
1222         struct adapter *adapter = NULL;
1223         char name[RTE_ETH_NAME_MAX_LEN];
1224         int err = 0;
1225
1226         CXGBE_FUNC_TRACE();
1227
1228         eth_dev->dev_ops = &cxgbe_eth_dev_ops;
1229         eth_dev->rx_pkt_burst = &cxgbe_recv_pkts;
1230         eth_dev->tx_pkt_burst = &cxgbe_xmit_pkts;
1231         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1232
1233         /* for secondary processes, we attach to ethdevs allocated by primary
1234          * and do minimal initialization.
1235          */
1236         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1237                 int i;
1238
1239                 for (i = 1; i < MAX_NPORTS; i++) {
1240                         struct rte_eth_dev *rest_eth_dev;
1241                         char namei[RTE_ETH_NAME_MAX_LEN];
1242
1243                         snprintf(namei, sizeof(namei), "%s_%d",
1244                                  pci_dev->device.name, i);
1245                         rest_eth_dev = rte_eth_dev_attach_secondary(namei);
1246                         if (rest_eth_dev) {
1247                                 rest_eth_dev->device = &pci_dev->device;
1248                                 rest_eth_dev->dev_ops =
1249                                         eth_dev->dev_ops;
1250                                 rest_eth_dev->rx_pkt_burst =
1251                                         eth_dev->rx_pkt_burst;
1252                                 rest_eth_dev->tx_pkt_burst =
1253                                         eth_dev->tx_pkt_burst;
1254                                 rte_eth_dev_probing_finish(rest_eth_dev);
1255                         }
1256                 }
1257                 return 0;
1258         }
1259
1260         snprintf(name, sizeof(name), "cxgbeadapter%d", eth_dev->data->port_id);
1261         adapter = rte_zmalloc(name, sizeof(*adapter), 0);
1262         if (!adapter)
1263                 return -1;
1264
1265         adapter->use_unpacked_mode = 1;
1266         adapter->regs = (void *)pci_dev->mem_resource[0].addr;
1267         if (!adapter->regs) {
1268                 dev_err(adapter, "%s: cannot map device registers\n", __func__);
1269                 err = -ENOMEM;
1270                 goto out_free_adapter;
1271         }
1272         adapter->pdev = pci_dev;
1273         adapter->eth_dev = eth_dev;
1274         pi->adapter = adapter;
1275
1276         cxgbe_process_devargs(adapter);
1277
1278         err = cxgbe_probe(adapter);
1279         if (err) {
1280                 dev_err(adapter, "%s: cxgbe probe failed with err %d\n",
1281                         __func__, err);
1282                 goto out_free_adapter;
1283         }
1284
1285         return 0;
1286
1287 out_free_adapter:
1288         rte_free(adapter);
1289         return err;
1290 }
1291
1292 static int eth_cxgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1293 {
1294         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1295         uint16_t port_id;
1296
1297         /* Free up other ports and all resources */
1298         RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device)
1299                 rte_eth_dev_close(port_id);
1300
1301         return 0;
1302 }
1303
1304 static int eth_cxgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1305         struct rte_pci_device *pci_dev)
1306 {
1307         return rte_eth_dev_pci_generic_probe(pci_dev,
1308                 sizeof(struct port_info), eth_cxgbe_dev_init);
1309 }
1310
1311 static int eth_cxgbe_pci_remove(struct rte_pci_device *pci_dev)
1312 {
1313         return rte_eth_dev_pci_generic_remove(pci_dev, eth_cxgbe_dev_uninit);
1314 }
1315
1316 static struct rte_pci_driver rte_cxgbe_pmd = {
1317         .id_table = cxgb4_pci_tbl,
1318         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1319         .probe = eth_cxgbe_pci_probe,
1320         .remove = eth_cxgbe_pci_remove,
1321 };
1322
1323 RTE_PMD_REGISTER_PCI(net_cxgbe, rte_cxgbe_pmd);
1324 RTE_PMD_REGISTER_PCI_TABLE(net_cxgbe, cxgb4_pci_tbl);
1325 RTE_PMD_REGISTER_KMOD_DEP(net_cxgbe, "* igb_uio | uio_pci_generic | vfio-pci");
1326 RTE_PMD_REGISTER_PARAM_STRING(net_cxgbe,
1327                               CXGBE_DEVARG_CMN_KEEP_OVLAN "=<0|1> "
1328                               CXGBE_DEVARG_CMN_TX_MODE_LATENCY "=<0|1> "
1329                               CXGBE_DEVARG_PF_FILTER_MODE "=<uint32> "
1330                               CXGBE_DEVARG_PF_FILTER_MASK "=<uint32> ");
1331 RTE_LOG_REGISTER(cxgbe_logtype, pmd.net.cxgbe, NOTICE);
1332 RTE_LOG_REGISTER(cxgbe_mbox_logtype, pmd.net.cxgbe.mbox, NOTICE);