4 * Copyright(c) 2014-2017 Chelsio Communications.
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8 * modification, are permitted provided that the following conditions
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14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
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18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
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22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
42 #include <netinet/in.h>
44 #include <rte_byteorder.h>
45 #include <rte_common.h>
46 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
55 #include <rte_tailq.h>
57 #include <rte_alarm.h>
58 #include <rte_ether.h>
59 #include <rte_ethdev.h>
60 #include <rte_ethdev_pci.h>
61 #include <rte_atomic.h>
62 #include <rte_malloc.h>
63 #include <rte_random.h>
69 * Macros needed to support the PCI Device ID Table ...
71 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
72 static const struct rte_pci_id cxgb4_pci_tbl[] = {
73 #define CH_PCI_DEVICE_ID_FUNCTION 0x4
75 #define PCI_VENDOR_ID_CHELSIO 0x1425
77 #define CH_PCI_ID_TABLE_ENTRY(devid) \
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CHELSIO, (devid)) }
80 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
85 *... and the PCI ID Table itself ...
87 #include "t4_pci_id_tbl.h"
89 static uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
92 struct sge_eth_txq *txq = (struct sge_eth_txq *)tx_queue;
93 uint16_t pkts_sent, pkts_remain;
94 uint16_t total_sent = 0;
97 CXGBE_DEBUG_TX(adapter, "%s: txq = %p; tx_pkts = %p; nb_pkts = %d\n",
98 __func__, txq, tx_pkts, nb_pkts);
100 t4_os_lock(&txq->txq_lock);
101 /* free up desc from already completed tx */
102 reclaim_completed_tx(&txq->q);
103 while (total_sent < nb_pkts) {
104 pkts_remain = nb_pkts - total_sent;
106 for (pkts_sent = 0; pkts_sent < pkts_remain; pkts_sent++) {
107 ret = t4_eth_xmit(txq, tx_pkts[total_sent + pkts_sent],
114 total_sent += pkts_sent;
115 /* reclaim as much as possible */
116 reclaim_completed_tx(&txq->q);
119 t4_os_unlock(&txq->txq_lock);
123 static uint16_t cxgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
126 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)rx_queue;
127 unsigned int work_done;
129 CXGBE_DEBUG_RX(adapter, "%s: rxq->rspq.cntxt_id = %u; nb_pkts = %d\n",
130 __func__, rxq->rspq.cntxt_id, nb_pkts);
132 if (cxgbe_poll(&rxq->rspq, rx_pkts, (unsigned int)nb_pkts, &work_done))
133 dev_err(adapter, "error in cxgbe poll\n");
135 CXGBE_DEBUG_RX(adapter, "%s: work_done = %u\n", __func__, work_done);
139 static void cxgbe_dev_info_get(struct rte_eth_dev *eth_dev,
140 struct rte_eth_dev_info *device_info)
142 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
143 struct adapter *adapter = pi->adapter;
144 int max_queues = adapter->sge.max_ethqsets / adapter->params.nports;
146 static const struct rte_eth_desc_lim cxgbe_desc_lim = {
147 .nb_max = CXGBE_MAX_RING_DESC_SIZE,
148 .nb_min = CXGBE_MIN_RING_DESC_SIZE,
152 device_info->pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
154 device_info->min_rx_bufsize = CXGBE_MIN_RX_BUFSIZE;
155 device_info->max_rx_pktlen = CXGBE_MAX_RX_PKTLEN;
156 device_info->max_rx_queues = max_queues;
157 device_info->max_tx_queues = max_queues;
158 device_info->max_mac_addrs = 1;
159 /* XXX: For now we support one MAC/port */
160 device_info->max_vfs = adapter->params.arch.vfcount;
161 device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */
163 device_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
164 DEV_RX_OFFLOAD_IPV4_CKSUM |
165 DEV_RX_OFFLOAD_UDP_CKSUM |
166 DEV_RX_OFFLOAD_TCP_CKSUM;
168 device_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
169 DEV_TX_OFFLOAD_IPV4_CKSUM |
170 DEV_TX_OFFLOAD_UDP_CKSUM |
171 DEV_TX_OFFLOAD_TCP_CKSUM |
172 DEV_TX_OFFLOAD_TCP_TSO;
174 device_info->reta_size = pi->rss_size;
176 device_info->rx_desc_lim = cxgbe_desc_lim;
177 device_info->tx_desc_lim = cxgbe_desc_lim;
178 device_info->speed_capa = ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G;
181 static void cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
183 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
184 struct adapter *adapter = pi->adapter;
186 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
187 1, -1, 1, -1, false);
190 static void cxgbe_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
192 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
193 struct adapter *adapter = pi->adapter;
195 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
196 0, -1, 1, -1, false);
199 static void cxgbe_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
201 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
202 struct adapter *adapter = pi->adapter;
204 /* TODO: address filters ?? */
206 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
207 -1, 1, 1, -1, false);
210 static void cxgbe_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
212 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
213 struct adapter *adapter = pi->adapter;
215 /* TODO: address filters ?? */
217 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
218 -1, 0, 1, -1, false);
221 static int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev,
222 __rte_unused int wait_to_complete)
224 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
225 struct adapter *adapter = pi->adapter;
226 struct sge *s = &adapter->sge;
227 struct rte_eth_link *old_link = ð_dev->data->dev_link;
228 unsigned int work_done, budget = 4;
230 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
231 if (old_link->link_status == pi->link_cfg.link_ok)
232 return -1; /* link not changed */
234 eth_dev->data->dev_link.link_status = pi->link_cfg.link_ok;
235 eth_dev->data->dev_link.link_duplex = ETH_LINK_FULL_DUPLEX;
236 eth_dev->data->dev_link.link_speed = pi->link_cfg.speed;
238 /* link has changed */
242 static int cxgbe_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
244 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
245 struct adapter *adapter = pi->adapter;
246 struct rte_eth_dev_info dev_info;
248 uint16_t new_mtu = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
250 cxgbe_dev_info_get(eth_dev, &dev_info);
252 /* Must accommodate at least ETHER_MIN_MTU */
253 if ((new_mtu < ETHER_MIN_MTU) || (new_mtu > dev_info.max_rx_pktlen))
256 /* set to jumbo mode if needed */
257 if (new_mtu > ETHER_MAX_LEN)
258 eth_dev->data->dev_conf.rxmode.jumbo_frame = 1;
260 eth_dev->data->dev_conf.rxmode.jumbo_frame = 0;
262 err = t4_set_rxmode(adapter, adapter->mbox, pi->viid, new_mtu, -1, -1,
265 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_mtu;
270 static int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev,
271 uint16_t tx_queue_id);
272 static int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev,
273 uint16_t tx_queue_id);
274 static void cxgbe_dev_tx_queue_release(void *q);
275 static void cxgbe_dev_rx_queue_release(void *q);
280 static void cxgbe_dev_close(struct rte_eth_dev *eth_dev)
282 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
283 struct adapter *adapter = pi->adapter;
288 if (!(adapter->flags & FULL_INIT_DONE))
294 * We clear queues only if both tx and rx path of the port
297 t4_sge_eth_clear_queues(pi);
299 /* See if all ports are down */
300 for_each_port(adapter, i) {
301 pi = adap2pinfo(adapter, i);
303 * Skip first port of the adapter since it will be closed
308 dev_down += (pi->eth_dev->data->dev_started == 0) ? 1 : 0;
311 /* If rest of the ports are stopped, then free up resources */
312 if (dev_down == (adapter->params.nports - 1))
313 cxgbe_close(adapter);
317 * It returns 0 on success.
319 static int cxgbe_dev_start(struct rte_eth_dev *eth_dev)
321 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
322 struct adapter *adapter = pi->adapter;
328 * If we don't have a connection to the firmware there's nothing we
331 if (!(adapter->flags & FW_OK)) {
336 if (!(adapter->flags & FULL_INIT_DONE)) {
337 err = cxgbe_up(adapter);
346 for (i = 0; i < pi->n_tx_qsets; i++) {
347 err = cxgbe_dev_tx_queue_start(eth_dev, i);
352 for (i = 0; i < pi->n_rx_qsets; i++) {
353 err = cxgbe_dev_rx_queue_start(eth_dev, i);
358 err = link_start(pi);
367 * Stop device: disable rx and tx functions to allow for reconfiguring.
369 static void cxgbe_dev_stop(struct rte_eth_dev *eth_dev)
371 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
372 struct adapter *adapter = pi->adapter;
376 if (!(adapter->flags & FULL_INIT_DONE))
382 * We clear queues only if both tx and rx path of the port
385 t4_sge_eth_clear_queues(pi);
388 static int cxgbe_dev_configure(struct rte_eth_dev *eth_dev)
390 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
391 struct adapter *adapter = pi->adapter;
396 if (!(adapter->flags & FW_QUEUE_BOUND)) {
397 err = setup_sge_fwevtq(adapter);
400 adapter->flags |= FW_QUEUE_BOUND;
403 err = cfg_queue_count(eth_dev);
410 static int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev,
411 uint16_t tx_queue_id)
414 struct sge_eth_txq *txq = (struct sge_eth_txq *)
415 (eth_dev->data->tx_queues[tx_queue_id]);
417 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
419 ret = t4_sge_eth_txq_start(txq);
421 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
426 static int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev,
427 uint16_t tx_queue_id)
430 struct sge_eth_txq *txq = (struct sge_eth_txq *)
431 (eth_dev->data->tx_queues[tx_queue_id]);
433 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
435 ret = t4_sge_eth_txq_stop(txq);
437 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
442 static int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev,
443 uint16_t queue_idx, uint16_t nb_desc,
444 unsigned int socket_id,
445 const struct rte_eth_txconf *tx_conf)
447 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
448 struct adapter *adapter = pi->adapter;
449 struct sge *s = &adapter->sge;
450 struct sge_eth_txq *txq = &s->ethtxq[pi->first_qset + queue_idx];
452 unsigned int temp_nb_desc;
454 RTE_SET_USED(tx_conf);
456 dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n",
457 __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc,
458 socket_id, pi->first_qset);
460 /* Free up the existing queue */
461 if (eth_dev->data->tx_queues[queue_idx]) {
462 cxgbe_dev_tx_queue_release(eth_dev->data->tx_queues[queue_idx]);
463 eth_dev->data->tx_queues[queue_idx] = NULL;
466 eth_dev->data->tx_queues[queue_idx] = (void *)txq;
470 * nb_desc should be > 1023 and <= CXGBE_MAX_RING_DESC_SIZE
472 temp_nb_desc = nb_desc;
473 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
474 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
475 __func__, CXGBE_MIN_RING_DESC_SIZE,
476 CXGBE_DEFAULT_TX_DESC_SIZE);
477 temp_nb_desc = CXGBE_DEFAULT_TX_DESC_SIZE;
478 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
479 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
480 __func__, CXGBE_MIN_RING_DESC_SIZE,
481 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_TX_DESC_SIZE);
485 txq->q.size = temp_nb_desc;
487 err = t4_sge_alloc_eth_txq(adapter, txq, eth_dev, queue_idx,
488 s->fw_evtq.cntxt_id, socket_id);
490 dev_debug(adapter, "%s: txq->q.cntxt_id= %d err = %d\n",
491 __func__, txq->q.cntxt_id, err);
496 static void cxgbe_dev_tx_queue_release(void *q)
498 struct sge_eth_txq *txq = (struct sge_eth_txq *)q;
501 struct port_info *pi = (struct port_info *)
502 (txq->eth_dev->data->dev_private);
503 struct adapter *adap = pi->adapter;
505 dev_debug(adapter, "%s: pi->port_id = %d; tx_queue_id = %d\n",
506 __func__, pi->port_id, txq->q.cntxt_id);
508 t4_sge_eth_txq_release(adap, txq);
512 static int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev,
513 uint16_t rx_queue_id)
516 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
517 struct adapter *adap = pi->adapter;
520 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
521 __func__, pi->port_id, rx_queue_id);
523 q = eth_dev->data->rx_queues[rx_queue_id];
525 ret = t4_sge_eth_rxq_start(adap, q);
527 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
532 static int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev,
533 uint16_t rx_queue_id)
536 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
537 struct adapter *adap = pi->adapter;
540 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
541 __func__, pi->port_id, rx_queue_id);
543 q = eth_dev->data->rx_queues[rx_queue_id];
544 ret = t4_sge_eth_rxq_stop(adap, q);
546 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
551 static int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev,
552 uint16_t queue_idx, uint16_t nb_desc,
553 unsigned int socket_id,
554 const struct rte_eth_rxconf *rx_conf,
555 struct rte_mempool *mp)
557 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
558 struct adapter *adapter = pi->adapter;
559 struct sge *s = &adapter->sge;
560 struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_qset + queue_idx];
563 unsigned int temp_nb_desc;
564 struct rte_eth_dev_info dev_info;
565 unsigned int pkt_len = eth_dev->data->dev_conf.rxmode.max_rx_pkt_len;
567 RTE_SET_USED(rx_conf);
569 dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n",
570 __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc,
573 cxgbe_dev_info_get(eth_dev, &dev_info);
575 /* Must accommodate at least ETHER_MIN_MTU */
576 if ((pkt_len < dev_info.min_rx_bufsize) ||
577 (pkt_len > dev_info.max_rx_pktlen)) {
578 dev_err(adap, "%s: max pkt len must be > %d and <= %d\n",
579 __func__, dev_info.min_rx_bufsize,
580 dev_info.max_rx_pktlen);
584 /* Free up the existing queue */
585 if (eth_dev->data->rx_queues[queue_idx]) {
586 cxgbe_dev_rx_queue_release(eth_dev->data->rx_queues[queue_idx]);
587 eth_dev->data->rx_queues[queue_idx] = NULL;
590 eth_dev->data->rx_queues[queue_idx] = (void *)rxq;
594 * nb_desc should be > 0 and <= CXGBE_MAX_RING_DESC_SIZE
596 temp_nb_desc = nb_desc;
597 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
598 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
599 __func__, CXGBE_MIN_RING_DESC_SIZE,
600 CXGBE_DEFAULT_RX_DESC_SIZE);
601 temp_nb_desc = CXGBE_DEFAULT_RX_DESC_SIZE;
602 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
603 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
604 __func__, CXGBE_MIN_RING_DESC_SIZE,
605 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_RX_DESC_SIZE);
609 rxq->rspq.size = temp_nb_desc;
610 if ((&rxq->fl) != NULL)
611 rxq->fl.size = temp_nb_desc;
613 /* Set to jumbo mode if necessary */
614 if (pkt_len > ETHER_MAX_LEN)
615 eth_dev->data->dev_conf.rxmode.jumbo_frame = 1;
617 eth_dev->data->dev_conf.rxmode.jumbo_frame = 0;
619 err = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx,
620 &rxq->fl, t4_ethrx_handler,
621 t4_get_tp_ch_map(adapter, pi->tx_chan), mp,
622 queue_idx, socket_id);
624 dev_debug(adapter, "%s: err = %d; port_id = %d; cntxt_id = %u\n",
625 __func__, err, pi->port_id, rxq->rspq.cntxt_id);
629 static void cxgbe_dev_rx_queue_release(void *q)
631 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)q;
632 struct sge_rspq *rq = &rxq->rspq;
635 struct port_info *pi = (struct port_info *)
636 (rq->eth_dev->data->dev_private);
637 struct adapter *adap = pi->adapter;
639 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
640 __func__, pi->port_id, rxq->rspq.cntxt_id);
642 t4_sge_eth_rxq_release(adap, rxq);
647 * Get port statistics.
649 static void cxgbe_dev_stats_get(struct rte_eth_dev *eth_dev,
650 struct rte_eth_stats *eth_stats)
652 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
653 struct adapter *adapter = pi->adapter;
654 struct sge *s = &adapter->sge;
655 struct port_stats ps;
658 cxgbe_stats_get(pi, &ps);
661 eth_stats->imissed = ps.rx_ovflow0 + ps.rx_ovflow1 +
662 ps.rx_ovflow2 + ps.rx_ovflow3 +
663 ps.rx_trunc0 + ps.rx_trunc1 +
664 ps.rx_trunc2 + ps.rx_trunc3;
665 eth_stats->ierrors = ps.rx_symbol_err + ps.rx_fcs_err +
666 ps.rx_jabber + ps.rx_too_long + ps.rx_runt +
670 eth_stats->opackets = ps.tx_frames;
671 eth_stats->obytes = ps.tx_octets;
672 eth_stats->oerrors = ps.tx_error_frames;
674 for (i = 0; i < pi->n_rx_qsets; i++) {
675 struct sge_eth_rxq *rxq =
676 &s->ethrxq[pi->first_qset + i];
678 eth_stats->q_ipackets[i] = rxq->stats.pkts;
679 eth_stats->q_ibytes[i] = rxq->stats.rx_bytes;
680 eth_stats->ipackets += eth_stats->q_ipackets[i];
681 eth_stats->ibytes += eth_stats->q_ibytes[i];
684 for (i = 0; i < pi->n_tx_qsets; i++) {
685 struct sge_eth_txq *txq =
686 &s->ethtxq[pi->first_qset + i];
688 eth_stats->q_opackets[i] = txq->stats.pkts;
689 eth_stats->q_obytes[i] = txq->stats.tx_bytes;
690 eth_stats->q_errors[i] = txq->stats.mapping_err;
695 * Reset port statistics.
697 static void cxgbe_dev_stats_reset(struct rte_eth_dev *eth_dev)
699 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
700 struct adapter *adapter = pi->adapter;
701 struct sge *s = &adapter->sge;
704 cxgbe_stats_reset(pi);
705 for (i = 0; i < pi->n_rx_qsets; i++) {
706 struct sge_eth_rxq *rxq =
707 &s->ethrxq[pi->first_qset + i];
710 rxq->stats.rx_bytes = 0;
712 for (i = 0; i < pi->n_tx_qsets; i++) {
713 struct sge_eth_txq *txq =
714 &s->ethtxq[pi->first_qset + i];
717 txq->stats.tx_bytes = 0;
718 txq->stats.mapping_err = 0;
722 static int cxgbe_flow_ctrl_get(struct rte_eth_dev *eth_dev,
723 struct rte_eth_fc_conf *fc_conf)
725 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
726 struct link_config *lc = &pi->link_cfg;
727 int rx_pause, tx_pause;
729 fc_conf->autoneg = lc->fc & PAUSE_AUTONEG;
730 rx_pause = lc->fc & PAUSE_RX;
731 tx_pause = lc->fc & PAUSE_TX;
733 if (rx_pause && tx_pause)
734 fc_conf->mode = RTE_FC_FULL;
736 fc_conf->mode = RTE_FC_RX_PAUSE;
738 fc_conf->mode = RTE_FC_TX_PAUSE;
740 fc_conf->mode = RTE_FC_NONE;
744 static int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev,
745 struct rte_eth_fc_conf *fc_conf)
747 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
748 struct adapter *adapter = pi->adapter;
749 struct link_config *lc = &pi->link_cfg;
751 if (lc->supported & FW_PORT_CAP_ANEG) {
752 if (fc_conf->autoneg)
753 lc->requested_fc |= PAUSE_AUTONEG;
755 lc->requested_fc &= ~PAUSE_AUTONEG;
758 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
759 (fc_conf->mode & RTE_FC_RX_PAUSE))
760 lc->requested_fc |= PAUSE_RX;
762 lc->requested_fc &= ~PAUSE_RX;
764 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
765 (fc_conf->mode & RTE_FC_TX_PAUSE))
766 lc->requested_fc |= PAUSE_TX;
768 lc->requested_fc &= ~PAUSE_TX;
770 return t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,
774 static const uint32_t *
775 cxgbe_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
777 static const uint32_t ptypes[] = {
783 if (eth_dev->rx_pkt_burst == cxgbe_recv_pkts)
788 static int cxgbe_get_eeprom_length(struct rte_eth_dev *dev)
795 * eeprom_ptov - translate a physical EEPROM address to virtual
796 * @phys_addr: the physical EEPROM address
797 * @fn: the PCI function number
798 * @sz: size of function-specific area
800 * Translate a physical EEPROM address to virtual. The first 1K is
801 * accessed through virtual addresses starting at 31K, the rest is
802 * accessed through virtual addresses starting at 0.
804 * The mapping is as follows:
805 * [0..1K) -> [31K..32K)
806 * [1K..1K+A) -> [31K-A..31K)
807 * [1K+A..ES) -> [0..ES-A-1K)
809 * where A = @fn * @sz, and ES = EEPROM size.
811 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
814 if (phys_addr < 1024)
815 return phys_addr + (31 << 10);
816 if (phys_addr < 1024 + fn)
817 return fn + phys_addr - 1024;
818 if (phys_addr < EEPROMSIZE)
819 return phys_addr - 1024 - fn;
820 if (phys_addr < EEPROMVSIZE)
821 return phys_addr - 1024;
825 /* The next two routines implement eeprom read/write from physical addresses.
827 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v)
829 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
832 vaddr = t4_seeprom_read(adap, vaddr, v);
833 return vaddr < 0 ? vaddr : 0;
836 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v)
838 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
841 vaddr = t4_seeprom_write(adap, vaddr, v);
842 return vaddr < 0 ? vaddr : 0;
845 #define EEPROM_MAGIC 0x38E2F10C
847 static int cxgbe_get_eeprom(struct rte_eth_dev *dev,
848 struct rte_dev_eeprom_info *e)
850 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
851 struct adapter *adapter = pi->adapter;
853 u8 *buf = rte_zmalloc(NULL, EEPROMSIZE, 0);
858 e->magic = EEPROM_MAGIC;
859 for (i = e->offset & ~3; !err && i < e->offset + e->length; i += 4)
860 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]);
863 rte_memcpy(e->data, buf + e->offset, e->length);
868 static int cxgbe_set_eeprom(struct rte_eth_dev *dev,
869 struct rte_dev_eeprom_info *eeprom)
871 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
872 struct adapter *adapter = pi->adapter;
875 u32 aligned_offset, aligned_len, *p;
877 if (eeprom->magic != EEPROM_MAGIC)
880 aligned_offset = eeprom->offset & ~3;
881 aligned_len = (eeprom->length + (eeprom->offset & 3) + 3) & ~3;
883 if (adapter->pf > 0) {
884 u32 start = 1024 + adapter->pf * EEPROMPFSIZE;
886 if (aligned_offset < start ||
887 aligned_offset + aligned_len > start + EEPROMPFSIZE)
891 if (aligned_offset != eeprom->offset || aligned_len != eeprom->length) {
892 /* RMW possibly needed for first or last words.
894 buf = rte_zmalloc(NULL, aligned_len, 0);
897 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf);
898 if (!err && aligned_len > 4)
899 err = eeprom_rd_phys(adapter,
900 aligned_offset + aligned_len - 4,
901 (u32 *)&buf[aligned_len - 4]);
904 rte_memcpy(buf + (eeprom->offset & 3), eeprom->data,
910 err = t4_seeprom_wp(adapter, false);
914 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
915 err = eeprom_wr_phys(adapter, aligned_offset, *p);
920 err = t4_seeprom_wp(adapter, true);
922 if (buf != eeprom->data)
927 static int cxgbe_get_regs_len(struct rte_eth_dev *eth_dev)
929 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
930 struct adapter *adapter = pi->adapter;
932 return t4_get_regs_len(adapter) / sizeof(uint32_t);
935 static int cxgbe_get_regs(struct rte_eth_dev *eth_dev,
936 struct rte_dev_reg_info *regs)
938 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
939 struct adapter *adapter = pi->adapter;
941 regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) |
942 (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) |
945 if (regs->data == NULL) {
946 regs->length = cxgbe_get_regs_len(eth_dev);
947 regs->width = sizeof(uint32_t);
952 t4_get_regs(adapter, regs->data, (regs->length * sizeof(uint32_t)));
957 static const struct eth_dev_ops cxgbe_eth_dev_ops = {
958 .dev_start = cxgbe_dev_start,
959 .dev_stop = cxgbe_dev_stop,
960 .dev_close = cxgbe_dev_close,
961 .promiscuous_enable = cxgbe_dev_promiscuous_enable,
962 .promiscuous_disable = cxgbe_dev_promiscuous_disable,
963 .allmulticast_enable = cxgbe_dev_allmulticast_enable,
964 .allmulticast_disable = cxgbe_dev_allmulticast_disable,
965 .dev_configure = cxgbe_dev_configure,
966 .dev_infos_get = cxgbe_dev_info_get,
967 .dev_supported_ptypes_get = cxgbe_dev_supported_ptypes_get,
968 .link_update = cxgbe_dev_link_update,
969 .mtu_set = cxgbe_dev_mtu_set,
970 .tx_queue_setup = cxgbe_dev_tx_queue_setup,
971 .tx_queue_start = cxgbe_dev_tx_queue_start,
972 .tx_queue_stop = cxgbe_dev_tx_queue_stop,
973 .tx_queue_release = cxgbe_dev_tx_queue_release,
974 .rx_queue_setup = cxgbe_dev_rx_queue_setup,
975 .rx_queue_start = cxgbe_dev_rx_queue_start,
976 .rx_queue_stop = cxgbe_dev_rx_queue_stop,
977 .rx_queue_release = cxgbe_dev_rx_queue_release,
978 .stats_get = cxgbe_dev_stats_get,
979 .stats_reset = cxgbe_dev_stats_reset,
980 .flow_ctrl_get = cxgbe_flow_ctrl_get,
981 .flow_ctrl_set = cxgbe_flow_ctrl_set,
982 .get_eeprom_length = cxgbe_get_eeprom_length,
983 .get_eeprom = cxgbe_get_eeprom,
984 .set_eeprom = cxgbe_set_eeprom,
985 .get_reg = cxgbe_get_regs,
990 * It returns 0 on success.
992 static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev)
994 struct rte_pci_device *pci_dev;
995 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
996 struct adapter *adapter = NULL;
997 char name[RTE_ETH_NAME_MAX_LEN];
1002 eth_dev->dev_ops = &cxgbe_eth_dev_ops;
1003 eth_dev->rx_pkt_burst = &cxgbe_recv_pkts;
1004 eth_dev->tx_pkt_burst = &cxgbe_xmit_pkts;
1006 /* for secondary processes, we don't initialise any further as primary
1007 * has already done this work.
1009 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1012 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1014 snprintf(name, sizeof(name), "cxgbeadapter%d", eth_dev->data->port_id);
1015 adapter = rte_zmalloc(name, sizeof(*adapter), 0);
1019 adapter->use_unpacked_mode = 1;
1020 adapter->regs = (void *)pci_dev->mem_resource[0].addr;
1021 if (!adapter->regs) {
1022 dev_err(adapter, "%s: cannot map device registers\n", __func__);
1024 goto out_free_adapter;
1026 adapter->pdev = pci_dev;
1027 adapter->eth_dev = eth_dev;
1028 pi->adapter = adapter;
1030 err = cxgbe_probe(adapter);
1032 dev_err(adapter, "%s: cxgbe probe failed with err %d\n",
1034 goto out_free_adapter;
1044 static int eth_cxgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1045 struct rte_pci_device *pci_dev)
1047 return rte_eth_dev_pci_generic_probe(pci_dev,
1048 sizeof(struct port_info), eth_cxgbe_dev_init);
1051 static int eth_cxgbe_pci_remove(struct rte_pci_device *pci_dev)
1053 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
1056 static struct rte_pci_driver rte_cxgbe_pmd = {
1057 .id_table = cxgb4_pci_tbl,
1058 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1059 .probe = eth_cxgbe_pci_probe,
1060 .remove = eth_cxgbe_pci_remove,
1063 RTE_PMD_REGISTER_PCI(net_cxgbe, rte_cxgbe_pmd);
1064 RTE_PMD_REGISTER_PCI_TABLE(net_cxgbe, cxgb4_pci_tbl);
1065 RTE_PMD_REGISTER_KMOD_DEP(net_cxgbe, "* igb_uio | uio_pci_generic | vfio-pci");