drivers/net/cxgbe/cxgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2014-2016 Chelsio Communications.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Chelsio Communications nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43
  44 #include <rte_byteorder.h>
  45 #include <rte_common.h>
  46 #include <rte_cycles.h>
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_tailq.h>
  56 #include <rte_eal.h>
  57 #include <rte_alarm.h>
  58 #include <rte_ether.h>
  59 #include <rte_ethdev.h>
  60 #include <rte_ethdev_pci.h>
  61 #include <rte_atomic.h>
  62 #include <rte_malloc.h>
  63 #include <rte_random.h>
  64 #include <rte_dev.h>
  65
  66 #include "cxgbe.h"
  67
  68 /*
  69  * Macros needed to support the PCI Device ID Table ...
  70  */
  71 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
  72         static const struct rte_pci_id cxgb4_pci_tbl[] = {
  73 #define CH_PCI_DEVICE_ID_FUNCTION 0x4
  74
  75 #define PCI_VENDOR_ID_CHELSIO 0x1425
  76
  77 #define CH_PCI_ID_TABLE_ENTRY(devid) \
  78                 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CHELSIO, (devid)) }
  79
  80 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
  81                 { .vendor_id = 0, } \
  82         }
  83
  84 /*
  85  *... and the PCI ID Table itself ...
  86  */
  87 #include "t4_pci_id_tbl.h"
  88
  89 static uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
  90                                 uint16_t nb_pkts)
  91 {
  92         struct sge_eth_txq *txq = (struct sge_eth_txq *)tx_queue;
  93         uint16_t pkts_sent, pkts_remain;
  94         uint16_t total_sent = 0;
  95         int ret = 0;
  96
  97         CXGBE_DEBUG_TX(adapter, "%s: txq = %p; tx_pkts = %p; nb_pkts = %d\n",
  98                        __func__, txq, tx_pkts, nb_pkts);
  99
 100         t4_os_lock(&txq->txq_lock);
 101         /* free up desc from already completed tx */
 102         reclaim_completed_tx(&txq->q);
 103         while (total_sent < nb_pkts) {
 104                 pkts_remain = nb_pkts - total_sent;
 105
 106                 for (pkts_sent = 0; pkts_sent < pkts_remain; pkts_sent++) {
 107                         ret = t4_eth_xmit(txq, tx_pkts[total_sent + pkts_sent]);
 108                         if (ret < 0)
 109                                 break;
 110                 }
 111                 if (!pkts_sent)
 112                         break;
 113                 total_sent += pkts_sent;
 114                 /* reclaim as much as possible */
 115                 reclaim_completed_tx(&txq->q);
 116         }
 117
 118         t4_os_unlock(&txq->txq_lock);
 119         return total_sent;
 120 }
 121
 122 static uint16_t cxgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
 123                                 uint16_t nb_pkts)
 124 {
 125         struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)rx_queue;
 126         unsigned int work_done;
 127
 128         CXGBE_DEBUG_RX(adapter, "%s: rxq->rspq.cntxt_id = %u; nb_pkts = %d\n",
 129                        __func__, rxq->rspq.cntxt_id, nb_pkts);
 130
 131         if (cxgbe_poll(&rxq->rspq, rx_pkts, (unsigned int)nb_pkts, &work_done))
 132                 dev_err(adapter, "error in cxgbe poll\n");
 133
 134         CXGBE_DEBUG_RX(adapter, "%s: work_done = %u\n", __func__, work_done);
 135         return work_done;
 136 }
 137
 138 static void cxgbe_dev_info_get(struct rte_eth_dev *eth_dev,
 139                                struct rte_eth_dev_info *device_info)
 140 {
 141         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 142         struct adapter *adapter = pi->adapter;
 143         int max_queues = adapter->sge.max_ethqsets / adapter->params.nports;
 144
 145         static const struct rte_eth_desc_lim cxgbe_desc_lim = {
 146                 .nb_max = CXGBE_MAX_RING_DESC_SIZE,
 147                 .nb_min = CXGBE_MIN_RING_DESC_SIZE,
 148                 .nb_align = 1,
 149         };
 150
 151         device_info->pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 152
 153         device_info->min_rx_bufsize = CXGBE_MIN_RX_BUFSIZE;
 154         device_info->max_rx_pktlen = CXGBE_MAX_RX_PKTLEN;
 155         device_info->max_rx_queues = max_queues;
 156         device_info->max_tx_queues = max_queues;
 157         device_info->max_mac_addrs = 1;
 158         /* XXX: For now we support one MAC/port */
 159         device_info->max_vfs = adapter->params.arch.vfcount;
 160         device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */
 161
 162         device_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
 163                                        DEV_RX_OFFLOAD_IPV4_CKSUM |
 164                                        DEV_RX_OFFLOAD_UDP_CKSUM |
 165                                        DEV_RX_OFFLOAD_TCP_CKSUM;
 166
 167         device_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
 168                                        DEV_TX_OFFLOAD_IPV4_CKSUM |
 169                                        DEV_TX_OFFLOAD_UDP_CKSUM |
 170                                        DEV_TX_OFFLOAD_TCP_CKSUM |
 171                                        DEV_TX_OFFLOAD_TCP_TSO;
 172
 173         device_info->reta_size = pi->rss_size;
 174
 175         device_info->rx_desc_lim = cxgbe_desc_lim;
 176         device_info->tx_desc_lim = cxgbe_desc_lim;
 177         device_info->speed_capa = ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G;
 178 }
 179
 180 static void cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
 181 {
 182         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 183         struct adapter *adapter = pi->adapter;
 184
 185         t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 186                       1, -1, 1, -1, false);
 187 }
 188
 189 static void cxgbe_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
 190 {
 191         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 192         struct adapter *adapter = pi->adapter;
 193
 194         t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 195                       0, -1, 1, -1, false);
 196 }
 197
 198 static void cxgbe_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
 199 {
 200         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 201         struct adapter *adapter = pi->adapter;
 202
 203         /* TODO: address filters ?? */
 204
 205         t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 206                       -1, 1, 1, -1, false);
 207 }
 208
 209 static void cxgbe_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
 210 {
 211         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 212         struct adapter *adapter = pi->adapter;
 213
 214         /* TODO: address filters ?? */
 215
 216         t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 217                       -1, 0, 1, -1, false);
 218 }
 219
 220 static int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev,
 221                                  __rte_unused int wait_to_complete)
 222 {
 223         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 224         struct adapter *adapter = pi->adapter;
 225         struct sge *s = &adapter->sge;
 226         struct rte_eth_link *old_link = &eth_dev->data->dev_link;
 227         unsigned int work_done, budget = 4;
 228
 229         cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
 230         if (old_link->link_status == pi->link_cfg.link_ok)
 231                 return -1;  /* link not changed */
 232
 233         eth_dev->data->dev_link.link_status = pi->link_cfg.link_ok;
 234         eth_dev->data->dev_link.link_duplex = ETH_LINK_FULL_DUPLEX;
 235         eth_dev->data->dev_link.link_speed = pi->link_cfg.speed;
 236
 237         /* link has changed */
 238         return 0;
 239 }
 240
 241 static int cxgbe_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
 242 {
 243         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 244         struct adapter *adapter = pi->adapter;
 245         struct rte_eth_dev_info dev_info;
 246         int err;
 247         uint16_t new_mtu = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
 248
 249         cxgbe_dev_info_get(eth_dev, &dev_info);
 250
 251         /* Must accommodate at least ETHER_MIN_MTU */
 252         if ((new_mtu < ETHER_MIN_MTU) || (new_mtu > dev_info.max_rx_pktlen))
 253                 return -EINVAL;
 254
 255         /* set to jumbo mode if needed */
 256         if (new_mtu > ETHER_MAX_LEN)
 257                 eth_dev->data->dev_conf.rxmode.jumbo_frame = 1;
 258         else
 259                 eth_dev->data->dev_conf.rxmode.jumbo_frame = 0;
 260
 261         err = t4_set_rxmode(adapter, adapter->mbox, pi->viid, new_mtu, -1, -1,
 262                             -1, -1, true);
 263         if (!err)
 264                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_mtu;
 265
 266         return err;
 267 }
 268
 269 static int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev,
 270                                     uint16_t tx_queue_id);
 271 static int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev,
 272                                     uint16_t tx_queue_id);
 273 static void cxgbe_dev_tx_queue_release(void *q);
 274 static void cxgbe_dev_rx_queue_release(void *q);
 275
 276 /*
 277  * Stop device.
 278  */
 279 static void cxgbe_dev_close(struct rte_eth_dev *eth_dev)
 280 {
 281         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 282         struct adapter *adapter = pi->adapter;
 283         int i, dev_down = 0;
 284
 285         CXGBE_FUNC_TRACE();
 286
 287         if (!(adapter->flags & FULL_INIT_DONE))
 288                 return;
 289
 290         cxgbe_down(pi);
 291
 292         /*
 293          *  We clear queues only if both tx and rx path of the port
 294          *  have been disabled
 295          */
 296         t4_sge_eth_clear_queues(pi);
 297
 298         /*  See if all ports are down */
 299         for_each_port(adapter, i) {
 300                 pi = adap2pinfo(adapter, i);
 301                 /*
 302                  * Skip first port of the adapter since it will be closed
 303                  * by DPDK
 304                  */
 305                 if (i == 0)
 306                         continue;
 307                 dev_down += (pi->eth_dev->data->dev_started == 0) ? 1 : 0;
 308         }
 309
 310         /* If rest of the ports are stopped, then free up resources */
 311         if (dev_down == (adapter->params.nports - 1))
 312                 cxgbe_close(adapter);
 313 }
 314
 315 /* Start the device.
 316  * It returns 0 on success.
 317  */
 318 static int cxgbe_dev_start(struct rte_eth_dev *eth_dev)
 319 {
 320         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 321         struct adapter *adapter = pi->adapter;
 322         int err = 0, i;
 323
 324         CXGBE_FUNC_TRACE();
 325
 326         /*
 327          * If we don't have a connection to the firmware there's nothing we
 328          * can do.
 329          */
 330         if (!(adapter->flags & FW_OK)) {
 331                 err = -ENXIO;
 332                 goto out;
 333         }
 334
 335         if (!(adapter->flags & FULL_INIT_DONE)) {
 336                 err = cxgbe_up(adapter);
 337                 if (err < 0)
 338                         goto out;
 339         }
 340
 341         err = setup_rss(pi);
 342         if (err)
 343                 goto out;
 344
 345         for (i = 0; i < pi->n_tx_qsets; i++) {
 346                 err = cxgbe_dev_tx_queue_start(eth_dev, i);
 347                 if (err)
 348                         goto out;
 349         }
 350
 351         for (i = 0; i < pi->n_rx_qsets; i++) {
 352                 err = cxgbe_dev_rx_queue_start(eth_dev, i);
 353                 if (err)
 354                         goto out;
 355         }
 356
 357         err = link_start(pi);
 358         if (err)
 359                 goto out;
 360
 361 out:
 362         return err;
 363 }
 364
 365 /*
 366  * Stop device: disable rx and tx functions to allow for reconfiguring.
 367  */
 368 static void cxgbe_dev_stop(struct rte_eth_dev *eth_dev)
 369 {
 370         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 371         struct adapter *adapter = pi->adapter;
 372
 373         CXGBE_FUNC_TRACE();
 374
 375         if (!(adapter->flags & FULL_INIT_DONE))
 376                 return;
 377
 378         cxgbe_down(pi);
 379
 380         /*
 381          *  We clear queues only if both tx and rx path of the port
 382          *  have been disabled
 383          */
 384         t4_sge_eth_clear_queues(pi);
 385 }
 386
 387 static int cxgbe_dev_configure(struct rte_eth_dev *eth_dev)
 388 {
 389         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 390         struct adapter *adapter = pi->adapter;
 391         int err;
 392
 393         CXGBE_FUNC_TRACE();
 394
 395         if (!(adapter->flags & FW_QUEUE_BOUND)) {
 396                 err = setup_sge_fwevtq(adapter);
 397                 if (err)
 398                         return err;
 399                 adapter->flags |= FW_QUEUE_BOUND;
 400         }
 401
 402         err = cfg_queue_count(eth_dev);
 403         if (err)
 404                 return err;
 405
 406         return 0;
 407 }
 408
 409 static int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev,
 410                                     uint16_t tx_queue_id)
 411 {
 412         int ret;
 413         struct sge_eth_txq *txq = (struct sge_eth_txq *)
 414                                   (eth_dev->data->tx_queues[tx_queue_id]);
 415
 416         dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
 417
 418         ret = t4_sge_eth_txq_start(txq);
 419         if (ret == 0)
 420                 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 421
 422         return ret;
 423 }
 424
 425 static int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev,
 426                                    uint16_t tx_queue_id)
 427 {
 428         int ret;
 429         struct sge_eth_txq *txq = (struct sge_eth_txq *)
 430                                   (eth_dev->data->tx_queues[tx_queue_id]);
 431
 432         dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
 433
 434         ret = t4_sge_eth_txq_stop(txq);
 435         if (ret == 0)
 436                 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 437
 438         return ret;
 439 }
 440
 441 static int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev,
 442                                     uint16_t queue_idx, uint16_t nb_desc,
 443                                     unsigned int socket_id,
 444                                     const struct rte_eth_txconf *tx_conf)
 445 {
 446         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 447         struct adapter *adapter = pi->adapter;
 448         struct sge *s = &adapter->sge;
 449         struct sge_eth_txq *txq = &s->ethtxq[pi->first_qset + queue_idx];
 450         int err = 0;
 451         unsigned int temp_nb_desc;
 452
 453         RTE_SET_USED(tx_conf);
 454
 455         dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n",
 456                   __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc,
 457                   socket_id, pi->first_qset);
 458
 459         /*  Free up the existing queue  */
 460         if (eth_dev->data->tx_queues[queue_idx]) {
 461                 cxgbe_dev_tx_queue_release(eth_dev->data->tx_queues[queue_idx]);
 462                 eth_dev->data->tx_queues[queue_idx] = NULL;
 463         }
 464
 465         eth_dev->data->tx_queues[queue_idx] = (void *)txq;
 466
 467         /* Sanity Checking
 468          *
 469          * nb_desc should be > 1023 and <= CXGBE_MAX_RING_DESC_SIZE
 470          */
 471         temp_nb_desc = nb_desc;
 472         if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
 473                 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
 474                          __func__, CXGBE_MIN_RING_DESC_SIZE,
 475                          CXGBE_DEFAULT_TX_DESC_SIZE);
 476                 temp_nb_desc = CXGBE_DEFAULT_TX_DESC_SIZE;
 477         } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
 478                 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
 479                         __func__, CXGBE_MIN_RING_DESC_SIZE,
 480                         CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_TX_DESC_SIZE);
 481                 return -(EINVAL);
 482         }
 483
 484         txq->q.size = temp_nb_desc;
 485
 486         err = t4_sge_alloc_eth_txq(adapter, txq, eth_dev, queue_idx,
 487                                    s->fw_evtq.cntxt_id, socket_id);
 488
 489         dev_debug(adapter, "%s: txq->q.cntxt_id= %d err = %d\n",
 490                   __func__, txq->q.cntxt_id, err);
 491
 492         return err;
 493 }
 494
 495 static void cxgbe_dev_tx_queue_release(void *q)
 496 {
 497         struct sge_eth_txq *txq = (struct sge_eth_txq *)q;
 498
 499         if (txq) {
 500                 struct port_info *pi = (struct port_info *)
 501                                        (txq->eth_dev->data->dev_private);
 502                 struct adapter *adap = pi->adapter;
 503
 504                 dev_debug(adapter, "%s: pi->port_id = %d; tx_queue_id = %d\n",
 505                           __func__, pi->port_id, txq->q.cntxt_id);
 506
 507                 t4_sge_eth_txq_release(adap, txq);
 508         }
 509 }
 510
 511 static int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev,
 512                                     uint16_t rx_queue_id)
 513 {
 514         int ret;
 515         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 516         struct adapter *adap = pi->adapter;
 517         struct sge_rspq *q;
 518
 519         dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
 520                   __func__, pi->port_id, rx_queue_id);
 521
 522         q = eth_dev->data->rx_queues[rx_queue_id];
 523
 524         ret = t4_sge_eth_rxq_start(adap, q);
 525         if (ret == 0)
 526                 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 527
 528         return ret;
 529 }
 530
 531 static int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev,
 532                                    uint16_t rx_queue_id)
 533 {
 534         int ret;
 535         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 536         struct adapter *adap = pi->adapter;
 537         struct sge_rspq *q;
 538
 539         dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
 540                   __func__, pi->port_id, rx_queue_id);
 541
 542         q = eth_dev->data->rx_queues[rx_queue_id];
 543         ret = t4_sge_eth_rxq_stop(adap, q);
 544         if (ret == 0)
 545                 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 546
 547         return ret;
 548 }
 549
 550 static int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev,
 551                                     uint16_t queue_idx, uint16_t nb_desc,
 552                                     unsigned int socket_id,
 553                                     const struct rte_eth_rxconf *rx_conf,
 554                                     struct rte_mempool *mp)
 555 {
 556         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 557         struct adapter *adapter = pi->adapter;
 558         struct sge *s = &adapter->sge;
 559         struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_qset + queue_idx];
 560         int err = 0;
 561         int msi_idx = 0;
 562         unsigned int temp_nb_desc;
 563         struct rte_eth_dev_info dev_info;
 564         unsigned int pkt_len = eth_dev->data->dev_conf.rxmode.max_rx_pkt_len;
 565
 566         RTE_SET_USED(rx_conf);
 567
 568         dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n",
 569                   __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc,
 570                   socket_id, mp);
 571
 572         cxgbe_dev_info_get(eth_dev, &dev_info);
 573
 574         /* Must accommodate at least ETHER_MIN_MTU */
 575         if ((pkt_len < dev_info.min_rx_bufsize) ||
 576             (pkt_len > dev_info.max_rx_pktlen)) {
 577                 dev_err(adap, "%s: max pkt len must be > %d and <= %d\n",
 578                         __func__, dev_info.min_rx_bufsize,
 579                         dev_info.max_rx_pktlen);
 580                 return -EINVAL;
 581         }
 582
 583         /*  Free up the existing queue  */
 584         if (eth_dev->data->rx_queues[queue_idx]) {
 585                 cxgbe_dev_rx_queue_release(eth_dev->data->rx_queues[queue_idx]);
 586                 eth_dev->data->rx_queues[queue_idx] = NULL;
 587         }
 588
 589         eth_dev->data->rx_queues[queue_idx] = (void *)rxq;
 590
 591         /* Sanity Checking
 592          *
 593          * nb_desc should be > 0 and <= CXGBE_MAX_RING_DESC_SIZE
 594          */
 595         temp_nb_desc = nb_desc;
 596         if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
 597                 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
 598                          __func__, CXGBE_MIN_RING_DESC_SIZE,
 599                          CXGBE_DEFAULT_RX_DESC_SIZE);
 600                 temp_nb_desc = CXGBE_DEFAULT_RX_DESC_SIZE;
 601         } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
 602                 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
 603                         __func__, CXGBE_MIN_RING_DESC_SIZE,
 604                         CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_RX_DESC_SIZE);
 605                 return -(EINVAL);
 606         }
 607
 608         rxq->rspq.size = temp_nb_desc;
 609         if ((&rxq->fl) != NULL)
 610                 rxq->fl.size = temp_nb_desc;
 611
 612         /* Set to jumbo mode if necessary */
 613         if (pkt_len > ETHER_MAX_LEN)
 614                 eth_dev->data->dev_conf.rxmode.jumbo_frame = 1;
 615         else
 616                 eth_dev->data->dev_conf.rxmode.jumbo_frame = 0;
 617
 618         err = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx,
 619                                &rxq->fl, t4_ethrx_handler,
 620                                t4_get_mps_bg_map(adapter, pi->tx_chan), mp,
 621                                queue_idx, socket_id);
 622
 623         dev_debug(adapter, "%s: err = %d; port_id = %d; cntxt_id = %u\n",
 624                   __func__, err, pi->port_id, rxq->rspq.cntxt_id);
 625         return err;
 626 }
 627
 628 static void cxgbe_dev_rx_queue_release(void *q)
 629 {
 630         struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)q;
 631         struct sge_rspq *rq = &rxq->rspq;
 632
 633         if (rq) {
 634                 struct port_info *pi = (struct port_info *)
 635                                        (rq->eth_dev->data->dev_private);
 636                 struct adapter *adap = pi->adapter;
 637
 638                 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
 639                           __func__, pi->port_id, rxq->rspq.cntxt_id);
 640
 641                 t4_sge_eth_rxq_release(adap, rxq);
 642         }
 643 }
 644
 645 /*
 646  * Get port statistics.
 647  */
 648 static void cxgbe_dev_stats_get(struct rte_eth_dev *eth_dev,
 649                                 struct rte_eth_stats *eth_stats)
 650 {
 651         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 652         struct adapter *adapter = pi->adapter;
 653         struct sge *s = &adapter->sge;
 654         struct port_stats ps;
 655         unsigned int i;
 656
 657         cxgbe_stats_get(pi, &ps);
 658
 659         /* RX Stats */
 660         eth_stats->ipackets = ps.rx_frames;
 661         eth_stats->ibytes   = ps.rx_octets;
 662         eth_stats->imissed  = ps.rx_ovflow0 + ps.rx_ovflow1 +
 663                               ps.rx_ovflow2 + ps.rx_ovflow3 +
 664                               ps.rx_trunc0 + ps.rx_trunc1 +
 665                               ps.rx_trunc2 + ps.rx_trunc3;
 666         eth_stats->ierrors  = ps.rx_symbol_err + ps.rx_fcs_err +
 667                               ps.rx_jabber + ps.rx_too_long + ps.rx_runt +
 668                               ps.rx_len_err;
 669
 670         /* TX Stats */
 671         eth_stats->opackets = ps.tx_frames;
 672         eth_stats->obytes   = ps.tx_octets;
 673         eth_stats->oerrors  = ps.tx_error_frames;
 674
 675         for (i = 0; i < pi->n_rx_qsets; i++) {
 676                 struct sge_eth_rxq *rxq =
 677                         &s->ethrxq[pi->first_qset + i];
 678
 679                 eth_stats->q_ipackets[i] = rxq->stats.pkts;
 680                 eth_stats->q_ibytes[i] = rxq->stats.rx_bytes;
 681         }
 682
 683         for (i = 0; i < pi->n_tx_qsets; i++) {
 684                 struct sge_eth_txq *txq =
 685                         &s->ethtxq[pi->first_qset + i];
 686
 687                 eth_stats->q_opackets[i] = txq->stats.pkts;
 688                 eth_stats->q_obytes[i] = txq->stats.tx_bytes;
 689                 eth_stats->q_errors[i] = txq->stats.mapping_err;
 690         }
 691 }
 692
 693 /*
 694  * Reset port statistics.
 695  */
 696 static void cxgbe_dev_stats_reset(struct rte_eth_dev *eth_dev)
 697 {
 698         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 699         struct adapter *adapter = pi->adapter;
 700         struct sge *s = &adapter->sge;
 701         unsigned int i;
 702
 703         cxgbe_stats_reset(pi);
 704         for (i = 0; i < pi->n_rx_qsets; i++) {
 705                 struct sge_eth_rxq *rxq =
 706                         &s->ethrxq[pi->first_qset + i];
 707
 708                 rxq->stats.pkts = 0;
 709                 rxq->stats.rx_bytes = 0;
 710         }
 711         for (i = 0; i < pi->n_tx_qsets; i++) {
 712                 struct sge_eth_txq *txq =
 713                         &s->ethtxq[pi->first_qset + i];
 714
 715                 txq->stats.pkts = 0;
 716                 txq->stats.tx_bytes = 0;
 717                 txq->stats.mapping_err = 0;
 718         }
 719 }
 720
 721 static int cxgbe_flow_ctrl_get(struct rte_eth_dev *eth_dev,
 722                                struct rte_eth_fc_conf *fc_conf)
 723 {
 724         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 725         struct link_config *lc = &pi->link_cfg;
 726         int rx_pause, tx_pause;
 727
 728         fc_conf->autoneg = lc->fc & PAUSE_AUTONEG;
 729         rx_pause = lc->fc & PAUSE_RX;
 730         tx_pause = lc->fc & PAUSE_TX;
 731
 732         if (rx_pause && tx_pause)
 733                 fc_conf->mode = RTE_FC_FULL;
 734         else if (rx_pause)
 735                 fc_conf->mode = RTE_FC_RX_PAUSE;
 736         else if (tx_pause)
 737                 fc_conf->mode = RTE_FC_TX_PAUSE;
 738         else
 739                 fc_conf->mode = RTE_FC_NONE;
 740         return 0;
 741 }
 742
 743 static int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev,
 744                                struct rte_eth_fc_conf *fc_conf)
 745 {
 746         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 747         struct adapter *adapter = pi->adapter;
 748         struct link_config *lc = &pi->link_cfg;
 749
 750         if (lc->supported & FW_PORT_CAP_ANEG) {
 751                 if (fc_conf->autoneg)
 752                         lc->requested_fc |= PAUSE_AUTONEG;
 753                 else
 754                         lc->requested_fc &= ~PAUSE_AUTONEG;
 755         }
 756
 757         if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
 758             (fc_conf->mode & RTE_FC_RX_PAUSE))
 759                 lc->requested_fc |= PAUSE_RX;
 760         else
 761                 lc->requested_fc &= ~PAUSE_RX;
 762
 763         if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
 764             (fc_conf->mode & RTE_FC_TX_PAUSE))
 765                 lc->requested_fc |= PAUSE_TX;
 766         else
 767                 lc->requested_fc &= ~PAUSE_TX;
 768
 769         return t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,
 770                              &pi->link_cfg);
 771 }
 772
 773 static const uint32_t *
 774 cxgbe_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
 775 {
 776         static const uint32_t ptypes[] = {
 777                 RTE_PTYPE_L3_IPV4,
 778                 RTE_PTYPE_L3_IPV6,
 779                 RTE_PTYPE_UNKNOWN
 780         };
 781
 782         if (eth_dev->rx_pkt_burst == cxgbe_recv_pkts)
 783                 return ptypes;
 784         return NULL;
 785 }
 786
 787 static int cxgbe_get_eeprom_length(struct rte_eth_dev *dev)
 788 {
 789         RTE_SET_USED(dev);
 790         return EEPROMSIZE;
 791 }
 792
 793 /**
 794  * eeprom_ptov - translate a physical EEPROM address to virtual
 795  * @phys_addr: the physical EEPROM address
 796  * @fn: the PCI function number
 797  * @sz: size of function-specific area
 798  *
 799  * Translate a physical EEPROM address to virtual.  The first 1K is
 800  * accessed through virtual addresses starting at 31K, the rest is
 801  * accessed through virtual addresses starting at 0.
 802  *
 803  * The mapping is as follows:
 804  * [0..1K) -> [31K..32K)
 805  * [1K..1K+A) -> [31K-A..31K)
 806  * [1K+A..ES) -> [0..ES-A-1K)
 807  *
 808  * where A = @fn * @sz, and ES = EEPROM size.
 809  */
 810 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
 811 {
 812         fn *= sz;
 813         if (phys_addr < 1024)
 814                 return phys_addr + (31 << 10);
 815         if (phys_addr < 1024 + fn)
 816                 return fn + phys_addr - 1024;
 817         if (phys_addr < EEPROMSIZE)
 818                 return phys_addr - 1024 - fn;
 819         if (phys_addr < EEPROMVSIZE)
 820                 return phys_addr - 1024;
 821         return -EINVAL;
 822 }
 823
 824 /* The next two routines implement eeprom read/write from physical addresses.
 825  */
 826 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v)
 827 {
 828         int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
 829
 830         if (vaddr >= 0)
 831                 vaddr = t4_seeprom_read(adap, vaddr, v);
 832         return vaddr < 0 ? vaddr : 0;
 833 }
 834
 835 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v)
 836 {
 837         int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
 838
 839         if (vaddr >= 0)
 840                 vaddr = t4_seeprom_write(adap, vaddr, v);
 841         return vaddr < 0 ? vaddr : 0;
 842 }
 843
 844 #define EEPROM_MAGIC 0x38E2F10C
 845
 846 static int cxgbe_get_eeprom(struct rte_eth_dev *dev,
 847                             struct rte_dev_eeprom_info *e)
 848 {
 849         struct port_info *pi = (struct port_info *)(dev->data->dev_private);
 850         struct adapter *adapter = pi->adapter;
 851         u32 i, err = 0;
 852         u8 *buf = rte_zmalloc(NULL, EEPROMSIZE, 0);
 853
 854         if (!buf)
 855                 return -ENOMEM;
 856
 857         e->magic = EEPROM_MAGIC;
 858         for (i = e->offset & ~3; !err && i < e->offset + e->length; i += 4)
 859                 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]);
 860
 861         if (!err)
 862                 rte_memcpy(e->data, buf + e->offset, e->length);
 863         rte_free(buf);
 864         return err;
 865 }
 866
 867 static int cxgbe_set_eeprom(struct rte_eth_dev *dev,
 868                             struct rte_dev_eeprom_info *eeprom)
 869 {
 870         struct port_info *pi = (struct port_info *)(dev->data->dev_private);
 871         struct adapter *adapter = pi->adapter;
 872         u8 *buf;
 873         int err = 0;
 874         u32 aligned_offset, aligned_len, *p;
 875
 876         if (eeprom->magic != EEPROM_MAGIC)
 877                 return -EINVAL;
 878
 879         aligned_offset = eeprom->offset & ~3;
 880         aligned_len = (eeprom->length + (eeprom->offset & 3) + 3) & ~3;
 881
 882         if (adapter->pf > 0) {
 883                 u32 start = 1024 + adapter->pf * EEPROMPFSIZE;
 884
 885                 if (aligned_offset < start ||
 886                     aligned_offset + aligned_len > start + EEPROMPFSIZE)
 887                         return -EPERM;
 888         }
 889
 890         if (aligned_offset != eeprom->offset || aligned_len != eeprom->length) {
 891                 /* RMW possibly needed for first or last words.
 892                  */
 893                 buf = rte_zmalloc(NULL, aligned_len, 0);
 894                 if (!buf)
 895                         return -ENOMEM;
 896                 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf);
 897                 if (!err && aligned_len > 4)
 898                         err = eeprom_rd_phys(adapter,
 899                                              aligned_offset + aligned_len - 4,
 900                                              (u32 *)&buf[aligned_len - 4]);
 901                 if (err)
 902                         goto out;
 903                 rte_memcpy(buf + (eeprom->offset & 3), eeprom->data,
 904                            eeprom->length);
 905         } else {
 906                 buf = eeprom->data;
 907         }
 908
 909         err = t4_seeprom_wp(adapter, false);
 910         if (err)
 911                 goto out;
 912
 913         for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
 914                 err = eeprom_wr_phys(adapter, aligned_offset, *p);
 915                 aligned_offset += 4;
 916         }
 917
 918         if (!err)
 919                 err = t4_seeprom_wp(adapter, true);
 920 out:
 921         if (buf != eeprom->data)
 922                 rte_free(buf);
 923         return err;
 924 }
 925
 926 static int cxgbe_get_regs_len(struct rte_eth_dev *eth_dev)
 927 {
 928         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 929         struct adapter *adapter = pi->adapter;
 930
 931         return t4_get_regs_len(adapter) / sizeof(uint32_t);
 932 }
 933
 934 static int cxgbe_get_regs(struct rte_eth_dev *eth_dev,
 935                           struct rte_dev_reg_info *regs)
 936 {
 937         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 938         struct adapter *adapter = pi->adapter;
 939
 940         regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) |
 941                 (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) |
 942                 (1 << 16);
 943
 944         if (regs->data == NULL) {
 945                 regs->length = cxgbe_get_regs_len(eth_dev);
 946                 regs->width = sizeof(uint32_t);
 947
 948                 return 0;
 949         }
 950
 951         t4_get_regs(adapter, regs->data, (regs->length * sizeof(uint32_t)));
 952
 953         return 0;
 954 }
 955
 956 static const struct eth_dev_ops cxgbe_eth_dev_ops = {
 957         .dev_start              = cxgbe_dev_start,
 958         .dev_stop               = cxgbe_dev_stop,
 959         .dev_close              = cxgbe_dev_close,
 960         .promiscuous_enable     = cxgbe_dev_promiscuous_enable,
 961         .promiscuous_disable    = cxgbe_dev_promiscuous_disable,
 962         .allmulticast_enable    = cxgbe_dev_allmulticast_enable,
 963         .allmulticast_disable   = cxgbe_dev_allmulticast_disable,
 964         .dev_configure          = cxgbe_dev_configure,
 965         .dev_infos_get          = cxgbe_dev_info_get,
 966         .dev_supported_ptypes_get = cxgbe_dev_supported_ptypes_get,
 967         .link_update            = cxgbe_dev_link_update,
 968         .mtu_set                = cxgbe_dev_mtu_set,
 969         .tx_queue_setup         = cxgbe_dev_tx_queue_setup,
 970         .tx_queue_start         = cxgbe_dev_tx_queue_start,
 971         .tx_queue_stop          = cxgbe_dev_tx_queue_stop,
 972         .tx_queue_release       = cxgbe_dev_tx_queue_release,
 973         .rx_queue_setup         = cxgbe_dev_rx_queue_setup,
 974         .rx_queue_start         = cxgbe_dev_rx_queue_start,
 975         .rx_queue_stop          = cxgbe_dev_rx_queue_stop,
 976         .rx_queue_release       = cxgbe_dev_rx_queue_release,
 977         .stats_get              = cxgbe_dev_stats_get,
 978         .stats_reset            = cxgbe_dev_stats_reset,
 979         .flow_ctrl_get          = cxgbe_flow_ctrl_get,
 980         .flow_ctrl_set          = cxgbe_flow_ctrl_set,
 981         .get_eeprom_length      = cxgbe_get_eeprom_length,
 982         .get_eeprom             = cxgbe_get_eeprom,
 983         .set_eeprom             = cxgbe_set_eeprom,
 984         .get_reg                = cxgbe_get_regs,
 985 };
 986
 987 /*
 988  * Initialize driver
 989  * It returns 0 on success.
 990  */
 991 static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev)
 992 {
 993         struct rte_pci_device *pci_dev;
 994         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 995         struct adapter *adapter = NULL;
 996         char name[RTE_ETH_NAME_MAX_LEN];
 997         int err = 0;
 998
 999         CXGBE_FUNC_TRACE();
1000
1001         eth_dev->dev_ops = &cxgbe_eth_dev_ops;
1002         eth_dev->rx_pkt_burst = &cxgbe_recv_pkts;
1003         eth_dev->tx_pkt_burst = &cxgbe_xmit_pkts;
1004
1005         /* for secondary processes, we don't initialise any further as primary
1006          * has already done this work.
1007          */
1008         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1009                 return 0;
1010
1011         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1012
1013         snprintf(name, sizeof(name), "cxgbeadapter%d", eth_dev->data->port_id);
1014         adapter = rte_zmalloc(name, sizeof(*adapter), 0);
1015         if (!adapter)
1016                 return -1;
1017
1018         adapter->use_unpacked_mode = 1;
1019         adapter->regs = (void *)pci_dev->mem_resource[0].addr;
1020         if (!adapter->regs) {
1021                 dev_err(adapter, "%s: cannot map device registers\n", __func__);
1022                 err = -ENOMEM;
1023                 goto out_free_adapter;
1024         }
1025         adapter->pdev = pci_dev;
1026         adapter->eth_dev = eth_dev;
1027         pi->adapter = adapter;
1028
1029         err = cxgbe_probe(adapter);
1030         if (err) {
1031                 dev_err(adapter, "%s: cxgbe probe failed with err %d\n",
1032                         __func__, err);
1033                 goto out_free_adapter;
1034         }
1035
1036         return 0;
1037
1038 out_free_adapter:
1039         rte_free(adapter);
1040         return err;
1041 }
1042
1043 static int eth_cxgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1044         struct rte_pci_device *pci_dev)
1045 {
1046         return rte_eth_dev_pci_generic_probe(pci_dev,
1047                 sizeof(struct port_info), eth_cxgbe_dev_init);
1048 }
1049
1050 static int eth_cxgbe_pci_remove(struct rte_pci_device *pci_dev)
1051 {
1052         return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
1053 }
1054
1055 static struct rte_pci_driver rte_cxgbe_pmd = {
1056         .id_table = cxgb4_pci_tbl,
1057         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1058         .probe = eth_cxgbe_pci_probe,
1059         .remove = eth_cxgbe_pci_remove,
1060 };
1061
1062 RTE_PMD_REGISTER_PCI(net_cxgbe, rte_cxgbe_pmd);
1063 RTE_PMD_REGISTER_PCI_TABLE(net_cxgbe, cxgb4_pci_tbl);
1064 RTE_PMD_REGISTER_KMOD_DEP(net_cxgbe, "* igb_uio | uio_pci_generic | vfio-pci");