ethdev: return diagnostic when setting MAC address
[dpdk.git] / drivers / net / cxgbe / cxgbe_ethdev.c
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(c) 2014-2018 Chelsio Communications.
3  * All rights reserved.
4  */
5
6 #include <sys/queue.h>
7 #include <stdio.h>
8 #include <errno.h>
9 #include <stdint.h>
10 #include <string.h>
11 #include <unistd.h>
12 #include <stdarg.h>
13 #include <inttypes.h>
14 #include <netinet/in.h>
15
16 #include <rte_byteorder.h>
17 #include <rte_common.h>
18 #include <rte_cycles.h>
19 #include <rte_interrupts.h>
20 #include <rte_log.h>
21 #include <rte_debug.h>
22 #include <rte_pci.h>
23 #include <rte_bus_pci.h>
24 #include <rte_atomic.h>
25 #include <rte_branch_prediction.h>
26 #include <rte_memory.h>
27 #include <rte_tailq.h>
28 #include <rte_eal.h>
29 #include <rte_alarm.h>
30 #include <rte_ether.h>
31 #include <rte_ethdev_driver.h>
32 #include <rte_ethdev_pci.h>
33 #include <rte_malloc.h>
34 #include <rte_random.h>
35 #include <rte_dev.h>
36
37 #include "cxgbe.h"
38 #include "cxgbe_pfvf.h"
39
40 /*
41  * Macros needed to support the PCI Device ID Table ...
42  */
43 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
44         static const struct rte_pci_id cxgb4_pci_tbl[] = {
45 #define CH_PCI_DEVICE_ID_FUNCTION 0x4
46
47 #define PCI_VENDOR_ID_CHELSIO 0x1425
48
49 #define CH_PCI_ID_TABLE_ENTRY(devid) \
50                 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CHELSIO, (devid)) }
51
52 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
53                 { .vendor_id = 0, } \
54         }
55
56 /*
57  *... and the PCI ID Table itself ...
58  */
59 #include "t4_pci_id_tbl.h"
60
61 #define CXGBE_TX_OFFLOADS (DEV_TX_OFFLOAD_VLAN_INSERT |\
62                            DEV_TX_OFFLOAD_IPV4_CKSUM |\
63                            DEV_TX_OFFLOAD_UDP_CKSUM |\
64                            DEV_TX_OFFLOAD_TCP_CKSUM |\
65                            DEV_TX_OFFLOAD_TCP_TSO)
66
67 #define CXGBE_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_STRIP |\
68                            DEV_RX_OFFLOAD_CRC_STRIP |\
69                            DEV_RX_OFFLOAD_IPV4_CKSUM |\
70                            DEV_RX_OFFLOAD_JUMBO_FRAME |\
71                            DEV_RX_OFFLOAD_UDP_CKSUM |\
72                            DEV_RX_OFFLOAD_TCP_CKSUM)
73
74 uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
75                          uint16_t nb_pkts)
76 {
77         struct sge_eth_txq *txq = (struct sge_eth_txq *)tx_queue;
78         uint16_t pkts_sent, pkts_remain;
79         uint16_t total_sent = 0;
80         int ret = 0;
81
82         CXGBE_DEBUG_TX(adapter, "%s: txq = %p; tx_pkts = %p; nb_pkts = %d\n",
83                        __func__, txq, tx_pkts, nb_pkts);
84
85         t4_os_lock(&txq->txq_lock);
86         /* free up desc from already completed tx */
87         reclaim_completed_tx(&txq->q);
88         while (total_sent < nb_pkts) {
89                 pkts_remain = nb_pkts - total_sent;
90
91                 for (pkts_sent = 0; pkts_sent < pkts_remain; pkts_sent++) {
92                         ret = t4_eth_xmit(txq, tx_pkts[total_sent + pkts_sent],
93                                           nb_pkts);
94                         if (ret < 0)
95                                 break;
96                 }
97                 if (!pkts_sent)
98                         break;
99                 total_sent += pkts_sent;
100                 /* reclaim as much as possible */
101                 reclaim_completed_tx(&txq->q);
102         }
103
104         t4_os_unlock(&txq->txq_lock);
105         return total_sent;
106 }
107
108 uint16_t cxgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
109                          uint16_t nb_pkts)
110 {
111         struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)rx_queue;
112         unsigned int work_done;
113
114         CXGBE_DEBUG_RX(adapter, "%s: rxq->rspq.cntxt_id = %u; nb_pkts = %d\n",
115                        __func__, rxq->rspq.cntxt_id, nb_pkts);
116
117         if (cxgbe_poll(&rxq->rspq, rx_pkts, (unsigned int)nb_pkts, &work_done))
118                 dev_err(adapter, "error in cxgbe poll\n");
119
120         CXGBE_DEBUG_RX(adapter, "%s: work_done = %u\n", __func__, work_done);
121         return work_done;
122 }
123
124 void cxgbe_dev_info_get(struct rte_eth_dev *eth_dev,
125                         struct rte_eth_dev_info *device_info)
126 {
127         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
128         struct adapter *adapter = pi->adapter;
129         int max_queues = adapter->sge.max_ethqsets / adapter->params.nports;
130
131         static const struct rte_eth_desc_lim cxgbe_desc_lim = {
132                 .nb_max = CXGBE_MAX_RING_DESC_SIZE,
133                 .nb_min = CXGBE_MIN_RING_DESC_SIZE,
134                 .nb_align = 1,
135         };
136
137         device_info->min_rx_bufsize = CXGBE_MIN_RX_BUFSIZE;
138         device_info->max_rx_pktlen = CXGBE_MAX_RX_PKTLEN;
139         device_info->max_rx_queues = max_queues;
140         device_info->max_tx_queues = max_queues;
141         device_info->max_mac_addrs = 1;
142         /* XXX: For now we support one MAC/port */
143         device_info->max_vfs = adapter->params.arch.vfcount;
144         device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */
145
146         device_info->rx_queue_offload_capa = 0UL;
147         device_info->rx_offload_capa = CXGBE_RX_OFFLOADS;
148
149         device_info->tx_queue_offload_capa = 0UL;
150         device_info->tx_offload_capa = CXGBE_TX_OFFLOADS;
151
152         device_info->reta_size = pi->rss_size;
153         device_info->hash_key_size = CXGBE_DEFAULT_RSS_KEY_LEN;
154         device_info->flow_type_rss_offloads = CXGBE_RSS_HF_ALL;
155
156         device_info->rx_desc_lim = cxgbe_desc_lim;
157         device_info->tx_desc_lim = cxgbe_desc_lim;
158         cxgbe_get_speed_caps(pi, &device_info->speed_capa);
159 }
160
161 void cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
162 {
163         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
164         struct adapter *adapter = pi->adapter;
165
166         t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
167                       1, -1, 1, -1, false);
168 }
169
170 void cxgbe_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
171 {
172         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
173         struct adapter *adapter = pi->adapter;
174
175         t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
176                       0, -1, 1, -1, false);
177 }
178
179 void cxgbe_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
180 {
181         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
182         struct adapter *adapter = pi->adapter;
183
184         /* TODO: address filters ?? */
185
186         t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
187                       -1, 1, 1, -1, false);
188 }
189
190 void cxgbe_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
191 {
192         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
193         struct adapter *adapter = pi->adapter;
194
195         /* TODO: address filters ?? */
196
197         t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
198                       -1, 0, 1, -1, false);
199 }
200
201 int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev,
202                           __rte_unused int wait_to_complete)
203 {
204         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
205         struct adapter *adapter = pi->adapter;
206         struct sge *s = &adapter->sge;
207         struct rte_eth_link *old_link = &eth_dev->data->dev_link;
208         unsigned int work_done, budget = 4;
209
210         cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
211         if (old_link->link_status == pi->link_cfg.link_ok)
212                 return -1;  /* link not changed */
213
214         eth_dev->data->dev_link.link_status = pi->link_cfg.link_ok;
215         eth_dev->data->dev_link.link_duplex = ETH_LINK_FULL_DUPLEX;
216         eth_dev->data->dev_link.link_speed = pi->link_cfg.speed;
217
218         /* link has changed */
219         return 0;
220 }
221
222 int cxgbe_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
223 {
224         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
225         struct adapter *adapter = pi->adapter;
226         struct rte_eth_dev_info dev_info;
227         int err;
228         uint16_t new_mtu = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
229
230         cxgbe_dev_info_get(eth_dev, &dev_info);
231
232         /* Must accommodate at least ETHER_MIN_MTU */
233         if ((new_mtu < ETHER_MIN_MTU) || (new_mtu > dev_info.max_rx_pktlen))
234                 return -EINVAL;
235
236         /* set to jumbo mode if needed */
237         if (new_mtu > ETHER_MAX_LEN)
238                 eth_dev->data->dev_conf.rxmode.offloads |=
239                         DEV_RX_OFFLOAD_JUMBO_FRAME;
240         else
241                 eth_dev->data->dev_conf.rxmode.offloads &=
242                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
243
244         err = t4_set_rxmode(adapter, adapter->mbox, pi->viid, new_mtu, -1, -1,
245                             -1, -1, true);
246         if (!err)
247                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_mtu;
248
249         return err;
250 }
251
252 /*
253  * Stop device.
254  */
255 void cxgbe_dev_close(struct rte_eth_dev *eth_dev)
256 {
257         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
258         struct adapter *adapter = pi->adapter;
259         int i, dev_down = 0;
260
261         CXGBE_FUNC_TRACE();
262
263         if (!(adapter->flags & FULL_INIT_DONE))
264                 return;
265
266         cxgbe_down(pi);
267
268         /*
269          *  We clear queues only if both tx and rx path of the port
270          *  have been disabled
271          */
272         t4_sge_eth_clear_queues(pi);
273
274         /*  See if all ports are down */
275         for_each_port(adapter, i) {
276                 pi = adap2pinfo(adapter, i);
277                 /*
278                  * Skip first port of the adapter since it will be closed
279                  * by DPDK
280                  */
281                 if (i == 0)
282                         continue;
283                 dev_down += (pi->eth_dev->data->dev_started == 0) ? 1 : 0;
284         }
285
286         /* If rest of the ports are stopped, then free up resources */
287         if (dev_down == (adapter->params.nports - 1))
288                 cxgbe_close(adapter);
289 }
290
291 /* Start the device.
292  * It returns 0 on success.
293  */
294 int cxgbe_dev_start(struct rte_eth_dev *eth_dev)
295 {
296         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
297         struct adapter *adapter = pi->adapter;
298         int err = 0, i;
299
300         CXGBE_FUNC_TRACE();
301
302         /*
303          * If we don't have a connection to the firmware there's nothing we
304          * can do.
305          */
306         if (!(adapter->flags & FW_OK)) {
307                 err = -ENXIO;
308                 goto out;
309         }
310
311         if (!(adapter->flags & FULL_INIT_DONE)) {
312                 err = cxgbe_up(adapter);
313                 if (err < 0)
314                         goto out;
315         }
316
317         cxgbe_enable_rx_queues(pi);
318
319         err = setup_rss(pi);
320         if (err)
321                 goto out;
322
323         for (i = 0; i < pi->n_tx_qsets; i++) {
324                 err = cxgbe_dev_tx_queue_start(eth_dev, i);
325                 if (err)
326                         goto out;
327         }
328
329         for (i = 0; i < pi->n_rx_qsets; i++) {
330                 err = cxgbe_dev_rx_queue_start(eth_dev, i);
331                 if (err)
332                         goto out;
333         }
334
335         err = link_start(pi);
336         if (err)
337                 goto out;
338
339 out:
340         return err;
341 }
342
343 /*
344  * Stop device: disable rx and tx functions to allow for reconfiguring.
345  */
346 void cxgbe_dev_stop(struct rte_eth_dev *eth_dev)
347 {
348         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
349         struct adapter *adapter = pi->adapter;
350
351         CXGBE_FUNC_TRACE();
352
353         if (!(adapter->flags & FULL_INIT_DONE))
354                 return;
355
356         cxgbe_down(pi);
357
358         /*
359          *  We clear queues only if both tx and rx path of the port
360          *  have been disabled
361          */
362         t4_sge_eth_clear_queues(pi);
363 }
364
365 int cxgbe_dev_configure(struct rte_eth_dev *eth_dev)
366 {
367         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
368         struct adapter *adapter = pi->adapter;
369         uint64_t unsupported_offloads, configured_offloads;
370         int err;
371
372         CXGBE_FUNC_TRACE();
373         configured_offloads = eth_dev->data->dev_conf.rxmode.offloads;
374         if (!(configured_offloads & DEV_RX_OFFLOAD_CRC_STRIP)) {
375                 dev_info(adapter, "can't disable hw crc strip\n");
376                 configured_offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
377         }
378
379         unsupported_offloads = configured_offloads & ~CXGBE_RX_OFFLOADS;
380         if (unsupported_offloads) {
381                 dev_err(adapter, "Rx offloads 0x%" PRIx64 " are not supported. "
382                         "Supported:0x%" PRIx64 "\n",
383                         unsupported_offloads, (uint64_t)CXGBE_RX_OFFLOADS);
384                 return -ENOTSUP;
385         }
386
387         configured_offloads = eth_dev->data->dev_conf.txmode.offloads;
388         unsupported_offloads = configured_offloads & ~CXGBE_TX_OFFLOADS;
389         if (unsupported_offloads) {
390                 dev_err(adapter, "Tx offloads 0x%" PRIx64 " are not supported. "
391                         "Supported:0x%" PRIx64 "\n",
392                         unsupported_offloads, (uint64_t)CXGBE_TX_OFFLOADS);
393                 return -ENOTSUP;
394         }
395
396         if (!(adapter->flags & FW_QUEUE_BOUND)) {
397                 err = setup_sge_fwevtq(adapter);
398                 if (err)
399                         return err;
400                 adapter->flags |= FW_QUEUE_BOUND;
401         }
402
403         err = cfg_queue_count(eth_dev);
404         if (err)
405                 return err;
406
407         return 0;
408 }
409
410 int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
411 {
412         int ret;
413         struct sge_eth_txq *txq = (struct sge_eth_txq *)
414                                   (eth_dev->data->tx_queues[tx_queue_id]);
415
416         dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
417
418         ret = t4_sge_eth_txq_start(txq);
419         if (ret == 0)
420                 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
421
422         return ret;
423 }
424
425 int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
426 {
427         int ret;
428         struct sge_eth_txq *txq = (struct sge_eth_txq *)
429                                   (eth_dev->data->tx_queues[tx_queue_id]);
430
431         dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
432
433         ret = t4_sge_eth_txq_stop(txq);
434         if (ret == 0)
435                 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
436
437         return ret;
438 }
439
440 int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev,
441                              uint16_t queue_idx, uint16_t nb_desc,
442                              unsigned int socket_id,
443                              const struct rte_eth_txconf *tx_conf)
444 {
445         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
446         struct adapter *adapter = pi->adapter;
447         struct sge *s = &adapter->sge;
448         struct sge_eth_txq *txq = &s->ethtxq[pi->first_qset + queue_idx];
449         int err = 0;
450         unsigned int temp_nb_desc;
451         uint64_t unsupported_offloads;
452
453         unsupported_offloads = tx_conf->offloads & ~CXGBE_TX_OFFLOADS;
454         if (unsupported_offloads) {
455                 dev_err(adapter, "Tx offloads 0x%" PRIx64 " are not supported. "
456                         "Supported:0x%" PRIx64 "\n",
457                         unsupported_offloads, (uint64_t)CXGBE_TX_OFFLOADS);
458                 return -ENOTSUP;
459         }
460
461         dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n",
462                   __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc,
463                   socket_id, pi->first_qset);
464
465         /*  Free up the existing queue  */
466         if (eth_dev->data->tx_queues[queue_idx]) {
467                 cxgbe_dev_tx_queue_release(eth_dev->data->tx_queues[queue_idx]);
468                 eth_dev->data->tx_queues[queue_idx] = NULL;
469         }
470
471         eth_dev->data->tx_queues[queue_idx] = (void *)txq;
472
473         /* Sanity Checking
474          *
475          * nb_desc should be > 1023 and <= CXGBE_MAX_RING_DESC_SIZE
476          */
477         temp_nb_desc = nb_desc;
478         if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
479                 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
480                          __func__, CXGBE_MIN_RING_DESC_SIZE,
481                          CXGBE_DEFAULT_TX_DESC_SIZE);
482                 temp_nb_desc = CXGBE_DEFAULT_TX_DESC_SIZE;
483         } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
484                 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
485                         __func__, CXGBE_MIN_RING_DESC_SIZE,
486                         CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_TX_DESC_SIZE);
487                 return -(EINVAL);
488         }
489
490         txq->q.size = temp_nb_desc;
491
492         err = t4_sge_alloc_eth_txq(adapter, txq, eth_dev, queue_idx,
493                                    s->fw_evtq.cntxt_id, socket_id);
494
495         dev_debug(adapter, "%s: txq->q.cntxt_id= %u txq->q.abs_id= %u err = %d\n",
496                   __func__, txq->q.cntxt_id, txq->q.abs_id, err);
497         return err;
498 }
499
500 void cxgbe_dev_tx_queue_release(void *q)
501 {
502         struct sge_eth_txq *txq = (struct sge_eth_txq *)q;
503
504         if (txq) {
505                 struct port_info *pi = (struct port_info *)
506                                        (txq->eth_dev->data->dev_private);
507                 struct adapter *adap = pi->adapter;
508
509                 dev_debug(adapter, "%s: pi->port_id = %d; tx_queue_id = %d\n",
510                           __func__, pi->port_id, txq->q.cntxt_id);
511
512                 t4_sge_eth_txq_release(adap, txq);
513         }
514 }
515
516 int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
517 {
518         int ret;
519         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
520         struct adapter *adap = pi->adapter;
521         struct sge_rspq *q;
522
523         dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
524                   __func__, pi->port_id, rx_queue_id);
525
526         q = eth_dev->data->rx_queues[rx_queue_id];
527
528         ret = t4_sge_eth_rxq_start(adap, q);
529         if (ret == 0)
530                 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
531
532         return ret;
533 }
534
535 int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
536 {
537         int ret;
538         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
539         struct adapter *adap = pi->adapter;
540         struct sge_rspq *q;
541
542         dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
543                   __func__, pi->port_id, rx_queue_id);
544
545         q = eth_dev->data->rx_queues[rx_queue_id];
546         ret = t4_sge_eth_rxq_stop(adap, q);
547         if (ret == 0)
548                 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
549
550         return ret;
551 }
552
553 int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev,
554                              uint16_t queue_idx, uint16_t nb_desc,
555                              unsigned int socket_id,
556                              const struct rte_eth_rxconf *rx_conf,
557                              struct rte_mempool *mp)
558 {
559         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
560         struct adapter *adapter = pi->adapter;
561         struct sge *s = &adapter->sge;
562         struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_qset + queue_idx];
563         int err = 0;
564         int msi_idx = 0;
565         unsigned int temp_nb_desc;
566         struct rte_eth_dev_info dev_info;
567         unsigned int pkt_len = eth_dev->data->dev_conf.rxmode.max_rx_pkt_len;
568         uint64_t unsupported_offloads, configured_offloads;
569
570         configured_offloads = rx_conf->offloads;
571         if (!(configured_offloads & DEV_RX_OFFLOAD_CRC_STRIP)) {
572                 dev_info(adapter, "can't disable hw crc strip\n");
573                 configured_offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
574         }
575
576         unsupported_offloads = configured_offloads & ~CXGBE_RX_OFFLOADS;
577         if (unsupported_offloads) {
578                 dev_err(adapter, "Rx offloads 0x%" PRIx64 " are not supported. "
579                         "Supported:0x%" PRIx64 "\n",
580                         unsupported_offloads, (uint64_t)CXGBE_RX_OFFLOADS);
581                 return -ENOTSUP;
582         }
583
584         dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n",
585                   __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc,
586                   socket_id, mp);
587
588         cxgbe_dev_info_get(eth_dev, &dev_info);
589
590         /* Must accommodate at least ETHER_MIN_MTU */
591         if ((pkt_len < dev_info.min_rx_bufsize) ||
592             (pkt_len > dev_info.max_rx_pktlen)) {
593                 dev_err(adap, "%s: max pkt len must be > %d and <= %d\n",
594                         __func__, dev_info.min_rx_bufsize,
595                         dev_info.max_rx_pktlen);
596                 return -EINVAL;
597         }
598
599         /*  Free up the existing queue  */
600         if (eth_dev->data->rx_queues[queue_idx]) {
601                 cxgbe_dev_rx_queue_release(eth_dev->data->rx_queues[queue_idx]);
602                 eth_dev->data->rx_queues[queue_idx] = NULL;
603         }
604
605         eth_dev->data->rx_queues[queue_idx] = (void *)rxq;
606
607         /* Sanity Checking
608          *
609          * nb_desc should be > 0 and <= CXGBE_MAX_RING_DESC_SIZE
610          */
611         temp_nb_desc = nb_desc;
612         if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
613                 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
614                          __func__, CXGBE_MIN_RING_DESC_SIZE,
615                          CXGBE_DEFAULT_RX_DESC_SIZE);
616                 temp_nb_desc = CXGBE_DEFAULT_RX_DESC_SIZE;
617         } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
618                 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
619                         __func__, CXGBE_MIN_RING_DESC_SIZE,
620                         CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_RX_DESC_SIZE);
621                 return -(EINVAL);
622         }
623
624         rxq->rspq.size = temp_nb_desc;
625         if ((&rxq->fl) != NULL)
626                 rxq->fl.size = temp_nb_desc;
627
628         /* Set to jumbo mode if necessary */
629         if (pkt_len > ETHER_MAX_LEN)
630                 eth_dev->data->dev_conf.rxmode.offloads |=
631                         DEV_RX_OFFLOAD_JUMBO_FRAME;
632         else
633                 eth_dev->data->dev_conf.rxmode.offloads &=
634                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
635
636         err = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx,
637                                &rxq->fl, t4_ethrx_handler,
638                                is_pf4(adapter) ?
639                                t4_get_tp_ch_map(adapter, pi->tx_chan) : 0, mp,
640                                queue_idx, socket_id);
641
642         dev_debug(adapter, "%s: err = %d; port_id = %d; cntxt_id = %u; abs_id = %u\n",
643                   __func__, err, pi->port_id, rxq->rspq.cntxt_id,
644                   rxq->rspq.abs_id);
645         return err;
646 }
647
648 void cxgbe_dev_rx_queue_release(void *q)
649 {
650         struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)q;
651         struct sge_rspq *rq = &rxq->rspq;
652
653         if (rq) {
654                 struct port_info *pi = (struct port_info *)
655                                        (rq->eth_dev->data->dev_private);
656                 struct adapter *adap = pi->adapter;
657
658                 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
659                           __func__, pi->port_id, rxq->rspq.cntxt_id);
660
661                 t4_sge_eth_rxq_release(adap, rxq);
662         }
663 }
664
665 /*
666  * Get port statistics.
667  */
668 static int cxgbe_dev_stats_get(struct rte_eth_dev *eth_dev,
669                                 struct rte_eth_stats *eth_stats)
670 {
671         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
672         struct adapter *adapter = pi->adapter;
673         struct sge *s = &adapter->sge;
674         struct port_stats ps;
675         unsigned int i;
676
677         cxgbe_stats_get(pi, &ps);
678
679         /* RX Stats */
680         eth_stats->imissed  = ps.rx_ovflow0 + ps.rx_ovflow1 +
681                               ps.rx_ovflow2 + ps.rx_ovflow3 +
682                               ps.rx_trunc0 + ps.rx_trunc1 +
683                               ps.rx_trunc2 + ps.rx_trunc3;
684         eth_stats->ierrors  = ps.rx_symbol_err + ps.rx_fcs_err +
685                               ps.rx_jabber + ps.rx_too_long + ps.rx_runt +
686                               ps.rx_len_err;
687
688         /* TX Stats */
689         eth_stats->opackets = ps.tx_frames;
690         eth_stats->obytes   = ps.tx_octets;
691         eth_stats->oerrors  = ps.tx_error_frames;
692
693         for (i = 0; i < pi->n_rx_qsets; i++) {
694                 struct sge_eth_rxq *rxq =
695                         &s->ethrxq[pi->first_qset + i];
696
697                 eth_stats->q_ipackets[i] = rxq->stats.pkts;
698                 eth_stats->q_ibytes[i] = rxq->stats.rx_bytes;
699                 eth_stats->ipackets += eth_stats->q_ipackets[i];
700                 eth_stats->ibytes += eth_stats->q_ibytes[i];
701         }
702
703         for (i = 0; i < pi->n_tx_qsets; i++) {
704                 struct sge_eth_txq *txq =
705                         &s->ethtxq[pi->first_qset + i];
706
707                 eth_stats->q_opackets[i] = txq->stats.pkts;
708                 eth_stats->q_obytes[i] = txq->stats.tx_bytes;
709                 eth_stats->q_errors[i] = txq->stats.mapping_err;
710         }
711         return 0;
712 }
713
714 /*
715  * Reset port statistics.
716  */
717 static void cxgbe_dev_stats_reset(struct rte_eth_dev *eth_dev)
718 {
719         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
720         struct adapter *adapter = pi->adapter;
721         struct sge *s = &adapter->sge;
722         unsigned int i;
723
724         cxgbe_stats_reset(pi);
725         for (i = 0; i < pi->n_rx_qsets; i++) {
726                 struct sge_eth_rxq *rxq =
727                         &s->ethrxq[pi->first_qset + i];
728
729                 rxq->stats.pkts = 0;
730                 rxq->stats.rx_bytes = 0;
731         }
732         for (i = 0; i < pi->n_tx_qsets; i++) {
733                 struct sge_eth_txq *txq =
734                         &s->ethtxq[pi->first_qset + i];
735
736                 txq->stats.pkts = 0;
737                 txq->stats.tx_bytes = 0;
738                 txq->stats.mapping_err = 0;
739         }
740 }
741
742 static int cxgbe_flow_ctrl_get(struct rte_eth_dev *eth_dev,
743                                struct rte_eth_fc_conf *fc_conf)
744 {
745         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
746         struct link_config *lc = &pi->link_cfg;
747         int rx_pause, tx_pause;
748
749         fc_conf->autoneg = lc->fc & PAUSE_AUTONEG;
750         rx_pause = lc->fc & PAUSE_RX;
751         tx_pause = lc->fc & PAUSE_TX;
752
753         if (rx_pause && tx_pause)
754                 fc_conf->mode = RTE_FC_FULL;
755         else if (rx_pause)
756                 fc_conf->mode = RTE_FC_RX_PAUSE;
757         else if (tx_pause)
758                 fc_conf->mode = RTE_FC_TX_PAUSE;
759         else
760                 fc_conf->mode = RTE_FC_NONE;
761         return 0;
762 }
763
764 static int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev,
765                                struct rte_eth_fc_conf *fc_conf)
766 {
767         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
768         struct adapter *adapter = pi->adapter;
769         struct link_config *lc = &pi->link_cfg;
770
771         if (lc->pcaps & FW_PORT_CAP32_ANEG) {
772                 if (fc_conf->autoneg)
773                         lc->requested_fc |= PAUSE_AUTONEG;
774                 else
775                         lc->requested_fc &= ~PAUSE_AUTONEG;
776         }
777
778         if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
779             (fc_conf->mode & RTE_FC_RX_PAUSE))
780                 lc->requested_fc |= PAUSE_RX;
781         else
782                 lc->requested_fc &= ~PAUSE_RX;
783
784         if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
785             (fc_conf->mode & RTE_FC_TX_PAUSE))
786                 lc->requested_fc |= PAUSE_TX;
787         else
788                 lc->requested_fc &= ~PAUSE_TX;
789
790         return t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,
791                              &pi->link_cfg);
792 }
793
794 const uint32_t *
795 cxgbe_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
796 {
797         static const uint32_t ptypes[] = {
798                 RTE_PTYPE_L3_IPV4,
799                 RTE_PTYPE_L3_IPV6,
800                 RTE_PTYPE_UNKNOWN
801         };
802
803         if (eth_dev->rx_pkt_burst == cxgbe_recv_pkts)
804                 return ptypes;
805         return NULL;
806 }
807
808 /* Update RSS hash configuration
809  */
810 static int cxgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
811                                      struct rte_eth_rss_conf *rss_conf)
812 {
813         struct port_info *pi = (struct port_info *)(dev->data->dev_private);
814         struct adapter *adapter = pi->adapter;
815         int err;
816
817         err = cxgbe_write_rss_conf(pi, rss_conf->rss_hf);
818         if (err)
819                 return err;
820
821         pi->rss_hf = rss_conf->rss_hf;
822
823         if (rss_conf->rss_key) {
824                 u32 key[10], mod_key[10];
825                 int i, j;
826
827                 memcpy(key, rss_conf->rss_key, CXGBE_DEFAULT_RSS_KEY_LEN);
828
829                 for (i = 9, j = 0; i >= 0; i--, j++)
830                         mod_key[j] = cpu_to_be32(key[i]);
831
832                 t4_write_rss_key(adapter, mod_key, -1);
833         }
834
835         return 0;
836 }
837
838 /* Get RSS hash configuration
839  */
840 static int cxgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
841                                        struct rte_eth_rss_conf *rss_conf)
842 {
843         struct port_info *pi = (struct port_info *)(dev->data->dev_private);
844         struct adapter *adapter = pi->adapter;
845         u64 rss_hf = 0;
846         u64 flags = 0;
847         int err;
848
849         err = t4_read_config_vi_rss(adapter, adapter->mbox, pi->viid,
850                                     &flags, NULL);
851
852         if (err)
853                 return err;
854
855         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) {
856                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
857                 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
858                         rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
859         }
860
861         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
862                 rss_hf |= ETH_RSS_IPV6;
863
864         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) {
865                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
866                 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
867                         rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
868         }
869
870         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
871                 rss_hf |= ETH_RSS_IPV4;
872
873         rss_conf->rss_hf = rss_hf;
874
875         if (rss_conf->rss_key) {
876                 u32 key[10], mod_key[10];
877                 int i, j;
878
879                 t4_read_rss_key(adapter, key);
880
881                 for (i = 9, j = 0; i >= 0; i--, j++)
882                         mod_key[j] = be32_to_cpu(key[i]);
883
884                 memcpy(rss_conf->rss_key, mod_key, CXGBE_DEFAULT_RSS_KEY_LEN);
885         }
886
887         return 0;
888 }
889
890 static int cxgbe_get_eeprom_length(struct rte_eth_dev *dev)
891 {
892         RTE_SET_USED(dev);
893         return EEPROMSIZE;
894 }
895
896 /**
897  * eeprom_ptov - translate a physical EEPROM address to virtual
898  * @phys_addr: the physical EEPROM address
899  * @fn: the PCI function number
900  * @sz: size of function-specific area
901  *
902  * Translate a physical EEPROM address to virtual.  The first 1K is
903  * accessed through virtual addresses starting at 31K, the rest is
904  * accessed through virtual addresses starting at 0.
905  *
906  * The mapping is as follows:
907  * [0..1K) -> [31K..32K)
908  * [1K..1K+A) -> [31K-A..31K)
909  * [1K+A..ES) -> [0..ES-A-1K)
910  *
911  * where A = @fn * @sz, and ES = EEPROM size.
912  */
913 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
914 {
915         fn *= sz;
916         if (phys_addr < 1024)
917                 return phys_addr + (31 << 10);
918         if (phys_addr < 1024 + fn)
919                 return fn + phys_addr - 1024;
920         if (phys_addr < EEPROMSIZE)
921                 return phys_addr - 1024 - fn;
922         if (phys_addr < EEPROMVSIZE)
923                 return phys_addr - 1024;
924         return -EINVAL;
925 }
926
927 /* The next two routines implement eeprom read/write from physical addresses.
928  */
929 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v)
930 {
931         int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
932
933         if (vaddr >= 0)
934                 vaddr = t4_seeprom_read(adap, vaddr, v);
935         return vaddr < 0 ? vaddr : 0;
936 }
937
938 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v)
939 {
940         int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
941
942         if (vaddr >= 0)
943                 vaddr = t4_seeprom_write(adap, vaddr, v);
944         return vaddr < 0 ? vaddr : 0;
945 }
946
947 #define EEPROM_MAGIC 0x38E2F10C
948
949 static int cxgbe_get_eeprom(struct rte_eth_dev *dev,
950                             struct rte_dev_eeprom_info *e)
951 {
952         struct port_info *pi = (struct port_info *)(dev->data->dev_private);
953         struct adapter *adapter = pi->adapter;
954         u32 i, err = 0;
955         u8 *buf = rte_zmalloc(NULL, EEPROMSIZE, 0);
956
957         if (!buf)
958                 return -ENOMEM;
959
960         e->magic = EEPROM_MAGIC;
961         for (i = e->offset & ~3; !err && i < e->offset + e->length; i += 4)
962                 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]);
963
964         if (!err)
965                 rte_memcpy(e->data, buf + e->offset, e->length);
966         rte_free(buf);
967         return err;
968 }
969
970 static int cxgbe_set_eeprom(struct rte_eth_dev *dev,
971                             struct rte_dev_eeprom_info *eeprom)
972 {
973         struct port_info *pi = (struct port_info *)(dev->data->dev_private);
974         struct adapter *adapter = pi->adapter;
975         u8 *buf;
976         int err = 0;
977         u32 aligned_offset, aligned_len, *p;
978
979         if (eeprom->magic != EEPROM_MAGIC)
980                 return -EINVAL;
981
982         aligned_offset = eeprom->offset & ~3;
983         aligned_len = (eeprom->length + (eeprom->offset & 3) + 3) & ~3;
984
985         if (adapter->pf > 0) {
986                 u32 start = 1024 + adapter->pf * EEPROMPFSIZE;
987
988                 if (aligned_offset < start ||
989                     aligned_offset + aligned_len > start + EEPROMPFSIZE)
990                         return -EPERM;
991         }
992
993         if (aligned_offset != eeprom->offset || aligned_len != eeprom->length) {
994                 /* RMW possibly needed for first or last words.
995                  */
996                 buf = rte_zmalloc(NULL, aligned_len, 0);
997                 if (!buf)
998                         return -ENOMEM;
999                 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf);
1000                 if (!err && aligned_len > 4)
1001                         err = eeprom_rd_phys(adapter,
1002                                              aligned_offset + aligned_len - 4,
1003                                              (u32 *)&buf[aligned_len - 4]);
1004                 if (err)
1005                         goto out;
1006                 rte_memcpy(buf + (eeprom->offset & 3), eeprom->data,
1007                            eeprom->length);
1008         } else {
1009                 buf = eeprom->data;
1010         }
1011
1012         err = t4_seeprom_wp(adapter, false);
1013         if (err)
1014                 goto out;
1015
1016         for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
1017                 err = eeprom_wr_phys(adapter, aligned_offset, *p);
1018                 aligned_offset += 4;
1019         }
1020
1021         if (!err)
1022                 err = t4_seeprom_wp(adapter, true);
1023 out:
1024         if (buf != eeprom->data)
1025                 rte_free(buf);
1026         return err;
1027 }
1028
1029 static int cxgbe_get_regs_len(struct rte_eth_dev *eth_dev)
1030 {
1031         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
1032         struct adapter *adapter = pi->adapter;
1033
1034         return t4_get_regs_len(adapter) / sizeof(uint32_t);
1035 }
1036
1037 static int cxgbe_get_regs(struct rte_eth_dev *eth_dev,
1038                           struct rte_dev_reg_info *regs)
1039 {
1040         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
1041         struct adapter *adapter = pi->adapter;
1042
1043         regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) |
1044                 (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) |
1045                 (1 << 16);
1046
1047         if (regs->data == NULL) {
1048                 regs->length = cxgbe_get_regs_len(eth_dev);
1049                 regs->width = sizeof(uint32_t);
1050
1051                 return 0;
1052         }
1053
1054         t4_get_regs(adapter, regs->data, (regs->length * sizeof(uint32_t)));
1055
1056         return 0;
1057 }
1058
1059 int cxgbe_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
1060 {
1061         struct port_info *pi = (struct port_info *)(dev->data->dev_private);
1062         struct adapter *adapter = pi->adapter;
1063         int ret;
1064
1065         ret = t4_change_mac(adapter, adapter->mbox, pi->viid,
1066                             pi->xact_addr_filt, (u8 *)addr, true, true);
1067         if (ret < 0) {
1068                 dev_err(adapter, "failed to set mac addr; err = %d\n",
1069                         ret);
1070                 return ret;
1071         }
1072         pi->xact_addr_filt = ret;
1073         return 0;
1074 }
1075
1076 static const struct eth_dev_ops cxgbe_eth_dev_ops = {
1077         .dev_start              = cxgbe_dev_start,
1078         .dev_stop               = cxgbe_dev_stop,
1079         .dev_close              = cxgbe_dev_close,
1080         .promiscuous_enable     = cxgbe_dev_promiscuous_enable,
1081         .promiscuous_disable    = cxgbe_dev_promiscuous_disable,
1082         .allmulticast_enable    = cxgbe_dev_allmulticast_enable,
1083         .allmulticast_disable   = cxgbe_dev_allmulticast_disable,
1084         .dev_configure          = cxgbe_dev_configure,
1085         .dev_infos_get          = cxgbe_dev_info_get,
1086         .dev_supported_ptypes_get = cxgbe_dev_supported_ptypes_get,
1087         .link_update            = cxgbe_dev_link_update,
1088         .mtu_set                = cxgbe_dev_mtu_set,
1089         .tx_queue_setup         = cxgbe_dev_tx_queue_setup,
1090         .tx_queue_start         = cxgbe_dev_tx_queue_start,
1091         .tx_queue_stop          = cxgbe_dev_tx_queue_stop,
1092         .tx_queue_release       = cxgbe_dev_tx_queue_release,
1093         .rx_queue_setup         = cxgbe_dev_rx_queue_setup,
1094         .rx_queue_start         = cxgbe_dev_rx_queue_start,
1095         .rx_queue_stop          = cxgbe_dev_rx_queue_stop,
1096         .rx_queue_release       = cxgbe_dev_rx_queue_release,
1097         .stats_get              = cxgbe_dev_stats_get,
1098         .stats_reset            = cxgbe_dev_stats_reset,
1099         .flow_ctrl_get          = cxgbe_flow_ctrl_get,
1100         .flow_ctrl_set          = cxgbe_flow_ctrl_set,
1101         .get_eeprom_length      = cxgbe_get_eeprom_length,
1102         .get_eeprom             = cxgbe_get_eeprom,
1103         .set_eeprom             = cxgbe_set_eeprom,
1104         .get_reg                = cxgbe_get_regs,
1105         .rss_hash_update        = cxgbe_dev_rss_hash_update,
1106         .rss_hash_conf_get      = cxgbe_dev_rss_hash_conf_get,
1107         .mac_addr_set           = cxgbe_mac_addr_set,
1108 };
1109
1110 /*
1111  * Initialize driver
1112  * It returns 0 on success.
1113  */
1114 static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev)
1115 {
1116         struct rte_pci_device *pci_dev;
1117         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
1118         struct adapter *adapter = NULL;
1119         char name[RTE_ETH_NAME_MAX_LEN];
1120         int err = 0;
1121
1122         CXGBE_FUNC_TRACE();
1123
1124         eth_dev->dev_ops = &cxgbe_eth_dev_ops;
1125         eth_dev->rx_pkt_burst = &cxgbe_recv_pkts;
1126         eth_dev->tx_pkt_burst = &cxgbe_xmit_pkts;
1127         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1128
1129         /* for secondary processes, we attach to ethdevs allocated by primary
1130          * and do minimal initialization.
1131          */
1132         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1133                 int i;
1134
1135                 for (i = 1; i < MAX_NPORTS; i++) {
1136                         struct rte_eth_dev *rest_eth_dev;
1137                         char namei[RTE_ETH_NAME_MAX_LEN];
1138
1139                         snprintf(namei, sizeof(namei), "%s_%d",
1140                                  pci_dev->device.name, i);
1141                         rest_eth_dev = rte_eth_dev_attach_secondary(namei);
1142                         if (rest_eth_dev) {
1143                                 rest_eth_dev->device = &pci_dev->device;
1144                                 rest_eth_dev->dev_ops =
1145                                         eth_dev->dev_ops;
1146                                 rest_eth_dev->rx_pkt_burst =
1147                                         eth_dev->rx_pkt_burst;
1148                                 rest_eth_dev->tx_pkt_burst =
1149                                         eth_dev->tx_pkt_burst;
1150                         }
1151                 }
1152                 return 0;
1153         }
1154
1155         snprintf(name, sizeof(name), "cxgbeadapter%d", eth_dev->data->port_id);
1156         adapter = rte_zmalloc(name, sizeof(*adapter), 0);
1157         if (!adapter)
1158                 return -1;
1159
1160         adapter->use_unpacked_mode = 1;
1161         adapter->regs = (void *)pci_dev->mem_resource[0].addr;
1162         if (!adapter->regs) {
1163                 dev_err(adapter, "%s: cannot map device registers\n", __func__);
1164                 err = -ENOMEM;
1165                 goto out_free_adapter;
1166         }
1167         adapter->pdev = pci_dev;
1168         adapter->eth_dev = eth_dev;
1169         pi->adapter = adapter;
1170
1171         err = cxgbe_probe(adapter);
1172         if (err) {
1173                 dev_err(adapter, "%s: cxgbe probe failed with err %d\n",
1174                         __func__, err);
1175                 goto out_free_adapter;
1176         }
1177
1178         return 0;
1179
1180 out_free_adapter:
1181         rte_free(adapter);
1182         return err;
1183 }
1184
1185 static int eth_cxgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1186         struct rte_pci_device *pci_dev)
1187 {
1188         return rte_eth_dev_pci_generic_probe(pci_dev,
1189                 sizeof(struct port_info), eth_cxgbe_dev_init);
1190 }
1191
1192 static int eth_cxgbe_pci_remove(struct rte_pci_device *pci_dev)
1193 {
1194         return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
1195 }
1196
1197 static struct rte_pci_driver rte_cxgbe_pmd = {
1198         .id_table = cxgb4_pci_tbl,
1199         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1200         .probe = eth_cxgbe_pci_probe,
1201         .remove = eth_cxgbe_pci_remove,
1202 };
1203
1204 RTE_PMD_REGISTER_PCI(net_cxgbe, rte_cxgbe_pmd);
1205 RTE_PMD_REGISTER_PCI_TABLE(net_cxgbe, cxgb4_pci_tbl);
1206 RTE_PMD_REGISTER_KMOD_DEP(net_cxgbe, "* igb_uio | uio_pci_generic | vfio-pci");