drivers/net/cxgbe/cxgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Chelsio Communications.
   3  * All rights reserved.
   4  */
   5
   6 #include <sys/queue.h>
   7 #include <stdio.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <string.h>
  11 #include <unistd.h>
  12 #include <stdarg.h>
  13 #include <inttypes.h>
  14 #include <netinet/in.h>
  15
  16 #include <rte_byteorder.h>
  17 #include <rte_common.h>
  18 #include <rte_cycles.h>
  19 #include <rte_interrupts.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_pci.h>
  23 #include <rte_bus_pci.h>
  24 #include <rte_atomic.h>
  25 #include <rte_branch_prediction.h>
  26 #include <rte_memory.h>
  27 #include <rte_tailq.h>
  28 #include <rte_eal.h>
  29 #include <rte_alarm.h>
  30 #include <rte_ether.h>
  31 #include <rte_ethdev_driver.h>
  32 #include <rte_ethdev_pci.h>
  33 #include <rte_malloc.h>
  34 #include <rte_random.h>
  35 #include <rte_dev.h>
  36
  37 #include "cxgbe.h"
  38 #include "cxgbe_pfvf.h"
  39 #include "cxgbe_flow.h"
  40
  41 /*
  42  * Macros needed to support the PCI Device ID Table ...
  43  */
  44 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
  45         static const struct rte_pci_id cxgb4_pci_tbl[] = {
  46 #define CH_PCI_DEVICE_ID_FUNCTION 0x4
  47
  48 #define PCI_VENDOR_ID_CHELSIO 0x1425
  49
  50 #define CH_PCI_ID_TABLE_ENTRY(devid) \
  51                 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CHELSIO, (devid)) }
  52
  53 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
  54                 { .vendor_id = 0, } \
  55         }
  56
  57 /*
  58  *... and the PCI ID Table itself ...
  59  */
  60 #include "base/t4_pci_id_tbl.h"
  61
  62 uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
  63                          uint16_t nb_pkts)
  64 {
  65         struct sge_eth_txq *txq = (struct sge_eth_txq *)tx_queue;
  66         uint16_t pkts_sent, pkts_remain;
  67         uint16_t total_sent = 0;
  68         uint16_t idx = 0;
  69         int ret = 0;
  70
  71         t4_os_lock(&txq->txq_lock);
  72         /* free up desc from already completed tx */
  73         reclaim_completed_tx(&txq->q);
  74         if (unlikely(!nb_pkts))
  75                 goto out_unlock;
  76
  77         rte_prefetch0(rte_pktmbuf_mtod(tx_pkts[0], volatile void *));
  78         while (total_sent < nb_pkts) {
  79                 pkts_remain = nb_pkts - total_sent;
  80
  81                 for (pkts_sent = 0; pkts_sent < pkts_remain; pkts_sent++) {
  82                         idx = total_sent + pkts_sent;
  83                         if ((idx + 1) < nb_pkts)
  84                                 rte_prefetch0(rte_pktmbuf_mtod(tx_pkts[idx + 1],
  85                                                         volatile void *));
  86                         ret = t4_eth_xmit(txq, tx_pkts[idx], nb_pkts);
  87                         if (ret < 0)
  88                                 break;
  89                 }
  90                 if (!pkts_sent)
  91                         break;
  92                 total_sent += pkts_sent;
  93                 /* reclaim as much as possible */
  94                 reclaim_completed_tx(&txq->q);
  95         }
  96
  97 out_unlock:
  98         t4_os_unlock(&txq->txq_lock);
  99         return total_sent;
 100 }
 101
 102 uint16_t cxgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
 103                          uint16_t nb_pkts)
 104 {
 105         struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)rx_queue;
 106         unsigned int work_done;
 107
 108         if (cxgbe_poll(&rxq->rspq, rx_pkts, (unsigned int)nb_pkts, &work_done))
 109                 dev_err(adapter, "error in cxgbe poll\n");
 110
 111         return work_done;
 112 }
 113
 114 int cxgbe_dev_info_get(struct rte_eth_dev *eth_dev,
 115                         struct rte_eth_dev_info *device_info)
 116 {
 117         struct port_info *pi = eth_dev->data->dev_private;
 118         struct adapter *adapter = pi->adapter;
 119         int max_queues = adapter->sge.max_ethqsets / adapter->params.nports;
 120
 121         static const struct rte_eth_desc_lim cxgbe_desc_lim = {
 122                 .nb_max = CXGBE_MAX_RING_DESC_SIZE,
 123                 .nb_min = CXGBE_MIN_RING_DESC_SIZE,
 124                 .nb_align = 1,
 125         };
 126
 127         device_info->min_rx_bufsize = CXGBE_MIN_RX_BUFSIZE;
 128         device_info->max_rx_pktlen = CXGBE_MAX_RX_PKTLEN;
 129         device_info->max_rx_queues = max_queues;
 130         device_info->max_tx_queues = max_queues;
 131         device_info->max_mac_addrs = 1;
 132         /* XXX: For now we support one MAC/port */
 133         device_info->max_vfs = adapter->params.arch.vfcount;
 134         device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */
 135
 136         device_info->rx_queue_offload_capa = 0UL;
 137         device_info->rx_offload_capa = CXGBE_RX_OFFLOADS;
 138
 139         device_info->tx_queue_offload_capa = 0UL;
 140         device_info->tx_offload_capa = CXGBE_TX_OFFLOADS;
 141
 142         device_info->reta_size = pi->rss_size;
 143         device_info->hash_key_size = CXGBE_DEFAULT_RSS_KEY_LEN;
 144         device_info->flow_type_rss_offloads = CXGBE_RSS_HF_ALL;
 145
 146         device_info->rx_desc_lim = cxgbe_desc_lim;
 147         device_info->tx_desc_lim = cxgbe_desc_lim;
 148         cxgbe_get_speed_caps(pi, &device_info->speed_capa);
 149
 150         return 0;
 151 }
 152
 153 int cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
 154 {
 155         struct port_info *pi = eth_dev->data->dev_private;
 156         struct adapter *adapter = pi->adapter;
 157
 158         return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 159                              1, -1, 1, -1, false);
 160 }
 161
 162 int cxgbe_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
 163 {
 164         struct port_info *pi = eth_dev->data->dev_private;
 165         struct adapter *adapter = pi->adapter;
 166
 167         return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 168                              0, -1, 1, -1, false);
 169 }
 170
 171 int cxgbe_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
 172 {
 173         struct port_info *pi = eth_dev->data->dev_private;
 174         struct adapter *adapter = pi->adapter;
 175
 176         /* TODO: address filters ?? */
 177
 178         return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 179                              -1, 1, 1, -1, false);
 180 }
 181
 182 int cxgbe_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
 183 {
 184         struct port_info *pi = eth_dev->data->dev_private;
 185         struct adapter *adapter = pi->adapter;
 186
 187         /* TODO: address filters ?? */
 188
 189         return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 190                              -1, 0, 1, -1, false);
 191 }
 192
 193 int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev,
 194                           int wait_to_complete)
 195 {
 196         struct port_info *pi = eth_dev->data->dev_private;
 197         struct adapter *adapter = pi->adapter;
 198         struct sge *s = &adapter->sge;
 199         struct rte_eth_link new_link = { 0 };
 200         unsigned int i, work_done, budget = 32;
 201         u8 old_link = pi->link_cfg.link_ok;
 202
 203         for (i = 0; i < CXGBE_LINK_STATUS_POLL_CNT; i++) {
 204                 if (!s->fw_evtq.desc)
 205                         break;
 206
 207                 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
 208
 209                 /* Exit if link status changed or always forced up */
 210                 if (pi->link_cfg.link_ok != old_link ||
 211                     cxgbe_force_linkup(adapter))
 212                         break;
 213
 214                 if (!wait_to_complete)
 215                         break;
 216
 217                 rte_delay_ms(CXGBE_LINK_STATUS_POLL_MS);
 218         }
 219
 220         new_link.link_status = cxgbe_force_linkup(adapter) ?
 221                                ETH_LINK_UP : pi->link_cfg.link_ok;
 222         new_link.link_autoneg = pi->link_cfg.autoneg;
 223         new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
 224         new_link.link_speed = pi->link_cfg.speed;
 225
 226         return rte_eth_linkstatus_set(eth_dev, &new_link);
 227 }
 228
 229 /**
 230  * Set device link up.
 231  */
 232 int cxgbe_dev_set_link_up(struct rte_eth_dev *dev)
 233 {
 234         struct port_info *pi = dev->data->dev_private;
 235         struct adapter *adapter = pi->adapter;
 236         unsigned int work_done, budget = 32;
 237         struct sge *s = &adapter->sge;
 238         int ret;
 239
 240         if (!s->fw_evtq.desc)
 241                 return -ENOMEM;
 242
 243         /* Flush all link events */
 244         cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
 245
 246         /* If link already up, nothing to do */
 247         if (pi->link_cfg.link_ok)
 248                 return 0;
 249
 250         ret = cxgbe_set_link_status(pi, true);
 251         if (ret)
 252                 return ret;
 253
 254         cxgbe_dev_link_update(dev, 1);
 255         return 0;
 256 }
 257
 258 /**
 259  * Set device link down.
 260  */
 261 int cxgbe_dev_set_link_down(struct rte_eth_dev *dev)
 262 {
 263         struct port_info *pi = dev->data->dev_private;
 264         struct adapter *adapter = pi->adapter;
 265         unsigned int work_done, budget = 32;
 266         struct sge *s = &adapter->sge;
 267         int ret;
 268
 269         if (!s->fw_evtq.desc)
 270                 return -ENOMEM;
 271
 272         /* Flush all link events */
 273         cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
 274
 275         /* If link already down, nothing to do */
 276         if (!pi->link_cfg.link_ok)
 277                 return 0;
 278
 279         ret = cxgbe_set_link_status(pi, false);
 280         if (ret)
 281                 return ret;
 282
 283         cxgbe_dev_link_update(dev, 0);
 284         return 0;
 285 }
 286
 287 int cxgbe_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
 288 {
 289         struct port_info *pi = eth_dev->data->dev_private;
 290         struct adapter *adapter = pi->adapter;
 291         struct rte_eth_dev_info dev_info;
 292         int err;
 293         uint16_t new_mtu = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN;
 294
 295         err = cxgbe_dev_info_get(eth_dev, &dev_info);
 296         if (err != 0)
 297                 return err;
 298
 299         /* Must accommodate at least RTE_ETHER_MIN_MTU */
 300         if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > dev_info.max_rx_pktlen)
 301                 return -EINVAL;
 302
 303         /* set to jumbo mode if needed */
 304         if (new_mtu > RTE_ETHER_MAX_LEN)
 305                 eth_dev->data->dev_conf.rxmode.offloads |=
 306                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 307         else
 308                 eth_dev->data->dev_conf.rxmode.offloads &=
 309                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 310
 311         err = t4_set_rxmode(adapter, adapter->mbox, pi->viid, new_mtu, -1, -1,
 312                             -1, -1, true);
 313         if (!err)
 314                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_mtu;
 315
 316         return err;
 317 }
 318
 319 /*
 320  * Stop device.
 321  */
 322 void cxgbe_dev_close(struct rte_eth_dev *eth_dev)
 323 {
 324         struct port_info *pi = eth_dev->data->dev_private;
 325         struct adapter *adapter = pi->adapter;
 326
 327         CXGBE_FUNC_TRACE();
 328
 329         if (!(adapter->flags & FULL_INIT_DONE))
 330                 return;
 331
 332         cxgbe_down(pi);
 333
 334         /*
 335          *  We clear queues only if both tx and rx path of the port
 336          *  have been disabled
 337          */
 338         t4_sge_eth_clear_queues(pi);
 339 }
 340
 341 /* Start the device.
 342  * It returns 0 on success.
 343  */
 344 int cxgbe_dev_start(struct rte_eth_dev *eth_dev)
 345 {
 346         struct port_info *pi = eth_dev->data->dev_private;
 347         struct rte_eth_rxmode *rx_conf = &eth_dev->data->dev_conf.rxmode;
 348         struct adapter *adapter = pi->adapter;
 349         int err = 0, i;
 350
 351         CXGBE_FUNC_TRACE();
 352
 353         /*
 354          * If we don't have a connection to the firmware there's nothing we
 355          * can do.
 356          */
 357         if (!(adapter->flags & FW_OK)) {
 358                 err = -ENXIO;
 359                 goto out;
 360         }
 361
 362         if (!(adapter->flags & FULL_INIT_DONE)) {
 363                 err = cxgbe_up(adapter);
 364                 if (err < 0)
 365                         goto out;
 366         }
 367
 368         if (rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER)
 369                 eth_dev->data->scattered_rx = 1;
 370         else
 371                 eth_dev->data->scattered_rx = 0;
 372
 373         cxgbe_enable_rx_queues(pi);
 374
 375         err = cxgbe_setup_rss(pi);
 376         if (err)
 377                 goto out;
 378
 379         for (i = 0; i < pi->n_tx_qsets; i++) {
 380                 err = cxgbe_dev_tx_queue_start(eth_dev, i);
 381                 if (err)
 382                         goto out;
 383         }
 384
 385         for (i = 0; i < pi->n_rx_qsets; i++) {
 386                 err = cxgbe_dev_rx_queue_start(eth_dev, i);
 387                 if (err)
 388                         goto out;
 389         }
 390
 391         err = cxgbe_link_start(pi);
 392         if (err)
 393                 goto out;
 394
 395 out:
 396         return err;
 397 }
 398
 399 /*
 400  * Stop device: disable rx and tx functions to allow for reconfiguring.
 401  */
 402 void cxgbe_dev_stop(struct rte_eth_dev *eth_dev)
 403 {
 404         struct port_info *pi = eth_dev->data->dev_private;
 405         struct adapter *adapter = pi->adapter;
 406
 407         CXGBE_FUNC_TRACE();
 408
 409         if (!(adapter->flags & FULL_INIT_DONE))
 410                 return;
 411
 412         cxgbe_down(pi);
 413
 414         /*
 415          *  We clear queues only if both tx and rx path of the port
 416          *  have been disabled
 417          */
 418         t4_sge_eth_clear_queues(pi);
 419         eth_dev->data->scattered_rx = 0;
 420 }
 421
 422 int cxgbe_dev_configure(struct rte_eth_dev *eth_dev)
 423 {
 424         struct port_info *pi = eth_dev->data->dev_private;
 425         struct adapter *adapter = pi->adapter;
 426         int err;
 427
 428         CXGBE_FUNC_TRACE();
 429
 430         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
 431                 eth_dev->data->dev_conf.rxmode.offloads |=
 432                         DEV_RX_OFFLOAD_RSS_HASH;
 433
 434         if (!(adapter->flags & FW_QUEUE_BOUND)) {
 435                 err = cxgbe_setup_sge_fwevtq(adapter);
 436                 if (err)
 437                         return err;
 438                 adapter->flags |= FW_QUEUE_BOUND;
 439                 if (is_pf4(adapter)) {
 440                         err = cxgbe_setup_sge_ctrl_txq(adapter);
 441                         if (err)
 442                                 return err;
 443                 }
 444         }
 445
 446         err = cxgbe_cfg_queue_count(eth_dev);
 447         if (err)
 448                 return err;
 449
 450         return 0;
 451 }
 452
 453 int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
 454 {
 455         int ret;
 456         struct sge_eth_txq *txq = (struct sge_eth_txq *)
 457                                   (eth_dev->data->tx_queues[tx_queue_id]);
 458
 459         dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
 460
 461         ret = t4_sge_eth_txq_start(txq);
 462         if (ret == 0)
 463                 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 464
 465         return ret;
 466 }
 467
 468 int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
 469 {
 470         int ret;
 471         struct sge_eth_txq *txq = (struct sge_eth_txq *)
 472                                   (eth_dev->data->tx_queues[tx_queue_id]);
 473
 474         dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
 475
 476         ret = t4_sge_eth_txq_stop(txq);
 477         if (ret == 0)
 478                 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 479
 480         return ret;
 481 }
 482
 483 int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev,
 484                              uint16_t queue_idx, uint16_t nb_desc,
 485                              unsigned int socket_id,
 486                              const struct rte_eth_txconf *tx_conf __rte_unused)
 487 {
 488         struct port_info *pi = eth_dev->data->dev_private;
 489         struct adapter *adapter = pi->adapter;
 490         struct sge *s = &adapter->sge;
 491         struct sge_eth_txq *txq = &s->ethtxq[pi->first_qset + queue_idx];
 492         int err = 0;
 493         unsigned int temp_nb_desc;
 494
 495         dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n",
 496                   __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc,
 497                   socket_id, pi->first_qset);
 498
 499         /*  Free up the existing queue  */
 500         if (eth_dev->data->tx_queues[queue_idx]) {
 501                 cxgbe_dev_tx_queue_release(eth_dev->data->tx_queues[queue_idx]);
 502                 eth_dev->data->tx_queues[queue_idx] = NULL;
 503         }
 504
 505         eth_dev->data->tx_queues[queue_idx] = (void *)txq;
 506
 507         /* Sanity Checking
 508          *
 509          * nb_desc should be > 1023 and <= CXGBE_MAX_RING_DESC_SIZE
 510          */
 511         temp_nb_desc = nb_desc;
 512         if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
 513                 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
 514                          __func__, CXGBE_MIN_RING_DESC_SIZE,
 515                          CXGBE_DEFAULT_TX_DESC_SIZE);
 516                 temp_nb_desc = CXGBE_DEFAULT_TX_DESC_SIZE;
 517         } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
 518                 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
 519                         __func__, CXGBE_MIN_RING_DESC_SIZE,
 520                         CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_TX_DESC_SIZE);
 521                 return -(EINVAL);
 522         }
 523
 524         txq->q.size = temp_nb_desc;
 525
 526         err = t4_sge_alloc_eth_txq(adapter, txq, eth_dev, queue_idx,
 527                                    s->fw_evtq.cntxt_id, socket_id);
 528
 529         dev_debug(adapter, "%s: txq->q.cntxt_id= %u txq->q.abs_id= %u err = %d\n",
 530                   __func__, txq->q.cntxt_id, txq->q.abs_id, err);
 531         return err;
 532 }
 533
 534 void cxgbe_dev_tx_queue_release(void *q)
 535 {
 536         struct sge_eth_txq *txq = (struct sge_eth_txq *)q;
 537
 538         if (txq) {
 539                 struct port_info *pi = (struct port_info *)
 540                                        (txq->eth_dev->data->dev_private);
 541                 struct adapter *adap = pi->adapter;
 542
 543                 dev_debug(adapter, "%s: pi->port_id = %d; tx_queue_id = %d\n",
 544                           __func__, pi->port_id, txq->q.cntxt_id);
 545
 546                 t4_sge_eth_txq_release(adap, txq);
 547         }
 548 }
 549
 550 int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
 551 {
 552         int ret;
 553         struct port_info *pi = eth_dev->data->dev_private;
 554         struct adapter *adap = pi->adapter;
 555         struct sge_rspq *q;
 556
 557         dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
 558                   __func__, pi->port_id, rx_queue_id);
 559
 560         q = eth_dev->data->rx_queues[rx_queue_id];
 561
 562         ret = t4_sge_eth_rxq_start(adap, q);
 563         if (ret == 0)
 564                 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 565
 566         return ret;
 567 }
 568
 569 int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
 570 {
 571         int ret;
 572         struct port_info *pi = eth_dev->data->dev_private;
 573         struct adapter *adap = pi->adapter;
 574         struct sge_rspq *q;
 575
 576         dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
 577                   __func__, pi->port_id, rx_queue_id);
 578
 579         q = eth_dev->data->rx_queues[rx_queue_id];
 580         ret = t4_sge_eth_rxq_stop(adap, q);
 581         if (ret == 0)
 582                 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 583
 584         return ret;
 585 }
 586
 587 int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev,
 588                              uint16_t queue_idx, uint16_t nb_desc,
 589                              unsigned int socket_id,
 590                              const struct rte_eth_rxconf *rx_conf __rte_unused,
 591                              struct rte_mempool *mp)
 592 {
 593         struct port_info *pi = eth_dev->data->dev_private;
 594         struct adapter *adapter = pi->adapter;
 595         struct sge *s = &adapter->sge;
 596         struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_qset + queue_idx];
 597         int err = 0;
 598         int msi_idx = 0;
 599         unsigned int temp_nb_desc;
 600         struct rte_eth_dev_info dev_info;
 601         unsigned int pkt_len = eth_dev->data->dev_conf.rxmode.max_rx_pkt_len;
 602
 603         dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n",
 604                   __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc,
 605                   socket_id, mp);
 606
 607         err = cxgbe_dev_info_get(eth_dev, &dev_info);
 608         if (err != 0) {
 609                 dev_err(adap, "%s: error during getting ethernet device info",
 610                         __func__);
 611                 return err;
 612         }
 613
 614         /* Must accommodate at least RTE_ETHER_MIN_MTU */
 615         if ((pkt_len < dev_info.min_rx_bufsize) ||
 616             (pkt_len > dev_info.max_rx_pktlen)) {
 617                 dev_err(adap, "%s: max pkt len must be > %d and <= %d\n",
 618                         __func__, dev_info.min_rx_bufsize,
 619                         dev_info.max_rx_pktlen);
 620                 return -EINVAL;
 621         }
 622
 623         /*  Free up the existing queue  */
 624         if (eth_dev->data->rx_queues[queue_idx]) {
 625                 cxgbe_dev_rx_queue_release(eth_dev->data->rx_queues[queue_idx]);
 626                 eth_dev->data->rx_queues[queue_idx] = NULL;
 627         }
 628
 629         eth_dev->data->rx_queues[queue_idx] = (void *)rxq;
 630
 631         /* Sanity Checking
 632          *
 633          * nb_desc should be > 0 and <= CXGBE_MAX_RING_DESC_SIZE
 634          */
 635         temp_nb_desc = nb_desc;
 636         if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
 637                 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
 638                          __func__, CXGBE_MIN_RING_DESC_SIZE,
 639                          CXGBE_DEFAULT_RX_DESC_SIZE);
 640                 temp_nb_desc = CXGBE_DEFAULT_RX_DESC_SIZE;
 641         } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
 642                 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
 643                         __func__, CXGBE_MIN_RING_DESC_SIZE,
 644                         CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_RX_DESC_SIZE);
 645                 return -(EINVAL);
 646         }
 647
 648         rxq->rspq.size = temp_nb_desc;
 649         if ((&rxq->fl) != NULL)
 650                 rxq->fl.size = temp_nb_desc;
 651
 652         /* Set to jumbo mode if necessary */
 653         if (pkt_len > RTE_ETHER_MAX_LEN)
 654                 eth_dev->data->dev_conf.rxmode.offloads |=
 655                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 656         else
 657                 eth_dev->data->dev_conf.rxmode.offloads &=
 658                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 659
 660         err = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx,
 661                                &rxq->fl, NULL,
 662                                is_pf4(adapter) ?
 663                                t4_get_tp_ch_map(adapter, pi->tx_chan) : 0, mp,
 664                                queue_idx, socket_id);
 665
 666         dev_debug(adapter, "%s: err = %d; port_id = %d; cntxt_id = %u; abs_id = %u\n",
 667                   __func__, err, pi->port_id, rxq->rspq.cntxt_id,
 668                   rxq->rspq.abs_id);
 669         return err;
 670 }
 671
 672 void cxgbe_dev_rx_queue_release(void *q)
 673 {
 674         struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)q;
 675         struct sge_rspq *rq = &rxq->rspq;
 676
 677         if (rq) {
 678                 struct port_info *pi = (struct port_info *)
 679                                        (rq->eth_dev->data->dev_private);
 680                 struct adapter *adap = pi->adapter;
 681
 682                 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
 683                           __func__, pi->port_id, rxq->rspq.cntxt_id);
 684
 685                 t4_sge_eth_rxq_release(adap, rxq);
 686         }
 687 }
 688
 689 /*
 690  * Get port statistics.
 691  */
 692 static int cxgbe_dev_stats_get(struct rte_eth_dev *eth_dev,
 693                                 struct rte_eth_stats *eth_stats)
 694 {
 695         struct port_info *pi = eth_dev->data->dev_private;
 696         struct adapter *adapter = pi->adapter;
 697         struct sge *s = &adapter->sge;
 698         struct port_stats ps;
 699         unsigned int i;
 700
 701         cxgbe_stats_get(pi, &ps);
 702
 703         /* RX Stats */
 704         eth_stats->imissed  = ps.rx_ovflow0 + ps.rx_ovflow1 +
 705                               ps.rx_ovflow2 + ps.rx_ovflow3 +
 706                               ps.rx_trunc0 + ps.rx_trunc1 +
 707                               ps.rx_trunc2 + ps.rx_trunc3;
 708         eth_stats->ierrors  = ps.rx_symbol_err + ps.rx_fcs_err +
 709                               ps.rx_jabber + ps.rx_too_long + ps.rx_runt +
 710                               ps.rx_len_err;
 711
 712         /* TX Stats */
 713         eth_stats->opackets = ps.tx_frames;
 714         eth_stats->obytes   = ps.tx_octets;
 715         eth_stats->oerrors  = ps.tx_error_frames;
 716
 717         for (i = 0; i < pi->n_rx_qsets; i++) {
 718                 struct sge_eth_rxq *rxq =
 719                         &s->ethrxq[pi->first_qset + i];
 720
 721                 eth_stats->q_ipackets[i] = rxq->stats.pkts;
 722                 eth_stats->q_ibytes[i] = rxq->stats.rx_bytes;
 723                 eth_stats->ipackets += eth_stats->q_ipackets[i];
 724                 eth_stats->ibytes += eth_stats->q_ibytes[i];
 725         }
 726
 727         for (i = 0; i < pi->n_tx_qsets; i++) {
 728                 struct sge_eth_txq *txq =
 729                         &s->ethtxq[pi->first_qset + i];
 730
 731                 eth_stats->q_opackets[i] = txq->stats.pkts;
 732                 eth_stats->q_obytes[i] = txq->stats.tx_bytes;
 733         }
 734         return 0;
 735 }
 736
 737 /*
 738  * Reset port statistics.
 739  */
 740 static int cxgbe_dev_stats_reset(struct rte_eth_dev *eth_dev)
 741 {
 742         struct port_info *pi = eth_dev->data->dev_private;
 743         struct adapter *adapter = pi->adapter;
 744         struct sge *s = &adapter->sge;
 745         unsigned int i;
 746
 747         cxgbe_stats_reset(pi);
 748         for (i = 0; i < pi->n_rx_qsets; i++) {
 749                 struct sge_eth_rxq *rxq =
 750                         &s->ethrxq[pi->first_qset + i];
 751
 752                 rxq->stats.pkts = 0;
 753                 rxq->stats.rx_bytes = 0;
 754         }
 755         for (i = 0; i < pi->n_tx_qsets; i++) {
 756                 struct sge_eth_txq *txq =
 757                         &s->ethtxq[pi->first_qset + i];
 758
 759                 txq->stats.pkts = 0;
 760                 txq->stats.tx_bytes = 0;
 761                 txq->stats.mapping_err = 0;
 762         }
 763
 764         return 0;
 765 }
 766
 767 static int cxgbe_flow_ctrl_get(struct rte_eth_dev *eth_dev,
 768                                struct rte_eth_fc_conf *fc_conf)
 769 {
 770         struct port_info *pi = eth_dev->data->dev_private;
 771         struct link_config *lc = &pi->link_cfg;
 772         int rx_pause, tx_pause;
 773
 774         fc_conf->autoneg = lc->fc & PAUSE_AUTONEG;
 775         rx_pause = lc->fc & PAUSE_RX;
 776         tx_pause = lc->fc & PAUSE_TX;
 777
 778         if (rx_pause && tx_pause)
 779                 fc_conf->mode = RTE_FC_FULL;
 780         else if (rx_pause)
 781                 fc_conf->mode = RTE_FC_RX_PAUSE;
 782         else if (tx_pause)
 783                 fc_conf->mode = RTE_FC_TX_PAUSE;
 784         else
 785                 fc_conf->mode = RTE_FC_NONE;
 786         return 0;
 787 }
 788
 789 static int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev,
 790                                struct rte_eth_fc_conf *fc_conf)
 791 {
 792         struct port_info *pi = eth_dev->data->dev_private;
 793         struct adapter *adapter = pi->adapter;
 794         struct link_config *lc = &pi->link_cfg;
 795
 796         if (lc->pcaps & FW_PORT_CAP32_ANEG) {
 797                 if (fc_conf->autoneg)
 798                         lc->requested_fc |= PAUSE_AUTONEG;
 799                 else
 800                         lc->requested_fc &= ~PAUSE_AUTONEG;
 801         }
 802
 803         if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
 804             (fc_conf->mode & RTE_FC_RX_PAUSE))
 805                 lc->requested_fc |= PAUSE_RX;
 806         else
 807                 lc->requested_fc &= ~PAUSE_RX;
 808
 809         if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
 810             (fc_conf->mode & RTE_FC_TX_PAUSE))
 811                 lc->requested_fc |= PAUSE_TX;
 812         else
 813                 lc->requested_fc &= ~PAUSE_TX;
 814
 815         return t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,
 816                              &pi->link_cfg);
 817 }
 818
 819 const uint32_t *
 820 cxgbe_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
 821 {
 822         static const uint32_t ptypes[] = {
 823                 RTE_PTYPE_L3_IPV4,
 824                 RTE_PTYPE_L3_IPV6,
 825                 RTE_PTYPE_UNKNOWN
 826         };
 827
 828         if (eth_dev->rx_pkt_burst == cxgbe_recv_pkts)
 829                 return ptypes;
 830         return NULL;
 831 }
 832
 833 /* Update RSS hash configuration
 834  */
 835 static int cxgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
 836                                      struct rte_eth_rss_conf *rss_conf)
 837 {
 838         struct port_info *pi = dev->data->dev_private;
 839         struct adapter *adapter = pi->adapter;
 840         int err;
 841
 842         err = cxgbe_write_rss_conf(pi, rss_conf->rss_hf);
 843         if (err)
 844                 return err;
 845
 846         pi->rss_hf = rss_conf->rss_hf;
 847
 848         if (rss_conf->rss_key) {
 849                 u32 key[10], mod_key[10];
 850                 int i, j;
 851
 852                 memcpy(key, rss_conf->rss_key, CXGBE_DEFAULT_RSS_KEY_LEN);
 853
 854                 for (i = 9, j = 0; i >= 0; i--, j++)
 855                         mod_key[j] = cpu_to_be32(key[i]);
 856
 857                 t4_write_rss_key(adapter, mod_key, -1);
 858         }
 859
 860         return 0;
 861 }
 862
 863 /* Get RSS hash configuration
 864  */
 865 static int cxgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 866                                        struct rte_eth_rss_conf *rss_conf)
 867 {
 868         struct port_info *pi = dev->data->dev_private;
 869         struct adapter *adapter = pi->adapter;
 870         u64 rss_hf = 0;
 871         u64 flags = 0;
 872         int err;
 873
 874         err = t4_read_config_vi_rss(adapter, adapter->mbox, pi->viid,
 875                                     &flags, NULL);
 876
 877         if (err)
 878                 return err;
 879
 880         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) {
 881                 rss_hf |= CXGBE_RSS_HF_TCP_IPV6_MASK;
 882                 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
 883                         rss_hf |= CXGBE_RSS_HF_UDP_IPV6_MASK;
 884         }
 885
 886         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
 887                 rss_hf |= CXGBE_RSS_HF_IPV6_MASK;
 888
 889         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) {
 890                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
 891                 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
 892                         rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
 893         }
 894
 895         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
 896                 rss_hf |= CXGBE_RSS_HF_IPV4_MASK;
 897
 898         rss_conf->rss_hf = rss_hf;
 899
 900         if (rss_conf->rss_key) {
 901                 u32 key[10], mod_key[10];
 902                 int i, j;
 903
 904                 t4_read_rss_key(adapter, key);
 905
 906                 for (i = 9, j = 0; i >= 0; i--, j++)
 907                         mod_key[j] = be32_to_cpu(key[i]);
 908
 909                 memcpy(rss_conf->rss_key, mod_key, CXGBE_DEFAULT_RSS_KEY_LEN);
 910         }
 911
 912         return 0;
 913 }
 914
 915 static int cxgbe_get_eeprom_length(struct rte_eth_dev *dev)
 916 {
 917         RTE_SET_USED(dev);
 918         return EEPROMSIZE;
 919 }
 920
 921 /**
 922  * eeprom_ptov - translate a physical EEPROM address to virtual
 923  * @phys_addr: the physical EEPROM address
 924  * @fn: the PCI function number
 925  * @sz: size of function-specific area
 926  *
 927  * Translate a physical EEPROM address to virtual.  The first 1K is
 928  * accessed through virtual addresses starting at 31K, the rest is
 929  * accessed through virtual addresses starting at 0.
 930  *
 931  * The mapping is as follows:
 932  * [0..1K) -> [31K..32K)
 933  * [1K..1K+A) -> [31K-A..31K)
 934  * [1K+A..ES) -> [0..ES-A-1K)
 935  *
 936  * where A = @fn * @sz, and ES = EEPROM size.
 937  */
 938 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
 939 {
 940         fn *= sz;
 941         if (phys_addr < 1024)
 942                 return phys_addr + (31 << 10);
 943         if (phys_addr < 1024 + fn)
 944                 return fn + phys_addr - 1024;
 945         if (phys_addr < EEPROMSIZE)
 946                 return phys_addr - 1024 - fn;
 947         if (phys_addr < EEPROMVSIZE)
 948                 return phys_addr - 1024;
 949         return -EINVAL;
 950 }
 951
 952 /* The next two routines implement eeprom read/write from physical addresses.
 953  */
 954 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v)
 955 {
 956         int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
 957
 958         if (vaddr >= 0)
 959                 vaddr = t4_seeprom_read(adap, vaddr, v);
 960         return vaddr < 0 ? vaddr : 0;
 961 }
 962
 963 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v)
 964 {
 965         int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
 966
 967         if (vaddr >= 0)
 968                 vaddr = t4_seeprom_write(adap, vaddr, v);
 969         return vaddr < 0 ? vaddr : 0;
 970 }
 971
 972 #define EEPROM_MAGIC 0x38E2F10C
 973
 974 static int cxgbe_get_eeprom(struct rte_eth_dev *dev,
 975                             struct rte_dev_eeprom_info *e)
 976 {
 977         struct port_info *pi = dev->data->dev_private;
 978         struct adapter *adapter = pi->adapter;
 979         u32 i, err = 0;
 980         u8 *buf = rte_zmalloc(NULL, EEPROMSIZE, 0);
 981
 982         if (!buf)
 983                 return -ENOMEM;
 984
 985         e->magic = EEPROM_MAGIC;
 986         for (i = e->offset & ~3; !err && i < e->offset + e->length; i += 4)
 987                 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]);
 988
 989         if (!err)
 990                 rte_memcpy(e->data, buf + e->offset, e->length);
 991         rte_free(buf);
 992         return err;
 993 }
 994
 995 static int cxgbe_set_eeprom(struct rte_eth_dev *dev,
 996                             struct rte_dev_eeprom_info *eeprom)
 997 {
 998         struct port_info *pi = dev->data->dev_private;
 999         struct adapter *adapter = pi->adapter;
1000         u8 *buf;
1001         int err = 0;
1002         u32 aligned_offset, aligned_len, *p;
1003
1004         if (eeprom->magic != EEPROM_MAGIC)
1005                 return -EINVAL;
1006
1007         aligned_offset = eeprom->offset & ~3;
1008         aligned_len = (eeprom->length + (eeprom->offset & 3) + 3) & ~3;
1009
1010         if (adapter->pf > 0) {
1011                 u32 start = 1024 + adapter->pf * EEPROMPFSIZE;
1012
1013                 if (aligned_offset < start ||
1014                     aligned_offset + aligned_len > start + EEPROMPFSIZE)
1015                         return -EPERM;
1016         }
1017
1018         if (aligned_offset != eeprom->offset || aligned_len != eeprom->length) {
1019                 /* RMW possibly needed for first or last words.
1020                  */
1021                 buf = rte_zmalloc(NULL, aligned_len, 0);
1022                 if (!buf)
1023                         return -ENOMEM;
1024                 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf);
1025                 if (!err && aligned_len > 4)
1026                         err = eeprom_rd_phys(adapter,
1027                                              aligned_offset + aligned_len - 4,
1028                                              (u32 *)&buf[aligned_len - 4]);
1029                 if (err)
1030                         goto out;
1031                 rte_memcpy(buf + (eeprom->offset & 3), eeprom->data,
1032                            eeprom->length);
1033         } else {
1034                 buf = eeprom->data;
1035         }
1036
1037         err = t4_seeprom_wp(adapter, false);
1038         if (err)
1039                 goto out;
1040
1041         for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
1042                 err = eeprom_wr_phys(adapter, aligned_offset, *p);
1043                 aligned_offset += 4;
1044         }
1045
1046         if (!err)
1047                 err = t4_seeprom_wp(adapter, true);
1048 out:
1049         if (buf != eeprom->data)
1050                 rte_free(buf);
1051         return err;
1052 }
1053
1054 static int cxgbe_get_regs_len(struct rte_eth_dev *eth_dev)
1055 {
1056         struct port_info *pi = eth_dev->data->dev_private;
1057         struct adapter *adapter = pi->adapter;
1058
1059         return t4_get_regs_len(adapter) / sizeof(uint32_t);
1060 }
1061
1062 static int cxgbe_get_regs(struct rte_eth_dev *eth_dev,
1063                           struct rte_dev_reg_info *regs)
1064 {
1065         struct port_info *pi = eth_dev->data->dev_private;
1066         struct adapter *adapter = pi->adapter;
1067
1068         regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) |
1069                 (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) |
1070                 (1 << 16);
1071
1072         if (regs->data == NULL) {
1073                 regs->length = cxgbe_get_regs_len(eth_dev);
1074                 regs->width = sizeof(uint32_t);
1075
1076                 return 0;
1077         }
1078
1079         t4_get_regs(adapter, regs->data, (regs->length * sizeof(uint32_t)));
1080
1081         return 0;
1082 }
1083
1084 int cxgbe_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
1085 {
1086         struct port_info *pi = dev->data->dev_private;
1087         int ret;
1088
1089         ret = cxgbe_mpstcam_modify(pi, (int)pi->xact_addr_filt, (u8 *)addr);
1090         if (ret < 0) {
1091                 dev_err(adapter, "failed to set mac addr; err = %d\n",
1092                         ret);
1093                 return ret;
1094         }
1095         pi->xact_addr_filt = ret;
1096         return 0;
1097 }
1098
1099 static const struct eth_dev_ops cxgbe_eth_dev_ops = {
1100         .dev_start              = cxgbe_dev_start,
1101         .dev_stop               = cxgbe_dev_stop,
1102         .dev_close              = cxgbe_dev_close,
1103         .promiscuous_enable     = cxgbe_dev_promiscuous_enable,
1104         .promiscuous_disable    = cxgbe_dev_promiscuous_disable,
1105         .allmulticast_enable    = cxgbe_dev_allmulticast_enable,
1106         .allmulticast_disable   = cxgbe_dev_allmulticast_disable,
1107         .dev_configure          = cxgbe_dev_configure,
1108         .dev_infos_get          = cxgbe_dev_info_get,
1109         .dev_supported_ptypes_get = cxgbe_dev_supported_ptypes_get,
1110         .link_update            = cxgbe_dev_link_update,
1111         .dev_set_link_up        = cxgbe_dev_set_link_up,
1112         .dev_set_link_down      = cxgbe_dev_set_link_down,
1113         .mtu_set                = cxgbe_dev_mtu_set,
1114         .tx_queue_setup         = cxgbe_dev_tx_queue_setup,
1115         .tx_queue_start         = cxgbe_dev_tx_queue_start,
1116         .tx_queue_stop          = cxgbe_dev_tx_queue_stop,
1117         .tx_queue_release       = cxgbe_dev_tx_queue_release,
1118         .rx_queue_setup         = cxgbe_dev_rx_queue_setup,
1119         .rx_queue_start         = cxgbe_dev_rx_queue_start,
1120         .rx_queue_stop          = cxgbe_dev_rx_queue_stop,
1121         .rx_queue_release       = cxgbe_dev_rx_queue_release,
1122         .filter_ctrl            = cxgbe_dev_filter_ctrl,
1123         .stats_get              = cxgbe_dev_stats_get,
1124         .stats_reset            = cxgbe_dev_stats_reset,
1125         .flow_ctrl_get          = cxgbe_flow_ctrl_get,
1126         .flow_ctrl_set          = cxgbe_flow_ctrl_set,
1127         .get_eeprom_length      = cxgbe_get_eeprom_length,
1128         .get_eeprom             = cxgbe_get_eeprom,
1129         .set_eeprom             = cxgbe_set_eeprom,
1130         .get_reg                = cxgbe_get_regs,
1131         .rss_hash_update        = cxgbe_dev_rss_hash_update,
1132         .rss_hash_conf_get      = cxgbe_dev_rss_hash_conf_get,
1133         .mac_addr_set           = cxgbe_mac_addr_set,
1134 };
1135
1136 /*
1137  * Initialize driver
1138  * It returns 0 on success.
1139  */
1140 static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev)
1141 {
1142         struct rte_pci_device *pci_dev;
1143         struct port_info *pi = eth_dev->data->dev_private;
1144         struct adapter *adapter = NULL;
1145         char name[RTE_ETH_NAME_MAX_LEN];
1146         int err = 0;
1147
1148         CXGBE_FUNC_TRACE();
1149
1150         eth_dev->dev_ops = &cxgbe_eth_dev_ops;
1151         eth_dev->rx_pkt_burst = &cxgbe_recv_pkts;
1152         eth_dev->tx_pkt_burst = &cxgbe_xmit_pkts;
1153         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1154
1155         /* for secondary processes, we attach to ethdevs allocated by primary
1156          * and do minimal initialization.
1157          */
1158         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1159                 int i;
1160
1161                 for (i = 1; i < MAX_NPORTS; i++) {
1162                         struct rte_eth_dev *rest_eth_dev;
1163                         char namei[RTE_ETH_NAME_MAX_LEN];
1164
1165                         snprintf(namei, sizeof(namei), "%s_%d",
1166                                  pci_dev->device.name, i);
1167                         rest_eth_dev = rte_eth_dev_attach_secondary(namei);
1168                         if (rest_eth_dev) {
1169                                 rest_eth_dev->device = &pci_dev->device;
1170                                 rest_eth_dev->dev_ops =
1171                                         eth_dev->dev_ops;
1172                                 rest_eth_dev->rx_pkt_burst =
1173                                         eth_dev->rx_pkt_burst;
1174                                 rest_eth_dev->tx_pkt_burst =
1175                                         eth_dev->tx_pkt_burst;
1176                                 rte_eth_dev_probing_finish(rest_eth_dev);
1177                         }
1178                 }
1179                 return 0;
1180         }
1181
1182         snprintf(name, sizeof(name), "cxgbeadapter%d", eth_dev->data->port_id);
1183         adapter = rte_zmalloc(name, sizeof(*adapter), 0);
1184         if (!adapter)
1185                 return -1;
1186
1187         adapter->use_unpacked_mode = 1;
1188         adapter->regs = (void *)pci_dev->mem_resource[0].addr;
1189         if (!adapter->regs) {
1190                 dev_err(adapter, "%s: cannot map device registers\n", __func__);
1191                 err = -ENOMEM;
1192                 goto out_free_adapter;
1193         }
1194         adapter->pdev = pci_dev;
1195         adapter->eth_dev = eth_dev;
1196         pi->adapter = adapter;
1197
1198         cxgbe_process_devargs(adapter);
1199
1200         err = cxgbe_probe(adapter);
1201         if (err) {
1202                 dev_err(adapter, "%s: cxgbe probe failed with err %d\n",
1203                         __func__, err);
1204                 goto out_free_adapter;
1205         }
1206
1207         return 0;
1208
1209 out_free_adapter:
1210         rte_free(adapter);
1211         return err;
1212 }
1213
1214 static int eth_cxgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1215 {
1216         struct port_info *pi = eth_dev->data->dev_private;
1217         struct adapter *adap = pi->adapter;
1218
1219         /* Free up other ports and all resources */
1220         cxgbe_close(adap);
1221         return 0;
1222 }
1223
1224 static int eth_cxgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1225         struct rte_pci_device *pci_dev)
1226 {
1227         return rte_eth_dev_pci_generic_probe(pci_dev,
1228                 sizeof(struct port_info), eth_cxgbe_dev_init);
1229 }
1230
1231 static int eth_cxgbe_pci_remove(struct rte_pci_device *pci_dev)
1232 {
1233         return rte_eth_dev_pci_generic_remove(pci_dev, eth_cxgbe_dev_uninit);
1234 }
1235
1236 static struct rte_pci_driver rte_cxgbe_pmd = {
1237         .id_table = cxgb4_pci_tbl,
1238         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1239         .probe = eth_cxgbe_pci_probe,
1240         .remove = eth_cxgbe_pci_remove,
1241 };
1242
1243 RTE_PMD_REGISTER_PCI(net_cxgbe, rte_cxgbe_pmd);
1244 RTE_PMD_REGISTER_PCI_TABLE(net_cxgbe, cxgb4_pci_tbl);
1245 RTE_PMD_REGISTER_KMOD_DEP(net_cxgbe, "* igb_uio | uio_pci_generic | vfio-pci");
1246 RTE_PMD_REGISTER_PARAM_STRING(net_cxgbe,
1247                               CXGBE_DEVARG_CMN_KEEP_OVLAN "=<0|1> "
1248                               CXGBE_DEVARG_CMN_TX_MODE_LATENCY "=<0|1> "
1249                               CXGBE_DEVARG_PF_FILTER_MODE "=<uint32> "
1250                               CXGBE_DEVARG_PF_FILTER_MASK "=<uint32> ");
1251 RTE_LOG_REGISTER(cxgbe_logtype, pmd.net.cxgbe, NOTICE);
1252 RTE_LOG_REGISTER(cxgbe_mbox_logtype, pmd.net.cxgbe.mbox, NOTICE);