drivers/net/cxgbe/cxgbe_filter.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Chelsio Communications.
   3  * All rights reserved.
   4  */
   5 #include <rte_net.h>
   6 #include "common.h"
   7 #include "t4_tcb.h"
   8 #include "t4_regs.h"
   9 #include "cxgbe_filter.h"
  10 #include "clip_tbl.h"
  11 #include "l2t.h"
  12
  13 /**
  14  * Initialize Hash Filters
  15  */
  16 int init_hash_filter(struct adapter *adap)
  17 {
  18         unsigned int n_user_filters;
  19         unsigned int user_filter_perc;
  20         int ret;
  21         u32 params[7], val[7];
  22
  23 #define FW_PARAM_DEV(param) \
  24         (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
  25         V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
  26
  27 #define FW_PARAM_PFVF(param) \
  28         (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
  29         V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param) |  \
  30         V_FW_PARAMS_PARAM_Y(0) | \
  31         V_FW_PARAMS_PARAM_Z(0))
  32
  33         params[0] = FW_PARAM_DEV(NTID);
  34         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
  35                               params, val);
  36         if (ret < 0)
  37                 return ret;
  38         adap->tids.ntids = val[0];
  39         adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
  40
  41         user_filter_perc = 100;
  42         n_user_filters = mult_frac(adap->tids.nftids,
  43                                    user_filter_perc,
  44                                    100);
  45
  46         adap->tids.nftids = n_user_filters;
  47         adap->params.hash_filter = 1;
  48         return 0;
  49 }
  50
  51 /**
  52  * Validate if the requested filter specification can be set by checking
  53  * if the requested features have been enabled
  54  */
  55 int validate_filter(struct adapter *adapter, struct ch_filter_specification *fs)
  56 {
  57         u32 fconf;
  58
  59         /*
  60          * Check for unconfigured fields being used.
  61          */
  62         fconf = adapter->params.tp.vlan_pri_map;
  63
  64 #define S(_field) \
  65         (fs->val._field || fs->mask._field)
  66 #define U(_mask, _field) \
  67         (!(fconf & (_mask)) && S(_field))
  68
  69         if (U(F_PORT, iport) || U(F_ETHERTYPE, ethtype) || U(F_PROTOCOL, proto))
  70                 return -EOPNOTSUPP;
  71
  72 #undef S
  73 #undef U
  74
  75         /*
  76          * If the user is requesting that the filter action loop
  77          * matching packets back out one of our ports, make sure that
  78          * the egress port is in range.
  79          */
  80         if (fs->action == FILTER_SWITCH &&
  81             fs->eport >= adapter->params.nports)
  82                 return -ERANGE;
  83
  84         /*
  85          * Don't allow various trivially obvious bogus out-of-range
  86          * values ...
  87          */
  88         if (fs->val.iport >= adapter->params.nports)
  89                 return -ERANGE;
  90
  91         return 0;
  92 }
  93
  94 /**
  95  * Get the queue to which the traffic must be steered to.
  96  */
  97 static unsigned int get_filter_steerq(struct rte_eth_dev *dev,
  98                                       struct ch_filter_specification *fs)
  99 {
 100         struct port_info *pi = ethdev2pinfo(dev);
 101         struct adapter *adapter = pi->adapter;
 102         unsigned int iq;
 103
 104         /*
 105          * If the user has requested steering matching Ingress Packets
 106          * to a specific Queue Set, we need to make sure it's in range
 107          * for the port and map that into the Absolute Queue ID of the
 108          * Queue Set's Response Queue.
 109          */
 110         if (!fs->dirsteer) {
 111                 iq = 0;
 112         } else {
 113                 /*
 114                  * If the iq id is greater than the number of qsets,
 115                  * then assume it is an absolute qid.
 116                  */
 117                 if (fs->iq < pi->n_rx_qsets)
 118                         iq = adapter->sge.ethrxq[pi->first_qset +
 119                                                  fs->iq].rspq.abs_id;
 120                 else
 121                         iq = fs->iq;
 122         }
 123
 124         return iq;
 125 }
 126
 127 /* Return an error number if the indicated filter isn't writable ... */
 128 int writable_filter(struct filter_entry *f)
 129 {
 130         if (f->locked)
 131                 return -EPERM;
 132         if (f->pending)
 133                 return -EBUSY;
 134
 135         return 0;
 136 }
 137
 138 /**
 139  * Send CPL_SET_TCB_FIELD message
 140  */
 141 static void set_tcb_field(struct adapter *adapter, unsigned int ftid,
 142                           u16 word, u64 mask, u64 val, int no_reply)
 143 {
 144         struct rte_mbuf *mbuf;
 145         struct cpl_set_tcb_field *req;
 146         struct sge_ctrl_txq *ctrlq;
 147
 148         ctrlq = &adapter->sge.ctrlq[0];
 149         mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
 150         WARN_ON(!mbuf);
 151
 152         mbuf->data_len = sizeof(*req);
 153         mbuf->pkt_len = mbuf->data_len;
 154
 155         req = rte_pktmbuf_mtod(mbuf, struct cpl_set_tcb_field *);
 156         memset(req, 0, sizeof(*req));
 157         INIT_TP_WR_MIT_CPL(req, CPL_SET_TCB_FIELD, ftid);
 158         req->reply_ctrl = cpu_to_be16(V_REPLY_CHAN(0) |
 159                                       V_QUEUENO(adapter->sge.fw_evtq.abs_id) |
 160                                       V_NO_REPLY(no_reply));
 161         req->word_cookie = cpu_to_be16(V_WORD(word) | V_COOKIE(ftid));
 162         req->mask = cpu_to_be64(mask);
 163         req->val = cpu_to_be64(val);
 164
 165         t4_mgmt_tx(ctrlq, mbuf);
 166 }
 167
 168 /**
 169  * Set one of the t_flags bits in the TCB.
 170  */
 171 static void set_tcb_tflag(struct adapter *adap, unsigned int ftid,
 172                           unsigned int bit_pos, unsigned int val, int no_reply)
 173 {
 174         set_tcb_field(adap, ftid,  W_TCB_T_FLAGS, 1ULL << bit_pos,
 175                       (unsigned long long)val << bit_pos, no_reply);
 176 }
 177
 178 /**
 179  * Build a CPL_SET_TCB_FIELD message as payload of a ULP_TX_PKT command.
 180  */
 181 static inline void mk_set_tcb_field_ulp(struct filter_entry *f,
 182                                         struct cpl_set_tcb_field *req,
 183                                         unsigned int word,
 184                                         u64 mask, u64 val, u8 cookie,
 185                                         int no_reply)
 186 {
 187         struct ulp_txpkt *txpkt = (struct ulp_txpkt *)req;
 188         struct ulptx_idata *sc = (struct ulptx_idata *)(txpkt + 1);
 189
 190         txpkt->cmd_dest = cpu_to_be32(V_ULPTX_CMD(ULP_TX_PKT) |
 191                                       V_ULP_TXPKT_DEST(0));
 192         txpkt->len = cpu_to_be32(DIV_ROUND_UP(sizeof(*req), 16));
 193         sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_IMM));
 194         sc->len = cpu_to_be32(sizeof(*req) - sizeof(struct work_request_hdr));
 195         OPCODE_TID(req) = cpu_to_be32(MK_OPCODE_TID(CPL_SET_TCB_FIELD, f->tid));
 196         req->reply_ctrl = cpu_to_be16(V_NO_REPLY(no_reply) | V_REPLY_CHAN(0) |
 197                                       V_QUEUENO(0));
 198         req->word_cookie = cpu_to_be16(V_WORD(word) | V_COOKIE(cookie));
 199         req->mask = cpu_to_be64(mask);
 200         req->val = cpu_to_be64(val);
 201         sc = (struct ulptx_idata *)(req + 1);
 202         sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_NOOP));
 203         sc->len = cpu_to_be32(0);
 204 }
 205
 206 /**
 207  * Check if entry already filled.
 208  */
 209 bool is_filter_set(struct tid_info *t, int fidx, int family)
 210 {
 211         bool result = FALSE;
 212         int i, max;
 213
 214         /* IPv6 requires four slots and IPv4 requires only 1 slot.
 215          * Ensure, there's enough slots available.
 216          */
 217         max = family == FILTER_TYPE_IPV6 ? fidx + 3 : fidx;
 218
 219         t4_os_lock(&t->ftid_lock);
 220         for (i = fidx; i <= max; i++) {
 221                 if (rte_bitmap_get(t->ftid_bmap, i)) {
 222                         result = TRUE;
 223                         break;
 224                 }
 225         }
 226         t4_os_unlock(&t->ftid_lock);
 227         return result;
 228 }
 229
 230 /**
 231  * Allocate a available free entry
 232  */
 233 int cxgbe_alloc_ftid(struct adapter *adap, unsigned int family)
 234 {
 235         struct tid_info *t = &adap->tids;
 236         int pos;
 237         int size = t->nftids;
 238
 239         t4_os_lock(&t->ftid_lock);
 240         if (family == FILTER_TYPE_IPV6)
 241                 pos = cxgbe_bitmap_find_free_region(t->ftid_bmap, size, 4);
 242         else
 243                 pos = cxgbe_find_first_zero_bit(t->ftid_bmap, size);
 244         t4_os_unlock(&t->ftid_lock);
 245
 246         return pos < size ? pos : -1;
 247 }
 248
 249 /**
 250  * Construct hash filter ntuple.
 251  */
 252 static u64 hash_filter_ntuple(const struct filter_entry *f)
 253 {
 254         struct adapter *adap = ethdev2adap(f->dev);
 255         struct tp_params *tp = &adap->params.tp;
 256         u64 ntuple = 0;
 257         u16 tcp_proto = IPPROTO_TCP; /* TCP Protocol Number */
 258
 259         if (tp->port_shift >= 0)
 260                 ntuple |= (u64)f->fs.mask.iport << tp->port_shift;
 261
 262         if (tp->protocol_shift >= 0) {
 263                 if (!f->fs.val.proto)
 264                         ntuple |= (u64)tcp_proto << tp->protocol_shift;
 265                 else
 266                         ntuple |= (u64)f->fs.val.proto << tp->protocol_shift;
 267         }
 268
 269         if (tp->ethertype_shift >= 0 && f->fs.mask.ethtype)
 270                 ntuple |= (u64)(f->fs.val.ethtype) << tp->ethertype_shift;
 271
 272         if (ntuple != tp->hash_filter_mask)
 273                 return 0;
 274
 275         return ntuple;
 276 }
 277
 278 /**
 279  * Build a CPL_ABORT_REQ message as payload of a ULP_TX_PKT command.
 280  */
 281 static void mk_abort_req_ulp(struct cpl_abort_req *abort_req,
 282                              unsigned int tid)
 283 {
 284         struct ulp_txpkt *txpkt = (struct ulp_txpkt *)abort_req;
 285         struct ulptx_idata *sc = (struct ulptx_idata *)(txpkt + 1);
 286
 287         txpkt->cmd_dest = cpu_to_be32(V_ULPTX_CMD(ULP_TX_PKT) |
 288                                       V_ULP_TXPKT_DEST(0));
 289         txpkt->len = cpu_to_be32(DIV_ROUND_UP(sizeof(*abort_req), 16));
 290         sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_IMM));
 291         sc->len = cpu_to_be32(sizeof(*abort_req) -
 292                               sizeof(struct work_request_hdr));
 293         OPCODE_TID(abort_req) = cpu_to_be32(MK_OPCODE_TID(CPL_ABORT_REQ, tid));
 294         abort_req->rsvd0 = cpu_to_be32(0);
 295         abort_req->rsvd1 = 0;
 296         abort_req->cmd = CPL_ABORT_NO_RST;
 297         sc = (struct ulptx_idata *)(abort_req + 1);
 298         sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_NOOP));
 299         sc->len = cpu_to_be32(0);
 300 }
 301
 302 /**
 303  * Build a CPL_ABORT_RPL message as payload of a ULP_TX_PKT command.
 304  */
 305 static void mk_abort_rpl_ulp(struct cpl_abort_rpl *abort_rpl,
 306                              unsigned int tid)
 307 {
 308         struct ulp_txpkt *txpkt = (struct ulp_txpkt *)abort_rpl;
 309         struct ulptx_idata *sc = (struct ulptx_idata *)(txpkt + 1);
 310
 311         txpkt->cmd_dest = cpu_to_be32(V_ULPTX_CMD(ULP_TX_PKT) |
 312                                       V_ULP_TXPKT_DEST(0));
 313         txpkt->len = cpu_to_be32(DIV_ROUND_UP(sizeof(*abort_rpl), 16));
 314         sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_IMM));
 315         sc->len = cpu_to_be32(sizeof(*abort_rpl) -
 316                               sizeof(struct work_request_hdr));
 317         OPCODE_TID(abort_rpl) = cpu_to_be32(MK_OPCODE_TID(CPL_ABORT_RPL, tid));
 318         abort_rpl->rsvd0 = cpu_to_be32(0);
 319         abort_rpl->rsvd1 = 0;
 320         abort_rpl->cmd = CPL_ABORT_NO_RST;
 321         sc = (struct ulptx_idata *)(abort_rpl + 1);
 322         sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_NOOP));
 323         sc->len = cpu_to_be32(0);
 324 }
 325
 326 /**
 327  * Delete the specified hash filter.
 328  */
 329 static int cxgbe_del_hash_filter(struct rte_eth_dev *dev,
 330                                  unsigned int filter_id,
 331                                  struct filter_ctx *ctx)
 332 {
 333         struct adapter *adapter = ethdev2adap(dev);
 334         struct tid_info *t = &adapter->tids;
 335         struct filter_entry *f;
 336         struct sge_ctrl_txq *ctrlq;
 337         unsigned int port_id = ethdev2pinfo(dev)->port_id;
 338         int ret;
 339
 340         if (filter_id > adapter->tids.ntids)
 341                 return -E2BIG;
 342
 343         f = lookup_tid(t, filter_id);
 344         if (!f) {
 345                 dev_err(adapter, "%s: no filter entry for filter_id = %d\n",
 346                         __func__, filter_id);
 347                 return -EINVAL;
 348         }
 349
 350         ret = writable_filter(f);
 351         if (ret)
 352                 return ret;
 353
 354         if (f->valid) {
 355                 unsigned int wrlen;
 356                 struct rte_mbuf *mbuf;
 357                 struct work_request_hdr *wr;
 358                 struct ulptx_idata *aligner;
 359                 struct cpl_set_tcb_field *req;
 360                 struct cpl_abort_req *abort_req;
 361                 struct cpl_abort_rpl *abort_rpl;
 362
 363                 f->ctx = ctx;
 364                 f->pending = 1;
 365
 366                 wrlen = cxgbe_roundup(sizeof(*wr) +
 367                                       (sizeof(*req) + sizeof(*aligner)) +
 368                                       sizeof(*abort_req) + sizeof(*abort_rpl),
 369                                       16);
 370
 371                 ctrlq = &adapter->sge.ctrlq[port_id];
 372                 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
 373                 if (!mbuf) {
 374                         dev_err(adapter, "%s: could not allocate skb ..\n",
 375                                 __func__);
 376                         goto out_err;
 377                 }
 378
 379                 mbuf->data_len = wrlen;
 380                 mbuf->pkt_len = mbuf->data_len;
 381
 382                 req = rte_pktmbuf_mtod(mbuf, struct cpl_set_tcb_field *);
 383                 INIT_ULPTX_WR(req, wrlen, 0, 0);
 384                 wr = (struct work_request_hdr *)req;
 385                 wr++;
 386                 req = (struct cpl_set_tcb_field *)wr;
 387                 mk_set_tcb_field_ulp(f, req, W_TCB_RSS_INFO,
 388                                 V_TCB_RSS_INFO(M_TCB_RSS_INFO),
 389                                 V_TCB_RSS_INFO(adapter->sge.fw_evtq.abs_id),
 390                                 0, 1);
 391                 aligner = (struct ulptx_idata *)(req + 1);
 392                 abort_req = (struct cpl_abort_req *)(aligner + 1);
 393                 mk_abort_req_ulp(abort_req, f->tid);
 394                 abort_rpl = (struct cpl_abort_rpl *)(abort_req + 1);
 395                 mk_abort_rpl_ulp(abort_rpl, f->tid);
 396                 t4_mgmt_tx(ctrlq, mbuf);
 397         }
 398         return 0;
 399
 400 out_err:
 401         return -ENOMEM;
 402 }
 403
 404 /**
 405  * Build a ACT_OPEN_REQ6 message for setting IPv6 hash filter.
 406  */
 407 static void mk_act_open_req6(struct filter_entry *f, struct rte_mbuf *mbuf,
 408                              unsigned int qid_filterid, struct adapter *adap)
 409 {
 410         struct cpl_t6_act_open_req6 *req = NULL;
 411         u64 local_lo, local_hi, peer_lo, peer_hi;
 412         u32 *lip = (u32 *)f->fs.val.lip;
 413         u32 *fip = (u32 *)f->fs.val.fip;
 414
 415         switch (CHELSIO_CHIP_VERSION(adap->params.chip)) {
 416         case CHELSIO_T6:
 417                 req = rte_pktmbuf_mtod(mbuf, struct cpl_t6_act_open_req6 *);
 418
 419                 INIT_TP_WR(req, 0);
 420                 break;
 421         default:
 422                 dev_err(adap, "%s: unsupported chip type!\n", __func__);
 423                 return;
 424         }
 425
 426         local_hi = ((u64)lip[1]) << 32 | lip[0];
 427         local_lo = ((u64)lip[3]) << 32 | lip[2];
 428         peer_hi = ((u64)fip[1]) << 32 | fip[0];
 429         peer_lo = ((u64)fip[3]) << 32 | fip[2];
 430
 431         OPCODE_TID(req) = cpu_to_be32(MK_OPCODE_TID(CPL_ACT_OPEN_REQ6,
 432                                                     qid_filterid));
 433         req->local_port = cpu_to_be16(f->fs.val.lport);
 434         req->peer_port = cpu_to_be16(f->fs.val.fport);
 435         req->local_ip_hi = local_hi;
 436         req->local_ip_lo = local_lo;
 437         req->peer_ip_hi = peer_hi;
 438         req->peer_ip_lo = peer_lo;
 439         req->opt0 = cpu_to_be64(V_NAGLE(f->fs.newvlan == VLAN_REMOVE ||
 440                                         f->fs.newvlan == VLAN_REWRITE) |
 441                                 V_DELACK(f->fs.hitcnts) |
 442                                 V_L2T_IDX(f->l2t ? f->l2t->idx : 0) |
 443                                 V_SMAC_SEL((cxgbe_port_viid(f->dev) & 0x7F)
 444                                            << 1) |
 445                                 V_TX_CHAN(f->fs.eport) |
 446                                 V_ULP_MODE(ULP_MODE_NONE) |
 447                                 F_TCAM_BYPASS | F_NON_OFFLOAD);
 448         req->params = cpu_to_be64(V_FILTER_TUPLE(hash_filter_ntuple(f)));
 449         req->opt2 = cpu_to_be32(F_RSS_QUEUE_VALID |
 450                             V_RSS_QUEUE(f->fs.iq) |
 451                             F_T5_OPT_2_VALID |
 452                             F_RX_CHANNEL |
 453                             V_CONG_CNTRL((f->fs.action == FILTER_DROP) |
 454                                          (f->fs.dirsteer << 1)) |
 455                             V_CCTRL_ECN(f->fs.action == FILTER_SWITCH));
 456 }
 457
 458 /**
 459  * Build a ACT_OPEN_REQ message for setting IPv4 hash filter.
 460  */
 461 static void mk_act_open_req(struct filter_entry *f, struct rte_mbuf *mbuf,
 462                             unsigned int qid_filterid, struct adapter *adap)
 463 {
 464         struct cpl_t6_act_open_req *req = NULL;
 465
 466         switch (CHELSIO_CHIP_VERSION(adap->params.chip)) {
 467         case CHELSIO_T6:
 468                 req = rte_pktmbuf_mtod(mbuf, struct cpl_t6_act_open_req *);
 469
 470                 INIT_TP_WR(req, 0);
 471                 break;
 472         default:
 473                 dev_err(adap, "%s: unsupported chip type!\n", __func__);
 474                 return;
 475         }
 476
 477         OPCODE_TID(req) = cpu_to_be32(MK_OPCODE_TID(CPL_ACT_OPEN_REQ,
 478                                                     qid_filterid));
 479         req->local_port = cpu_to_be16(f->fs.val.lport);
 480         req->peer_port = cpu_to_be16(f->fs.val.fport);
 481         req->local_ip = f->fs.val.lip[0] | f->fs.val.lip[1] << 8 |
 482                         f->fs.val.lip[2] << 16 | f->fs.val.lip[3] << 24;
 483         req->peer_ip = f->fs.val.fip[0] | f->fs.val.fip[1] << 8 |
 484                         f->fs.val.fip[2] << 16 | f->fs.val.fip[3] << 24;
 485         req->opt0 = cpu_to_be64(V_NAGLE(f->fs.newvlan == VLAN_REMOVE ||
 486                                         f->fs.newvlan == VLAN_REWRITE) |
 487                                 V_DELACK(f->fs.hitcnts) |
 488                                 V_L2T_IDX(f->l2t ? f->l2t->idx : 0) |
 489                                 V_SMAC_SEL((cxgbe_port_viid(f->dev) & 0x7F)
 490                                            << 1) |
 491                                 V_TX_CHAN(f->fs.eport) |
 492                                 V_ULP_MODE(ULP_MODE_NONE) |
 493                                 F_TCAM_BYPASS | F_NON_OFFLOAD);
 494         req->params = cpu_to_be64(V_FILTER_TUPLE(hash_filter_ntuple(f)));
 495         req->opt2 = cpu_to_be32(F_RSS_QUEUE_VALID |
 496                             V_RSS_QUEUE(f->fs.iq) |
 497                             F_T5_OPT_2_VALID |
 498                             F_RX_CHANNEL |
 499                             V_CONG_CNTRL((f->fs.action == FILTER_DROP) |
 500                                          (f->fs.dirsteer << 1)) |
 501                             V_CCTRL_ECN(f->fs.action == FILTER_SWITCH));
 502 }
 503
 504 /**
 505  * Set the specified hash filter.
 506  */
 507 static int cxgbe_set_hash_filter(struct rte_eth_dev *dev,
 508                                  struct ch_filter_specification *fs,
 509                                  struct filter_ctx *ctx)
 510 {
 511         struct port_info *pi = ethdev2pinfo(dev);
 512         struct adapter *adapter = pi->adapter;
 513         struct tid_info *t = &adapter->tids;
 514         struct filter_entry *f;
 515         struct rte_mbuf *mbuf;
 516         struct sge_ctrl_txq *ctrlq;
 517         unsigned int iq;
 518         int atid, size;
 519         int ret = 0;
 520
 521         ret = validate_filter(adapter, fs);
 522         if (ret)
 523                 return ret;
 524
 525         iq = get_filter_steerq(dev, fs);
 526
 527         ctrlq = &adapter->sge.ctrlq[pi->port_id];
 528
 529         f = t4_os_alloc(sizeof(*f));
 530         if (!f)
 531                 goto out_err;
 532
 533         f->fs = *fs;
 534         f->ctx = ctx;
 535         f->dev = dev;
 536         f->fs.iq = iq;
 537
 538         /*
 539          * If the new filter requires loopback Destination MAC and/or VLAN
 540          * rewriting then we need to allocate a Layer 2 Table (L2T) entry for
 541          * the filter.
 542          */
 543         if (f->fs.newvlan == VLAN_INSERT ||
 544             f->fs.newvlan == VLAN_REWRITE) {
 545                 /* allocate L2T entry for new filter */
 546                 f->l2t = cxgbe_l2t_alloc_switching(dev, f->fs.vlan,
 547                                                    f->fs.eport, f->fs.dmac);
 548                 if (!f->l2t) {
 549                         ret = -ENOMEM;
 550                         goto out_err;
 551                 }
 552         }
 553
 554         atid = cxgbe_alloc_atid(t, f);
 555         if (atid < 0)
 556                 goto out_err;
 557
 558         if (f->fs.type) {
 559                 /* IPv6 hash filter */
 560                 f->clipt = cxgbe_clip_alloc(f->dev, (u32 *)&f->fs.val.lip);
 561                 if (!f->clipt)
 562                         goto free_atid;
 563
 564                 size = sizeof(struct cpl_t6_act_open_req6);
 565                 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
 566                 if (!mbuf) {
 567                         ret = -ENOMEM;
 568                         goto free_clip;
 569                 }
 570
 571                 mbuf->data_len = size;
 572                 mbuf->pkt_len = mbuf->data_len;
 573
 574                 mk_act_open_req6(f, mbuf,
 575                                  ((adapter->sge.fw_evtq.abs_id << 14) | atid),
 576                                  adapter);
 577         } else {
 578                 /* IPv4 hash filter */
 579                 size = sizeof(struct cpl_t6_act_open_req);
 580                 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
 581                 if (!mbuf) {
 582                         ret = -ENOMEM;
 583                         goto free_atid;
 584                 }
 585
 586                 mbuf->data_len = size;
 587                 mbuf->pkt_len = mbuf->data_len;
 588
 589                 mk_act_open_req(f, mbuf,
 590                                 ((adapter->sge.fw_evtq.abs_id << 14) | atid),
 591                                 adapter);
 592         }
 593
 594         f->pending = 1;
 595         t4_mgmt_tx(ctrlq, mbuf);
 596         return 0;
 597
 598 free_clip:
 599         cxgbe_clip_release(f->dev, f->clipt);
 600 free_atid:
 601         cxgbe_free_atid(t, atid);
 602
 603 out_err:
 604         t4_os_free(f);
 605         return ret;
 606 }
 607
 608 /**
 609  * Clear a filter and release any of its resources that we own.  This also
 610  * clears the filter's "pending" status.
 611  */
 612 void clear_filter(struct filter_entry *f)
 613 {
 614         if (f->clipt)
 615                 cxgbe_clip_release(f->dev, f->clipt);
 616
 617         /*
 618          * The zeroing of the filter rule below clears the filter valid,
 619          * pending, locked flags etc. so it's all we need for
 620          * this operation.
 621          */
 622         memset(f, 0, sizeof(*f));
 623 }
 624
 625 /**
 626  * t4_mk_filtdelwr - create a delete filter WR
 627  * @ftid: the filter ID
 628  * @wr: the filter work request to populate
 629  * @qid: ingress queue to receive the delete notification
 630  *
 631  * Creates a filter work request to delete the supplied filter.  If @qid is
 632  * negative the delete notification is suppressed.
 633  */
 634 static void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
 635 {
 636         memset(wr, 0, sizeof(*wr));
 637         wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR));
 638         wr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*wr) / 16));
 639         wr->tid_to_iq = cpu_to_be32(V_FW_FILTER_WR_TID(ftid) |
 640                                     V_FW_FILTER_WR_NOREPLY(qid < 0));
 641         wr->del_filter_to_l2tix = cpu_to_be32(F_FW_FILTER_WR_DEL_FILTER);
 642         if (qid >= 0)
 643                 wr->rx_chan_rx_rpl_iq =
 644                                 cpu_to_be16(V_FW_FILTER_WR_RX_RPL_IQ(qid));
 645 }
 646
 647 /**
 648  * Create FW work request to delete the filter at a specified index
 649  */
 650 static int del_filter_wr(struct rte_eth_dev *dev, unsigned int fidx)
 651 {
 652         struct adapter *adapter = ethdev2adap(dev);
 653         struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
 654         struct rte_mbuf *mbuf;
 655         struct fw_filter_wr *fwr;
 656         struct sge_ctrl_txq *ctrlq;
 657         unsigned int port_id = ethdev2pinfo(dev)->port_id;
 658
 659         ctrlq = &adapter->sge.ctrlq[port_id];
 660         mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
 661         if (!mbuf)
 662                 return -ENOMEM;
 663
 664         mbuf->data_len = sizeof(*fwr);
 665         mbuf->pkt_len = mbuf->data_len;
 666
 667         fwr = rte_pktmbuf_mtod(mbuf, struct fw_filter_wr *);
 668         t4_mk_filtdelwr(f->tid, fwr, adapter->sge.fw_evtq.abs_id);
 669
 670         /*
 671          * Mark the filter as "pending" and ship off the Filter Work Request.
 672          * When we get the Work Request Reply we'll clear the pending status.
 673          */
 674         f->pending = 1;
 675         t4_mgmt_tx(ctrlq, mbuf);
 676         return 0;
 677 }
 678
 679 int set_filter_wr(struct rte_eth_dev *dev, unsigned int fidx)
 680 {
 681         struct adapter *adapter = ethdev2adap(dev);
 682         struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
 683         struct rte_mbuf *mbuf;
 684         struct fw_filter_wr *fwr;
 685         struct sge_ctrl_txq *ctrlq;
 686         unsigned int port_id = ethdev2pinfo(dev)->port_id;
 687         int ret;
 688
 689         /*
 690          * If the new filter requires loopback Destination MAC and/or VLAN
 691          * rewriting then we need to allocate a Layer 2 Table (L2T) entry for
 692          * the filter.
 693          */
 694         if (f->fs.newvlan) {
 695                 /* allocate L2T entry for new filter */
 696                 f->l2t = cxgbe_l2t_alloc_switching(f->dev, f->fs.vlan,
 697                                                    f->fs.eport, f->fs.dmac);
 698                 if (!f->l2t)
 699                         return -ENOMEM;
 700         }
 701
 702         ctrlq = &adapter->sge.ctrlq[port_id];
 703         mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
 704         if (!mbuf) {
 705                 ret = -ENOMEM;
 706                 goto out;
 707         }
 708
 709         mbuf->data_len = sizeof(*fwr);
 710         mbuf->pkt_len = mbuf->data_len;
 711
 712         fwr = rte_pktmbuf_mtod(mbuf, struct fw_filter_wr *);
 713         memset(fwr, 0, sizeof(*fwr));
 714
 715         /*
 716          * Construct the work request to set the filter.
 717          */
 718         fwr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR));
 719         fwr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*fwr) / 16));
 720         fwr->tid_to_iq =
 721                 cpu_to_be32(V_FW_FILTER_WR_TID(f->tid) |
 722                             V_FW_FILTER_WR_RQTYPE(f->fs.type) |
 723                             V_FW_FILTER_WR_NOREPLY(0) |
 724                             V_FW_FILTER_WR_IQ(f->fs.iq));
 725         fwr->del_filter_to_l2tix =
 726                 cpu_to_be32(V_FW_FILTER_WR_DROP(f->fs.action == FILTER_DROP) |
 727                             V_FW_FILTER_WR_DIRSTEER(f->fs.dirsteer) |
 728                             V_FW_FILTER_WR_LPBK(f->fs.action == FILTER_SWITCH) |
 729                             V_FW_FILTER_WR_INSVLAN
 730                                 (f->fs.newvlan == VLAN_INSERT ||
 731                                  f->fs.newvlan == VLAN_REWRITE) |
 732                             V_FW_FILTER_WR_RMVLAN
 733                                 (f->fs.newvlan == VLAN_REMOVE ||
 734                                  f->fs.newvlan == VLAN_REWRITE) |
 735                             V_FW_FILTER_WR_HITCNTS(f->fs.hitcnts) |
 736                             V_FW_FILTER_WR_TXCHAN(f->fs.eport) |
 737                             V_FW_FILTER_WR_PRIO(f->fs.prio) |
 738                             V_FW_FILTER_WR_L2TIX(f->l2t ? f->l2t->idx : 0));
 739         fwr->ethtype = cpu_to_be16(f->fs.val.ethtype);
 740         fwr->ethtypem = cpu_to_be16(f->fs.mask.ethtype);
 741         fwr->smac_sel = 0;
 742         fwr->rx_chan_rx_rpl_iq =
 743                 cpu_to_be16(V_FW_FILTER_WR_RX_CHAN(0) |
 744                             V_FW_FILTER_WR_RX_RPL_IQ(adapter->sge.fw_evtq.abs_id
 745                                                      ));
 746         fwr->maci_to_matchtypem =
 747                 cpu_to_be32(V_FW_FILTER_WR_PORT(f->fs.val.iport) |
 748                             V_FW_FILTER_WR_PORTM(f->fs.mask.iport));
 749         fwr->ptcl = f->fs.val.proto;
 750         fwr->ptclm = f->fs.mask.proto;
 751         rte_memcpy(fwr->lip, f->fs.val.lip, sizeof(fwr->lip));
 752         rte_memcpy(fwr->lipm, f->fs.mask.lip, sizeof(fwr->lipm));
 753         rte_memcpy(fwr->fip, f->fs.val.fip, sizeof(fwr->fip));
 754         rte_memcpy(fwr->fipm, f->fs.mask.fip, sizeof(fwr->fipm));
 755         fwr->lp = cpu_to_be16(f->fs.val.lport);
 756         fwr->lpm = cpu_to_be16(f->fs.mask.lport);
 757         fwr->fp = cpu_to_be16(f->fs.val.fport);
 758         fwr->fpm = cpu_to_be16(f->fs.mask.fport);
 759
 760         /*
 761          * Mark the filter as "pending" and ship off the Filter Work Request.
 762          * When we get the Work Request Reply we'll clear the pending status.
 763          */
 764         f->pending = 1;
 765         t4_mgmt_tx(ctrlq, mbuf);
 766         return 0;
 767
 768 out:
 769         return ret;
 770 }
 771
 772 /**
 773  * Set the corresponding entry in the bitmap. 4 slots are
 774  * marked for IPv6, whereas only 1 slot is marked for IPv4.
 775  */
 776 static int cxgbe_set_ftid(struct tid_info *t, int fidx, int family)
 777 {
 778         t4_os_lock(&t->ftid_lock);
 779         if (rte_bitmap_get(t->ftid_bmap, fidx)) {
 780                 t4_os_unlock(&t->ftid_lock);
 781                 return -EBUSY;
 782         }
 783
 784         if (family == FILTER_TYPE_IPV4) {
 785                 rte_bitmap_set(t->ftid_bmap, fidx);
 786         } else {
 787                 rte_bitmap_set(t->ftid_bmap, fidx);
 788                 rte_bitmap_set(t->ftid_bmap, fidx + 1);
 789                 rte_bitmap_set(t->ftid_bmap, fidx + 2);
 790                 rte_bitmap_set(t->ftid_bmap, fidx + 3);
 791         }
 792         t4_os_unlock(&t->ftid_lock);
 793         return 0;
 794 }
 795
 796 /**
 797  * Clear the corresponding entry in the bitmap. 4 slots are
 798  * cleared for IPv6, whereas only 1 slot is cleared for IPv4.
 799  */
 800 static void cxgbe_clear_ftid(struct tid_info *t, int fidx, int family)
 801 {
 802         t4_os_lock(&t->ftid_lock);
 803         if (family == FILTER_TYPE_IPV4) {
 804                 rte_bitmap_clear(t->ftid_bmap, fidx);
 805         } else {
 806                 rte_bitmap_clear(t->ftid_bmap, fidx);
 807                 rte_bitmap_clear(t->ftid_bmap, fidx + 1);
 808                 rte_bitmap_clear(t->ftid_bmap, fidx + 2);
 809                 rte_bitmap_clear(t->ftid_bmap, fidx + 3);
 810         }
 811         t4_os_unlock(&t->ftid_lock);
 812 }
 813
 814 /**
 815  * Check a delete filter request for validity and send it to the hardware.
 816  * Return 0 on success, an error number otherwise.  We attach any provided
 817  * filter operation context to the internal filter specification in order to
 818  * facilitate signaling completion of the operation.
 819  */
 820 int cxgbe_del_filter(struct rte_eth_dev *dev, unsigned int filter_id,
 821                      struct ch_filter_specification *fs,
 822                      struct filter_ctx *ctx)
 823 {
 824         struct port_info *pi = (struct port_info *)(dev->data->dev_private);
 825         struct adapter *adapter = pi->adapter;
 826         struct filter_entry *f;
 827         unsigned int chip_ver;
 828         int ret;
 829
 830         if (is_hashfilter(adapter) && fs->cap)
 831                 return cxgbe_del_hash_filter(dev, filter_id, ctx);
 832
 833         if (filter_id >= adapter->tids.nftids)
 834                 return -ERANGE;
 835
 836         chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
 837
 838         ret = is_filter_set(&adapter->tids, filter_id, fs->type);
 839         if (!ret) {
 840                 dev_warn(adap, "%s: could not find filter entry: %u\n",
 841                          __func__, filter_id);
 842                 return -EINVAL;
 843         }
 844
 845         /*
 846          * Ensure filter id is aligned on the 2 slot boundary for T6,
 847          * and 4 slot boundary for cards below T6.
 848          */
 849         if (fs->type) {
 850                 if (chip_ver < CHELSIO_T6)
 851                         filter_id &= ~(0x3);
 852                 else
 853                         filter_id &= ~(0x1);
 854         }
 855
 856         f = &adapter->tids.ftid_tab[filter_id];
 857         ret = writable_filter(f);
 858         if (ret)
 859                 return ret;
 860
 861         if (f->valid) {
 862                 f->ctx = ctx;
 863                 cxgbe_clear_ftid(&adapter->tids,
 864                                  f->tid - adapter->tids.ftid_base,
 865                                  f->fs.type ? FILTER_TYPE_IPV6 :
 866                                               FILTER_TYPE_IPV4);
 867                 return del_filter_wr(dev, filter_id);
 868         }
 869
 870         /*
 871          * If the caller has passed in a Completion Context then we need to
 872          * mark it as a successful completion so they don't stall waiting
 873          * for it.
 874          */
 875         if (ctx) {
 876                 ctx->result = 0;
 877                 t4_complete(&ctx->completion);
 878         }
 879
 880         return 0;
 881 }
 882
 883 /**
 884  * Check a Chelsio Filter Request for validity, convert it into our internal
 885  * format and send it to the hardware.  Return 0 on success, an error number
 886  * otherwise.  We attach any provided filter operation context to the internal
 887  * filter specification in order to facilitate signaling completion of the
 888  * operation.
 889  */
 890 int cxgbe_set_filter(struct rte_eth_dev *dev, unsigned int filter_id,
 891                      struct ch_filter_specification *fs,
 892                      struct filter_ctx *ctx)
 893 {
 894         struct port_info *pi = ethdev2pinfo(dev);
 895         struct adapter *adapter = pi->adapter;
 896         unsigned int fidx, iq, fid_bit = 0;
 897         struct filter_entry *f;
 898         unsigned int chip_ver;
 899         uint8_t bitoff[16] = {0};
 900         int ret;
 901
 902         if (is_hashfilter(adapter) && fs->cap)
 903                 return cxgbe_set_hash_filter(dev, fs, ctx);
 904
 905         if (filter_id >= adapter->tids.nftids)
 906                 return -ERANGE;
 907
 908         chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
 909
 910         ret = validate_filter(adapter, fs);
 911         if (ret)
 912                 return ret;
 913
 914         /*
 915          * Ensure filter id is aligned on the 4 slot boundary for IPv6
 916          * maskfull filters.
 917          */
 918         if (fs->type)
 919                 filter_id &= ~(0x3);
 920
 921         ret = is_filter_set(&adapter->tids, filter_id, fs->type);
 922         if (ret)
 923                 return -EBUSY;
 924
 925         iq = get_filter_steerq(dev, fs);
 926
 927         /*
 928          * IPv6 filters occupy four slots and must be aligned on four-slot
 929          * boundaries for T5. On T6, IPv6 filters occupy two-slots and
 930          * must be aligned on two-slot boundaries.
 931          *
 932          * IPv4 filters only occupy a single slot and have no alignment
 933          * requirements but writing a new IPv4 filter into the middle
 934          * of an existing IPv6 filter requires clearing the old IPv6
 935          * filter.
 936          */
 937         if (fs->type == FILTER_TYPE_IPV4) { /* IPv4 */
 938                 /*
 939                  * For T6, If our IPv4 filter isn't being written to a
 940                  * multiple of two filter index and there's an IPv6
 941                  * filter at the multiple of 2 base slot, then we need
 942                  * to delete that IPv6 filter ...
 943                  * For adapters below T6, IPv6 filter occupies 4 entries.
 944                  */
 945                 if (chip_ver < CHELSIO_T6)
 946                         fidx = filter_id & ~0x3;
 947                 else
 948                         fidx = filter_id & ~0x1;
 949
 950                 if (fidx != filter_id && adapter->tids.ftid_tab[fidx].fs.type) {
 951                         f = &adapter->tids.ftid_tab[fidx];
 952                         if (f->valid)
 953                                 return -EBUSY;
 954                 }
 955         } else { /* IPv6 */
 956                 unsigned int max_filter_id;
 957
 958                 if (chip_ver < CHELSIO_T6) {
 959                         /*
 960                          * Ensure that the IPv6 filter is aligned on a
 961                          * multiple of 4 boundary.
 962                          */
 963                         if (filter_id & 0x3)
 964                                 return -EINVAL;
 965
 966                         max_filter_id = filter_id + 4;
 967                 } else {
 968                         /*
 969                          * For T6, CLIP being enabled, IPv6 filter would occupy
 970                          * 2 entries.
 971                          */
 972                         if (filter_id & 0x1)
 973                                 return -EINVAL;
 974
 975                         max_filter_id = filter_id + 2;
 976                 }
 977
 978                 /*
 979                  * Check all except the base overlapping IPv4 filter
 980                  * slots.
 981                  */
 982                 for (fidx = filter_id + 1; fidx < max_filter_id; fidx++) {
 983                         f = &adapter->tids.ftid_tab[fidx];
 984                         if (f->valid)
 985                                 return -EBUSY;
 986                 }
 987         }
 988
 989         /*
 990          * Check to make sure that provided filter index is not
 991          * already in use by someone else
 992          */
 993         f = &adapter->tids.ftid_tab[filter_id];
 994         if (f->valid)
 995                 return -EBUSY;
 996
 997         fidx = adapter->tids.ftid_base + filter_id;
 998         fid_bit = filter_id;
 999         ret = cxgbe_set_ftid(&adapter->tids, fid_bit,
1000                              fs->type ? FILTER_TYPE_IPV6 : FILTER_TYPE_IPV4);
1001         if (ret)
1002                 return ret;
1003
1004         /*
1005          * Check to make sure the filter requested is writable ...
1006          */
1007         ret = writable_filter(f);
1008         if (ret) {
1009                 /* Clear the bits we have set above */
1010                 cxgbe_clear_ftid(&adapter->tids, fid_bit,
1011                                  fs->type ? FILTER_TYPE_IPV6 :
1012                                             FILTER_TYPE_IPV4);
1013                 return ret;
1014         }
1015
1016         /*
1017          * Allocate a clip table entry only if we have non-zero IPv6 address
1018          */
1019         if (chip_ver > CHELSIO_T5 && fs->type &&
1020             memcmp(fs->val.lip, bitoff, sizeof(bitoff))) {
1021                 f->clipt = cxgbe_clip_alloc(f->dev, (u32 *)&f->fs.val.lip);
1022                 if (!f->clipt)
1023                         goto free_tid;
1024         }
1025
1026         /*
1027          * Convert the filter specification into our internal format.
1028          * We copy the PF/VF specification into the Outer VLAN field
1029          * here so the rest of the code -- including the interface to
1030          * the firmware -- doesn't have to constantly do these checks.
1031          */
1032         f->fs = *fs;
1033         f->fs.iq = iq;
1034         f->dev = dev;
1035
1036         /*
1037          * Attempt to set the filter.  If we don't succeed, we clear
1038          * it and return the failure.
1039          */
1040         f->ctx = ctx;
1041         f->tid = fidx; /* Save the actual tid */
1042         ret = set_filter_wr(dev, filter_id);
1043         if (ret) {
1044                 fid_bit = f->tid - adapter->tids.ftid_base;
1045                 goto free_tid;
1046         }
1047
1048         return ret;
1049
1050 free_tid:
1051         cxgbe_clear_ftid(&adapter->tids, fid_bit,
1052                          fs->type ? FILTER_TYPE_IPV6 :
1053                                     FILTER_TYPE_IPV4);
1054         clear_filter(f);
1055         return ret;
1056 }
1057
1058 /**
1059  * Handle a Hash filter write reply.
1060  */
1061 void hash_filter_rpl(struct adapter *adap, const struct cpl_act_open_rpl *rpl)
1062 {
1063         struct tid_info *t = &adap->tids;
1064         struct filter_entry *f;
1065         struct filter_ctx *ctx = NULL;
1066         unsigned int tid = GET_TID(rpl);
1067         unsigned int ftid = G_TID_TID(G_AOPEN_ATID
1068                                       (be32_to_cpu(rpl->atid_status)));
1069         unsigned int status  = G_AOPEN_STATUS(be32_to_cpu(rpl->atid_status));
1070
1071         f = lookup_atid(t, ftid);
1072         if (!f) {
1073                 dev_warn(adap, "%s: could not find filter entry: %d\n",
1074                          __func__, ftid);
1075                 return;
1076         }
1077
1078         ctx = f->ctx;
1079         f->ctx = NULL;
1080
1081         switch (status) {
1082         case CPL_ERR_NONE: {
1083                 f->tid = tid;
1084                 f->pending = 0;  /* asynchronous setup completed */
1085                 f->valid = 1;
1086
1087                 cxgbe_insert_tid(t, f, f->tid, 0);
1088                 cxgbe_free_atid(t, ftid);
1089                 if (ctx) {
1090                         ctx->tid = f->tid;
1091                         ctx->result = 0;
1092                 }
1093                 if (f->fs.hitcnts)
1094                         set_tcb_field(adap, tid,
1095                                       W_TCB_TIMESTAMP,
1096                                       V_TCB_TIMESTAMP(M_TCB_TIMESTAMP) |
1097                                       V_TCB_T_RTT_TS_RECENT_AGE
1098                                               (M_TCB_T_RTT_TS_RECENT_AGE),
1099                                       V_TCB_TIMESTAMP(0ULL) |
1100                                       V_TCB_T_RTT_TS_RECENT_AGE(0ULL),
1101                                       1);
1102                 if (f->fs.newvlan == VLAN_INSERT ||
1103                     f->fs.newvlan == VLAN_REWRITE)
1104                         set_tcb_tflag(adap, tid, S_TF_CCTRL_RFR, 1, 1);
1105                 break;
1106         }
1107         default:
1108                 dev_warn(adap, "%s: filter creation failed with status = %u\n",
1109                          __func__, status);
1110
1111                 if (ctx) {
1112                         if (status == CPL_ERR_TCAM_FULL)
1113                                 ctx->result = -EAGAIN;
1114                         else
1115                                 ctx->result = -EINVAL;
1116                 }
1117
1118                 cxgbe_free_atid(t, ftid);
1119                 t4_os_free(f);
1120         }
1121
1122         if (ctx)
1123                 t4_complete(&ctx->completion);
1124 }
1125
1126 /**
1127  * Handle a LE-TCAM filter write/deletion reply.
1128  */
1129 void filter_rpl(struct adapter *adap, const struct cpl_set_tcb_rpl *rpl)
1130 {
1131         struct filter_entry *f = NULL;
1132         unsigned int tid = GET_TID(rpl);
1133         int idx, max_fidx = adap->tids.nftids;
1134
1135         /* Get the corresponding filter entry for this tid */
1136         if (adap->tids.ftid_tab) {
1137                 /* Check this in normal filter region */
1138                 idx = tid - adap->tids.ftid_base;
1139                 if (idx >= max_fidx)
1140                         return;
1141
1142                 f = &adap->tids.ftid_tab[idx];
1143                 if (f->tid != tid)
1144                         return;
1145         }
1146
1147         /* We found the filter entry for this tid */
1148         if (f) {
1149                 unsigned int ret = G_COOKIE(rpl->cookie);
1150                 struct filter_ctx *ctx;
1151
1152                 /*
1153                  * Pull off any filter operation context attached to the
1154                  * filter.
1155                  */
1156                 ctx = f->ctx;
1157                 f->ctx = NULL;
1158
1159                 if (ret == FW_FILTER_WR_FLT_ADDED) {
1160                         f->pending = 0;  /* asynchronous setup completed */
1161                         f->valid = 1;
1162                         if (ctx) {
1163                                 ctx->tid = f->tid;
1164                                 ctx->result = 0;
1165                         }
1166                 } else if (ret == FW_FILTER_WR_FLT_DELETED) {
1167                         /*
1168                          * Clear the filter when we get confirmation from the
1169                          * hardware that the filter has been deleted.
1170                          */
1171                         clear_filter(f);
1172                         if (ctx)
1173                                 ctx->result = 0;
1174                 } else {
1175                         /*
1176                          * Something went wrong.  Issue a warning about the
1177                          * problem and clear everything out.
1178                          */
1179                         dev_warn(adap, "filter %u setup failed with error %u\n",
1180                                  idx, ret);
1181                         clear_filter(f);
1182                         if (ctx)
1183                                 ctx->result = -EINVAL;
1184                 }
1185
1186                 if (ctx)
1187                         t4_complete(&ctx->completion);
1188         }
1189 }
1190
1191 /*
1192  * Retrieve the packet count for the specified filter.
1193  */
1194 int cxgbe_get_filter_count(struct adapter *adapter, unsigned int fidx,
1195                            u64 *c, int hash, bool get_byte)
1196 {
1197         struct filter_entry *f;
1198         unsigned int tcb_base, tcbaddr;
1199         int ret;
1200
1201         tcb_base = t4_read_reg(adapter, A_TP_CMM_TCB_BASE);
1202         if (is_hashfilter(adapter) && hash) {
1203                 if (fidx < adapter->tids.ntids) {
1204                         f = adapter->tids.tid_tab[fidx];
1205                         if (!f)
1206                                 return -EINVAL;
1207
1208                         if (is_t5(adapter->params.chip)) {
1209                                 *c = 0;
1210                                 return 0;
1211                         }
1212                         tcbaddr = tcb_base + (fidx * TCB_SIZE);
1213                         goto get_count;
1214                 } else {
1215                         return -ERANGE;
1216                 }
1217         } else {
1218                 if (fidx >= adapter->tids.nftids)
1219                         return -ERANGE;
1220
1221                 f = &adapter->tids.ftid_tab[fidx];
1222                 if (!f->valid)
1223                         return -EINVAL;
1224
1225                 tcbaddr = tcb_base + f->tid * TCB_SIZE;
1226         }
1227
1228         f = &adapter->tids.ftid_tab[fidx];
1229         if (!f->valid)
1230                 return -EINVAL;
1231
1232 get_count:
1233         if (is_t5(adapter->params.chip) || is_t6(adapter->params.chip)) {
1234                 /*
1235                  * For T5, the Filter Packet Hit Count is maintained as a
1236                  * 32-bit Big Endian value in the TCB field {timestamp}.
1237                  * Similar to the craziness above, instead of the filter hit
1238                  * count showing up at offset 20 ((W_TCB_TIMESTAMP == 5) *
1239                  * sizeof(u32)), it actually shows up at offset 24.  Whacky.
1240                  */
1241                 if (get_byte) {
1242                         unsigned int word_offset = 4;
1243                         __be64 be64_byte_count;
1244
1245                         t4_os_lock(&adapter->win0_lock);
1246                         ret = t4_memory_rw(adapter, MEMWIN_NIC, MEM_EDC0,
1247                                            tcbaddr +
1248                                            (word_offset * sizeof(__be32)),
1249                                            sizeof(be64_byte_count),
1250                                            &be64_byte_count,
1251                                            T4_MEMORY_READ);
1252                         t4_os_unlock(&adapter->win0_lock);
1253                         if (ret < 0)
1254                                 return ret;
1255                         *c = be64_to_cpu(be64_byte_count);
1256                 } else {
1257                         unsigned int word_offset = 6;
1258                         __be32 be32_count;
1259
1260                         t4_os_lock(&adapter->win0_lock);
1261                         ret = t4_memory_rw(adapter, MEMWIN_NIC, MEM_EDC0,
1262                                            tcbaddr +
1263                                            (word_offset * sizeof(__be32)),
1264                                            sizeof(be32_count), &be32_count,
1265                                            T4_MEMORY_READ);
1266                         t4_os_unlock(&adapter->win0_lock);
1267                         if (ret < 0)
1268                                 return ret;
1269                         *c = (u64)be32_to_cpu(be32_count);
1270                 }
1271         }
1272         return 0;
1273 }
1274
1275 /**
1276  * Handle a Hash filter delete reply.
1277  */
1278 void hash_del_filter_rpl(struct adapter *adap,
1279                          const struct cpl_abort_rpl_rss *rpl)
1280 {
1281         struct tid_info *t = &adap->tids;
1282         struct filter_entry *f;
1283         struct filter_ctx *ctx = NULL;
1284         unsigned int tid = GET_TID(rpl);
1285
1286         f = lookup_tid(t, tid);
1287         if (!f) {
1288                 dev_warn(adap, "%s: could not find filter entry: %u\n",
1289                          __func__, tid);
1290                 return;
1291         }
1292
1293         ctx = f->ctx;
1294         f->ctx = NULL;
1295
1296         f->valid = 0;
1297
1298         if (f->clipt)
1299                 cxgbe_clip_release(f->dev, f->clipt);
1300
1301         cxgbe_remove_tid(t, 0, tid, 0);
1302         t4_os_free(f);
1303
1304         if (ctx) {
1305                 ctx->result = 0;
1306                 t4_complete(&ctx->completion);
1307         }
1308 }