drivers/net/cxgbe/cxgbe_filter.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Chelsio Communications.
   3  * All rights reserved.
   4  */
   5
   6 #include "common.h"
   7 #include "t4_regs.h"
   8 #include "cxgbe_filter.h"
   9 #include "clip_tbl.h"
  10
  11 /**
  12  * Initialize Hash Filters
  13  */
  14 int init_hash_filter(struct adapter *adap)
  15 {
  16         unsigned int n_user_filters;
  17         unsigned int user_filter_perc;
  18         int ret;
  19         u32 params[7], val[7];
  20
  21 #define FW_PARAM_DEV(param) \
  22         (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
  23         V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
  24
  25 #define FW_PARAM_PFVF(param) \
  26         (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
  27         V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param) |  \
  28         V_FW_PARAMS_PARAM_Y(0) | \
  29         V_FW_PARAMS_PARAM_Z(0))
  30
  31         params[0] = FW_PARAM_DEV(NTID);
  32         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
  33                               params, val);
  34         if (ret < 0)
  35                 return ret;
  36         adap->tids.ntids = val[0];
  37         adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
  38
  39         user_filter_perc = 100;
  40         n_user_filters = mult_frac(adap->tids.nftids,
  41                                    user_filter_perc,
  42                                    100);
  43
  44         adap->tids.nftids = n_user_filters;
  45         adap->params.hash_filter = 1;
  46         return 0;
  47 }
  48
  49 /**
  50  * Validate if the requested filter specification can be set by checking
  51  * if the requested features have been enabled
  52  */
  53 int validate_filter(struct adapter *adapter, struct ch_filter_specification *fs)
  54 {
  55         u32 fconf;
  56
  57         /*
  58          * Check for unconfigured fields being used.
  59          */
  60         fconf = adapter->params.tp.vlan_pri_map;
  61
  62 #define S(_field) \
  63         (fs->val._field || fs->mask._field)
  64 #define U(_mask, _field) \
  65         (!(fconf & (_mask)) && S(_field))
  66
  67         if (U(F_ETHERTYPE, ethtype) || U(F_PROTOCOL, proto))
  68                 return -EOPNOTSUPP;
  69
  70 #undef S
  71 #undef U
  72         return 0;
  73 }
  74
  75 /**
  76  * Get the queue to which the traffic must be steered to.
  77  */
  78 static unsigned int get_filter_steerq(struct rte_eth_dev *dev,
  79                                       struct ch_filter_specification *fs)
  80 {
  81         struct port_info *pi = ethdev2pinfo(dev);
  82         struct adapter *adapter = pi->adapter;
  83         unsigned int iq;
  84
  85         /*
  86          * If the user has requested steering matching Ingress Packets
  87          * to a specific Queue Set, we need to make sure it's in range
  88          * for the port and map that into the Absolute Queue ID of the
  89          * Queue Set's Response Queue.
  90          */
  91         if (!fs->dirsteer) {
  92                 iq = 0;
  93         } else {
  94                 /*
  95                  * If the iq id is greater than the number of qsets,
  96                  * then assume it is an absolute qid.
  97                  */
  98                 if (fs->iq < pi->n_rx_qsets)
  99                         iq = adapter->sge.ethrxq[pi->first_qset +
 100                                                  fs->iq].rspq.abs_id;
 101                 else
 102                         iq = fs->iq;
 103         }
 104
 105         return iq;
 106 }
 107
 108 /* Return an error number if the indicated filter isn't writable ... */
 109 int writable_filter(struct filter_entry *f)
 110 {
 111         if (f->locked)
 112                 return -EPERM;
 113         if (f->pending)
 114                 return -EBUSY;
 115
 116         return 0;
 117 }
 118
 119 /**
 120  * Check if entry already filled.
 121  */
 122 bool is_filter_set(struct tid_info *t, int fidx, int family)
 123 {
 124         bool result = FALSE;
 125         int i, max;
 126
 127         /* IPv6 requires four slots and IPv4 requires only 1 slot.
 128          * Ensure, there's enough slots available.
 129          */
 130         max = family == FILTER_TYPE_IPV6 ? fidx + 3 : fidx;
 131
 132         t4_os_lock(&t->ftid_lock);
 133         for (i = fidx; i <= max; i++) {
 134                 if (rte_bitmap_get(t->ftid_bmap, i)) {
 135                         result = TRUE;
 136                         break;
 137                 }
 138         }
 139         t4_os_unlock(&t->ftid_lock);
 140         return result;
 141 }
 142
 143 /**
 144  * Allocate a available free entry
 145  */
 146 int cxgbe_alloc_ftid(struct adapter *adap, unsigned int family)
 147 {
 148         struct tid_info *t = &adap->tids;
 149         int pos;
 150         int size = t->nftids;
 151
 152         t4_os_lock(&t->ftid_lock);
 153         if (family == FILTER_TYPE_IPV6)
 154                 pos = cxgbe_bitmap_find_free_region(t->ftid_bmap, size, 4);
 155         else
 156                 pos = cxgbe_find_first_zero_bit(t->ftid_bmap, size);
 157         t4_os_unlock(&t->ftid_lock);
 158
 159         return pos < size ? pos : -1;
 160 }
 161
 162 /**
 163  * Clear a filter and release any of its resources that we own.  This also
 164  * clears the filter's "pending" status.
 165  */
 166 void clear_filter(struct filter_entry *f)
 167 {
 168         if (f->clipt)
 169                 cxgbe_clip_release(f->dev, f->clipt);
 170
 171         /*
 172          * The zeroing of the filter rule below clears the filter valid,
 173          * pending, locked flags etc. so it's all we need for
 174          * this operation.
 175          */
 176         memset(f, 0, sizeof(*f));
 177 }
 178
 179 /**
 180  * t4_mk_filtdelwr - create a delete filter WR
 181  * @ftid: the filter ID
 182  * @wr: the filter work request to populate
 183  * @qid: ingress queue to receive the delete notification
 184  *
 185  * Creates a filter work request to delete the supplied filter.  If @qid is
 186  * negative the delete notification is suppressed.
 187  */
 188 static void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
 189 {
 190         memset(wr, 0, sizeof(*wr));
 191         wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR));
 192         wr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*wr) / 16));
 193         wr->tid_to_iq = cpu_to_be32(V_FW_FILTER_WR_TID(ftid) |
 194                                     V_FW_FILTER_WR_NOREPLY(qid < 0));
 195         wr->del_filter_to_l2tix = cpu_to_be32(F_FW_FILTER_WR_DEL_FILTER);
 196         if (qid >= 0)
 197                 wr->rx_chan_rx_rpl_iq =
 198                                 cpu_to_be16(V_FW_FILTER_WR_RX_RPL_IQ(qid));
 199 }
 200
 201 /**
 202  * Create FW work request to delete the filter at a specified index
 203  */
 204 static int del_filter_wr(struct rte_eth_dev *dev, unsigned int fidx)
 205 {
 206         struct adapter *adapter = ethdev2adap(dev);
 207         struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
 208         struct rte_mbuf *mbuf;
 209         struct fw_filter_wr *fwr;
 210         struct sge_ctrl_txq *ctrlq;
 211         unsigned int port_id = ethdev2pinfo(dev)->port_id;
 212
 213         ctrlq = &adapter->sge.ctrlq[port_id];
 214         mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
 215         if (!mbuf)
 216                 return -ENOMEM;
 217
 218         mbuf->data_len = sizeof(*fwr);
 219         mbuf->pkt_len = mbuf->data_len;
 220
 221         fwr = rte_pktmbuf_mtod(mbuf, struct fw_filter_wr *);
 222         t4_mk_filtdelwr(f->tid, fwr, adapter->sge.fw_evtq.abs_id);
 223
 224         /*
 225          * Mark the filter as "pending" and ship off the Filter Work Request.
 226          * When we get the Work Request Reply we'll clear the pending status.
 227          */
 228         f->pending = 1;
 229         t4_mgmt_tx(ctrlq, mbuf);
 230         return 0;
 231 }
 232
 233 int set_filter_wr(struct rte_eth_dev *dev, unsigned int fidx)
 234 {
 235         struct adapter *adapter = ethdev2adap(dev);
 236         struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
 237         struct rte_mbuf *mbuf;
 238         struct fw_filter_wr *fwr;
 239         struct sge_ctrl_txq *ctrlq;
 240         unsigned int port_id = ethdev2pinfo(dev)->port_id;
 241         int ret;
 242
 243         ctrlq = &adapter->sge.ctrlq[port_id];
 244         mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
 245         if (!mbuf) {
 246                 ret = -ENOMEM;
 247                 goto out;
 248         }
 249
 250         mbuf->data_len = sizeof(*fwr);
 251         mbuf->pkt_len = mbuf->data_len;
 252
 253         fwr = rte_pktmbuf_mtod(mbuf, struct fw_filter_wr *);
 254         memset(fwr, 0, sizeof(*fwr));
 255
 256         /*
 257          * Construct the work request to set the filter.
 258          */
 259         fwr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR));
 260         fwr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*fwr) / 16));
 261         fwr->tid_to_iq =
 262                 cpu_to_be32(V_FW_FILTER_WR_TID(f->tid) |
 263                             V_FW_FILTER_WR_RQTYPE(f->fs.type) |
 264                             V_FW_FILTER_WR_NOREPLY(0) |
 265                             V_FW_FILTER_WR_IQ(f->fs.iq));
 266         fwr->del_filter_to_l2tix =
 267                 cpu_to_be32(V_FW_FILTER_WR_DROP(f->fs.action == FILTER_DROP) |
 268                             V_FW_FILTER_WR_DIRSTEER(f->fs.dirsteer) |
 269                             V_FW_FILTER_WR_HITCNTS(f->fs.hitcnts) |
 270                             V_FW_FILTER_WR_PRIO(f->fs.prio));
 271         fwr->ethtype = cpu_to_be16(f->fs.val.ethtype);
 272         fwr->ethtypem = cpu_to_be16(f->fs.mask.ethtype);
 273         fwr->smac_sel = 0;
 274         fwr->rx_chan_rx_rpl_iq =
 275                 cpu_to_be16(V_FW_FILTER_WR_RX_CHAN(0) |
 276                             V_FW_FILTER_WR_RX_RPL_IQ(adapter->sge.fw_evtq.abs_id
 277                                                      ));
 278         fwr->ptcl = f->fs.val.proto;
 279         fwr->ptclm = f->fs.mask.proto;
 280         rte_memcpy(fwr->lip, f->fs.val.lip, sizeof(fwr->lip));
 281         rte_memcpy(fwr->lipm, f->fs.mask.lip, sizeof(fwr->lipm));
 282         rte_memcpy(fwr->fip, f->fs.val.fip, sizeof(fwr->fip));
 283         rte_memcpy(fwr->fipm, f->fs.mask.fip, sizeof(fwr->fipm));
 284         fwr->lp = cpu_to_be16(f->fs.val.lport);
 285         fwr->lpm = cpu_to_be16(f->fs.mask.lport);
 286         fwr->fp = cpu_to_be16(f->fs.val.fport);
 287         fwr->fpm = cpu_to_be16(f->fs.mask.fport);
 288
 289         /*
 290          * Mark the filter as "pending" and ship off the Filter Work Request.
 291          * When we get the Work Request Reply we'll clear the pending status.
 292          */
 293         f->pending = 1;
 294         t4_mgmt_tx(ctrlq, mbuf);
 295         return 0;
 296
 297 out:
 298         return ret;
 299 }
 300
 301 /**
 302  * Set the corresponding entry in the bitmap. 4 slots are
 303  * marked for IPv6, whereas only 1 slot is marked for IPv4.
 304  */
 305 static int cxgbe_set_ftid(struct tid_info *t, int fidx, int family)
 306 {
 307         t4_os_lock(&t->ftid_lock);
 308         if (rte_bitmap_get(t->ftid_bmap, fidx)) {
 309                 t4_os_unlock(&t->ftid_lock);
 310                 return -EBUSY;
 311         }
 312
 313         if (family == FILTER_TYPE_IPV4) {
 314                 rte_bitmap_set(t->ftid_bmap, fidx);
 315         } else {
 316                 rte_bitmap_set(t->ftid_bmap, fidx);
 317                 rte_bitmap_set(t->ftid_bmap, fidx + 1);
 318                 rte_bitmap_set(t->ftid_bmap, fidx + 2);
 319                 rte_bitmap_set(t->ftid_bmap, fidx + 3);
 320         }
 321         t4_os_unlock(&t->ftid_lock);
 322         return 0;
 323 }
 324
 325 /**
 326  * Clear the corresponding entry in the bitmap. 4 slots are
 327  * cleared for IPv6, whereas only 1 slot is cleared for IPv4.
 328  */
 329 static void cxgbe_clear_ftid(struct tid_info *t, int fidx, int family)
 330 {
 331         t4_os_lock(&t->ftid_lock);
 332         if (family == FILTER_TYPE_IPV4) {
 333                 rte_bitmap_clear(t->ftid_bmap, fidx);
 334         } else {
 335                 rte_bitmap_clear(t->ftid_bmap, fidx);
 336                 rte_bitmap_clear(t->ftid_bmap, fidx + 1);
 337                 rte_bitmap_clear(t->ftid_bmap, fidx + 2);
 338                 rte_bitmap_clear(t->ftid_bmap, fidx + 3);
 339         }
 340         t4_os_unlock(&t->ftid_lock);
 341 }
 342
 343 /**
 344  * Check a delete filter request for validity and send it to the hardware.
 345  * Return 0 on success, an error number otherwise.  We attach any provided
 346  * filter operation context to the internal filter specification in order to
 347  * facilitate signaling completion of the operation.
 348  */
 349 int cxgbe_del_filter(struct rte_eth_dev *dev, unsigned int filter_id,
 350                      struct ch_filter_specification *fs,
 351                      struct filter_ctx *ctx)
 352 {
 353         struct port_info *pi = (struct port_info *)(dev->data->dev_private);
 354         struct adapter *adapter = pi->adapter;
 355         struct filter_entry *f;
 356         unsigned int chip_ver;
 357         int ret;
 358
 359         if (filter_id >= adapter->tids.nftids)
 360                 return -ERANGE;
 361
 362         chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
 363
 364         ret = is_filter_set(&adapter->tids, filter_id, fs->type);
 365         if (!ret) {
 366                 dev_warn(adap, "%s: could not find filter entry: %u\n",
 367                          __func__, filter_id);
 368                 return -EINVAL;
 369         }
 370
 371         /*
 372          * Ensure filter id is aligned on the 2 slot boundary for T6,
 373          * and 4 slot boundary for cards below T6.
 374          */
 375         if (fs->type) {
 376                 if (chip_ver < CHELSIO_T6)
 377                         filter_id &= ~(0x3);
 378                 else
 379                         filter_id &= ~(0x1);
 380         }
 381
 382         f = &adapter->tids.ftid_tab[filter_id];
 383         ret = writable_filter(f);
 384         if (ret)
 385                 return ret;
 386
 387         if (f->valid) {
 388                 f->ctx = ctx;
 389                 cxgbe_clear_ftid(&adapter->tids,
 390                                  f->tid - adapter->tids.ftid_base,
 391                                  f->fs.type ? FILTER_TYPE_IPV6 :
 392                                               FILTER_TYPE_IPV4);
 393                 return del_filter_wr(dev, filter_id);
 394         }
 395
 396         /*
 397          * If the caller has passed in a Completion Context then we need to
 398          * mark it as a successful completion so they don't stall waiting
 399          * for it.
 400          */
 401         if (ctx) {
 402                 ctx->result = 0;
 403                 t4_complete(&ctx->completion);
 404         }
 405
 406         return 0;
 407 }
 408
 409 /**
 410  * Check a Chelsio Filter Request for validity, convert it into our internal
 411  * format and send it to the hardware.  Return 0 on success, an error number
 412  * otherwise.  We attach any provided filter operation context to the internal
 413  * filter specification in order to facilitate signaling completion of the
 414  * operation.
 415  */
 416 int cxgbe_set_filter(struct rte_eth_dev *dev, unsigned int filter_id,
 417                      struct ch_filter_specification *fs,
 418                      struct filter_ctx *ctx)
 419 {
 420         struct port_info *pi = ethdev2pinfo(dev);
 421         struct adapter *adapter = pi->adapter;
 422         unsigned int fidx, iq, fid_bit = 0;
 423         struct filter_entry *f;
 424         unsigned int chip_ver;
 425         uint8_t bitoff[16] = {0};
 426         int ret;
 427
 428         if (filter_id >= adapter->tids.nftids)
 429                 return -ERANGE;
 430
 431         chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
 432
 433         ret = validate_filter(adapter, fs);
 434         if (ret)
 435                 return ret;
 436
 437         /*
 438          * Ensure filter id is aligned on the 4 slot boundary for IPv6
 439          * maskfull filters.
 440          */
 441         if (fs->type)
 442                 filter_id &= ~(0x3);
 443
 444         ret = is_filter_set(&adapter->tids, filter_id, fs->type);
 445         if (ret)
 446                 return -EBUSY;
 447
 448         iq = get_filter_steerq(dev, fs);
 449
 450         /*
 451          * IPv6 filters occupy four slots and must be aligned on four-slot
 452          * boundaries for T5. On T6, IPv6 filters occupy two-slots and
 453          * must be aligned on two-slot boundaries.
 454          *
 455          * IPv4 filters only occupy a single slot and have no alignment
 456          * requirements but writing a new IPv4 filter into the middle
 457          * of an existing IPv6 filter requires clearing the old IPv6
 458          * filter.
 459          */
 460         if (fs->type == FILTER_TYPE_IPV4) { /* IPv4 */
 461                 /*
 462                  * For T6, If our IPv4 filter isn't being written to a
 463                  * multiple of two filter index and there's an IPv6
 464                  * filter at the multiple of 2 base slot, then we need
 465                  * to delete that IPv6 filter ...
 466                  * For adapters below T6, IPv6 filter occupies 4 entries.
 467                  */
 468                 if (chip_ver < CHELSIO_T6)
 469                         fidx = filter_id & ~0x3;
 470                 else
 471                         fidx = filter_id & ~0x1;
 472
 473                 if (fidx != filter_id && adapter->tids.ftid_tab[fidx].fs.type) {
 474                         f = &adapter->tids.ftid_tab[fidx];
 475                         if (f->valid)
 476                                 return -EBUSY;
 477                 }
 478         } else { /* IPv6 */
 479                 unsigned int max_filter_id;
 480
 481                 if (chip_ver < CHELSIO_T6) {
 482                         /*
 483                          * Ensure that the IPv6 filter is aligned on a
 484                          * multiple of 4 boundary.
 485                          */
 486                         if (filter_id & 0x3)
 487                                 return -EINVAL;
 488
 489                         max_filter_id = filter_id + 4;
 490                 } else {
 491                         /*
 492                          * For T6, CLIP being enabled, IPv6 filter would occupy
 493                          * 2 entries.
 494                          */
 495                         if (filter_id & 0x1)
 496                                 return -EINVAL;
 497
 498                         max_filter_id = filter_id + 2;
 499                 }
 500
 501                 /*
 502                  * Check all except the base overlapping IPv4 filter
 503                  * slots.
 504                  */
 505                 for (fidx = filter_id + 1; fidx < max_filter_id; fidx++) {
 506                         f = &adapter->tids.ftid_tab[fidx];
 507                         if (f->valid)
 508                                 return -EBUSY;
 509                 }
 510         }
 511
 512         /*
 513          * Check to make sure that provided filter index is not
 514          * already in use by someone else
 515          */
 516         f = &adapter->tids.ftid_tab[filter_id];
 517         if (f->valid)
 518                 return -EBUSY;
 519
 520         fidx = adapter->tids.ftid_base + filter_id;
 521         fid_bit = filter_id;
 522         ret = cxgbe_set_ftid(&adapter->tids, fid_bit,
 523                              fs->type ? FILTER_TYPE_IPV6 : FILTER_TYPE_IPV4);
 524         if (ret)
 525                 return ret;
 526
 527         /*
 528          * Check to make sure the filter requested is writable ...
 529          */
 530         ret = writable_filter(f);
 531         if (ret) {
 532                 /* Clear the bits we have set above */
 533                 cxgbe_clear_ftid(&adapter->tids, fid_bit,
 534                                  fs->type ? FILTER_TYPE_IPV6 :
 535                                             FILTER_TYPE_IPV4);
 536                 return ret;
 537         }
 538
 539         /*
 540          * Allocate a clip table entry only if we have non-zero IPv6 address
 541          */
 542         if (chip_ver > CHELSIO_T5 && fs->type &&
 543             memcmp(fs->val.lip, bitoff, sizeof(bitoff))) {
 544                 f->clipt = cxgbe_clip_alloc(f->dev, (u32 *)&f->fs.val.lip);
 545                 if (!f->clipt)
 546                         goto free_tid;
 547         }
 548
 549         /*
 550          * Convert the filter specification into our internal format.
 551          * We copy the PF/VF specification into the Outer VLAN field
 552          * here so the rest of the code -- including the interface to
 553          * the firmware -- doesn't have to constantly do these checks.
 554          */
 555         f->fs = *fs;
 556         f->fs.iq = iq;
 557         f->dev = dev;
 558
 559         /*
 560          * Attempt to set the filter.  If we don't succeed, we clear
 561          * it and return the failure.
 562          */
 563         f->ctx = ctx;
 564         f->tid = fidx; /* Save the actual tid */
 565         ret = set_filter_wr(dev, filter_id);
 566         if (ret) {
 567                 fid_bit = f->tid - adapter->tids.ftid_base;
 568                 goto free_tid;
 569         }
 570
 571         return ret;
 572
 573 free_tid:
 574         cxgbe_clear_ftid(&adapter->tids, fid_bit,
 575                          fs->type ? FILTER_TYPE_IPV6 :
 576                                     FILTER_TYPE_IPV4);
 577         clear_filter(f);
 578         return ret;
 579 }
 580
 581 /**
 582  * Handle a LE-TCAM filter write/deletion reply.
 583  */
 584 void filter_rpl(struct adapter *adap, const struct cpl_set_tcb_rpl *rpl)
 585 {
 586         struct filter_entry *f = NULL;
 587         unsigned int tid = GET_TID(rpl);
 588         int idx, max_fidx = adap->tids.nftids;
 589
 590         /* Get the corresponding filter entry for this tid */
 591         if (adap->tids.ftid_tab) {
 592                 /* Check this in normal filter region */
 593                 idx = tid - adap->tids.ftid_base;
 594                 if (idx >= max_fidx)
 595                         return;
 596
 597                 f = &adap->tids.ftid_tab[idx];
 598                 if (f->tid != tid)
 599                         return;
 600         }
 601
 602         /* We found the filter entry for this tid */
 603         if (f) {
 604                 unsigned int ret = G_COOKIE(rpl->cookie);
 605                 struct filter_ctx *ctx;
 606
 607                 /*
 608                  * Pull off any filter operation context attached to the
 609                  * filter.
 610                  */
 611                 ctx = f->ctx;
 612                 f->ctx = NULL;
 613
 614                 if (ret == FW_FILTER_WR_FLT_ADDED) {
 615                         f->pending = 0;  /* asynchronous setup completed */
 616                         f->valid = 1;
 617                         if (ctx) {
 618                                 ctx->tid = f->tid;
 619                                 ctx->result = 0;
 620                         }
 621                 } else if (ret == FW_FILTER_WR_FLT_DELETED) {
 622                         /*
 623                          * Clear the filter when we get confirmation from the
 624                          * hardware that the filter has been deleted.
 625                          */
 626                         clear_filter(f);
 627                         if (ctx)
 628                                 ctx->result = 0;
 629                 } else {
 630                         /*
 631                          * Something went wrong.  Issue a warning about the
 632                          * problem and clear everything out.
 633                          */
 634                         dev_warn(adap, "filter %u setup failed with error %u\n",
 635                                  idx, ret);
 636                         clear_filter(f);
 637                         if (ctx)
 638                                 ctx->result = -EINVAL;
 639                 }
 640
 641                 if (ctx)
 642                         t4_complete(&ctx->completion);
 643         }
 644 }
 645
 646 /*
 647  * Retrieve the packet count for the specified filter.
 648  */
 649 int cxgbe_get_filter_count(struct adapter *adapter, unsigned int fidx,
 650                            u64 *c, bool get_byte)
 651 {
 652         struct filter_entry *f;
 653         unsigned int tcb_base, tcbaddr;
 654         int ret;
 655
 656         tcb_base = t4_read_reg(adapter, A_TP_CMM_TCB_BASE);
 657         if (fidx >= adapter->tids.nftids)
 658                 return -ERANGE;
 659
 660         f = &adapter->tids.ftid_tab[fidx];
 661         if (!f->valid)
 662                 return -EINVAL;
 663
 664         tcbaddr = tcb_base + f->tid * TCB_SIZE;
 665
 666         if (is_t5(adapter->params.chip) || is_t6(adapter->params.chip)) {
 667                 /*
 668                  * For T5, the Filter Packet Hit Count is maintained as a
 669                  * 32-bit Big Endian value in the TCB field {timestamp}.
 670                  * Similar to the craziness above, instead of the filter hit
 671                  * count showing up at offset 20 ((W_TCB_TIMESTAMP == 5) *
 672                  * sizeof(u32)), it actually shows up at offset 24.  Whacky.
 673                  */
 674                 if (get_byte) {
 675                         unsigned int word_offset = 4;
 676                         __be64 be64_byte_count;
 677
 678                         t4_os_lock(&adapter->win0_lock);
 679                         ret = t4_memory_rw(adapter, MEMWIN_NIC, MEM_EDC0,
 680                                            tcbaddr +
 681                                            (word_offset * sizeof(__be32)),
 682                                            sizeof(be64_byte_count),
 683                                            &be64_byte_count,
 684                                            T4_MEMORY_READ);
 685                         t4_os_unlock(&adapter->win0_lock);
 686                         if (ret < 0)
 687                                 return ret;
 688                         *c = be64_to_cpu(be64_byte_count);
 689                 } else {
 690                         unsigned int word_offset = 6;
 691                         __be32 be32_count;
 692
 693                         t4_os_lock(&adapter->win0_lock);
 694                         ret = t4_memory_rw(adapter, MEMWIN_NIC, MEM_EDC0,
 695                                            tcbaddr +
 696                                            (word_offset * sizeof(__be32)),
 697                                            sizeof(be32_count), &be32_count,
 698                                            T4_MEMORY_READ);
 699                         t4_os_unlock(&adapter->win0_lock);
 700                         if (ret < 0)
 701                                 return ret;
 702                         *c = (u64)be32_to_cpu(be32_count);
 703                 }
 704         }
 705         return 0;
 706 }