drivers/net/cxgbe/cxgbe_main.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2014-2017 Chelsio Communications.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Chelsio Communications nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43
  44 #include <rte_byteorder.h>
  45 #include <rte_common.h>
  46 #include <rte_cycles.h>
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_tailq.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev_driver.h>
  59 #include <rte_ethdev_pci.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "common.h"
  65 #include "t4_regs.h"
  66 #include "t4_msg.h"
  67 #include "cxgbe.h"
  68
  69 /*
  70  * Response queue handler for the FW event queue.
  71  */
  72 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
  73                           __rte_unused const struct pkt_gl *gl)
  74 {
  75         u8 opcode = ((const struct rss_header *)rsp)->opcode;
  76
  77         rsp++;                                          /* skip RSS header */
  78
  79         /*
  80          * FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
  81          */
  82         if (unlikely(opcode == CPL_FW4_MSG &&
  83                      ((const struct cpl_fw4_msg *)rsp)->type ==
  84                       FW_TYPE_RSSCPL)) {
  85                 rsp++;
  86                 opcode = ((const struct rss_header *)rsp)->opcode;
  87                 rsp++;
  88                 if (opcode != CPL_SGE_EGR_UPDATE) {
  89                         dev_err(q->adapter, "unexpected FW4/CPL %#x on FW event queue\n",
  90                                 opcode);
  91                         goto out;
  92                 }
  93         }
  94
  95         if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
  96                 /* do nothing */
  97         } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
  98                 const struct cpl_fw6_msg *msg = (const void *)rsp;
  99
 100                 t4_handle_fw_rpl(q->adapter, msg->data);
 101         } else {
 102                 dev_err(adapter, "unexpected CPL %#x on FW event queue\n",
 103                         opcode);
 104         }
 105 out:
 106         return 0;
 107 }
 108
 109 int setup_sge_fwevtq(struct adapter *adapter)
 110 {
 111         struct sge *s = &adapter->sge;
 112         int err = 0;
 113         int msi_idx = 0;
 114
 115         err = t4_sge_alloc_rxq(adapter, &s->fw_evtq, true, adapter->eth_dev,
 116                                msi_idx, NULL, fwevtq_handler, -1, NULL, 0,
 117                                rte_socket_id());
 118         return err;
 119 }
 120
 121 static int closest_timer(const struct sge *s, int time)
 122 {
 123         unsigned int i, match = 0;
 124         int delta, min_delta = INT_MAX;
 125
 126         for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
 127                 delta = time - s->timer_val[i];
 128                 if (delta < 0)
 129                         delta = -delta;
 130                 if (delta < min_delta) {
 131                         min_delta = delta;
 132                         match = i;
 133                 }
 134         }
 135         return match;
 136 }
 137
 138 static int closest_thres(const struct sge *s, int thres)
 139 {
 140         unsigned int i, match = 0;
 141         int delta, min_delta = INT_MAX;
 142
 143         for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
 144                 delta = thres - s->counter_val[i];
 145                 if (delta < 0)
 146                         delta = -delta;
 147                 if (delta < min_delta) {
 148                         min_delta = delta;
 149                         match = i;
 150                 }
 151         }
 152         return match;
 153 }
 154
 155 /**
 156  * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters
 157  * @q: the Rx queue
 158  * @us: the hold-off time in us, or 0 to disable timer
 159  * @cnt: the hold-off packet count, or 0 to disable counter
 160  *
 161  * Sets an Rx queue's interrupt hold-off time and packet count.  At least
 162  * one of the two needs to be enabled for the queue to generate interrupts.
 163  */
 164 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
 165                                unsigned int cnt)
 166 {
 167         struct adapter *adap = q->adapter;
 168         unsigned int timer_val;
 169
 170         if (cnt) {
 171                 int err;
 172                 u32 v, new_idx;
 173
 174                 new_idx = closest_thres(&adap->sge, cnt);
 175                 if (q->desc && q->pktcnt_idx != new_idx) {
 176                         /* the queue has already been created, update it */
 177                         v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
 178                             V_FW_PARAMS_PARAM_X(
 179                             FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
 180                             V_FW_PARAMS_PARAM_YZ(q->cntxt_id);
 181                         err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
 182                                             &v, &new_idx);
 183                         if (err)
 184                                 return err;
 185                 }
 186                 q->pktcnt_idx = new_idx;
 187         }
 188
 189         timer_val = (us == 0) ? X_TIMERREG_RESTART_COUNTER :
 190                                 closest_timer(&adap->sge, us);
 191
 192         if ((us | cnt) == 0)
 193                 q->intr_params = V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX);
 194         else
 195                 q->intr_params = V_QINTR_TIMER_IDX(timer_val) |
 196                                  V_QINTR_CNT_EN(cnt > 0);
 197         return 0;
 198 }
 199
 200 static inline bool is_x_1g_port(const struct link_config *lc)
 201 {
 202         return (lc->pcaps & FW_PORT_CAP32_SPEED_1G) != 0;
 203 }
 204
 205 static inline bool is_x_10g_port(const struct link_config *lc)
 206 {
 207         unsigned int speeds, high_speeds;
 208
 209         speeds = V_FW_PORT_CAP32_SPEED(G_FW_PORT_CAP32_SPEED(lc->pcaps));
 210         high_speeds = speeds &
 211                       ~(FW_PORT_CAP32_SPEED_100M | FW_PORT_CAP32_SPEED_1G);
 212
 213         return high_speeds != 0;
 214 }
 215
 216 inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
 217                       unsigned int us, unsigned int cnt,
 218                       unsigned int size, unsigned int iqe_size)
 219 {
 220         q->adapter = adap;
 221         cxgb4_set_rspq_intr_params(q, us, cnt);
 222         q->iqe_len = iqe_size;
 223         q->size = size;
 224 }
 225
 226 int cfg_queue_count(struct rte_eth_dev *eth_dev)
 227 {
 228         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 229         struct adapter *adap = pi->adapter;
 230         struct sge *s = &adap->sge;
 231         unsigned int max_queues = s->max_ethqsets / adap->params.nports;
 232
 233         if ((eth_dev->data->nb_rx_queues < 1) ||
 234             (eth_dev->data->nb_tx_queues < 1))
 235                 return -EINVAL;
 236
 237         if ((eth_dev->data->nb_rx_queues > max_queues) ||
 238             (eth_dev->data->nb_tx_queues > max_queues))
 239                 return -EINVAL;
 240
 241         if (eth_dev->data->nb_rx_queues > pi->rss_size)
 242                 return -EINVAL;
 243
 244         /* We must configure RSS, since config has changed*/
 245         pi->flags &= ~PORT_RSS_DONE;
 246
 247         pi->n_rx_qsets = eth_dev->data->nb_rx_queues;
 248         pi->n_tx_qsets = eth_dev->data->nb_tx_queues;
 249
 250         return 0;
 251 }
 252
 253 void cfg_queues(struct rte_eth_dev *eth_dev)
 254 {
 255         struct rte_config *config = rte_eal_get_configuration();
 256         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 257         struct adapter *adap = pi->adapter;
 258         struct sge *s = &adap->sge;
 259         unsigned int i, nb_ports = 0, qidx = 0;
 260         unsigned int q_per_port = 0;
 261
 262         if (!(adap->flags & CFG_QUEUES)) {
 263                 for_each_port(adap, i) {
 264                         struct port_info *tpi = adap2pinfo(adap, i);
 265
 266                         nb_ports += (is_x_10g_port(&tpi->link_cfg)) ||
 267                                      is_x_1g_port(&tpi->link_cfg) ? 1 : 0;
 268                 }
 269
 270                 /*
 271                  * We default up to # of cores queues per 1G/10G port.
 272                  */
 273                 if (nb_ports)
 274                         q_per_port = (MAX_ETH_QSETS -
 275                                      (adap->params.nports - nb_ports)) /
 276                                      nb_ports;
 277
 278                 if (q_per_port > config->lcore_count)
 279                         q_per_port = config->lcore_count;
 280
 281                 for_each_port(adap, i) {
 282                         struct port_info *pi = adap2pinfo(adap, i);
 283
 284                         pi->first_qset = qidx;
 285
 286                         /* Initially n_rx_qsets == n_tx_qsets */
 287                         pi->n_rx_qsets = (is_x_10g_port(&pi->link_cfg) ||
 288                                           is_x_1g_port(&pi->link_cfg)) ?
 289                                           q_per_port : 1;
 290                         pi->n_tx_qsets = pi->n_rx_qsets;
 291
 292                         if (pi->n_rx_qsets > pi->rss_size)
 293                                 pi->n_rx_qsets = pi->rss_size;
 294
 295                         qidx += pi->n_rx_qsets;
 296                 }
 297
 298                 s->max_ethqsets = qidx;
 299
 300                 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
 301                         struct sge_eth_rxq *r = &s->ethrxq[i];
 302
 303                         init_rspq(adap, &r->rspq, 5, 32, 1024, 64);
 304                         r->usembufs = 1;
 305                         r->fl.size = (r->usembufs ? 1024 : 72);
 306                 }
 307
 308                 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
 309                         s->ethtxq[i].q.size = 1024;
 310
 311                 init_rspq(adap, &adap->sge.fw_evtq, 0, 0, 1024, 64);
 312                 adap->flags |= CFG_QUEUES;
 313         }
 314 }
 315
 316 void cxgbe_stats_get(struct port_info *pi, struct port_stats *stats)
 317 {
 318         t4_get_port_stats_offset(pi->adapter, pi->tx_chan, stats,
 319                                  &pi->stats_base);
 320 }
 321
 322 void cxgbe_stats_reset(struct port_info *pi)
 323 {
 324         t4_clr_port_stats(pi->adapter, pi->tx_chan);
 325 }
 326
 327 static void setup_memwin(struct adapter *adap)
 328 {
 329         u32 mem_win0_base;
 330
 331         /* For T5, only relative offset inside the PCIe BAR is passed */
 332         mem_win0_base = MEMWIN0_BASE;
 333
 334         /*
 335          * Set up memory window for accessing adapter memory ranges.  (Read
 336          * back MA register to ensure that changes propagate before we attempt
 337          * to use the new values.)
 338          */
 339         t4_write_reg(adap,
 340                      PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN,
 341                                          MEMWIN_NIC),
 342                      mem_win0_base | V_BIR(0) |
 343                      V_WINDOW(ilog2(MEMWIN0_APERTURE) - X_WINDOW_SHIFT));
 344         t4_read_reg(adap,
 345                     PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN,
 346                                         MEMWIN_NIC));
 347 }
 348
 349 int init_rss(struct adapter *adap)
 350 {
 351         unsigned int i;
 352
 353         if (is_pf4(adap)) {
 354                 int err;
 355
 356                 err = t4_init_rss_mode(adap, adap->mbox);
 357                 if (err)
 358                         return err;
 359         }
 360
 361         for_each_port(adap, i) {
 362                 struct port_info *pi = adap2pinfo(adap, i);
 363
 364                 pi->rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0);
 365                 if (!pi->rss)
 366                         return -ENOMEM;
 367
 368                 pi->rss_hf = CXGBE_RSS_HF_ALL;
 369         }
 370         return 0;
 371 }
 372
 373 /**
 374  * Dump basic information about the adapter.
 375  */
 376 void print_adapter_info(struct adapter *adap)
 377 {
 378         /**
 379          * Hardware/Firmware/etc. Version/Revision IDs.
 380          */
 381         t4_dump_version_info(adap);
 382 }
 383
 384 void print_port_info(struct adapter *adap)
 385 {
 386         int i;
 387         char buf[80];
 388         struct rte_pci_addr *loc = &adap->pdev->addr;
 389
 390         for_each_port(adap, i) {
 391                 const struct port_info *pi = adap2pinfo(adap, i);
 392                 char *bufp = buf;
 393
 394                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100M)
 395                         bufp += sprintf(bufp, "100M/");
 396                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_1G)
 397                         bufp += sprintf(bufp, "1G/");
 398                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_10G)
 399                         bufp += sprintf(bufp, "10G/");
 400                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_25G)
 401                         bufp += sprintf(bufp, "25G/");
 402                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_40G)
 403                         bufp += sprintf(bufp, "40G/");
 404                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_50G)
 405                         bufp += sprintf(bufp, "50G/");
 406                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100G)
 407                         bufp += sprintf(bufp, "100G/");
 408                 if (bufp != buf)
 409                         --bufp;
 410                 sprintf(bufp, "BASE-%s",
 411                         t4_get_port_type_description(
 412                                         (enum fw_port_type)pi->port_type));
 413
 414                 dev_info(adap,
 415                          " " PCI_PRI_FMT " Chelsio rev %d %s %s\n",
 416                          loc->domain, loc->bus, loc->devid, loc->function,
 417                          CHELSIO_CHIP_RELEASE(adap->params.chip), buf,
 418                          (adap->flags & USING_MSIX) ? " MSI-X" :
 419                          (adap->flags & USING_MSI) ? " MSI" : "");
 420         }
 421 }
 422
 423 static void configure_pcie_ext_tag(struct adapter *adapter)
 424 {
 425         u16 v;
 426         int pos = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
 427
 428         if (!pos)
 429                 return;
 430
 431         if (pos > 0) {
 432                 t4_os_pci_read_cfg2(adapter, pos + PCI_EXP_DEVCTL, &v);
 433                 v |= PCI_EXP_DEVCTL_EXT_TAG;
 434                 t4_os_pci_write_cfg2(adapter, pos + PCI_EXP_DEVCTL, v);
 435                 if (is_t6(adapter->params.chip)) {
 436                         t4_set_reg_field(adapter, A_PCIE_CFG2,
 437                                          V_T6_TOTMAXTAG(M_T6_TOTMAXTAG),
 438                                          V_T6_TOTMAXTAG(7));
 439                         t4_set_reg_field(adapter, A_PCIE_CMD_CFG,
 440                                          V_T6_MINTAG(M_T6_MINTAG),
 441                                          V_T6_MINTAG(8));
 442                 } else {
 443                         t4_set_reg_field(adapter, A_PCIE_CFG2,
 444                                          V_TOTMAXTAG(M_TOTMAXTAG),
 445                                          V_TOTMAXTAG(3));
 446                         t4_set_reg_field(adapter, A_PCIE_CMD_CFG,
 447                                          V_MINTAG(M_MINTAG),
 448                                          V_MINTAG(8));
 449                 }
 450         }
 451 }
 452
 453 /*
 454  * Tweak configuration based on system architecture, etc.  Most of these have
 455  * defaults assigned to them by Firmware Configuration Files (if we're using
 456  * them) but need to be explicitly set if we're using hard-coded
 457  * initialization. So these are essentially common tweaks/settings for
 458  * Configuration Files and hard-coded initialization ...
 459  */
 460 static int adap_init0_tweaks(struct adapter *adapter)
 461 {
 462         u8 rx_dma_offset;
 463
 464         /*
 465          * Fix up various Host-Dependent Parameters like Page Size, Cache
 466          * Line Size, etc.  The firmware default is for a 4KB Page Size and
 467          * 64B Cache Line Size ...
 468          */
 469         t4_fixup_host_params_compat(adapter, CXGBE_PAGE_SIZE, L1_CACHE_BYTES,
 470                                     T5_LAST_REV);
 471
 472         /*
 473          * Keep the chip default offset to deliver Ingress packets into our
 474          * DMA buffers to zero
 475          */
 476         rx_dma_offset = 0;
 477         t4_set_reg_field(adapter, A_SGE_CONTROL, V_PKTSHIFT(M_PKTSHIFT),
 478                          V_PKTSHIFT(rx_dma_offset));
 479
 480         t4_set_reg_field(adapter, A_SGE_FLM_CFG,
 481                          V_CREDITCNT(M_CREDITCNT) | M_CREDITCNTPACKING,
 482                          V_CREDITCNT(3) | V_CREDITCNTPACKING(1));
 483
 484         t4_set_reg_field(adapter, A_SGE_INGRESS_RX_THRESHOLD,
 485                          V_THRESHOLD_3(M_THRESHOLD_3), V_THRESHOLD_3(32U));
 486
 487         t4_set_reg_field(adapter, A_SGE_CONTROL2, V_IDMAARBROUNDROBIN(1U),
 488                          V_IDMAARBROUNDROBIN(1U));
 489
 490         /*
 491          * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
 492          * adds the pseudo header itself.
 493          */
 494         t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG,
 495                                F_CSUM_HAS_PSEUDO_HDR, 0);
 496
 497         return 0;
 498 }
 499
 500 /*
 501  * Attempt to initialize the adapter via a Firmware Configuration File.
 502  */
 503 static int adap_init0_config(struct adapter *adapter, int reset)
 504 {
 505         struct fw_caps_config_cmd caps_cmd;
 506         unsigned long mtype = 0, maddr = 0;
 507         u32 finiver, finicsum, cfcsum;
 508         int ret;
 509         int config_issued = 0;
 510         int cfg_addr;
 511         char config_name[20];
 512
 513         /*
 514          * Reset device if necessary.
 515          */
 516         if (reset) {
 517                 ret = t4_fw_reset(adapter, adapter->mbox,
 518                                   F_PIORSTMODE | F_PIORST);
 519                 if (ret < 0) {
 520                         dev_warn(adapter, "Firmware reset failed, error %d\n",
 521                                  -ret);
 522                         goto bye;
 523                 }
 524         }
 525
 526         cfg_addr = t4_flash_cfg_addr(adapter);
 527         if (cfg_addr < 0) {
 528                 ret = cfg_addr;
 529                 dev_warn(adapter, "Finding address for firmware config file in flash failed, error %d\n",
 530                          -ret);
 531                 goto bye;
 532         }
 533
 534         strcpy(config_name, "On Flash");
 535         mtype = FW_MEMTYPE_CF_FLASH;
 536         maddr = cfg_addr;
 537
 538         /*
 539          * Issue a Capability Configuration command to the firmware to get it
 540          * to parse the Configuration File.  We don't use t4_fw_config_file()
 541          * because we want the ability to modify various features after we've
 542          * processed the configuration file ...
 543          */
 544         memset(&caps_cmd, 0, sizeof(caps_cmd));
 545         caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
 546                                            F_FW_CMD_REQUEST | F_FW_CMD_READ);
 547         caps_cmd.cfvalid_to_len16 =
 548                 cpu_to_be32(F_FW_CAPS_CONFIG_CMD_CFVALID |
 549                             V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
 550                             V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) |
 551                             FW_LEN16(caps_cmd));
 552         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
 553                          &caps_cmd);
 554         /*
 555          * If the CAPS_CONFIG failed with an ENOENT (for a Firmware
 556          * Configuration File in FLASH), our last gasp effort is to use the
 557          * Firmware Configuration File which is embedded in the firmware.  A
 558          * very few early versions of the firmware didn't have one embedded
 559          * but we can ignore those.
 560          */
 561         if (ret == -ENOENT) {
 562                 dev_info(adapter, "%s: Going for embedded config in firmware..\n",
 563                          __func__);
 564
 565                 memset(&caps_cmd, 0, sizeof(caps_cmd));
 566                 caps_cmd.op_to_write =
 567                         cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
 568                                     F_FW_CMD_REQUEST | F_FW_CMD_READ);
 569                 caps_cmd.cfvalid_to_len16 = cpu_to_be32(FW_LEN16(caps_cmd));
 570                 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
 571                                  sizeof(caps_cmd), &caps_cmd);
 572                 strcpy(config_name, "Firmware Default");
 573         }
 574
 575         config_issued = 1;
 576         if (ret < 0)
 577                 goto bye;
 578
 579         finiver = be32_to_cpu(caps_cmd.finiver);
 580         finicsum = be32_to_cpu(caps_cmd.finicsum);
 581         cfcsum = be32_to_cpu(caps_cmd.cfcsum);
 582         if (finicsum != cfcsum)
 583                 dev_warn(adapter, "Configuration File checksum mismatch: [fini] csum=%#x, computed csum=%#x\n",
 584                          finicsum, cfcsum);
 585
 586         /*
 587          * If we're a pure NIC driver then disable all offloading facilities.
 588          * This will allow the firmware to optimize aspects of the hardware
 589          * configuration which will result in improved performance.
 590          */
 591         caps_cmd.niccaps &= cpu_to_be16(~(FW_CAPS_CONFIG_NIC_HASHFILTER |
 592                                           FW_CAPS_CONFIG_NIC_ETHOFLD));
 593         caps_cmd.toecaps = 0;
 594         caps_cmd.iscsicaps = 0;
 595         caps_cmd.rdmacaps = 0;
 596         caps_cmd.fcoecaps = 0;
 597
 598         /*
 599          * And now tell the firmware to use the configuration we just loaded.
 600          */
 601         caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
 602                                            F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
 603         caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
 604         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
 605                          NULL);
 606         if (ret < 0) {
 607                 dev_warn(adapter, "Unable to finalize Firmware Capabilities %d\n",
 608                          -ret);
 609                 goto bye;
 610         }
 611
 612         /*
 613          * Tweak configuration based on system architecture, etc.
 614          */
 615         ret = adap_init0_tweaks(adapter);
 616         if (ret < 0) {
 617                 dev_warn(adapter, "Unable to do init0-tweaks %d\n", -ret);
 618                 goto bye;
 619         }
 620
 621         /*
 622          * And finally tell the firmware to initialize itself using the
 623          * parameters from the Configuration File.
 624          */
 625         ret = t4_fw_initialize(adapter, adapter->mbox);
 626         if (ret < 0) {
 627                 dev_warn(adapter, "Initializing Firmware failed, error %d\n",
 628                          -ret);
 629                 goto bye;
 630         }
 631
 632         /*
 633          * Return successfully and note that we're operating with parameters
 634          * not supplied by the driver, rather than from hard-wired
 635          * initialization constants buried in the driver.
 636          */
 637         dev_info(adapter,
 638                  "Successfully configured using Firmware Configuration File \"%s\", version %#x, computed checksum %#x\n",
 639                  config_name, finiver, cfcsum);
 640
 641         return 0;
 642
 643         /*
 644          * Something bad happened.  Return the error ...  (If the "error"
 645          * is that there's no Configuration File on the adapter we don't
 646          * want to issue a warning since this is fairly common.)
 647          */
 648 bye:
 649         if (config_issued && ret != -ENOENT)
 650                 dev_warn(adapter, "\"%s\" configuration file error %d\n",
 651                          config_name, -ret);
 652
 653         dev_debug(adapter, "%s: returning ret = %d ..\n", __func__, ret);
 654         return ret;
 655 }
 656
 657 static int adap_init0(struct adapter *adap)
 658 {
 659         int ret = 0;
 660         u32 v, port_vec;
 661         enum dev_state state;
 662         u32 params[7], val[7];
 663         int reset = 1;
 664         int mbox = adap->mbox;
 665
 666         /*
 667          * Contact FW, advertising Master capability.
 668          */
 669         ret = t4_fw_hello(adap, adap->mbox, adap->mbox, MASTER_MAY, &state);
 670         if (ret < 0) {
 671                 dev_err(adap, "%s: could not connect to FW, error %d\n",
 672                         __func__, -ret);
 673                 goto bye;
 674         }
 675
 676         CXGBE_DEBUG_MBOX(adap, "%s: adap->mbox = %d; ret = %d\n", __func__,
 677                          adap->mbox, ret);
 678
 679         if (ret == mbox)
 680                 adap->flags |= MASTER_PF;
 681
 682         if (state == DEV_STATE_INIT) {
 683                 /*
 684                  * Force halt and reset FW because a previous instance may have
 685                  * exited abnormally without properly shutting down
 686                  */
 687                 ret = t4_fw_halt(adap, adap->mbox, reset);
 688                 if (ret < 0) {
 689                         dev_err(adap, "Failed to halt. Exit.\n");
 690                         goto bye;
 691                 }
 692
 693                 ret = t4_fw_restart(adap, adap->mbox, reset);
 694                 if (ret < 0) {
 695                         dev_err(adap, "Failed to restart. Exit.\n");
 696                         goto bye;
 697                 }
 698                 state = (enum dev_state)((unsigned)state & ~DEV_STATE_INIT);
 699         }
 700
 701         t4_get_version_info(adap);
 702
 703         ret = t4_get_core_clock(adap, &adap->params.vpd);
 704         if (ret < 0) {
 705                 dev_err(adap, "%s: could not get core clock, error %d\n",
 706                         __func__, -ret);
 707                 goto bye;
 708         }
 709
 710         /*
 711          * If the firmware is initialized already (and we're not forcing a
 712          * master initialization), note that we're living with existing
 713          * adapter parameters.  Otherwise, it's time to try initializing the
 714          * adapter ...
 715          */
 716         if (state == DEV_STATE_INIT) {
 717                 dev_info(adap, "Coming up as %s: Adapter already initialized\n",
 718                          adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
 719         } else {
 720                 dev_info(adap, "Coming up as MASTER: Initializing adapter\n");
 721
 722                 ret = adap_init0_config(adap, reset);
 723                 if (ret == -ENOENT) {
 724                         dev_err(adap,
 725                                 "No Configuration File present on adapter. Using hard-wired configuration parameters.\n");
 726                         goto bye;
 727                 }
 728         }
 729         if (ret < 0) {
 730                 dev_err(adap, "could not initialize adapter, error %d\n", -ret);
 731                 goto bye;
 732         }
 733
 734         /* Find out what ports are available to us. */
 735         v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
 736             V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_PORTVEC);
 737         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec);
 738         if (ret < 0) {
 739                 dev_err(adap, "%s: failure in t4_query_params; error = %d\n",
 740                         __func__, ret);
 741                 goto bye;
 742         }
 743
 744         adap->params.nports = hweight32(port_vec);
 745         adap->params.portvec = port_vec;
 746
 747         dev_debug(adap, "%s: adap->params.nports = %u\n", __func__,
 748                   adap->params.nports);
 749
 750         /*
 751          * Give the SGE code a chance to pull in anything that it needs ...
 752          * Note that this must be called after we retrieve our VPD parameters
 753          * in order to know how to convert core ticks to seconds, etc.
 754          */
 755         ret = t4_sge_init(adap);
 756         if (ret < 0) {
 757                 dev_err(adap, "t4_sge_init failed with error %d\n",
 758                         -ret);
 759                 goto bye;
 760         }
 761
 762         /*
 763          * Grab some of our basic fundamental operating parameters.
 764          */
 765 #define FW_PARAM_DEV(param) \
 766         (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
 767          V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
 768
 769 #define FW_PARAM_PFVF(param) \
 770         (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
 771          V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param) |  \
 772          V_FW_PARAMS_PARAM_Y(0) | \
 773          V_FW_PARAMS_PARAM_Z(0))
 774
 775         /* If we're running on newer firmware, let it know that we're
 776          * prepared to deal with encapsulated CPL messages.  Older
 777          * firmware won't understand this and we'll just get
 778          * unencapsulated messages ...
 779          */
 780         params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
 781         val[0] = 1;
 782         (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
 783
 784         /*
 785          * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
 786          * capability.  Earlier versions of the firmware didn't have the
 787          * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
 788          * permission to use ULPTX MEMWRITE DSGL.
 789          */
 790         if (is_t4(adap->params.chip)) {
 791                 adap->params.ulptx_memwrite_dsgl = false;
 792         } else {
 793                 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
 794                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
 795                                       1, params, val);
 796                 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
 797         }
 798
 799         /*
 800          * The MTU/MSS Table is initialized by now, so load their values.  If
 801          * we're initializing the adapter, then we'll make any modifications
 802          * we want to the MTU/MSS Table and also initialize the congestion
 803          * parameters.
 804          */
 805         t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
 806         if (state != DEV_STATE_INIT) {
 807                 int i;
 808
 809                 /*
 810                  * The default MTU Table contains values 1492 and 1500.
 811                  * However, for TCP, it's better to have two values which are
 812                  * a multiple of 8 +/- 4 bytes apart near this popular MTU.
 813                  * This allows us to have a TCP Data Payload which is a
 814                  * multiple of 8 regardless of what combination of TCP Options
 815                  * are in use (always a multiple of 4 bytes) which is
 816                  * important for performance reasons.  For instance, if no
 817                  * options are in use, then we have a 20-byte IP header and a
 818                  * 20-byte TCP header.  In this case, a 1500-byte MSS would
 819                  * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
 820                  * which is not a multiple of 8.  So using an MSS of 1488 in
 821                  * this case results in a TCP Data Payload of 1448 bytes which
 822                  * is a multiple of 8.  On the other hand, if 12-byte TCP Time
 823                  * Stamps have been negotiated, then an MTU of 1500 bytes
 824                  * results in a TCP Data Payload of 1448 bytes which, as
 825                  * above, is a multiple of 8 bytes ...
 826                  */
 827                 for (i = 0; i < NMTUS; i++)
 828                         if (adap->params.mtus[i] == 1492) {
 829                                 adap->params.mtus[i] = 1488;
 830                                 break;
 831                         }
 832
 833                 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
 834                              adap->params.b_wnd);
 835         }
 836         t4_init_sge_params(adap);
 837         t4_init_tp_params(adap);
 838         configure_pcie_ext_tag(adap);
 839
 840         adap->params.drv_memwin = MEMWIN_NIC;
 841         adap->flags |= FW_OK;
 842         dev_debug(adap, "%s: returning zero..\n", __func__);
 843         return 0;
 844
 845         /*
 846          * Something bad happened.  If a command timed out or failed with EIO
 847          * FW does not operate within its spec or something catastrophic
 848          * happened to HW/FW, stop issuing commands.
 849          */
 850 bye:
 851         if (ret != -ETIMEDOUT && ret != -EIO)
 852                 t4_fw_bye(adap, adap->mbox);
 853         return ret;
 854 }
 855
 856 /**
 857  * t4_os_portmod_changed - handle port module changes
 858  * @adap: the adapter associated with the module change
 859  * @port_id: the port index whose module status has changed
 860  *
 861  * This is the OS-dependent handler for port module changes.  It is
 862  * invoked when a port module is removed or inserted for any OS-specific
 863  * processing.
 864  */
 865 void t4_os_portmod_changed(const struct adapter *adap, int port_id)
 866 {
 867         static const char * const mod_str[] = {
 868                 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
 869         };
 870
 871         const struct port_info *pi = adap2pinfo(adap, port_id);
 872
 873         if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
 874                 dev_info(adap, "Port%d: port module unplugged\n", pi->port_id);
 875         else if (pi->mod_type < ARRAY_SIZE(mod_str))
 876                 dev_info(adap, "Port%d: %s port module inserted\n", pi->port_id,
 877                          mod_str[pi->mod_type]);
 878         else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
 879                 dev_info(adap, "Port%d: unsupported port module inserted\n",
 880                          pi->port_id);
 881         else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
 882                 dev_info(adap, "Port%d: unknown port module inserted\n",
 883                          pi->port_id);
 884         else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR)
 885                 dev_info(adap, "Port%d: transceiver module error\n",
 886                          pi->port_id);
 887         else
 888                 dev_info(adap, "Port%d: unknown module type %d inserted\n",
 889                          pi->port_id, pi->mod_type);
 890 }
 891
 892 /**
 893  * link_start - enable a port
 894  * @dev: the port to enable
 895  *
 896  * Performs the MAC and PHY actions needed to enable a port.
 897  */
 898 int link_start(struct port_info *pi)
 899 {
 900         struct adapter *adapter = pi->adapter;
 901         int ret;
 902         unsigned int mtu;
 903
 904         mtu = pi->eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 905               (ETHER_HDR_LEN + ETHER_CRC_LEN);
 906
 907         /*
 908          * We do not set address filters and promiscuity here, the stack does
 909          * that step explicitly.
 910          */
 911         ret = t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu, -1, -1,
 912                             -1, 1, true);
 913         if (ret == 0) {
 914                 ret = t4_change_mac(adapter, adapter->mbox, pi->viid,
 915                                     pi->xact_addr_filt,
 916                                     (u8 *)&pi->eth_dev->data->mac_addrs[0],
 917                                     true, true);
 918                 if (ret >= 0) {
 919                         pi->xact_addr_filt = ret;
 920                         ret = 0;
 921                 }
 922         }
 923         if (ret == 0 && is_pf4(adapter))
 924                 ret = t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,
 925                                     &pi->link_cfg);
 926         if (ret == 0) {
 927                 /*
 928                  * Enabling a Virtual Interface can result in an interrupt
 929                  * during the processing of the VI Enable command and, in some
 930                  * paths, result in an attempt to issue another command in the
 931                  * interrupt context.  Thus, we disable interrupts during the
 932                  * course of the VI Enable command ...
 933                  */
 934                 ret = t4_enable_vi_params(adapter, adapter->mbox, pi->viid,
 935                                           true, true, false);
 936         }
 937         return ret;
 938 }
 939
 940 /**
 941  * cxgbe_write_rss_conf - flash the RSS configuration for a given port
 942  * @pi: the port
 943  * @rss_hf: Hash configuration to apply
 944  */
 945 int cxgbe_write_rss_conf(const struct port_info *pi, uint64_t rss_hf)
 946 {
 947         struct adapter *adapter = pi->adapter;
 948         const struct sge_eth_rxq *rxq;
 949         u64 flags = 0;
 950         u16 rss;
 951         int err;
 952
 953         /*  Should never be called before setting up sge eth rx queues */
 954         if (!(adapter->flags & FULL_INIT_DONE)) {
 955                 dev_err(adap, "%s No RXQs available on port %d\n",
 956                         __func__, pi->port_id);
 957                 return -EINVAL;
 958         }
 959
 960         /* Don't allow unsupported hash functions */
 961         if (rss_hf & ~CXGBE_RSS_HF_ALL)
 962                 return -EINVAL;
 963
 964         if (rss_hf & ETH_RSS_IPV4)
 965                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN;
 966
 967         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
 968                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
 969
 970         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
 971                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
 972                          F_FW_RSS_VI_CONFIG_CMD_UDPEN;
 973
 974         if (rss_hf & ETH_RSS_IPV6)
 975                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN;
 976
 977         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
 978                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
 979
 980         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
 981                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN |
 982                          F_FW_RSS_VI_CONFIG_CMD_UDPEN;
 983
 984         rxq = &adapter->sge.ethrxq[pi->first_qset];
 985         rss = rxq[0].rspq.abs_id;
 986
 987         /* If Tunnel All Lookup isn't specified in the global RSS
 988          * Configuration, then we need to specify a default Ingress
 989          * Queue for any ingress packets which aren't hashed.  We'll
 990          * use our first ingress queue ...
 991          */
 992         err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,
 993                                flags, rss);
 994         return err;
 995 }
 996
 997 /**
 998  * cxgbe_write_rss - write the RSS table for a given port
 999  * @pi: the port
1000  * @queues: array of queue indices for RSS
1001  *
1002  * Sets up the portion of the HW RSS table for the port's VI to distribute
1003  * packets to the Rx queues in @queues.
1004  */
1005 int cxgbe_write_rss(const struct port_info *pi, const u16 *queues)
1006 {
1007         u16 *rss;
1008         int i, err;
1009         struct adapter *adapter = pi->adapter;
1010         const struct sge_eth_rxq *rxq;
1011
1012         /*  Should never be called before setting up sge eth rx queues */
1013         BUG_ON(!(adapter->flags & FULL_INIT_DONE));
1014
1015         rxq = &adapter->sge.ethrxq[pi->first_qset];
1016         rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0);
1017         if (!rss)
1018                 return -ENOMEM;
1019
1020         /* map the queue indices to queue ids */
1021         for (i = 0; i < pi->rss_size; i++, queues++)
1022                 rss[i] = rxq[*queues].rspq.abs_id;
1023
1024         err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0,
1025                                   pi->rss_size, rss, pi->rss_size);
1026         rte_free(rss);
1027         return err;
1028 }
1029
1030 /**
1031  * setup_rss - configure RSS
1032  * @adapter: the adapter
1033  *
1034  * Sets up RSS to distribute packets to multiple receive queues.  We
1035  * configure the RSS CPU lookup table to distribute to the number of HW
1036  * receive queues, and the response queue lookup table to narrow that
1037  * down to the response queues actually configured for each port.
1038  * We always configure the RSS mapping for all ports since the mapping
1039  * table has plenty of entries.
1040  */
1041 int setup_rss(struct port_info *pi)
1042 {
1043         int j, err;
1044         struct adapter *adapter = pi->adapter;
1045
1046         dev_debug(adapter, "%s:  pi->rss_size = %u; pi->n_rx_qsets = %u\n",
1047                   __func__, pi->rss_size, pi->n_rx_qsets);
1048
1049         if (!(pi->flags & PORT_RSS_DONE)) {
1050                 if (adapter->flags & FULL_INIT_DONE) {
1051                         /* Fill default values with equal distribution */
1052                         for (j = 0; j < pi->rss_size; j++)
1053                                 pi->rss[j] = j % pi->n_rx_qsets;
1054
1055                         err = cxgbe_write_rss(pi, pi->rss);
1056                         if (err)
1057                                 return err;
1058
1059                         err = cxgbe_write_rss_conf(pi, pi->rss_hf);
1060                         if (err)
1061                                 return err;
1062                         pi->flags |= PORT_RSS_DONE;
1063                 }
1064         }
1065         return 0;
1066 }
1067
1068 /*
1069  * Enable NAPI scheduling and interrupt generation for all Rx queues.
1070  */
1071 static void enable_rx(struct adapter *adap, struct sge_rspq *q)
1072 {
1073         /* 0-increment GTS to start the timer and enable interrupts */
1074         t4_write_reg(adap, is_pf4(adap) ? MYPF_REG(A_SGE_PF_GTS) :
1075                                           T4VF_SGE_BASE_ADDR + A_SGE_VF_GTS,
1076                      V_SEINTARM(q->intr_params) |
1077                      V_INGRESSQID(q->cntxt_id));
1078 }
1079
1080 void cxgbe_enable_rx_queues(struct port_info *pi)
1081 {
1082         struct adapter *adap = pi->adapter;
1083         struct sge *s = &adap->sge;
1084         unsigned int i;
1085
1086         for (i = 0; i < pi->n_rx_qsets; i++)
1087                 enable_rx(adap, &s->ethrxq[pi->first_qset + i].rspq);
1088 }
1089
1090 /**
1091  * fw_caps_to_speed_caps - translate Firmware Port Caps to Speed Caps.
1092  * @port_type: Firmware Port Type
1093  * @fw_caps: Firmware Port Capabilities
1094  * @speed_caps: Device Info Speed Capabilities
1095  *
1096  * Translate a Firmware Port Capabilities specification to Device Info
1097  * Speed Capabilities.
1098  */
1099 static void fw_caps_to_speed_caps(enum fw_port_type port_type,
1100                                   unsigned int fw_caps,
1101                                   u32 *speed_caps)
1102 {
1103 #define SET_SPEED(__speed_name) \
1104         do { \
1105                 *speed_caps |= ETH_LINK_ ## __speed_name; \
1106         } while (0)
1107
1108 #define FW_CAPS_TO_SPEED(__fw_name) \
1109         do { \
1110                 if (fw_caps & FW_PORT_CAP32_ ## __fw_name) \
1111                         SET_SPEED(__fw_name); \
1112         } while (0)
1113
1114         switch (port_type) {
1115         case FW_PORT_TYPE_BT_SGMII:
1116         case FW_PORT_TYPE_BT_XFI:
1117         case FW_PORT_TYPE_BT_XAUI:
1118                 FW_CAPS_TO_SPEED(SPEED_100M);
1119                 FW_CAPS_TO_SPEED(SPEED_1G);
1120                 FW_CAPS_TO_SPEED(SPEED_10G);
1121                 break;
1122
1123         case FW_PORT_TYPE_KX4:
1124         case FW_PORT_TYPE_KX:
1125         case FW_PORT_TYPE_FIBER_XFI:
1126         case FW_PORT_TYPE_FIBER_XAUI:
1127         case FW_PORT_TYPE_SFP:
1128         case FW_PORT_TYPE_QSFP_10G:
1129         case FW_PORT_TYPE_QSA:
1130                 FW_CAPS_TO_SPEED(SPEED_1G);
1131                 FW_CAPS_TO_SPEED(SPEED_10G);
1132                 break;
1133
1134         case FW_PORT_TYPE_KR:
1135                 SET_SPEED(SPEED_10G);
1136                 break;
1137
1138         case FW_PORT_TYPE_BP_AP:
1139         case FW_PORT_TYPE_BP4_AP:
1140                 SET_SPEED(SPEED_1G);
1141                 SET_SPEED(SPEED_10G);
1142                 break;
1143
1144         case FW_PORT_TYPE_BP40_BA:
1145         case FW_PORT_TYPE_QSFP:
1146                 SET_SPEED(SPEED_40G);
1147                 break;
1148
1149         case FW_PORT_TYPE_CR_QSFP:
1150         case FW_PORT_TYPE_SFP28:
1151         case FW_PORT_TYPE_KR_SFP28:
1152                 FW_CAPS_TO_SPEED(SPEED_1G);
1153                 FW_CAPS_TO_SPEED(SPEED_10G);
1154                 FW_CAPS_TO_SPEED(SPEED_25G);
1155                 break;
1156
1157         case FW_PORT_TYPE_CR2_QSFP:
1158                 SET_SPEED(SPEED_50G);
1159                 break;
1160
1161         case FW_PORT_TYPE_KR4_100G:
1162         case FW_PORT_TYPE_CR4_QSFP:
1163                 FW_CAPS_TO_SPEED(SPEED_25G);
1164                 FW_CAPS_TO_SPEED(SPEED_40G);
1165                 FW_CAPS_TO_SPEED(SPEED_50G);
1166                 FW_CAPS_TO_SPEED(SPEED_100G);
1167                 break;
1168
1169         default:
1170                 break;
1171         }
1172
1173 #undef FW_CAPS_TO_SPEED
1174 #undef SET_SPEED
1175 }
1176
1177 /**
1178  * cxgbe_get_speed_caps - Fetch supported speed capabilities
1179  * @pi: Underlying port's info
1180  * @speed_caps: Device Info speed capabilities
1181  *
1182  * Fetch supported speed capabilities of the underlying port.
1183  */
1184 void cxgbe_get_speed_caps(struct port_info *pi, u32 *speed_caps)
1185 {
1186         *speed_caps = 0;
1187
1188         fw_caps_to_speed_caps(pi->port_type, pi->link_cfg.pcaps,
1189                               speed_caps);
1190
1191         if (!(pi->link_cfg.pcaps & FW_PORT_CAP32_ANEG))
1192                 *speed_caps |= ETH_LINK_SPEED_FIXED;
1193 }
1194
1195 /**
1196  * cxgb_up - enable the adapter
1197  * @adap: adapter being enabled
1198  *
1199  * Called when the first port is enabled, this function performs the
1200  * actions necessary to make an adapter operational, such as completing
1201  * the initialization of HW modules, and enabling interrupts.
1202  */
1203 int cxgbe_up(struct adapter *adap)
1204 {
1205         enable_rx(adap, &adap->sge.fw_evtq);
1206         t4_sge_tx_monitor_start(adap);
1207         if (is_pf4(adap))
1208                 t4_intr_enable(adap);
1209         adap->flags |= FULL_INIT_DONE;
1210
1211         /* TODO: deadman watchdog ?? */
1212         return 0;
1213 }
1214
1215 /*
1216  * Close the port
1217  */
1218 int cxgbe_down(struct port_info *pi)
1219 {
1220         struct adapter *adapter = pi->adapter;
1221         int err = 0;
1222
1223         err = t4_enable_vi(adapter, adapter->mbox, pi->viid, false, false);
1224         if (err) {
1225                 dev_err(adapter, "%s: disable_vi failed: %d\n", __func__, err);
1226                 return err;
1227         }
1228
1229         t4_reset_link_config(adapter, pi->pidx);
1230         return 0;
1231 }
1232
1233 /*
1234  * Release resources when all the ports have been stopped.
1235  */
1236 void cxgbe_close(struct adapter *adapter)
1237 {
1238         struct port_info *pi;
1239         int i;
1240
1241         if (adapter->flags & FULL_INIT_DONE) {
1242                 if (is_pf4(adapter))
1243                         t4_intr_disable(adapter);
1244                 t4_sge_tx_monitor_stop(adapter);
1245                 t4_free_sge_resources(adapter);
1246                 for_each_port(adapter, i) {
1247                         pi = adap2pinfo(adapter, i);
1248                         if (pi->viid != 0)
1249                                 t4_free_vi(adapter, adapter->mbox,
1250                                            adapter->pf, 0, pi->viid);
1251                         rte_free(pi->eth_dev->data->mac_addrs);
1252                         /* Skip first port since it'll be freed by DPDK stack */
1253                         if (i) {
1254                                 rte_free(pi->eth_dev->data->dev_private);
1255                                 rte_eth_dev_release_port(pi->eth_dev);
1256                         }
1257                 }
1258                 adapter->flags &= ~FULL_INIT_DONE;
1259         }
1260
1261         if (is_pf4(adapter) && (adapter->flags & FW_OK))
1262                 t4_fw_bye(adapter, adapter->mbox);
1263 }
1264
1265 int cxgbe_probe(struct adapter *adapter)
1266 {
1267         struct port_info *pi;
1268         int chip;
1269         int func, i;
1270         int err = 0;
1271         u32 whoami;
1272
1273         whoami = t4_read_reg(adapter, A_PL_WHOAMI);
1274         chip = t4_get_chip_type(adapter,
1275                         CHELSIO_PCI_ID_VER(adapter->pdev->id.device_id));
1276         if (chip < 0)
1277                 return chip;
1278
1279         func = CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5 ?
1280                G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
1281
1282         adapter->mbox = func;
1283         adapter->pf = func;
1284
1285         t4_os_lock_init(&adapter->mbox_lock);
1286         TAILQ_INIT(&adapter->mbox_list);
1287
1288         err = t4_prep_adapter(adapter);
1289         if (err)
1290                 return err;
1291
1292         setup_memwin(adapter);
1293         err = adap_init0(adapter);
1294         if (err) {
1295                 dev_err(adapter, "%s: Adapter initialization failed, error %d\n",
1296                         __func__, err);
1297                 goto out_free;
1298         }
1299
1300         if (!is_t4(adapter->params.chip)) {
1301                 /*
1302                  * The userspace doorbell BAR is split evenly into doorbell
1303                  * regions, each associated with an egress queue.  If this
1304                  * per-queue region is large enough (at least UDBS_SEG_SIZE)
1305                  * then it can be used to submit a tx work request with an
1306                  * implied doorbell.  Enable write combining on the BAR if
1307                  * there is room for such work requests.
1308                  */
1309                 int s_qpp, qpp, num_seg;
1310
1311                 s_qpp = (S_QUEUESPERPAGEPF0 +
1312                         (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) *
1313                         adapter->pf);
1314                 qpp = 1 << ((t4_read_reg(adapter,
1315                                 A_SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp)
1316                                 & M_QUEUESPERPAGEPF0);
1317                 num_seg = CXGBE_PAGE_SIZE / UDBS_SEG_SIZE;
1318                 if (qpp > num_seg)
1319                         dev_warn(adapter, "Incorrect SGE EGRESS QUEUES_PER_PAGE configuration, continuing in debug mode\n");
1320
1321                 adapter->bar2 = (void *)adapter->pdev->mem_resource[2].addr;
1322                 if (!adapter->bar2) {
1323                         dev_err(adapter, "cannot map device bar2 region\n");
1324                         err = -ENOMEM;
1325                         goto out_free;
1326                 }
1327                 t4_write_reg(adapter, A_SGE_STAT_CFG, V_STATSOURCE_T5(7) |
1328                              V_STATMODE(0));
1329         }
1330
1331         for_each_port(adapter, i) {
1332                 const unsigned int numa_node = rte_socket_id();
1333                 char name[RTE_ETH_NAME_MAX_LEN];
1334                 struct rte_eth_dev *eth_dev;
1335
1336                 snprintf(name, sizeof(name), "%s_%d",
1337                          adapter->pdev->device.name, i);
1338
1339                 if (i == 0) {
1340                         /* First port is already allocated by DPDK */
1341                         eth_dev = adapter->eth_dev;
1342                         goto allocate_mac;
1343                 }
1344
1345                 /*
1346                  * now do all data allocation - for eth_dev structure,
1347                  * and internal (private) data for the remaining ports
1348                  */
1349
1350                 /* reserve an ethdev entry */
1351                 eth_dev = rte_eth_dev_allocate(name);
1352                 if (!eth_dev)
1353                         goto out_free;
1354
1355                 eth_dev->data->dev_private =
1356                         rte_zmalloc_socket(name, sizeof(struct port_info),
1357                                            RTE_CACHE_LINE_SIZE, numa_node);
1358                 if (!eth_dev->data->dev_private)
1359                         goto out_free;
1360
1361 allocate_mac:
1362                 pi = (struct port_info *)eth_dev->data->dev_private;
1363                 adapter->port[i] = pi;
1364                 pi->eth_dev = eth_dev;
1365                 pi->adapter = adapter;
1366                 pi->xact_addr_filt = -1;
1367                 pi->port_id = i;
1368                 pi->pidx = i;
1369
1370                 pi->eth_dev->device = &adapter->pdev->device;
1371                 pi->eth_dev->dev_ops = adapter->eth_dev->dev_ops;
1372                 pi->eth_dev->tx_pkt_burst = adapter->eth_dev->tx_pkt_burst;
1373                 pi->eth_dev->rx_pkt_burst = adapter->eth_dev->rx_pkt_burst;
1374
1375                 rte_eth_copy_pci_info(pi->eth_dev, adapter->pdev);
1376
1377                 pi->eth_dev->data->mac_addrs = rte_zmalloc(name,
1378                                                            ETHER_ADDR_LEN, 0);
1379                 if (!pi->eth_dev->data->mac_addrs) {
1380                         dev_err(adapter, "%s: Mem allocation failed for storing mac addr, aborting\n",
1381                                 __func__);
1382                         err = -1;
1383                         goto out_free;
1384                 }
1385         }
1386
1387         if (adapter->flags & FW_OK) {
1388                 err = t4_port_init(adapter, adapter->mbox, adapter->pf, 0);
1389                 if (err) {
1390                         dev_err(adapter, "%s: t4_port_init failed with err %d\n",
1391                                 __func__, err);
1392                         goto out_free;
1393                 }
1394         }
1395
1396         cfg_queues(adapter->eth_dev);
1397
1398         print_adapter_info(adapter);
1399         print_port_info(adapter);
1400
1401         err = init_rss(adapter);
1402         if (err)
1403                 goto out_free;
1404
1405         return 0;
1406
1407 out_free:
1408         for_each_port(adapter, i) {
1409                 pi = adap2pinfo(adapter, i);
1410                 if (pi->viid != 0)
1411                         t4_free_vi(adapter, adapter->mbox, adapter->pf,
1412                                    0, pi->viid);
1413                 /* Skip first port since it'll be de-allocated by DPDK */
1414                 if (i == 0)
1415                         continue;
1416                 if (pi->eth_dev) {
1417                         if (pi->eth_dev->data->dev_private)
1418                                 rte_free(pi->eth_dev->data->dev_private);
1419                         rte_eth_dev_release_port(pi->eth_dev);
1420                 }
1421         }
1422
1423         if (adapter->flags & FW_OK)
1424                 t4_fw_bye(adapter, adapter->mbox);
1425         return -err;
1426 }