4 * Copyright(c) 2014-2015 Chelsio Communications.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Chelsio Communications nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
42 #include <netinet/in.h>
44 #include <rte_byteorder.h>
45 #include <rte_common.h>
46 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
55 #include <rte_tailq.h>
57 #include <rte_alarm.h>
58 #include <rte_ether.h>
59 #include <rte_ethdev.h>
60 #include <rte_atomic.h>
61 #include <rte_malloc.h>
62 #include <rte_random.h>
71 * Response queue handler for the FW event queue.
73 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
74 __rte_unused const struct pkt_gl *gl)
76 u8 opcode = ((const struct rss_header *)rsp)->opcode;
78 rsp++; /* skip RSS header */
81 * FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
83 if (unlikely(opcode == CPL_FW4_MSG &&
84 ((const struct cpl_fw4_msg *)rsp)->type ==
87 opcode = ((const struct rss_header *)rsp)->opcode;
89 if (opcode != CPL_SGE_EGR_UPDATE) {
90 dev_err(q->adapter, "unexpected FW4/CPL %#x on FW event queue\n",
96 if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
98 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
99 const struct cpl_fw6_msg *msg = (const void *)rsp;
101 t4_handle_fw_rpl(q->adapter, msg->data);
103 dev_err(adapter, "unexpected CPL %#x on FW event queue\n",
110 int setup_sge_fwevtq(struct adapter *adapter)
112 struct sge *s = &adapter->sge;
116 err = t4_sge_alloc_rxq(adapter, &s->fw_evtq, true, adapter->eth_dev,
117 msi_idx, NULL, fwevtq_handler, -1, NULL, 0,
122 static int closest_timer(const struct sge *s, int time)
124 unsigned int i, match = 0;
125 int delta, min_delta = INT_MAX;
127 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
128 delta = time - s->timer_val[i];
131 if (delta < min_delta) {
139 static int closest_thres(const struct sge *s, int thres)
141 unsigned int i, match = 0;
142 int delta, min_delta = INT_MAX;
144 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
145 delta = thres - s->counter_val[i];
148 if (delta < min_delta) {
157 * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters
159 * @us: the hold-off time in us, or 0 to disable timer
160 * @cnt: the hold-off packet count, or 0 to disable counter
162 * Sets an Rx queue's interrupt hold-off time and packet count. At least
163 * one of the two needs to be enabled for the queue to generate interrupts.
165 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
168 struct adapter *adap = q->adapter;
169 unsigned int timer_val;
175 new_idx = closest_thres(&adap->sge, cnt);
176 if (q->desc && q->pktcnt_idx != new_idx) {
177 /* the queue has already been created, update it */
178 v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
180 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
181 V_FW_PARAMS_PARAM_YZ(q->cntxt_id);
182 err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
187 q->pktcnt_idx = new_idx;
190 timer_val = (us == 0) ? X_TIMERREG_RESTART_COUNTER :
191 closest_timer(&adap->sge, us);
194 q->intr_params = V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX);
196 q->intr_params = V_QINTR_TIMER_IDX(timer_val) |
197 V_QINTR_CNT_EN(cnt > 0);
201 static inline bool is_x_1g_port(const struct link_config *lc)
203 return ((lc->supported & FW_PORT_CAP_SPEED_1G) != 0);
206 static inline bool is_x_10g_port(const struct link_config *lc)
208 return ((lc->supported & FW_PORT_CAP_SPEED_10G) != 0 ||
209 (lc->supported & FW_PORT_CAP_SPEED_40G) != 0 ||
210 (lc->supported & FW_PORT_CAP_SPEED_100G) != 0);
213 inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
214 unsigned int us, unsigned int cnt,
215 unsigned int size, unsigned int iqe_size)
218 cxgb4_set_rspq_intr_params(q, us, cnt);
219 q->iqe_len = iqe_size;
223 int cfg_queue_count(struct rte_eth_dev *eth_dev)
225 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
226 struct adapter *adap = pi->adapter;
227 struct sge *s = &adap->sge;
228 unsigned int max_queues = s->max_ethqsets / adap->params.nports;
230 if ((eth_dev->data->nb_rx_queues < 1) ||
231 (eth_dev->data->nb_tx_queues < 1))
234 if ((eth_dev->data->nb_rx_queues > max_queues) ||
235 (eth_dev->data->nb_tx_queues > max_queues))
238 if (eth_dev->data->nb_rx_queues > pi->rss_size)
241 /* We must configure RSS, since config has changed*/
242 pi->flags &= ~PORT_RSS_DONE;
244 pi->n_rx_qsets = eth_dev->data->nb_rx_queues;
245 pi->n_tx_qsets = eth_dev->data->nb_tx_queues;
250 void cfg_queues(struct rte_eth_dev *eth_dev)
252 struct rte_config *config = rte_eal_get_configuration();
253 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
254 struct adapter *adap = pi->adapter;
255 struct sge *s = &adap->sge;
256 unsigned int i, nb_ports = 0, qidx = 0;
257 unsigned int q_per_port = 0;
259 if (!(adap->flags & CFG_QUEUES)) {
260 for_each_port(adap, i) {
261 struct port_info *tpi = adap2pinfo(adap, i);
263 nb_ports += (is_x_10g_port(&tpi->link_cfg)) ||
264 is_x_1g_port(&tpi->link_cfg) ? 1 : 0;
268 * We default up to # of cores queues per 1G/10G port.
271 q_per_port = (MAX_ETH_QSETS -
272 (adap->params.nports - nb_ports)) /
275 if (q_per_port > config->lcore_count)
276 q_per_port = config->lcore_count;
278 for_each_port(adap, i) {
279 struct port_info *pi = adap2pinfo(adap, i);
281 pi->first_qset = qidx;
283 /* Initially n_rx_qsets == n_tx_qsets */
284 pi->n_rx_qsets = (is_x_10g_port(&pi->link_cfg) ||
285 is_x_1g_port(&pi->link_cfg)) ?
287 pi->n_tx_qsets = pi->n_rx_qsets;
289 if (pi->n_rx_qsets > pi->rss_size)
290 pi->n_rx_qsets = pi->rss_size;
292 qidx += pi->n_rx_qsets;
295 s->max_ethqsets = qidx;
297 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
298 struct sge_eth_rxq *r = &s->ethrxq[i];
300 init_rspq(adap, &r->rspq, 0, 0, 1024, 64);
302 r->fl.size = (r->usembufs ? 1024 : 72);
305 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
306 s->ethtxq[i].q.size = 1024;
308 init_rspq(adap, &adap->sge.fw_evtq, 0, 0, 1024, 64);
309 adap->flags |= CFG_QUEUES;
313 static void setup_memwin(struct adapter *adap)
317 /* For T5, only relative offset inside the PCIe BAR is passed */
318 mem_win0_base = MEMWIN0_BASE;
321 * Set up memory window for accessing adapter memory ranges. (Read
322 * back MA register to ensure that changes propagate before we attempt
323 * to use the new values.)
326 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN,
328 mem_win0_base | V_BIR(0) |
329 V_WINDOW(ilog2(MEMWIN0_APERTURE) - X_WINDOW_SHIFT));
331 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN,
335 static int init_rss(struct adapter *adap)
340 err = t4_init_rss_mode(adap, adap->mbox);
344 for_each_port(adap, i) {
345 struct port_info *pi = adap2pinfo(adap, i);
347 pi->rss = rte_zmalloc(NULL, pi->rss_size, 0);
354 static void print_port_info(struct adapter *adap)
358 struct rte_pci_addr *loc = &adap->pdev->addr;
360 for_each_port(adap, i) {
361 const struct port_info *pi = &adap->port[i];
364 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M)
365 bufp += sprintf(bufp, "100/");
366 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G)
367 bufp += sprintf(bufp, "1000/");
368 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G)
369 bufp += sprintf(bufp, "10G/");
370 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G)
371 bufp += sprintf(bufp, "40G/");
374 sprintf(bufp, "BASE-%s",
375 t4_get_port_type_description(pi->port_type));
378 " " PCI_PRI_FMT " Chelsio rev %d %s %s\n",
379 loc->domain, loc->bus, loc->devid, loc->function,
380 CHELSIO_CHIP_RELEASE(adap->params.chip), buf,
381 (adap->flags & USING_MSIX) ? " MSI-X" :
382 (adap->flags & USING_MSI) ? " MSI" : "");
387 * Tweak configuration based on system architecture, etc. Most of these have
388 * defaults assigned to them by Firmware Configuration Files (if we're using
389 * them) but need to be explicitly set if we're using hard-coded
390 * initialization. So these are essentially common tweaks/settings for
391 * Configuration Files and hard-coded initialization ...
393 static int adap_init0_tweaks(struct adapter *adapter)
398 * Fix up various Host-Dependent Parameters like Page Size, Cache
399 * Line Size, etc. The firmware default is for a 4KB Page Size and
400 * 64B Cache Line Size ...
402 t4_fixup_host_params_compat(adapter, PAGE_SIZE, L1_CACHE_BYTES,
406 * Keep the chip default offset to deliver Ingress packets into our
407 * DMA buffers to zero
410 t4_set_reg_field(adapter, A_SGE_CONTROL, V_PKTSHIFT(M_PKTSHIFT),
411 V_PKTSHIFT(rx_dma_offset));
414 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
415 * adds the pseudo header itself.
417 t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG,
418 F_CSUM_HAS_PSEUDO_HDR, 0);
424 * Attempt to initialize the adapter via a Firmware Configuration File.
426 static int adap_init0_config(struct adapter *adapter, int reset)
428 struct fw_caps_config_cmd caps_cmd;
429 unsigned long mtype = 0, maddr = 0;
430 u32 finiver, finicsum, cfcsum;
432 int config_issued = 0;
434 char config_name[20];
437 * Reset device if necessary.
440 ret = t4_fw_reset(adapter, adapter->mbox,
441 F_PIORSTMODE | F_PIORST);
443 dev_warn(adapter, "Firmware reset failed, error %d\n",
449 cfg_addr = t4_flash_cfg_addr(adapter);
452 dev_warn(adapter, "Finding address for firmware config file in flash failed, error %d\n",
457 strcpy(config_name, "On Flash");
458 mtype = FW_MEMTYPE_CF_FLASH;
462 * Issue a Capability Configuration command to the firmware to get it
463 * to parse the Configuration File. We don't use t4_fw_config_file()
464 * because we want the ability to modify various features after we've
465 * processed the configuration file ...
467 memset(&caps_cmd, 0, sizeof(caps_cmd));
468 caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
469 F_FW_CMD_REQUEST | F_FW_CMD_READ);
470 caps_cmd.cfvalid_to_len16 =
471 cpu_to_be32(F_FW_CAPS_CONFIG_CMD_CFVALID |
472 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
473 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) |
475 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
478 * If the CAPS_CONFIG failed with an ENOENT (for a Firmware
479 * Configuration File in FLASH), our last gasp effort is to use the
480 * Firmware Configuration File which is embedded in the firmware. A
481 * very few early versions of the firmware didn't have one embedded
482 * but we can ignore those.
484 if (ret == -ENOENT) {
485 dev_info(adapter, "%s: Going for embedded config in firmware..\n",
488 memset(&caps_cmd, 0, sizeof(caps_cmd));
489 caps_cmd.op_to_write =
490 cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
491 F_FW_CMD_REQUEST | F_FW_CMD_READ);
492 caps_cmd.cfvalid_to_len16 = cpu_to_be32(FW_LEN16(caps_cmd));
493 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
494 sizeof(caps_cmd), &caps_cmd);
495 strcpy(config_name, "Firmware Default");
502 finiver = be32_to_cpu(caps_cmd.finiver);
503 finicsum = be32_to_cpu(caps_cmd.finicsum);
504 cfcsum = be32_to_cpu(caps_cmd.cfcsum);
505 if (finicsum != cfcsum)
506 dev_warn(adapter, "Configuration File checksum mismatch: [fini] csum=%#x, computed csum=%#x\n",
510 * If we're a pure NIC driver then disable all offloading facilities.
511 * This will allow the firmware to optimize aspects of the hardware
512 * configuration which will result in improved performance.
514 caps_cmd.niccaps &= cpu_to_be16(~(FW_CAPS_CONFIG_NIC_HASHFILTER |
515 FW_CAPS_CONFIG_NIC_ETHOFLD));
516 caps_cmd.toecaps = 0;
517 caps_cmd.iscsicaps = 0;
518 caps_cmd.rdmacaps = 0;
519 caps_cmd.fcoecaps = 0;
522 * And now tell the firmware to use the configuration we just loaded.
524 caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
525 F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
526 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
527 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
530 dev_warn(adapter, "Unable to finalize Firmware Capabilities %d\n",
536 * Tweak configuration based on system architecture, etc.
538 ret = adap_init0_tweaks(adapter);
540 dev_warn(adapter, "Unable to do init0-tweaks %d\n", -ret);
545 * And finally tell the firmware to initialize itself using the
546 * parameters from the Configuration File.
548 ret = t4_fw_initialize(adapter, adapter->mbox);
550 dev_warn(adapter, "Initializing Firmware failed, error %d\n",
556 * Return successfully and note that we're operating with parameters
557 * not supplied by the driver, rather than from hard-wired
558 * initialization constants burried in the driver.
561 "Successfully configured using Firmware Configuration File \"%s\", version %#x, computed checksum %#x\n",
562 config_name, finiver, cfcsum);
567 * Something bad happened. Return the error ... (If the "error"
568 * is that there's no Configuration File on the adapter we don't
569 * want to issue a warning since this is fairly common.)
572 if (config_issued && ret != -ENOENT)
573 dev_warn(adapter, "\"%s\" configuration file error %d\n",
576 dev_debug(adapter, "%s: returning ret = %d ..\n", __func__, ret);
580 static int adap_init0(struct adapter *adap)
584 enum dev_state state;
585 u32 params[7], val[7];
587 int mbox = adap->mbox;
590 * Contact FW, advertising Master capability.
592 ret = t4_fw_hello(adap, adap->mbox, adap->mbox, MASTER_MAY, &state);
594 dev_err(adap, "%s: could not connect to FW, error %d\n",
599 CXGBE_DEBUG_MBOX(adap, "%s: adap->mbox = %d; ret = %d\n", __func__,
603 adap->flags |= MASTER_PF;
605 if (state == DEV_STATE_INIT) {
607 * Force halt and reset FW because a previous instance may have
608 * exited abnormally without properly shutting down
610 ret = t4_fw_halt(adap, adap->mbox, reset);
612 dev_err(adap, "Failed to halt. Exit.\n");
616 ret = t4_fw_restart(adap, adap->mbox, reset);
618 dev_err(adap, "Failed to restart. Exit.\n");
621 state &= ~DEV_STATE_INIT;
624 t4_get_fw_version(adap, &adap->params.fw_vers);
625 t4_get_tp_version(adap, &adap->params.tp_vers);
627 dev_info(adap, "fw: %u.%u.%u.%u, TP: %u.%u.%u.%u\n",
628 G_FW_HDR_FW_VER_MAJOR(adap->params.fw_vers),
629 G_FW_HDR_FW_VER_MINOR(adap->params.fw_vers),
630 G_FW_HDR_FW_VER_MICRO(adap->params.fw_vers),
631 G_FW_HDR_FW_VER_BUILD(adap->params.fw_vers),
632 G_FW_HDR_FW_VER_MAJOR(adap->params.tp_vers),
633 G_FW_HDR_FW_VER_MINOR(adap->params.tp_vers),
634 G_FW_HDR_FW_VER_MICRO(adap->params.tp_vers),
635 G_FW_HDR_FW_VER_BUILD(adap->params.tp_vers));
637 ret = t4_get_core_clock(adap, &adap->params.vpd);
639 dev_err(adap, "%s: could not get core clock, error %d\n",
645 * Find out what ports are available to us. Note that we need to do
646 * this before calling adap_init0_no_config() since it needs nports
649 v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
650 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_PORTVEC);
651 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec);
653 dev_err(adap, "%s: failure in t4_queury_params; error = %d\n",
658 adap->params.nports = hweight32(port_vec);
659 adap->params.portvec = port_vec;
661 dev_debug(adap, "%s: adap->params.nports = %u\n", __func__,
662 adap->params.nports);
665 * If the firmware is initialized already (and we're not forcing a
666 * master initialization), note that we're living with existing
667 * adapter parameters. Otherwise, it's time to try initializing the
670 if (state == DEV_STATE_INIT) {
671 dev_info(adap, "Coming up as %s: Adapter already initialized\n",
672 adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
674 dev_info(adap, "Coming up as MASTER: Initializing adapter\n");
676 ret = adap_init0_config(adap, reset);
677 if (ret == -ENOENT) {
679 "No Configuration File present on adapter. Using hard-wired configuration parameters.\n");
684 dev_err(adap, "could not initialize adapter, error %d\n", -ret);
689 * Give the SGE code a chance to pull in anything that it needs ...
690 * Note that this must be called after we retrieve our VPD parameters
691 * in order to know how to convert core ticks to seconds, etc.
693 ret = t4_sge_init(adap);
695 dev_err(adap, "t4_sge_init failed with error %d\n",
701 * Grab some of our basic fundamental operating parameters.
703 #define FW_PARAM_DEV(param) \
704 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
705 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
707 #define FW_PARAM_PFVF(param) \
708 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
709 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param) | \
710 V_FW_PARAMS_PARAM_Y(0) | \
711 V_FW_PARAMS_PARAM_Z(0))
713 /* If we're running on newer firmware, let it know that we're
714 * prepared to deal with encapsulated CPL messages. Older
715 * firmware won't understand this and we'll just get
716 * unencapsulated messages ...
718 params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
720 (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
723 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
724 * capability. Earlier versions of the firmware didn't have the
725 * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
726 * permission to use ULPTX MEMWRITE DSGL.
728 if (is_t4(adap->params.chip)) {
729 adap->params.ulptx_memwrite_dsgl = false;
731 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
732 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
734 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
738 * The MTU/MSS Table is initialized by now, so load their values. If
739 * we're initializing the adapter, then we'll make any modifications
740 * we want to the MTU/MSS Table and also initialize the congestion
743 t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
744 if (state != DEV_STATE_INIT) {
748 * The default MTU Table contains values 1492 and 1500.
749 * However, for TCP, it's better to have two values which are
750 * a multiple of 8 +/- 4 bytes apart near this popular MTU.
751 * This allows us to have a TCP Data Payload which is a
752 * multiple of 8 regardless of what combination of TCP Options
753 * are in use (always a multiple of 4 bytes) which is
754 * important for performance reasons. For instance, if no
755 * options are in use, then we have a 20-byte IP header and a
756 * 20-byte TCP header. In this case, a 1500-byte MSS would
757 * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
758 * which is not a multiple of 8. So using an MSS of 1488 in
759 * this case results in a TCP Data Payload of 1448 bytes which
760 * is a multiple of 8. On the other hand, if 12-byte TCP Time
761 * Stamps have been negotiated, then an MTU of 1500 bytes
762 * results in a TCP Data Payload of 1448 bytes which, as
763 * above, is a multiple of 8 bytes ...
765 for (i = 0; i < NMTUS; i++)
766 if (adap->params.mtus[i] == 1492) {
767 adap->params.mtus[i] = 1488;
771 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
774 t4_init_sge_params(adap);
775 t4_init_tp_params(adap);
777 adap->params.drv_memwin = MEMWIN_NIC;
778 adap->flags |= FW_OK;
779 dev_debug(adap, "%s: returning zero..\n", __func__);
783 * Something bad happened. If a command timed out or failed with EIO
784 * FW does not operate within its spec or something catastrophic
785 * happened to HW/FW, stop issuing commands.
788 if (ret != -ETIMEDOUT && ret != -EIO)
789 t4_fw_bye(adap, adap->mbox);
794 * t4_os_portmod_changed - handle port module changes
795 * @adap: the adapter associated with the module change
796 * @port_id: the port index whose module status has changed
798 * This is the OS-dependent handler for port module changes. It is
799 * invoked when a port module is removed or inserted for any OS-specific
802 void t4_os_portmod_changed(const struct adapter *adap, int port_id)
804 static const char * const mod_str[] = {
805 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
808 const struct port_info *pi = &adap->port[port_id];
810 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
811 dev_info(adap, "Port%d: port module unplugged\n", pi->port_id);
812 else if (pi->mod_type < ARRAY_SIZE(mod_str))
813 dev_info(adap, "Port%d: %s port module inserted\n", pi->port_id,
814 mod_str[pi->mod_type]);
815 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
816 dev_info(adap, "Port%d: unsupported optical port module inserted\n",
818 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
819 dev_info(adap, "Port%d: unknown port module inserted, forcing TWINAX\n",
821 else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR)
822 dev_info(adap, "Port%d: transceiver module error\n",
825 dev_info(adap, "Port%d: unknown module type %d inserted\n",
826 pi->port_id, pi->mod_type);
830 * link_start - enable a port
831 * @dev: the port to enable
833 * Performs the MAC and PHY actions needed to enable a port.
835 int link_start(struct port_info *pi)
837 struct adapter *adapter = pi->adapter;
841 * We do not set address filters and promiscuity here, the stack does
842 * that step explicitly.
844 ret = t4_set_rxmode(adapter, adapter->mbox, pi->viid, 1500, -1, -1,
847 ret = t4_change_mac(adapter, adapter->mbox, pi->viid,
849 (u8 *)&pi->eth_dev->data->mac_addrs[0],
852 pi->xact_addr_filt = ret;
857 ret = t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,
861 * Enabling a Virtual Interface can result in an interrupt
862 * during the processing of the VI Enable command and, in some
863 * paths, result in an attempt to issue another command in the
864 * interrupt context. Thus, we disable interrupts during the
865 * course of the VI Enable command ...
867 ret = t4_enable_vi_params(adapter, adapter->mbox, pi->viid,
874 * cxgb4_write_rss - write the RSS table for a given port
876 * @queues: array of queue indices for RSS
878 * Sets up the portion of the HW RSS table for the port's VI to distribute
879 * packets to the Rx queues in @queues.
881 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues)
885 struct adapter *adapter = pi->adapter;
886 const struct sge_eth_rxq *rxq;
888 /* Should never be called before setting up sge eth rx queues */
889 BUG_ON(!(adapter->flags & FULL_INIT_DONE));
891 rxq = &adapter->sge.ethrxq[pi->first_qset];
892 rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0);
896 /* map the queue indices to queue ids */
897 for (i = 0; i < pi->rss_size; i++, queues++)
898 rss[i] = rxq[*queues].rspq.abs_id;
900 err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0,
901 pi->rss_size, rss, pi->rss_size);
903 * If Tunnel All Lookup isn't specified in the global RSS
904 * Configuration, then we need to specify a default Ingress
905 * Queue for any ingress packets which aren't hashed. We'll
906 * use our first ingress queue ...
909 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,
910 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN |
911 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN |
912 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
913 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN |
914 F_FW_RSS_VI_CONFIG_CMD_UDPEN,
921 * setup_rss - configure RSS
922 * @adapter: the adapter
924 * Sets up RSS to distribute packets to multiple receive queues. We
925 * configure the RSS CPU lookup table to distribute to the number of HW
926 * receive queues, and the response queue lookup table to narrow that
927 * down to the response queues actually configured for each port.
928 * We always configure the RSS mapping for all ports since the mapping
929 * table has plenty of entries.
931 int setup_rss(struct port_info *pi)
934 struct adapter *adapter = pi->adapter;
936 dev_debug(adapter, "%s: pi->rss_size = %u; pi->n_rx_qsets = %u\n",
937 __func__, pi->rss_size, pi->n_rx_qsets);
939 if (!pi->flags & PORT_RSS_DONE) {
940 if (adapter->flags & FULL_INIT_DONE) {
941 /* Fill default values with equal distribution */
942 for (j = 0; j < pi->rss_size; j++)
943 pi->rss[j] = j % pi->n_rx_qsets;
945 err = cxgb4_write_rss(pi, pi->rss);
948 pi->flags |= PORT_RSS_DONE;
955 * Enable NAPI scheduling and interrupt generation for all Rx queues.
957 static void enable_rx(struct adapter *adap)
959 struct sge *s = &adap->sge;
960 struct sge_rspq *q = &s->fw_evtq;
963 /* 0-increment GTS to start the timer and enable interrupts */
964 t4_write_reg(adap, MYPF_REG(A_SGE_PF_GTS),
965 V_SEINTARM(q->intr_params) |
966 V_INGRESSQID(q->cntxt_id));
968 for_each_port(adap, i) {
969 const struct port_info *pi = &adap->port[i];
970 struct rte_eth_dev *eth_dev = pi->eth_dev;
972 for (j = 0; j < eth_dev->data->nb_rx_queues; j++) {
973 q = eth_dev->data->rx_queues[j];
976 * 0-increment GTS to start the timer and enable
979 t4_write_reg(adap, MYPF_REG(A_SGE_PF_GTS),
980 V_SEINTARM(q->intr_params) |
981 V_INGRESSQID(q->cntxt_id));
987 * cxgb_up - enable the adapter
988 * @adap: adapter being enabled
990 * Called when the first port is enabled, this function performs the
991 * actions necessary to make an adapter operational, such as completing
992 * the initialization of HW modules, and enabling interrupts.
994 int cxgbe_up(struct adapter *adap)
997 t4_sge_tx_monitor_start(adap);
998 t4_intr_enable(adap);
999 adap->flags |= FULL_INIT_DONE;
1001 /* TODO: deadman watchdog ?? */
1008 int cxgbe_down(struct port_info *pi)
1010 struct adapter *adapter = pi->adapter;
1013 err = t4_enable_vi(adapter, adapter->mbox, pi->viid, false, false);
1015 dev_err(adapter, "%s: disable_vi failed: %d\n", __func__, err);
1019 t4_reset_link_config(adapter, pi->port_id);
1024 * Release resources when all the ports have been stopped.
1026 void cxgbe_close(struct adapter *adapter)
1028 struct port_info *pi;
1031 if (adapter->flags & FULL_INIT_DONE) {
1032 t4_intr_disable(adapter);
1033 t4_sge_tx_monitor_stop(adapter);
1034 t4_free_sge_resources(adapter);
1035 for_each_port(adapter, i) {
1036 pi = adap2pinfo(adapter, i);
1038 t4_free_vi(adapter, adapter->mbox,
1039 adapter->pf, 0, pi->viid);
1040 rte_free(pi->eth_dev->data->mac_addrs);
1042 adapter->flags &= ~FULL_INIT_DONE;
1045 if (adapter->flags & FW_OK)
1046 t4_fw_bye(adapter, adapter->mbox);
1049 int cxgbe_probe(struct adapter *adapter)
1051 struct port_info *pi;
1055 func = G_SOURCEPF(t4_read_reg(adapter, A_PL_WHOAMI));
1056 adapter->mbox = func;
1059 t4_os_lock_init(&adapter->mbox_lock);
1060 TAILQ_INIT(&adapter->mbox_list);
1062 err = t4_prep_adapter(adapter);
1066 setup_memwin(adapter);
1067 err = adap_init0(adapter);
1069 dev_err(adapter, "%s: Adapter initialization failed, error %d\n",
1074 if (!is_t4(adapter->params.chip)) {
1076 * The userspace doorbell BAR is split evenly into doorbell
1077 * regions, each associated with an egress queue. If this
1078 * per-queue region is large enough (at least UDBS_SEG_SIZE)
1079 * then it can be used to submit a tx work request with an
1080 * implied doorbell. Enable write combining on the BAR if
1081 * there is room for such work requests.
1083 int s_qpp, qpp, num_seg;
1085 s_qpp = (S_QUEUESPERPAGEPF0 +
1086 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) *
1088 qpp = 1 << ((t4_read_reg(adapter,
1089 A_SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp)
1090 & M_QUEUESPERPAGEPF0);
1091 num_seg = PAGE_SIZE / UDBS_SEG_SIZE;
1093 dev_warn(adapter, "Incorrect SGE EGRESS QUEUES_PER_PAGE configuration, continuing in debug mode\n");
1095 adapter->bar2 = (void *)adapter->pdev->mem_resource[2].addr;
1096 if (!adapter->bar2) {
1097 dev_err(adapter, "cannot map device bar2 region\n");
1101 t4_write_reg(adapter, A_SGE_STAT_CFG, V_STATSOURCE_T5(7) |
1105 for_each_port(adapter, i) {
1106 char name[RTE_ETH_NAME_MAX_LEN];
1107 struct rte_eth_dev_data *data = NULL;
1108 const unsigned int numa_node = rte_socket_id();
1110 pi = &adapter->port[i];
1111 pi->adapter = adapter;
1112 pi->xact_addr_filt = -1;
1115 snprintf(name, sizeof(name), "cxgbe%d",
1116 adapter->eth_dev->data->port_id + i);
1119 /* First port is already allocated by DPDK */
1120 pi->eth_dev = adapter->eth_dev;
1125 * now do all data allocation - for eth_dev structure,
1126 * and internal (private) data for the remaining ports
1129 /* reserve an ethdev entry */
1130 pi->eth_dev = rte_eth_dev_allocate(name, RTE_ETH_DEV_PCI);
1134 data = rte_zmalloc_socket(name, sizeof(*data), 0, numa_node);
1138 data->port_id = adapter->eth_dev->data->port_id + i;
1140 pi->eth_dev->data = data;
1143 pi->eth_dev->pci_dev = adapter->pdev;
1144 pi->eth_dev->data->dev_private = pi;
1145 pi->eth_dev->driver = adapter->eth_dev->driver;
1146 pi->eth_dev->dev_ops = adapter->eth_dev->dev_ops;
1147 pi->eth_dev->tx_pkt_burst = adapter->eth_dev->tx_pkt_burst;
1148 pi->eth_dev->rx_pkt_burst = adapter->eth_dev->rx_pkt_burst;
1149 TAILQ_INIT(&pi->eth_dev->link_intr_cbs);
1151 pi->eth_dev->data->mac_addrs = rte_zmalloc(name,
1153 if (!pi->eth_dev->data->mac_addrs) {
1154 dev_err(adapter, "%s: Mem allocation failed for storing mac addr, aborting\n",
1161 if (adapter->flags & FW_OK) {
1162 err = t4_port_init(adapter, adapter->mbox, adapter->pf, 0);
1164 dev_err(adapter, "%s: t4_port_init failed with err %d\n",
1170 cfg_queues(adapter->eth_dev);
1172 print_port_info(adapter);
1174 err = init_rss(adapter);
1181 for_each_port(adapter, i) {
1182 pi = adap2pinfo(adapter, i);
1184 t4_free_vi(adapter, adapter->mbox, adapter->pf,
1186 /* Skip first port since it'll be de-allocated by DPDK */
1189 if (pi->eth_dev->data)
1190 rte_free(pi->eth_dev->data);
1193 if (adapter->flags & FW_OK)
1194 t4_fw_bye(adapter, adapter->mbox);