drivers/net/cxgbe/cxgbe_main.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Chelsio Communications.
   3  * All rights reserved.
   4  */
   5
   6 #include <sys/queue.h>
   7 #include <stdio.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <string.h>
  11 #include <unistd.h>
  12 #include <stdarg.h>
  13 #include <inttypes.h>
  14 #include <netinet/in.h>
  15
  16 #include <rte_byteorder.h>
  17 #include <rte_common.h>
  18 #include <rte_cycles.h>
  19 #include <rte_interrupts.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_pci.h>
  23 #include <rte_atomic.h>
  24 #include <rte_branch_prediction.h>
  25 #include <rte_memory.h>
  26 #include <rte_tailq.h>
  27 #include <rte_eal.h>
  28 #include <rte_alarm.h>
  29 #include <rte_ether.h>
  30 #include <rte_ethdev_driver.h>
  31 #include <rte_ethdev_pci.h>
  32 #include <rte_random.h>
  33 #include <rte_dev.h>
  34 #include <rte_kvargs.h>
  35
  36 #include "common.h"
  37 #include "t4_regs.h"
  38 #include "t4_msg.h"
  39 #include "cxgbe.h"
  40
  41 /**
  42  * Allocate a chunk of memory. The allocated memory is cleared.
  43  */
  44 void *t4_alloc_mem(size_t size)
  45 {
  46         return rte_zmalloc(NULL, size, 0);
  47 }
  48
  49 /**
  50  * Free memory allocated through t4_alloc_mem().
  51  */
  52 void t4_free_mem(void *addr)
  53 {
  54         rte_free(addr);
  55 }
  56
  57 /*
  58  * Response queue handler for the FW event queue.
  59  */
  60 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
  61                           __rte_unused const struct pkt_gl *gl)
  62 {
  63         u8 opcode = ((const struct rss_header *)rsp)->opcode;
  64
  65         rsp++;                                          /* skip RSS header */
  66
  67         /*
  68          * FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
  69          */
  70         if (unlikely(opcode == CPL_FW4_MSG &&
  71                      ((const struct cpl_fw4_msg *)rsp)->type ==
  72                       FW_TYPE_RSSCPL)) {
  73                 rsp++;
  74                 opcode = ((const struct rss_header *)rsp)->opcode;
  75                 rsp++;
  76                 if (opcode != CPL_SGE_EGR_UPDATE) {
  77                         dev_err(q->adapter, "unexpected FW4/CPL %#x on FW event queue\n",
  78                                 opcode);
  79                         goto out;
  80                 }
  81         }
  82
  83         if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
  84                 /* do nothing */
  85         } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
  86                 const struct cpl_fw6_msg *msg = (const void *)rsp;
  87
  88                 t4_handle_fw_rpl(q->adapter, msg->data);
  89         } else {
  90                 dev_err(adapter, "unexpected CPL %#x on FW event queue\n",
  91                         opcode);
  92         }
  93 out:
  94         return 0;
  95 }
  96
  97 /**
  98  * Setup sge control queues to pass control information.
  99  */
 100 int setup_sge_ctrl_txq(struct adapter *adapter)
 101 {
 102         struct sge *s = &adapter->sge;
 103         int err = 0, i = 0;
 104
 105         for_each_port(adapter, i) {
 106                 char name[RTE_ETH_NAME_MAX_LEN];
 107                 struct sge_ctrl_txq *q = &s->ctrlq[i];
 108
 109                 q->q.size = 1024;
 110                 err = t4_sge_alloc_ctrl_txq(adapter, q,
 111                                             adapter->eth_dev,  i,
 112                                             s->fw_evtq.cntxt_id,
 113                                             rte_socket_id());
 114                 if (err) {
 115                         dev_err(adapter, "Failed to alloc ctrl txq. Err: %d",
 116                                 err);
 117                         goto out;
 118                 }
 119                 snprintf(name, sizeof(name), "cxgbe_ctrl_pool_%d", i);
 120                 q->mb_pool = rte_pktmbuf_pool_create(name, s->ctrlq[i].q.size,
 121                                                      RTE_CACHE_LINE_SIZE,
 122                                                      RTE_MBUF_PRIV_ALIGN,
 123                                                      RTE_MBUF_DEFAULT_BUF_SIZE,
 124                                                      SOCKET_ID_ANY);
 125                 if (!q->mb_pool) {
 126                         dev_err(adapter, "Can't create ctrl pool for port: %d",
 127                                 i);
 128                         err = -ENOMEM;
 129                         goto out;
 130                 }
 131         }
 132         return 0;
 133 out:
 134         t4_free_sge_resources(adapter);
 135         return err;
 136 }
 137
 138 int setup_sge_fwevtq(struct adapter *adapter)
 139 {
 140         struct sge *s = &adapter->sge;
 141         int err = 0;
 142         int msi_idx = 0;
 143
 144         err = t4_sge_alloc_rxq(adapter, &s->fw_evtq, true, adapter->eth_dev,
 145                                msi_idx, NULL, fwevtq_handler, -1, NULL, 0,
 146                                rte_socket_id());
 147         return err;
 148 }
 149
 150 static int closest_timer(const struct sge *s, int time)
 151 {
 152         unsigned int i, match = 0;
 153         int delta, min_delta = INT_MAX;
 154
 155         for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
 156                 delta = time - s->timer_val[i];
 157                 if (delta < 0)
 158                         delta = -delta;
 159                 if (delta < min_delta) {
 160                         min_delta = delta;
 161                         match = i;
 162                 }
 163         }
 164         return match;
 165 }
 166
 167 static int closest_thres(const struct sge *s, int thres)
 168 {
 169         unsigned int i, match = 0;
 170         int delta, min_delta = INT_MAX;
 171
 172         for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
 173                 delta = thres - s->counter_val[i];
 174                 if (delta < 0)
 175                         delta = -delta;
 176                 if (delta < min_delta) {
 177                         min_delta = delta;
 178                         match = i;
 179                 }
 180         }
 181         return match;
 182 }
 183
 184 /**
 185  * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters
 186  * @q: the Rx queue
 187  * @us: the hold-off time in us, or 0 to disable timer
 188  * @cnt: the hold-off packet count, or 0 to disable counter
 189  *
 190  * Sets an Rx queue's interrupt hold-off time and packet count.  At least
 191  * one of the two needs to be enabled for the queue to generate interrupts.
 192  */
 193 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
 194                                unsigned int cnt)
 195 {
 196         struct adapter *adap = q->adapter;
 197         unsigned int timer_val;
 198
 199         if (cnt) {
 200                 int err;
 201                 u32 v, new_idx;
 202
 203                 new_idx = closest_thres(&adap->sge, cnt);
 204                 if (q->desc && q->pktcnt_idx != new_idx) {
 205                         /* the queue has already been created, update it */
 206                         v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
 207                             V_FW_PARAMS_PARAM_X(
 208                             FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
 209                             V_FW_PARAMS_PARAM_YZ(q->cntxt_id);
 210                         err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
 211                                             &v, &new_idx);
 212                         if (err)
 213                                 return err;
 214                 }
 215                 q->pktcnt_idx = new_idx;
 216         }
 217
 218         timer_val = (us == 0) ? X_TIMERREG_RESTART_COUNTER :
 219                                 closest_timer(&adap->sge, us);
 220
 221         if ((us | cnt) == 0)
 222                 q->intr_params = V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX);
 223         else
 224                 q->intr_params = V_QINTR_TIMER_IDX(timer_val) |
 225                                  V_QINTR_CNT_EN(cnt > 0);
 226         return 0;
 227 }
 228
 229 /**
 230  * Free TID tables.
 231  */
 232 static void tid_free(struct tid_info *t)
 233 {
 234         if (t->tid_tab) {
 235                 if (t->ftid_bmap)
 236                         rte_bitmap_free(t->ftid_bmap);
 237
 238                 if (t->ftid_bmap_array)
 239                         t4_os_free(t->ftid_bmap_array);
 240
 241                 t4_os_free(t->tid_tab);
 242         }
 243
 244         memset(t, 0, sizeof(struct tid_info));
 245 }
 246
 247 /**
 248  * Allocate and initialize the TID tables.  Returns 0 on success.
 249  */
 250 static int tid_init(struct tid_info *t)
 251 {
 252         size_t size;
 253         unsigned int ftid_bmap_size;
 254         unsigned int max_ftids = t->nftids;
 255
 256         ftid_bmap_size = rte_bitmap_get_memory_footprint(t->nftids);
 257         size = t->ntids * sizeof(*t->tid_tab) +
 258                 max_ftids * sizeof(*t->ftid_tab);
 259
 260         t->tid_tab = t4_os_alloc(size);
 261         if (!t->tid_tab)
 262                 return -ENOMEM;
 263
 264         t->ftid_tab = (struct filter_entry *)&t->tid_tab[t->ntids];
 265         t->ftid_bmap_array = t4_os_alloc(ftid_bmap_size);
 266         if (!t->ftid_bmap_array) {
 267                 tid_free(t);
 268                 return -ENOMEM;
 269         }
 270
 271         t4_os_lock_init(&t->ftid_lock);
 272         t->ftid_bmap = rte_bitmap_init(t->nftids, t->ftid_bmap_array,
 273                                        ftid_bmap_size);
 274         if (!t->ftid_bmap) {
 275                 tid_free(t);
 276                 return -ENOMEM;
 277         }
 278
 279         return 0;
 280 }
 281
 282 static inline bool is_x_1g_port(const struct link_config *lc)
 283 {
 284         return (lc->pcaps & FW_PORT_CAP32_SPEED_1G) != 0;
 285 }
 286
 287 static inline bool is_x_10g_port(const struct link_config *lc)
 288 {
 289         unsigned int speeds, high_speeds;
 290
 291         speeds = V_FW_PORT_CAP32_SPEED(G_FW_PORT_CAP32_SPEED(lc->pcaps));
 292         high_speeds = speeds &
 293                       ~(FW_PORT_CAP32_SPEED_100M | FW_PORT_CAP32_SPEED_1G);
 294
 295         return high_speeds != 0;
 296 }
 297
 298 inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
 299                       unsigned int us, unsigned int cnt,
 300                       unsigned int size, unsigned int iqe_size)
 301 {
 302         q->adapter = adap;
 303         cxgb4_set_rspq_intr_params(q, us, cnt);
 304         q->iqe_len = iqe_size;
 305         q->size = size;
 306 }
 307
 308 int cfg_queue_count(struct rte_eth_dev *eth_dev)
 309 {
 310         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 311         struct adapter *adap = pi->adapter;
 312         struct sge *s = &adap->sge;
 313         unsigned int max_queues = s->max_ethqsets / adap->params.nports;
 314
 315         if ((eth_dev->data->nb_rx_queues < 1) ||
 316             (eth_dev->data->nb_tx_queues < 1))
 317                 return -EINVAL;
 318
 319         if ((eth_dev->data->nb_rx_queues > max_queues) ||
 320             (eth_dev->data->nb_tx_queues > max_queues))
 321                 return -EINVAL;
 322
 323         if (eth_dev->data->nb_rx_queues > pi->rss_size)
 324                 return -EINVAL;
 325
 326         /* We must configure RSS, since config has changed*/
 327         pi->flags &= ~PORT_RSS_DONE;
 328
 329         pi->n_rx_qsets = eth_dev->data->nb_rx_queues;
 330         pi->n_tx_qsets = eth_dev->data->nb_tx_queues;
 331
 332         return 0;
 333 }
 334
 335 void cfg_queues(struct rte_eth_dev *eth_dev)
 336 {
 337         struct rte_config *config = rte_eal_get_configuration();
 338         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 339         struct adapter *adap = pi->adapter;
 340         struct sge *s = &adap->sge;
 341         unsigned int i, nb_ports = 0, qidx = 0;
 342         unsigned int q_per_port = 0;
 343
 344         if (!(adap->flags & CFG_QUEUES)) {
 345                 for_each_port(adap, i) {
 346                         struct port_info *tpi = adap2pinfo(adap, i);
 347
 348                         nb_ports += (is_x_10g_port(&tpi->link_cfg)) ||
 349                                      is_x_1g_port(&tpi->link_cfg) ? 1 : 0;
 350                 }
 351
 352                 /*
 353                  * We default up to # of cores queues per 1G/10G port.
 354                  */
 355                 if (nb_ports)
 356                         q_per_port = (MAX_ETH_QSETS -
 357                                      (adap->params.nports - nb_ports)) /
 358                                      nb_ports;
 359
 360                 if (q_per_port > config->lcore_count)
 361                         q_per_port = config->lcore_count;
 362
 363                 for_each_port(adap, i) {
 364                         struct port_info *pi = adap2pinfo(adap, i);
 365
 366                         pi->first_qset = qidx;
 367
 368                         /* Initially n_rx_qsets == n_tx_qsets */
 369                         pi->n_rx_qsets = (is_x_10g_port(&pi->link_cfg) ||
 370                                           is_x_1g_port(&pi->link_cfg)) ?
 371                                           q_per_port : 1;
 372                         pi->n_tx_qsets = pi->n_rx_qsets;
 373
 374                         if (pi->n_rx_qsets > pi->rss_size)
 375                                 pi->n_rx_qsets = pi->rss_size;
 376
 377                         qidx += pi->n_rx_qsets;
 378                 }
 379
 380                 s->max_ethqsets = qidx;
 381
 382                 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
 383                         struct sge_eth_rxq *r = &s->ethrxq[i];
 384
 385                         init_rspq(adap, &r->rspq, 5, 32, 1024, 64);
 386                         r->usembufs = 1;
 387                         r->fl.size = (r->usembufs ? 1024 : 72);
 388                 }
 389
 390                 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
 391                         s->ethtxq[i].q.size = 1024;
 392
 393                 init_rspq(adap, &adap->sge.fw_evtq, 0, 0, 1024, 64);
 394                 adap->flags |= CFG_QUEUES;
 395         }
 396 }
 397
 398 void cxgbe_stats_get(struct port_info *pi, struct port_stats *stats)
 399 {
 400         t4_get_port_stats_offset(pi->adapter, pi->tx_chan, stats,
 401                                  &pi->stats_base);
 402 }
 403
 404 void cxgbe_stats_reset(struct port_info *pi)
 405 {
 406         t4_clr_port_stats(pi->adapter, pi->tx_chan);
 407 }
 408
 409 static void setup_memwin(struct adapter *adap)
 410 {
 411         u32 mem_win0_base;
 412
 413         /* For T5, only relative offset inside the PCIe BAR is passed */
 414         mem_win0_base = MEMWIN0_BASE;
 415
 416         /*
 417          * Set up memory window for accessing adapter memory ranges.  (Read
 418          * back MA register to ensure that changes propagate before we attempt
 419          * to use the new values.)
 420          */
 421         t4_write_reg(adap,
 422                      PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN,
 423                                          MEMWIN_NIC),
 424                      mem_win0_base | V_BIR(0) |
 425                      V_WINDOW(ilog2(MEMWIN0_APERTURE) - X_WINDOW_SHIFT));
 426         t4_read_reg(adap,
 427                     PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN,
 428                                         MEMWIN_NIC));
 429 }
 430
 431 int init_rss(struct adapter *adap)
 432 {
 433         unsigned int i;
 434
 435         if (is_pf4(adap)) {
 436                 int err;
 437
 438                 err = t4_init_rss_mode(adap, adap->mbox);
 439                 if (err)
 440                         return err;
 441         }
 442
 443         for_each_port(adap, i) {
 444                 struct port_info *pi = adap2pinfo(adap, i);
 445
 446                 pi->rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0);
 447                 if (!pi->rss)
 448                         return -ENOMEM;
 449
 450                 pi->rss_hf = CXGBE_RSS_HF_ALL;
 451         }
 452         return 0;
 453 }
 454
 455 /**
 456  * Dump basic information about the adapter.
 457  */
 458 void print_adapter_info(struct adapter *adap)
 459 {
 460         /**
 461          * Hardware/Firmware/etc. Version/Revision IDs.
 462          */
 463         t4_dump_version_info(adap);
 464 }
 465
 466 void print_port_info(struct adapter *adap)
 467 {
 468         int i;
 469         char buf[80];
 470         struct rte_pci_addr *loc = &adap->pdev->addr;
 471
 472         for_each_port(adap, i) {
 473                 const struct port_info *pi = adap2pinfo(adap, i);
 474                 char *bufp = buf;
 475
 476                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100M)
 477                         bufp += sprintf(bufp, "100M/");
 478                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_1G)
 479                         bufp += sprintf(bufp, "1G/");
 480                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_10G)
 481                         bufp += sprintf(bufp, "10G/");
 482                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_25G)
 483                         bufp += sprintf(bufp, "25G/");
 484                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_40G)
 485                         bufp += sprintf(bufp, "40G/");
 486                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_50G)
 487                         bufp += sprintf(bufp, "50G/");
 488                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100G)
 489                         bufp += sprintf(bufp, "100G/");
 490                 if (bufp != buf)
 491                         --bufp;
 492                 sprintf(bufp, "BASE-%s",
 493                         t4_get_port_type_description(
 494                                         (enum fw_port_type)pi->port_type));
 495
 496                 dev_info(adap,
 497                          " " PCI_PRI_FMT " Chelsio rev %d %s %s\n",
 498                          loc->domain, loc->bus, loc->devid, loc->function,
 499                          CHELSIO_CHIP_RELEASE(adap->params.chip), buf,
 500                          (adap->flags & USING_MSIX) ? " MSI-X" :
 501                          (adap->flags & USING_MSI) ? " MSI" : "");
 502         }
 503 }
 504
 505 static int
 506 check_devargs_handler(__rte_unused const char *key, const char *value,
 507                       __rte_unused void *opaque)
 508 {
 509         if (strcmp(value, "1"))
 510                 return -1;
 511
 512         return 0;
 513 }
 514
 515 int cxgbe_get_devargs(struct rte_devargs *devargs, const char *key)
 516 {
 517         struct rte_kvargs *kvlist;
 518
 519         if (!devargs)
 520                 return 0;
 521
 522         kvlist = rte_kvargs_parse(devargs->args, NULL);
 523         if (!kvlist)
 524                 return 0;
 525
 526         if (!rte_kvargs_count(kvlist, key)) {
 527                 rte_kvargs_free(kvlist);
 528                 return 0;
 529         }
 530
 531         if (rte_kvargs_process(kvlist, key,
 532                                check_devargs_handler, NULL) < 0) {
 533                 rte_kvargs_free(kvlist);
 534                 return 0;
 535         }
 536         rte_kvargs_free(kvlist);
 537
 538         return 1;
 539 }
 540
 541 static void configure_vlan_types(struct adapter *adapter)
 542 {
 543         struct rte_pci_device *pdev = adapter->pdev;
 544         int i;
 545
 546         for_each_port(adapter, i) {
 547                 /* OVLAN Type 0x88a8 */
 548                 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN0),
 549                                  V_OVLAN_MASK(M_OVLAN_MASK) |
 550                                  V_OVLAN_ETYPE(M_OVLAN_ETYPE),
 551                                  V_OVLAN_MASK(M_OVLAN_MASK) |
 552                                  V_OVLAN_ETYPE(0x88a8));
 553                 /* OVLAN Type 0x9100 */
 554                 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN1),
 555                                  V_OVLAN_MASK(M_OVLAN_MASK) |
 556                                  V_OVLAN_ETYPE(M_OVLAN_ETYPE),
 557                                  V_OVLAN_MASK(M_OVLAN_MASK) |
 558                                  V_OVLAN_ETYPE(0x9100));
 559                 /* OVLAN Type 0x8100 */
 560                 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN2),
 561                                  V_OVLAN_MASK(M_OVLAN_MASK) |
 562                                  V_OVLAN_ETYPE(M_OVLAN_ETYPE),
 563                                  V_OVLAN_MASK(M_OVLAN_MASK) |
 564                                  V_OVLAN_ETYPE(0x8100));
 565
 566                 /* IVLAN 0X8100 */
 567                 t4_set_reg_field(adapter, MPS_PORT_RX_IVLAN(i),
 568                                  V_IVLAN_ETYPE(M_IVLAN_ETYPE),
 569                                  V_IVLAN_ETYPE(0x8100));
 570
 571                 t4_set_reg_field(adapter, MPS_PORT_RX_CTL(i),
 572                                  F_OVLAN_EN0 | F_OVLAN_EN1 |
 573                                  F_OVLAN_EN2 | F_IVLAN_EN,
 574                                  F_OVLAN_EN0 | F_OVLAN_EN1 |
 575                                  F_OVLAN_EN2 | F_IVLAN_EN);
 576         }
 577
 578         if (cxgbe_get_devargs(pdev->device.devargs, CXGBE_DEVARG_KEEP_OVLAN))
 579                 t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG,
 580                                        V_RM_OVLAN(1), V_RM_OVLAN(0));
 581 }
 582
 583 static void configure_pcie_ext_tag(struct adapter *adapter)
 584 {
 585         u16 v;
 586         int pos = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
 587
 588         if (!pos)
 589                 return;
 590
 591         if (pos > 0) {
 592                 t4_os_pci_read_cfg2(adapter, pos + PCI_EXP_DEVCTL, &v);
 593                 v |= PCI_EXP_DEVCTL_EXT_TAG;
 594                 t4_os_pci_write_cfg2(adapter, pos + PCI_EXP_DEVCTL, v);
 595                 if (is_t6(adapter->params.chip)) {
 596                         t4_set_reg_field(adapter, A_PCIE_CFG2,
 597                                          V_T6_TOTMAXTAG(M_T6_TOTMAXTAG),
 598                                          V_T6_TOTMAXTAG(7));
 599                         t4_set_reg_field(adapter, A_PCIE_CMD_CFG,
 600                                          V_T6_MINTAG(M_T6_MINTAG),
 601                                          V_T6_MINTAG(8));
 602                 } else {
 603                         t4_set_reg_field(adapter, A_PCIE_CFG2,
 604                                          V_TOTMAXTAG(M_TOTMAXTAG),
 605                                          V_TOTMAXTAG(3));
 606                         t4_set_reg_field(adapter, A_PCIE_CMD_CFG,
 607                                          V_MINTAG(M_MINTAG),
 608                                          V_MINTAG(8));
 609                 }
 610         }
 611 }
 612
 613 /*
 614  * Tweak configuration based on system architecture, etc.  Most of these have
 615  * defaults assigned to them by Firmware Configuration Files (if we're using
 616  * them) but need to be explicitly set if we're using hard-coded
 617  * initialization. So these are essentially common tweaks/settings for
 618  * Configuration Files and hard-coded initialization ...
 619  */
 620 static int adap_init0_tweaks(struct adapter *adapter)
 621 {
 622         u8 rx_dma_offset;
 623
 624         /*
 625          * Fix up various Host-Dependent Parameters like Page Size, Cache
 626          * Line Size, etc.  The firmware default is for a 4KB Page Size and
 627          * 64B Cache Line Size ...
 628          */
 629         t4_fixup_host_params_compat(adapter, CXGBE_PAGE_SIZE, L1_CACHE_BYTES,
 630                                     T5_LAST_REV);
 631
 632         /*
 633          * Keep the chip default offset to deliver Ingress packets into our
 634          * DMA buffers to zero
 635          */
 636         rx_dma_offset = 0;
 637         t4_set_reg_field(adapter, A_SGE_CONTROL, V_PKTSHIFT(M_PKTSHIFT),
 638                          V_PKTSHIFT(rx_dma_offset));
 639
 640         t4_set_reg_field(adapter, A_SGE_FLM_CFG,
 641                          V_CREDITCNT(M_CREDITCNT) | M_CREDITCNTPACKING,
 642                          V_CREDITCNT(3) | V_CREDITCNTPACKING(1));
 643
 644         t4_set_reg_field(adapter, A_SGE_INGRESS_RX_THRESHOLD,
 645                          V_THRESHOLD_3(M_THRESHOLD_3), V_THRESHOLD_3(32U));
 646
 647         t4_set_reg_field(adapter, A_SGE_CONTROL2, V_IDMAARBROUNDROBIN(1U),
 648                          V_IDMAARBROUNDROBIN(1U));
 649
 650         /*
 651          * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
 652          * adds the pseudo header itself.
 653          */
 654         t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG,
 655                                F_CSUM_HAS_PSEUDO_HDR, 0);
 656
 657         return 0;
 658 }
 659
 660 /*
 661  * Attempt to initialize the adapter via a Firmware Configuration File.
 662  */
 663 static int adap_init0_config(struct adapter *adapter, int reset)
 664 {
 665         struct fw_caps_config_cmd caps_cmd;
 666         unsigned long mtype = 0, maddr = 0;
 667         u32 finiver, finicsum, cfcsum;
 668         int ret;
 669         int config_issued = 0;
 670         int cfg_addr;
 671         char config_name[20];
 672
 673         /*
 674          * Reset device if necessary.
 675          */
 676         if (reset) {
 677                 ret = t4_fw_reset(adapter, adapter->mbox,
 678                                   F_PIORSTMODE | F_PIORST);
 679                 if (ret < 0) {
 680                         dev_warn(adapter, "Firmware reset failed, error %d\n",
 681                                  -ret);
 682                         goto bye;
 683                 }
 684         }
 685
 686         cfg_addr = t4_flash_cfg_addr(adapter);
 687         if (cfg_addr < 0) {
 688                 ret = cfg_addr;
 689                 dev_warn(adapter, "Finding address for firmware config file in flash failed, error %d\n",
 690                          -ret);
 691                 goto bye;
 692         }
 693
 694         strcpy(config_name, "On Flash");
 695         mtype = FW_MEMTYPE_CF_FLASH;
 696         maddr = cfg_addr;
 697
 698         /*
 699          * Issue a Capability Configuration command to the firmware to get it
 700          * to parse the Configuration File.  We don't use t4_fw_config_file()
 701          * because we want the ability to modify various features after we've
 702          * processed the configuration file ...
 703          */
 704         memset(&caps_cmd, 0, sizeof(caps_cmd));
 705         caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
 706                                            F_FW_CMD_REQUEST | F_FW_CMD_READ);
 707         caps_cmd.cfvalid_to_len16 =
 708                 cpu_to_be32(F_FW_CAPS_CONFIG_CMD_CFVALID |
 709                             V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
 710                             V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) |
 711                             FW_LEN16(caps_cmd));
 712         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
 713                          &caps_cmd);
 714         /*
 715          * If the CAPS_CONFIG failed with an ENOENT (for a Firmware
 716          * Configuration File in FLASH), our last gasp effort is to use the
 717          * Firmware Configuration File which is embedded in the firmware.  A
 718          * very few early versions of the firmware didn't have one embedded
 719          * but we can ignore those.
 720          */
 721         if (ret == -ENOENT) {
 722                 dev_info(adapter, "%s: Going for embedded config in firmware..\n",
 723                          __func__);
 724
 725                 memset(&caps_cmd, 0, sizeof(caps_cmd));
 726                 caps_cmd.op_to_write =
 727                         cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
 728                                     F_FW_CMD_REQUEST | F_FW_CMD_READ);
 729                 caps_cmd.cfvalid_to_len16 = cpu_to_be32(FW_LEN16(caps_cmd));
 730                 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
 731                                  sizeof(caps_cmd), &caps_cmd);
 732                 strcpy(config_name, "Firmware Default");
 733         }
 734
 735         config_issued = 1;
 736         if (ret < 0)
 737                 goto bye;
 738
 739         finiver = be32_to_cpu(caps_cmd.finiver);
 740         finicsum = be32_to_cpu(caps_cmd.finicsum);
 741         cfcsum = be32_to_cpu(caps_cmd.cfcsum);
 742         if (finicsum != cfcsum)
 743                 dev_warn(adapter, "Configuration File checksum mismatch: [fini] csum=%#x, computed csum=%#x\n",
 744                          finicsum, cfcsum);
 745
 746         /*
 747          * If we're a pure NIC driver then disable all offloading facilities.
 748          * This will allow the firmware to optimize aspects of the hardware
 749          * configuration which will result in improved performance.
 750          */
 751         caps_cmd.niccaps &= cpu_to_be16(~(FW_CAPS_CONFIG_NIC_HASHFILTER |
 752                                           FW_CAPS_CONFIG_NIC_ETHOFLD));
 753         caps_cmd.toecaps = 0;
 754         caps_cmd.iscsicaps = 0;
 755         caps_cmd.rdmacaps = 0;
 756         caps_cmd.fcoecaps = 0;
 757
 758         /*
 759          * And now tell the firmware to use the configuration we just loaded.
 760          */
 761         caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
 762                                            F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
 763         caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
 764         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
 765                          NULL);
 766         if (ret < 0) {
 767                 dev_warn(adapter, "Unable to finalize Firmware Capabilities %d\n",
 768                          -ret);
 769                 goto bye;
 770         }
 771
 772         /*
 773          * Tweak configuration based on system architecture, etc.
 774          */
 775         ret = adap_init0_tweaks(adapter);
 776         if (ret < 0) {
 777                 dev_warn(adapter, "Unable to do init0-tweaks %d\n", -ret);
 778                 goto bye;
 779         }
 780
 781         /*
 782          * And finally tell the firmware to initialize itself using the
 783          * parameters from the Configuration File.
 784          */
 785         ret = t4_fw_initialize(adapter, adapter->mbox);
 786         if (ret < 0) {
 787                 dev_warn(adapter, "Initializing Firmware failed, error %d\n",
 788                          -ret);
 789                 goto bye;
 790         }
 791
 792         /*
 793          * Return successfully and note that we're operating with parameters
 794          * not supplied by the driver, rather than from hard-wired
 795          * initialization constants buried in the driver.
 796          */
 797         dev_info(adapter,
 798                  "Successfully configured using Firmware Configuration File \"%s\", version %#x, computed checksum %#x\n",
 799                  config_name, finiver, cfcsum);
 800
 801         return 0;
 802
 803         /*
 804          * Something bad happened.  Return the error ...  (If the "error"
 805          * is that there's no Configuration File on the adapter we don't
 806          * want to issue a warning since this is fairly common.)
 807          */
 808 bye:
 809         if (config_issued && ret != -ENOENT)
 810                 dev_warn(adapter, "\"%s\" configuration file error %d\n",
 811                          config_name, -ret);
 812
 813         dev_debug(adapter, "%s: returning ret = %d ..\n", __func__, ret);
 814         return ret;
 815 }
 816
 817 static int adap_init0(struct adapter *adap)
 818 {
 819         struct fw_caps_config_cmd caps_cmd;
 820         int ret = 0;
 821         u32 v, port_vec;
 822         enum dev_state state;
 823         u32 params[7], val[7];
 824         int reset = 1;
 825         int mbox = adap->mbox;
 826
 827         /*
 828          * Contact FW, advertising Master capability.
 829          */
 830         ret = t4_fw_hello(adap, adap->mbox, adap->mbox, MASTER_MAY, &state);
 831         if (ret < 0) {
 832                 dev_err(adap, "%s: could not connect to FW, error %d\n",
 833                         __func__, -ret);
 834                 goto bye;
 835         }
 836
 837         CXGBE_DEBUG_MBOX(adap, "%s: adap->mbox = %d; ret = %d\n", __func__,
 838                          adap->mbox, ret);
 839
 840         if (ret == mbox)
 841                 adap->flags |= MASTER_PF;
 842
 843         if (state == DEV_STATE_INIT) {
 844                 /*
 845                  * Force halt and reset FW because a previous instance may have
 846                  * exited abnormally without properly shutting down
 847                  */
 848                 ret = t4_fw_halt(adap, adap->mbox, reset);
 849                 if (ret < 0) {
 850                         dev_err(adap, "Failed to halt. Exit.\n");
 851                         goto bye;
 852                 }
 853
 854                 ret = t4_fw_restart(adap, adap->mbox, reset);
 855                 if (ret < 0) {
 856                         dev_err(adap, "Failed to restart. Exit.\n");
 857                         goto bye;
 858                 }
 859                 state = (enum dev_state)((unsigned)state & ~DEV_STATE_INIT);
 860         }
 861
 862         t4_get_version_info(adap);
 863
 864         ret = t4_get_core_clock(adap, &adap->params.vpd);
 865         if (ret < 0) {
 866                 dev_err(adap, "%s: could not get core clock, error %d\n",
 867                         __func__, -ret);
 868                 goto bye;
 869         }
 870
 871         /*
 872          * If the firmware is initialized already (and we're not forcing a
 873          * master initialization), note that we're living with existing
 874          * adapter parameters.  Otherwise, it's time to try initializing the
 875          * adapter ...
 876          */
 877         if (state == DEV_STATE_INIT) {
 878                 dev_info(adap, "Coming up as %s: Adapter already initialized\n",
 879                          adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
 880         } else {
 881                 dev_info(adap, "Coming up as MASTER: Initializing adapter\n");
 882
 883                 ret = adap_init0_config(adap, reset);
 884                 if (ret == -ENOENT) {
 885                         dev_err(adap,
 886                                 "No Configuration File present on adapter. Using hard-wired configuration parameters.\n");
 887                         goto bye;
 888                 }
 889         }
 890         if (ret < 0) {
 891                 dev_err(adap, "could not initialize adapter, error %d\n", -ret);
 892                 goto bye;
 893         }
 894
 895         /* Find out what ports are available to us. */
 896         v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
 897             V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_PORTVEC);
 898         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec);
 899         if (ret < 0) {
 900                 dev_err(adap, "%s: failure in t4_query_params; error = %d\n",
 901                         __func__, ret);
 902                 goto bye;
 903         }
 904
 905         adap->params.nports = hweight32(port_vec);
 906         adap->params.portvec = port_vec;
 907
 908         dev_debug(adap, "%s: adap->params.nports = %u\n", __func__,
 909                   adap->params.nports);
 910
 911         /*
 912          * Give the SGE code a chance to pull in anything that it needs ...
 913          * Note that this must be called after we retrieve our VPD parameters
 914          * in order to know how to convert core ticks to seconds, etc.
 915          */
 916         ret = t4_sge_init(adap);
 917         if (ret < 0) {
 918                 dev_err(adap, "t4_sge_init failed with error %d\n",
 919                         -ret);
 920                 goto bye;
 921         }
 922
 923         /*
 924          * Grab some of our basic fundamental operating parameters.
 925          */
 926 #define FW_PARAM_DEV(param) \
 927         (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
 928          V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
 929
 930 #define FW_PARAM_PFVF(param) \
 931         (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
 932          V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param) |  \
 933          V_FW_PARAMS_PARAM_Y(0) | \
 934          V_FW_PARAMS_PARAM_Z(0))
 935
 936         params[0] = FW_PARAM_PFVF(FILTER_START);
 937         params[1] = FW_PARAM_PFVF(FILTER_END);
 938         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
 939         if (ret < 0)
 940                 goto bye;
 941         adap->tids.ftid_base = val[0];
 942         adap->tids.nftids = val[1] - val[0] + 1;
 943
 944         /*
 945          * Get device capabilities so we can determine what resources we need
 946          * to manage.
 947          */
 948         memset(&caps_cmd, 0, sizeof(caps_cmd));
 949         caps_cmd.op_to_write = htonl(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
 950                                      F_FW_CMD_REQUEST | F_FW_CMD_READ);
 951         caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
 952         ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
 953                          &caps_cmd);
 954         if (ret < 0)
 955                 goto bye;
 956
 957         /* query tid-related parameters */
 958         params[0] = FW_PARAM_DEV(NTID);
 959         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
 960                               params, val);
 961         if (ret < 0)
 962                 goto bye;
 963         adap->tids.ntids = val[0];
 964
 965         /* If we're running on newer firmware, let it know that we're
 966          * prepared to deal with encapsulated CPL messages.  Older
 967          * firmware won't understand this and we'll just get
 968          * unencapsulated messages ...
 969          */
 970         params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
 971         val[0] = 1;
 972         (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
 973
 974         /*
 975          * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
 976          * capability.  Earlier versions of the firmware didn't have the
 977          * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
 978          * permission to use ULPTX MEMWRITE DSGL.
 979          */
 980         if (is_t4(adap->params.chip)) {
 981                 adap->params.ulptx_memwrite_dsgl = false;
 982         } else {
 983                 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
 984                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
 985                                       1, params, val);
 986                 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
 987         }
 988
 989         /*
 990          * The MTU/MSS Table is initialized by now, so load their values.  If
 991          * we're initializing the adapter, then we'll make any modifications
 992          * we want to the MTU/MSS Table and also initialize the congestion
 993          * parameters.
 994          */
 995         t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
 996         if (state != DEV_STATE_INIT) {
 997                 int i;
 998
 999                 /*
1000                  * The default MTU Table contains values 1492 and 1500.
1001                  * However, for TCP, it's better to have two values which are
1002                  * a multiple of 8 +/- 4 bytes apart near this popular MTU.
1003                  * This allows us to have a TCP Data Payload which is a
1004                  * multiple of 8 regardless of what combination of TCP Options
1005                  * are in use (always a multiple of 4 bytes) which is
1006                  * important for performance reasons.  For instance, if no
1007                  * options are in use, then we have a 20-byte IP header and a
1008                  * 20-byte TCP header.  In this case, a 1500-byte MSS would
1009                  * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
1010                  * which is not a multiple of 8.  So using an MSS of 1488 in
1011                  * this case results in a TCP Data Payload of 1448 bytes which
1012                  * is a multiple of 8.  On the other hand, if 12-byte TCP Time
1013                  * Stamps have been negotiated, then an MTU of 1500 bytes
1014                  * results in a TCP Data Payload of 1448 bytes which, as
1015                  * above, is a multiple of 8 bytes ...
1016                  */
1017                 for (i = 0; i < NMTUS; i++)
1018                         if (adap->params.mtus[i] == 1492) {
1019                                 adap->params.mtus[i] = 1488;
1020                                 break;
1021                         }
1022
1023                 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
1024                              adap->params.b_wnd);
1025         }
1026         t4_init_sge_params(adap);
1027         t4_init_tp_params(adap);
1028         configure_pcie_ext_tag(adap);
1029         configure_vlan_types(adap);
1030
1031         adap->params.drv_memwin = MEMWIN_NIC;
1032         adap->flags |= FW_OK;
1033         dev_debug(adap, "%s: returning zero..\n", __func__);
1034         return 0;
1035
1036         /*
1037          * Something bad happened.  If a command timed out or failed with EIO
1038          * FW does not operate within its spec or something catastrophic
1039          * happened to HW/FW, stop issuing commands.
1040          */
1041 bye:
1042         if (ret != -ETIMEDOUT && ret != -EIO)
1043                 t4_fw_bye(adap, adap->mbox);
1044         return ret;
1045 }
1046
1047 /**
1048  * t4_os_portmod_changed - handle port module changes
1049  * @adap: the adapter associated with the module change
1050  * @port_id: the port index whose module status has changed
1051  *
1052  * This is the OS-dependent handler for port module changes.  It is
1053  * invoked when a port module is removed or inserted for any OS-specific
1054  * processing.
1055  */
1056 void t4_os_portmod_changed(const struct adapter *adap, int port_id)
1057 {
1058         static const char * const mod_str[] = {
1059                 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
1060         };
1061
1062         const struct port_info *pi = adap2pinfo(adap, port_id);
1063
1064         if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
1065                 dev_info(adap, "Port%d: port module unplugged\n", pi->port_id);
1066         else if (pi->mod_type < ARRAY_SIZE(mod_str))
1067                 dev_info(adap, "Port%d: %s port module inserted\n", pi->port_id,
1068                          mod_str[pi->mod_type]);
1069         else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
1070                 dev_info(adap, "Port%d: unsupported port module inserted\n",
1071                          pi->port_id);
1072         else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
1073                 dev_info(adap, "Port%d: unknown port module inserted\n",
1074                          pi->port_id);
1075         else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR)
1076                 dev_info(adap, "Port%d: transceiver module error\n",
1077                          pi->port_id);
1078         else
1079                 dev_info(adap, "Port%d: unknown module type %d inserted\n",
1080                          pi->port_id, pi->mod_type);
1081 }
1082
1083 inline bool force_linkup(struct adapter *adap)
1084 {
1085         struct rte_pci_device *pdev = adap->pdev;
1086
1087         if (is_pf4(adap))
1088                 return false;   /* force_linkup not required for pf driver*/
1089         if (!cxgbe_get_devargs(pdev->device.devargs,
1090                                CXGBE_DEVARG_FORCE_LINK_UP))
1091                 return false;
1092         return true;
1093 }
1094
1095 /**
1096  * link_start - enable a port
1097  * @dev: the port to enable
1098  *
1099  * Performs the MAC and PHY actions needed to enable a port.
1100  */
1101 int link_start(struct port_info *pi)
1102 {
1103         struct adapter *adapter = pi->adapter;
1104         int ret;
1105         unsigned int mtu;
1106
1107         mtu = pi->eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1108               (ETHER_HDR_LEN + ETHER_CRC_LEN);
1109
1110         /*
1111          * We do not set address filters and promiscuity here, the stack does
1112          * that step explicitly.
1113          */
1114         ret = t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu, -1, -1,
1115                             -1, 1, true);
1116         if (ret == 0) {
1117                 ret = t4_change_mac(adapter, adapter->mbox, pi->viid,
1118                                     pi->xact_addr_filt,
1119                                     (u8 *)&pi->eth_dev->data->mac_addrs[0],
1120                                     true, true);
1121                 if (ret >= 0) {
1122                         pi->xact_addr_filt = ret;
1123                         ret = 0;
1124                 }
1125         }
1126         if (ret == 0 && is_pf4(adapter))
1127                 ret = t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,
1128                                     &pi->link_cfg);
1129         if (ret == 0) {
1130                 /*
1131                  * Enabling a Virtual Interface can result in an interrupt
1132                  * during the processing of the VI Enable command and, in some
1133                  * paths, result in an attempt to issue another command in the
1134                  * interrupt context.  Thus, we disable interrupts during the
1135                  * course of the VI Enable command ...
1136                  */
1137                 ret = t4_enable_vi_params(adapter, adapter->mbox, pi->viid,
1138                                           true, true, false);
1139         }
1140
1141         if (ret == 0 && force_linkup(adapter))
1142                 pi->eth_dev->data->dev_link.link_status = ETH_LINK_UP;
1143         return ret;
1144 }
1145
1146 /**
1147  * cxgbe_write_rss_conf - flash the RSS configuration for a given port
1148  * @pi: the port
1149  * @rss_hf: Hash configuration to apply
1150  */
1151 int cxgbe_write_rss_conf(const struct port_info *pi, uint64_t rss_hf)
1152 {
1153         struct adapter *adapter = pi->adapter;
1154         const struct sge_eth_rxq *rxq;
1155         u64 flags = 0;
1156         u16 rss;
1157         int err;
1158
1159         /*  Should never be called before setting up sge eth rx queues */
1160         if (!(adapter->flags & FULL_INIT_DONE)) {
1161                 dev_err(adap, "%s No RXQs available on port %d\n",
1162                         __func__, pi->port_id);
1163                 return -EINVAL;
1164         }
1165
1166         /* Don't allow unsupported hash functions */
1167         if (rss_hf & ~CXGBE_RSS_HF_ALL)
1168                 return -EINVAL;
1169
1170         if (rss_hf & ETH_RSS_IPV4)
1171                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN;
1172
1173         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1174                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
1175
1176         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1177                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
1178                          F_FW_RSS_VI_CONFIG_CMD_UDPEN;
1179
1180         if (rss_hf & ETH_RSS_IPV6)
1181                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN;
1182
1183         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
1184                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
1185
1186         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
1187                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN |
1188                          F_FW_RSS_VI_CONFIG_CMD_UDPEN;
1189
1190         rxq = &adapter->sge.ethrxq[pi->first_qset];
1191         rss = rxq[0].rspq.abs_id;
1192
1193         /* If Tunnel All Lookup isn't specified in the global RSS
1194          * Configuration, then we need to specify a default Ingress
1195          * Queue for any ingress packets which aren't hashed.  We'll
1196          * use our first ingress queue ...
1197          */
1198         err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,
1199                                flags, rss);
1200         return err;
1201 }
1202
1203 /**
1204  * cxgbe_write_rss - write the RSS table for a given port
1205  * @pi: the port
1206  * @queues: array of queue indices for RSS
1207  *
1208  * Sets up the portion of the HW RSS table for the port's VI to distribute
1209  * packets to the Rx queues in @queues.
1210  */
1211 int cxgbe_write_rss(const struct port_info *pi, const u16 *queues)
1212 {
1213         u16 *rss;
1214         int i, err;
1215         struct adapter *adapter = pi->adapter;
1216         const struct sge_eth_rxq *rxq;
1217
1218         /*  Should never be called before setting up sge eth rx queues */
1219         BUG_ON(!(adapter->flags & FULL_INIT_DONE));
1220
1221         rxq = &adapter->sge.ethrxq[pi->first_qset];
1222         rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0);
1223         if (!rss)
1224                 return -ENOMEM;
1225
1226         /* map the queue indices to queue ids */
1227         for (i = 0; i < pi->rss_size; i++, queues++)
1228                 rss[i] = rxq[*queues].rspq.abs_id;
1229
1230         err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0,
1231                                   pi->rss_size, rss, pi->rss_size);
1232         rte_free(rss);
1233         return err;
1234 }
1235
1236 /**
1237  * setup_rss - configure RSS
1238  * @adapter: the adapter
1239  *
1240  * Sets up RSS to distribute packets to multiple receive queues.  We
1241  * configure the RSS CPU lookup table to distribute to the number of HW
1242  * receive queues, and the response queue lookup table to narrow that
1243  * down to the response queues actually configured for each port.
1244  * We always configure the RSS mapping for all ports since the mapping
1245  * table has plenty of entries.
1246  */
1247 int setup_rss(struct port_info *pi)
1248 {
1249         int j, err;
1250         struct adapter *adapter = pi->adapter;
1251
1252         dev_debug(adapter, "%s:  pi->rss_size = %u; pi->n_rx_qsets = %u\n",
1253                   __func__, pi->rss_size, pi->n_rx_qsets);
1254
1255         if (!(pi->flags & PORT_RSS_DONE)) {
1256                 if (adapter->flags & FULL_INIT_DONE) {
1257                         /* Fill default values with equal distribution */
1258                         for (j = 0; j < pi->rss_size; j++)
1259                                 pi->rss[j] = j % pi->n_rx_qsets;
1260
1261                         err = cxgbe_write_rss(pi, pi->rss);
1262                         if (err)
1263                                 return err;
1264
1265                         err = cxgbe_write_rss_conf(pi, pi->rss_hf);
1266                         if (err)
1267                                 return err;
1268                         pi->flags |= PORT_RSS_DONE;
1269                 }
1270         }
1271         return 0;
1272 }
1273
1274 /*
1275  * Enable NAPI scheduling and interrupt generation for all Rx queues.
1276  */
1277 static void enable_rx(struct adapter *adap, struct sge_rspq *q)
1278 {
1279         /* 0-increment GTS to start the timer and enable interrupts */
1280         t4_write_reg(adap, is_pf4(adap) ? MYPF_REG(A_SGE_PF_GTS) :
1281                                           T4VF_SGE_BASE_ADDR + A_SGE_VF_GTS,
1282                      V_SEINTARM(q->intr_params) |
1283                      V_INGRESSQID(q->cntxt_id));
1284 }
1285
1286 void cxgbe_enable_rx_queues(struct port_info *pi)
1287 {
1288         struct adapter *adap = pi->adapter;
1289         struct sge *s = &adap->sge;
1290         unsigned int i;
1291
1292         for (i = 0; i < pi->n_rx_qsets; i++)
1293                 enable_rx(adap, &s->ethrxq[pi->first_qset + i].rspq);
1294 }
1295
1296 /**
1297  * fw_caps_to_speed_caps - translate Firmware Port Caps to Speed Caps.
1298  * @port_type: Firmware Port Type
1299  * @fw_caps: Firmware Port Capabilities
1300  * @speed_caps: Device Info Speed Capabilities
1301  *
1302  * Translate a Firmware Port Capabilities specification to Device Info
1303  * Speed Capabilities.
1304  */
1305 static void fw_caps_to_speed_caps(enum fw_port_type port_type,
1306                                   unsigned int fw_caps,
1307                                   u32 *speed_caps)
1308 {
1309 #define SET_SPEED(__speed_name) \
1310         do { \
1311                 *speed_caps |= ETH_LINK_ ## __speed_name; \
1312         } while (0)
1313
1314 #define FW_CAPS_TO_SPEED(__fw_name) \
1315         do { \
1316                 if (fw_caps & FW_PORT_CAP32_ ## __fw_name) \
1317                         SET_SPEED(__fw_name); \
1318         } while (0)
1319
1320         switch (port_type) {
1321         case FW_PORT_TYPE_BT_SGMII:
1322         case FW_PORT_TYPE_BT_XFI:
1323         case FW_PORT_TYPE_BT_XAUI:
1324                 FW_CAPS_TO_SPEED(SPEED_100M);
1325                 FW_CAPS_TO_SPEED(SPEED_1G);
1326                 FW_CAPS_TO_SPEED(SPEED_10G);
1327                 break;
1328
1329         case FW_PORT_TYPE_KX4:
1330         case FW_PORT_TYPE_KX:
1331         case FW_PORT_TYPE_FIBER_XFI:
1332         case FW_PORT_TYPE_FIBER_XAUI:
1333         case FW_PORT_TYPE_SFP:
1334         case FW_PORT_TYPE_QSFP_10G:
1335         case FW_PORT_TYPE_QSA:
1336                 FW_CAPS_TO_SPEED(SPEED_1G);
1337                 FW_CAPS_TO_SPEED(SPEED_10G);
1338                 break;
1339
1340         case FW_PORT_TYPE_KR:
1341                 SET_SPEED(SPEED_10G);
1342                 break;
1343
1344         case FW_PORT_TYPE_BP_AP:
1345         case FW_PORT_TYPE_BP4_AP:
1346                 SET_SPEED(SPEED_1G);
1347                 SET_SPEED(SPEED_10G);
1348                 break;
1349
1350         case FW_PORT_TYPE_BP40_BA:
1351         case FW_PORT_TYPE_QSFP:
1352                 SET_SPEED(SPEED_40G);
1353                 break;
1354
1355         case FW_PORT_TYPE_CR_QSFP:
1356         case FW_PORT_TYPE_SFP28:
1357         case FW_PORT_TYPE_KR_SFP28:
1358                 FW_CAPS_TO_SPEED(SPEED_1G);
1359                 FW_CAPS_TO_SPEED(SPEED_10G);
1360                 FW_CAPS_TO_SPEED(SPEED_25G);
1361                 break;
1362
1363         case FW_PORT_TYPE_CR2_QSFP:
1364                 SET_SPEED(SPEED_50G);
1365                 break;
1366
1367         case FW_PORT_TYPE_KR4_100G:
1368         case FW_PORT_TYPE_CR4_QSFP:
1369                 FW_CAPS_TO_SPEED(SPEED_25G);
1370                 FW_CAPS_TO_SPEED(SPEED_40G);
1371                 FW_CAPS_TO_SPEED(SPEED_50G);
1372                 FW_CAPS_TO_SPEED(SPEED_100G);
1373                 break;
1374
1375         default:
1376                 break;
1377         }
1378
1379 #undef FW_CAPS_TO_SPEED
1380 #undef SET_SPEED
1381 }
1382
1383 /**
1384  * cxgbe_get_speed_caps - Fetch supported speed capabilities
1385  * @pi: Underlying port's info
1386  * @speed_caps: Device Info speed capabilities
1387  *
1388  * Fetch supported speed capabilities of the underlying port.
1389  */
1390 void cxgbe_get_speed_caps(struct port_info *pi, u32 *speed_caps)
1391 {
1392         *speed_caps = 0;
1393
1394         fw_caps_to_speed_caps(pi->port_type, pi->link_cfg.pcaps,
1395                               speed_caps);
1396
1397         if (!(pi->link_cfg.pcaps & FW_PORT_CAP32_ANEG))
1398                 *speed_caps |= ETH_LINK_SPEED_FIXED;
1399 }
1400
1401 /**
1402  * cxgb_up - enable the adapter
1403  * @adap: adapter being enabled
1404  *
1405  * Called when the first port is enabled, this function performs the
1406  * actions necessary to make an adapter operational, such as completing
1407  * the initialization of HW modules, and enabling interrupts.
1408  */
1409 int cxgbe_up(struct adapter *adap)
1410 {
1411         enable_rx(adap, &adap->sge.fw_evtq);
1412         t4_sge_tx_monitor_start(adap);
1413         if (is_pf4(adap))
1414                 t4_intr_enable(adap);
1415         adap->flags |= FULL_INIT_DONE;
1416
1417         /* TODO: deadman watchdog ?? */
1418         return 0;
1419 }
1420
1421 /*
1422  * Close the port
1423  */
1424 int cxgbe_down(struct port_info *pi)
1425 {
1426         struct adapter *adapter = pi->adapter;
1427         int err = 0;
1428
1429         err = t4_enable_vi(adapter, adapter->mbox, pi->viid, false, false);
1430         if (err) {
1431                 dev_err(adapter, "%s: disable_vi failed: %d\n", __func__, err);
1432                 return err;
1433         }
1434
1435         t4_reset_link_config(adapter, pi->pidx);
1436         return 0;
1437 }
1438
1439 /*
1440  * Release resources when all the ports have been stopped.
1441  */
1442 void cxgbe_close(struct adapter *adapter)
1443 {
1444         struct port_info *pi;
1445         int i;
1446
1447         if (adapter->flags & FULL_INIT_DONE) {
1448                 if (is_pf4(adapter))
1449                         t4_intr_disable(adapter);
1450                 tid_free(&adapter->tids);
1451                 t4_sge_tx_monitor_stop(adapter);
1452                 t4_free_sge_resources(adapter);
1453                 for_each_port(adapter, i) {
1454                         pi = adap2pinfo(adapter, i);
1455                         if (pi->viid != 0)
1456                                 t4_free_vi(adapter, adapter->mbox,
1457                                            adapter->pf, 0, pi->viid);
1458                         rte_free(pi->eth_dev->data->mac_addrs);
1459                         /* Skip first port since it'll be freed by DPDK stack */
1460                         if (i) {
1461                                 rte_free(pi->eth_dev->data->dev_private);
1462                                 rte_eth_dev_release_port(pi->eth_dev);
1463                         }
1464                 }
1465                 adapter->flags &= ~FULL_INIT_DONE;
1466         }
1467
1468         if (is_pf4(adapter) && (adapter->flags & FW_OK))
1469                 t4_fw_bye(adapter, adapter->mbox);
1470 }
1471
1472 int cxgbe_probe(struct adapter *adapter)
1473 {
1474         struct port_info *pi;
1475         int chip;
1476         int func, i;
1477         int err = 0;
1478         u32 whoami;
1479
1480         whoami = t4_read_reg(adapter, A_PL_WHOAMI);
1481         chip = t4_get_chip_type(adapter,
1482                         CHELSIO_PCI_ID_VER(adapter->pdev->id.device_id));
1483         if (chip < 0)
1484                 return chip;
1485
1486         func = CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5 ?
1487                G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
1488
1489         adapter->mbox = func;
1490         adapter->pf = func;
1491
1492         t4_os_lock_init(&adapter->mbox_lock);
1493         TAILQ_INIT(&adapter->mbox_list);
1494
1495         err = t4_prep_adapter(adapter);
1496         if (err)
1497                 return err;
1498
1499         setup_memwin(adapter);
1500         err = adap_init0(adapter);
1501         if (err) {
1502                 dev_err(adapter, "%s: Adapter initialization failed, error %d\n",
1503                         __func__, err);
1504                 goto out_free;
1505         }
1506
1507         if (!is_t4(adapter->params.chip)) {
1508                 /*
1509                  * The userspace doorbell BAR is split evenly into doorbell
1510                  * regions, each associated with an egress queue.  If this
1511                  * per-queue region is large enough (at least UDBS_SEG_SIZE)
1512                  * then it can be used to submit a tx work request with an
1513                  * implied doorbell.  Enable write combining on the BAR if
1514                  * there is room for such work requests.
1515                  */
1516                 int s_qpp, qpp, num_seg;
1517
1518                 s_qpp = (S_QUEUESPERPAGEPF0 +
1519                         (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) *
1520                         adapter->pf);
1521                 qpp = 1 << ((t4_read_reg(adapter,
1522                                 A_SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp)
1523                                 & M_QUEUESPERPAGEPF0);
1524                 num_seg = CXGBE_PAGE_SIZE / UDBS_SEG_SIZE;
1525                 if (qpp > num_seg)
1526                         dev_warn(adapter, "Incorrect SGE EGRESS QUEUES_PER_PAGE configuration, continuing in debug mode\n");
1527
1528                 adapter->bar2 = (void *)adapter->pdev->mem_resource[2].addr;
1529                 if (!adapter->bar2) {
1530                         dev_err(adapter, "cannot map device bar2 region\n");
1531                         err = -ENOMEM;
1532                         goto out_free;
1533                 }
1534                 t4_write_reg(adapter, A_SGE_STAT_CFG, V_STATSOURCE_T5(7) |
1535                              V_STATMODE(0));
1536         }
1537
1538         for_each_port(adapter, i) {
1539                 const unsigned int numa_node = rte_socket_id();
1540                 char name[RTE_ETH_NAME_MAX_LEN];
1541                 struct rte_eth_dev *eth_dev;
1542
1543                 snprintf(name, sizeof(name), "%s_%d",
1544                          adapter->pdev->device.name, i);
1545
1546                 if (i == 0) {
1547                         /* First port is already allocated by DPDK */
1548                         eth_dev = adapter->eth_dev;
1549                         goto allocate_mac;
1550                 }
1551
1552                 /*
1553                  * now do all data allocation - for eth_dev structure,
1554                  * and internal (private) data for the remaining ports
1555                  */
1556
1557                 /* reserve an ethdev entry */
1558                 eth_dev = rte_eth_dev_allocate(name);
1559                 if (!eth_dev)
1560                         goto out_free;
1561
1562                 eth_dev->data->dev_private =
1563                         rte_zmalloc_socket(name, sizeof(struct port_info),
1564                                            RTE_CACHE_LINE_SIZE, numa_node);
1565                 if (!eth_dev->data->dev_private)
1566                         goto out_free;
1567
1568 allocate_mac:
1569                 pi = (struct port_info *)eth_dev->data->dev_private;
1570                 adapter->port[i] = pi;
1571                 pi->eth_dev = eth_dev;
1572                 pi->adapter = adapter;
1573                 pi->xact_addr_filt = -1;
1574                 pi->port_id = i;
1575                 pi->pidx = i;
1576
1577                 pi->eth_dev->device = &adapter->pdev->device;
1578                 pi->eth_dev->dev_ops = adapter->eth_dev->dev_ops;
1579                 pi->eth_dev->tx_pkt_burst = adapter->eth_dev->tx_pkt_burst;
1580                 pi->eth_dev->rx_pkt_burst = adapter->eth_dev->rx_pkt_burst;
1581
1582                 rte_eth_copy_pci_info(pi->eth_dev, adapter->pdev);
1583
1584                 pi->eth_dev->data->mac_addrs = rte_zmalloc(name,
1585                                                            ETHER_ADDR_LEN, 0);
1586                 if (!pi->eth_dev->data->mac_addrs) {
1587                         dev_err(adapter, "%s: Mem allocation failed for storing mac addr, aborting\n",
1588                                 __func__);
1589                         err = -1;
1590                         goto out_free;
1591                 }
1592
1593                 if (i > 0) {
1594                         /* First port will be notified by upper layer */
1595                         rte_eth_dev_probing_finish(eth_dev);
1596                 }
1597         }
1598
1599         if (adapter->flags & FW_OK) {
1600                 err = t4_port_init(adapter, adapter->mbox, adapter->pf, 0);
1601                 if (err) {
1602                         dev_err(adapter, "%s: t4_port_init failed with err %d\n",
1603                                 __func__, err);
1604                         goto out_free;
1605                 }
1606         }
1607
1608         cfg_queues(adapter->eth_dev);
1609
1610         print_adapter_info(adapter);
1611         print_port_info(adapter);
1612
1613         if (tid_init(&adapter->tids) < 0) {
1614                 /* Disable filtering support */
1615                 dev_warn(adapter, "could not allocate TID table, "
1616                          "filter support disabled. Continuing\n");
1617         }
1618
1619         err = init_rss(adapter);
1620         if (err)
1621                 goto out_free;
1622
1623         return 0;
1624
1625 out_free:
1626         for_each_port(adapter, i) {
1627                 pi = adap2pinfo(adapter, i);
1628                 if (pi->viid != 0)
1629                         t4_free_vi(adapter, adapter->mbox, adapter->pf,
1630                                    0, pi->viid);
1631                 /* Skip first port since it'll be de-allocated by DPDK */
1632                 if (i == 0)
1633                         continue;
1634                 if (pi->eth_dev) {
1635                         if (pi->eth_dev->data->dev_private)
1636                                 rte_free(pi->eth_dev->data->dev_private);
1637                         rte_eth_dev_release_port(pi->eth_dev);
1638                 }
1639         }
1640
1641         if (adapter->flags & FW_OK)
1642                 t4_fw_bye(adapter, adapter->mbox);
1643         return -err;
1644 }