drivers/net/cxgbe/cxgbe_main.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2014-2017 Chelsio Communications.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Chelsio Communications nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43
  44 #include <rte_byteorder.h>
  45 #include <rte_common.h>
  46 #include <rte_cycles.h>
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_tailq.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev_driver.h>
  59 #include <rte_ethdev_pci.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "common.h"
  65 #include "t4_regs.h"
  66 #include "t4_msg.h"
  67 #include "cxgbe.h"
  68
  69 /*
  70  * Response queue handler for the FW event queue.
  71  */
  72 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
  73                           __rte_unused const struct pkt_gl *gl)
  74 {
  75         u8 opcode = ((const struct rss_header *)rsp)->opcode;
  76
  77         rsp++;                                          /* skip RSS header */
  78
  79         /*
  80          * FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
  81          */
  82         if (unlikely(opcode == CPL_FW4_MSG &&
  83                      ((const struct cpl_fw4_msg *)rsp)->type ==
  84                       FW_TYPE_RSSCPL)) {
  85                 rsp++;
  86                 opcode = ((const struct rss_header *)rsp)->opcode;
  87                 rsp++;
  88                 if (opcode != CPL_SGE_EGR_UPDATE) {
  89                         dev_err(q->adapter, "unexpected FW4/CPL %#x on FW event queue\n",
  90                                 opcode);
  91                         goto out;
  92                 }
  93         }
  94
  95         if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
  96                 /* do nothing */
  97         } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
  98                 const struct cpl_fw6_msg *msg = (const void *)rsp;
  99
 100                 t4_handle_fw_rpl(q->adapter, msg->data);
 101         } else {
 102                 dev_err(adapter, "unexpected CPL %#x on FW event queue\n",
 103                         opcode);
 104         }
 105 out:
 106         return 0;
 107 }
 108
 109 int setup_sge_fwevtq(struct adapter *adapter)
 110 {
 111         struct sge *s = &adapter->sge;
 112         int err = 0;
 113         int msi_idx = 0;
 114
 115         err = t4_sge_alloc_rxq(adapter, &s->fw_evtq, true, adapter->eth_dev,
 116                                msi_idx, NULL, fwevtq_handler, -1, NULL, 0,
 117                                rte_socket_id());
 118         return err;
 119 }
 120
 121 static int closest_timer(const struct sge *s, int time)
 122 {
 123         unsigned int i, match = 0;
 124         int delta, min_delta = INT_MAX;
 125
 126         for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
 127                 delta = time - s->timer_val[i];
 128                 if (delta < 0)
 129                         delta = -delta;
 130                 if (delta < min_delta) {
 131                         min_delta = delta;
 132                         match = i;
 133                 }
 134         }
 135         return match;
 136 }
 137
 138 static int closest_thres(const struct sge *s, int thres)
 139 {
 140         unsigned int i, match = 0;
 141         int delta, min_delta = INT_MAX;
 142
 143         for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
 144                 delta = thres - s->counter_val[i];
 145                 if (delta < 0)
 146                         delta = -delta;
 147                 if (delta < min_delta) {
 148                         min_delta = delta;
 149                         match = i;
 150                 }
 151         }
 152         return match;
 153 }
 154
 155 /**
 156  * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters
 157  * @q: the Rx queue
 158  * @us: the hold-off time in us, or 0 to disable timer
 159  * @cnt: the hold-off packet count, or 0 to disable counter
 160  *
 161  * Sets an Rx queue's interrupt hold-off time and packet count.  At least
 162  * one of the two needs to be enabled for the queue to generate interrupts.
 163  */
 164 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
 165                                unsigned int cnt)
 166 {
 167         struct adapter *adap = q->adapter;
 168         unsigned int timer_val;
 169
 170         if (cnt) {
 171                 int err;
 172                 u32 v, new_idx;
 173
 174                 new_idx = closest_thres(&adap->sge, cnt);
 175                 if (q->desc && q->pktcnt_idx != new_idx) {
 176                         /* the queue has already been created, update it */
 177                         v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
 178                             V_FW_PARAMS_PARAM_X(
 179                             FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
 180                             V_FW_PARAMS_PARAM_YZ(q->cntxt_id);
 181                         err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
 182                                             &v, &new_idx);
 183                         if (err)
 184                                 return err;
 185                 }
 186                 q->pktcnt_idx = new_idx;
 187         }
 188
 189         timer_val = (us == 0) ? X_TIMERREG_RESTART_COUNTER :
 190                                 closest_timer(&adap->sge, us);
 191
 192         if ((us | cnt) == 0)
 193                 q->intr_params = V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX);
 194         else
 195                 q->intr_params = V_QINTR_TIMER_IDX(timer_val) |
 196                                  V_QINTR_CNT_EN(cnt > 0);
 197         return 0;
 198 }
 199
 200 static inline bool is_x_1g_port(const struct link_config *lc)
 201 {
 202         return (lc->pcaps & FW_PORT_CAP32_SPEED_1G) != 0;
 203 }
 204
 205 static inline bool is_x_10g_port(const struct link_config *lc)
 206 {
 207         unsigned int speeds, high_speeds;
 208
 209         speeds = V_FW_PORT_CAP32_SPEED(G_FW_PORT_CAP32_SPEED(lc->pcaps));
 210         high_speeds = speeds &
 211                       ~(FW_PORT_CAP32_SPEED_100M | FW_PORT_CAP32_SPEED_1G);
 212
 213         return high_speeds != 0;
 214 }
 215
 216 inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
 217                       unsigned int us, unsigned int cnt,
 218                       unsigned int size, unsigned int iqe_size)
 219 {
 220         q->adapter = adap;
 221         cxgb4_set_rspq_intr_params(q, us, cnt);
 222         q->iqe_len = iqe_size;
 223         q->size = size;
 224 }
 225
 226 int cfg_queue_count(struct rte_eth_dev *eth_dev)
 227 {
 228         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 229         struct adapter *adap = pi->adapter;
 230         struct sge *s = &adap->sge;
 231         unsigned int max_queues = s->max_ethqsets / adap->params.nports;
 232
 233         if ((eth_dev->data->nb_rx_queues < 1) ||
 234             (eth_dev->data->nb_tx_queues < 1))
 235                 return -EINVAL;
 236
 237         if ((eth_dev->data->nb_rx_queues > max_queues) ||
 238             (eth_dev->data->nb_tx_queues > max_queues))
 239                 return -EINVAL;
 240
 241         if (eth_dev->data->nb_rx_queues > pi->rss_size)
 242                 return -EINVAL;
 243
 244         /* We must configure RSS, since config has changed*/
 245         pi->flags &= ~PORT_RSS_DONE;
 246
 247         pi->n_rx_qsets = eth_dev->data->nb_rx_queues;
 248         pi->n_tx_qsets = eth_dev->data->nb_tx_queues;
 249
 250         return 0;
 251 }
 252
 253 void cfg_queues(struct rte_eth_dev *eth_dev)
 254 {
 255         struct rte_config *config = rte_eal_get_configuration();
 256         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 257         struct adapter *adap = pi->adapter;
 258         struct sge *s = &adap->sge;
 259         unsigned int i, nb_ports = 0, qidx = 0;
 260         unsigned int q_per_port = 0;
 261
 262         if (!(adap->flags & CFG_QUEUES)) {
 263                 for_each_port(adap, i) {
 264                         struct port_info *tpi = adap2pinfo(adap, i);
 265
 266                         nb_ports += (is_x_10g_port(&tpi->link_cfg)) ||
 267                                      is_x_1g_port(&tpi->link_cfg) ? 1 : 0;
 268                 }
 269
 270                 /*
 271                  * We default up to # of cores queues per 1G/10G port.
 272                  */
 273                 if (nb_ports)
 274                         q_per_port = (MAX_ETH_QSETS -
 275                                      (adap->params.nports - nb_ports)) /
 276                                      nb_ports;
 277
 278                 if (q_per_port > config->lcore_count)
 279                         q_per_port = config->lcore_count;
 280
 281                 for_each_port(adap, i) {
 282                         struct port_info *pi = adap2pinfo(adap, i);
 283
 284                         pi->first_qset = qidx;
 285
 286                         /* Initially n_rx_qsets == n_tx_qsets */
 287                         pi->n_rx_qsets = (is_x_10g_port(&pi->link_cfg) ||
 288                                           is_x_1g_port(&pi->link_cfg)) ?
 289                                           q_per_port : 1;
 290                         pi->n_tx_qsets = pi->n_rx_qsets;
 291
 292                         if (pi->n_rx_qsets > pi->rss_size)
 293                                 pi->n_rx_qsets = pi->rss_size;
 294
 295                         qidx += pi->n_rx_qsets;
 296                 }
 297
 298                 s->max_ethqsets = qidx;
 299
 300                 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
 301                         struct sge_eth_rxq *r = &s->ethrxq[i];
 302
 303                         init_rspq(adap, &r->rspq, 5, 32, 1024, 64);
 304                         r->usembufs = 1;
 305                         r->fl.size = (r->usembufs ? 1024 : 72);
 306                 }
 307
 308                 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
 309                         s->ethtxq[i].q.size = 1024;
 310
 311                 init_rspq(adap, &adap->sge.fw_evtq, 0, 0, 1024, 64);
 312                 adap->flags |= CFG_QUEUES;
 313         }
 314 }
 315
 316 void cxgbe_stats_get(struct port_info *pi, struct port_stats *stats)
 317 {
 318         t4_get_port_stats_offset(pi->adapter, pi->tx_chan, stats,
 319                                  &pi->stats_base);
 320 }
 321
 322 void cxgbe_stats_reset(struct port_info *pi)
 323 {
 324         t4_clr_port_stats(pi->adapter, pi->tx_chan);
 325 }
 326
 327 static void setup_memwin(struct adapter *adap)
 328 {
 329         u32 mem_win0_base;
 330
 331         /* For T5, only relative offset inside the PCIe BAR is passed */
 332         mem_win0_base = MEMWIN0_BASE;
 333
 334         /*
 335          * Set up memory window for accessing adapter memory ranges.  (Read
 336          * back MA register to ensure that changes propagate before we attempt
 337          * to use the new values.)
 338          */
 339         t4_write_reg(adap,
 340                      PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN,
 341                                          MEMWIN_NIC),
 342                      mem_win0_base | V_BIR(0) |
 343                      V_WINDOW(ilog2(MEMWIN0_APERTURE) - X_WINDOW_SHIFT));
 344         t4_read_reg(adap,
 345                     PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN,
 346                                         MEMWIN_NIC));
 347 }
 348
 349 static int init_rss(struct adapter *adap)
 350 {
 351         unsigned int i;
 352         int err;
 353
 354         err = t4_init_rss_mode(adap, adap->mbox);
 355         if (err)
 356                 return err;
 357
 358         for_each_port(adap, i) {
 359                 struct port_info *pi = adap2pinfo(adap, i);
 360
 361                 pi->rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0);
 362                 if (!pi->rss)
 363                         return -ENOMEM;
 364
 365                 pi->rss_hf = CXGBE_RSS_HF_ALL;
 366         }
 367         return 0;
 368 }
 369
 370 /**
 371  * Dump basic information about the adapter.
 372  */
 373 static void print_adapter_info(struct adapter *adap)
 374 {
 375         /**
 376          * Hardware/Firmware/etc. Version/Revision IDs.
 377          */
 378         t4_dump_version_info(adap);
 379 }
 380
 381 static void print_port_info(struct adapter *adap)
 382 {
 383         int i;
 384         char buf[80];
 385         struct rte_pci_addr *loc = &adap->pdev->addr;
 386
 387         for_each_port(adap, i) {
 388                 const struct port_info *pi = adap2pinfo(adap, i);
 389                 char *bufp = buf;
 390
 391                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100M)
 392                         bufp += sprintf(bufp, "100M/");
 393                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_1G)
 394                         bufp += sprintf(bufp, "1G/");
 395                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_10G)
 396                         bufp += sprintf(bufp, "10G/");
 397                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_25G)
 398                         bufp += sprintf(bufp, "25G/");
 399                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_40G)
 400                         bufp += sprintf(bufp, "40G/");
 401                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_50G)
 402                         bufp += sprintf(bufp, "50G/");
 403                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100G)
 404                         bufp += sprintf(bufp, "100G/");
 405                 if (bufp != buf)
 406                         --bufp;
 407                 sprintf(bufp, "BASE-%s",
 408                         t4_get_port_type_description(
 409                                         (enum fw_port_type)pi->port_type));
 410
 411                 dev_info(adap,
 412                          " " PCI_PRI_FMT " Chelsio rev %d %s %s\n",
 413                          loc->domain, loc->bus, loc->devid, loc->function,
 414                          CHELSIO_CHIP_RELEASE(adap->params.chip), buf,
 415                          (adap->flags & USING_MSIX) ? " MSI-X" :
 416                          (adap->flags & USING_MSI) ? " MSI" : "");
 417         }
 418 }
 419
 420 static void configure_pcie_ext_tag(struct adapter *adapter)
 421 {
 422         u16 v;
 423         int pos = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
 424
 425         if (!pos)
 426                 return;
 427
 428         if (pos > 0) {
 429                 t4_os_pci_read_cfg2(adapter, pos + PCI_EXP_DEVCTL, &v);
 430                 v |= PCI_EXP_DEVCTL_EXT_TAG;
 431                 t4_os_pci_write_cfg2(adapter, pos + PCI_EXP_DEVCTL, v);
 432                 if (is_t6(adapter->params.chip)) {
 433                         t4_set_reg_field(adapter, A_PCIE_CFG2,
 434                                          V_T6_TOTMAXTAG(M_T6_TOTMAXTAG),
 435                                          V_T6_TOTMAXTAG(7));
 436                         t4_set_reg_field(adapter, A_PCIE_CMD_CFG,
 437                                          V_T6_MINTAG(M_T6_MINTAG),
 438                                          V_T6_MINTAG(8));
 439                 } else {
 440                         t4_set_reg_field(adapter, A_PCIE_CFG2,
 441                                          V_TOTMAXTAG(M_TOTMAXTAG),
 442                                          V_TOTMAXTAG(3));
 443                         t4_set_reg_field(adapter, A_PCIE_CMD_CFG,
 444                                          V_MINTAG(M_MINTAG),
 445                                          V_MINTAG(8));
 446                 }
 447         }
 448 }
 449
 450 /*
 451  * Tweak configuration based on system architecture, etc.  Most of these have
 452  * defaults assigned to them by Firmware Configuration Files (if we're using
 453  * them) but need to be explicitly set if we're using hard-coded
 454  * initialization. So these are essentially common tweaks/settings for
 455  * Configuration Files and hard-coded initialization ...
 456  */
 457 static int adap_init0_tweaks(struct adapter *adapter)
 458 {
 459         u8 rx_dma_offset;
 460
 461         /*
 462          * Fix up various Host-Dependent Parameters like Page Size, Cache
 463          * Line Size, etc.  The firmware default is for a 4KB Page Size and
 464          * 64B Cache Line Size ...
 465          */
 466         t4_fixup_host_params_compat(adapter, CXGBE_PAGE_SIZE, L1_CACHE_BYTES,
 467                                     T5_LAST_REV);
 468
 469         /*
 470          * Keep the chip default offset to deliver Ingress packets into our
 471          * DMA buffers to zero
 472          */
 473         rx_dma_offset = 0;
 474         t4_set_reg_field(adapter, A_SGE_CONTROL, V_PKTSHIFT(M_PKTSHIFT),
 475                          V_PKTSHIFT(rx_dma_offset));
 476
 477         t4_set_reg_field(adapter, A_SGE_FLM_CFG,
 478                          V_CREDITCNT(M_CREDITCNT) | M_CREDITCNTPACKING,
 479                          V_CREDITCNT(3) | V_CREDITCNTPACKING(1));
 480
 481         t4_set_reg_field(adapter, A_SGE_INGRESS_RX_THRESHOLD,
 482                          V_THRESHOLD_3(M_THRESHOLD_3), V_THRESHOLD_3(32U));
 483
 484         t4_set_reg_field(adapter, A_SGE_CONTROL2, V_IDMAARBROUNDROBIN(1U),
 485                          V_IDMAARBROUNDROBIN(1U));
 486
 487         /*
 488          * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
 489          * adds the pseudo header itself.
 490          */
 491         t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG,
 492                                F_CSUM_HAS_PSEUDO_HDR, 0);
 493
 494         return 0;
 495 }
 496
 497 /*
 498  * Attempt to initialize the adapter via a Firmware Configuration File.
 499  */
 500 static int adap_init0_config(struct adapter *adapter, int reset)
 501 {
 502         struct fw_caps_config_cmd caps_cmd;
 503         unsigned long mtype = 0, maddr = 0;
 504         u32 finiver, finicsum, cfcsum;
 505         int ret;
 506         int config_issued = 0;
 507         int cfg_addr;
 508         char config_name[20];
 509
 510         /*
 511          * Reset device if necessary.
 512          */
 513         if (reset) {
 514                 ret = t4_fw_reset(adapter, adapter->mbox,
 515                                   F_PIORSTMODE | F_PIORST);
 516                 if (ret < 0) {
 517                         dev_warn(adapter, "Firmware reset failed, error %d\n",
 518                                  -ret);
 519                         goto bye;
 520                 }
 521         }
 522
 523         cfg_addr = t4_flash_cfg_addr(adapter);
 524         if (cfg_addr < 0) {
 525                 ret = cfg_addr;
 526                 dev_warn(adapter, "Finding address for firmware config file in flash failed, error %d\n",
 527                          -ret);
 528                 goto bye;
 529         }
 530
 531         strcpy(config_name, "On Flash");
 532         mtype = FW_MEMTYPE_CF_FLASH;
 533         maddr = cfg_addr;
 534
 535         /*
 536          * Issue a Capability Configuration command to the firmware to get it
 537          * to parse the Configuration File.  We don't use t4_fw_config_file()
 538          * because we want the ability to modify various features after we've
 539          * processed the configuration file ...
 540          */
 541         memset(&caps_cmd, 0, sizeof(caps_cmd));
 542         caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
 543                                            F_FW_CMD_REQUEST | F_FW_CMD_READ);
 544         caps_cmd.cfvalid_to_len16 =
 545                 cpu_to_be32(F_FW_CAPS_CONFIG_CMD_CFVALID |
 546                             V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
 547                             V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) |
 548                             FW_LEN16(caps_cmd));
 549         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
 550                          &caps_cmd);
 551         /*
 552          * If the CAPS_CONFIG failed with an ENOENT (for a Firmware
 553          * Configuration File in FLASH), our last gasp effort is to use the
 554          * Firmware Configuration File which is embedded in the firmware.  A
 555          * very few early versions of the firmware didn't have one embedded
 556          * but we can ignore those.
 557          */
 558         if (ret == -ENOENT) {
 559                 dev_info(adapter, "%s: Going for embedded config in firmware..\n",
 560                          __func__);
 561
 562                 memset(&caps_cmd, 0, sizeof(caps_cmd));
 563                 caps_cmd.op_to_write =
 564                         cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
 565                                     F_FW_CMD_REQUEST | F_FW_CMD_READ);
 566                 caps_cmd.cfvalid_to_len16 = cpu_to_be32(FW_LEN16(caps_cmd));
 567                 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
 568                                  sizeof(caps_cmd), &caps_cmd);
 569                 strcpy(config_name, "Firmware Default");
 570         }
 571
 572         config_issued = 1;
 573         if (ret < 0)
 574                 goto bye;
 575
 576         finiver = be32_to_cpu(caps_cmd.finiver);
 577         finicsum = be32_to_cpu(caps_cmd.finicsum);
 578         cfcsum = be32_to_cpu(caps_cmd.cfcsum);
 579         if (finicsum != cfcsum)
 580                 dev_warn(adapter, "Configuration File checksum mismatch: [fini] csum=%#x, computed csum=%#x\n",
 581                          finicsum, cfcsum);
 582
 583         /*
 584          * If we're a pure NIC driver then disable all offloading facilities.
 585          * This will allow the firmware to optimize aspects of the hardware
 586          * configuration which will result in improved performance.
 587          */
 588         caps_cmd.niccaps &= cpu_to_be16(~(FW_CAPS_CONFIG_NIC_HASHFILTER |
 589                                           FW_CAPS_CONFIG_NIC_ETHOFLD));
 590         caps_cmd.toecaps = 0;
 591         caps_cmd.iscsicaps = 0;
 592         caps_cmd.rdmacaps = 0;
 593         caps_cmd.fcoecaps = 0;
 594
 595         /*
 596          * And now tell the firmware to use the configuration we just loaded.
 597          */
 598         caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
 599                                            F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
 600         caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
 601         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
 602                          NULL);
 603         if (ret < 0) {
 604                 dev_warn(adapter, "Unable to finalize Firmware Capabilities %d\n",
 605                          -ret);
 606                 goto bye;
 607         }
 608
 609         /*
 610          * Tweak configuration based on system architecture, etc.
 611          */
 612         ret = adap_init0_tweaks(adapter);
 613         if (ret < 0) {
 614                 dev_warn(adapter, "Unable to do init0-tweaks %d\n", -ret);
 615                 goto bye;
 616         }
 617
 618         /*
 619          * And finally tell the firmware to initialize itself using the
 620          * parameters from the Configuration File.
 621          */
 622         ret = t4_fw_initialize(adapter, adapter->mbox);
 623         if (ret < 0) {
 624                 dev_warn(adapter, "Initializing Firmware failed, error %d\n",
 625                          -ret);
 626                 goto bye;
 627         }
 628
 629         /*
 630          * Return successfully and note that we're operating with parameters
 631          * not supplied by the driver, rather than from hard-wired
 632          * initialization constants buried in the driver.
 633          */
 634         dev_info(adapter,
 635                  "Successfully configured using Firmware Configuration File \"%s\", version %#x, computed checksum %#x\n",
 636                  config_name, finiver, cfcsum);
 637
 638         return 0;
 639
 640         /*
 641          * Something bad happened.  Return the error ...  (If the "error"
 642          * is that there's no Configuration File on the adapter we don't
 643          * want to issue a warning since this is fairly common.)
 644          */
 645 bye:
 646         if (config_issued && ret != -ENOENT)
 647                 dev_warn(adapter, "\"%s\" configuration file error %d\n",
 648                          config_name, -ret);
 649
 650         dev_debug(adapter, "%s: returning ret = %d ..\n", __func__, ret);
 651         return ret;
 652 }
 653
 654 static int adap_init0(struct adapter *adap)
 655 {
 656         int ret = 0;
 657         u32 v, port_vec;
 658         enum dev_state state;
 659         u32 params[7], val[7];
 660         int reset = 1;
 661         int mbox = adap->mbox;
 662
 663         /*
 664          * Contact FW, advertising Master capability.
 665          */
 666         ret = t4_fw_hello(adap, adap->mbox, adap->mbox, MASTER_MAY, &state);
 667         if (ret < 0) {
 668                 dev_err(adap, "%s: could not connect to FW, error %d\n",
 669                         __func__, -ret);
 670                 goto bye;
 671         }
 672
 673         CXGBE_DEBUG_MBOX(adap, "%s: adap->mbox = %d; ret = %d\n", __func__,
 674                          adap->mbox, ret);
 675
 676         if (ret == mbox)
 677                 adap->flags |= MASTER_PF;
 678
 679         if (state == DEV_STATE_INIT) {
 680                 /*
 681                  * Force halt and reset FW because a previous instance may have
 682                  * exited abnormally without properly shutting down
 683                  */
 684                 ret = t4_fw_halt(adap, adap->mbox, reset);
 685                 if (ret < 0) {
 686                         dev_err(adap, "Failed to halt. Exit.\n");
 687                         goto bye;
 688                 }
 689
 690                 ret = t4_fw_restart(adap, adap->mbox, reset);
 691                 if (ret < 0) {
 692                         dev_err(adap, "Failed to restart. Exit.\n");
 693                         goto bye;
 694                 }
 695                 state = (enum dev_state)((unsigned)state & ~DEV_STATE_INIT);
 696         }
 697
 698         t4_get_version_info(adap);
 699
 700         ret = t4_get_core_clock(adap, &adap->params.vpd);
 701         if (ret < 0) {
 702                 dev_err(adap, "%s: could not get core clock, error %d\n",
 703                         __func__, -ret);
 704                 goto bye;
 705         }
 706
 707         /*
 708          * If the firmware is initialized already (and we're not forcing a
 709          * master initialization), note that we're living with existing
 710          * adapter parameters.  Otherwise, it's time to try initializing the
 711          * adapter ...
 712          */
 713         if (state == DEV_STATE_INIT) {
 714                 dev_info(adap, "Coming up as %s: Adapter already initialized\n",
 715                          adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
 716         } else {
 717                 dev_info(adap, "Coming up as MASTER: Initializing adapter\n");
 718
 719                 ret = adap_init0_config(adap, reset);
 720                 if (ret == -ENOENT) {
 721                         dev_err(adap,
 722                                 "No Configuration File present on adapter. Using hard-wired configuration parameters.\n");
 723                         goto bye;
 724                 }
 725         }
 726         if (ret < 0) {
 727                 dev_err(adap, "could not initialize adapter, error %d\n", -ret);
 728                 goto bye;
 729         }
 730
 731         /* Find out what ports are available to us. */
 732         v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
 733             V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_PORTVEC);
 734         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec);
 735         if (ret < 0) {
 736                 dev_err(adap, "%s: failure in t4_query_params; error = %d\n",
 737                         __func__, ret);
 738                 goto bye;
 739         }
 740
 741         adap->params.nports = hweight32(port_vec);
 742         adap->params.portvec = port_vec;
 743
 744         dev_debug(adap, "%s: adap->params.nports = %u\n", __func__,
 745                   adap->params.nports);
 746
 747         /*
 748          * Give the SGE code a chance to pull in anything that it needs ...
 749          * Note that this must be called after we retrieve our VPD parameters
 750          * in order to know how to convert core ticks to seconds, etc.
 751          */
 752         ret = t4_sge_init(adap);
 753         if (ret < 0) {
 754                 dev_err(adap, "t4_sge_init failed with error %d\n",
 755                         -ret);
 756                 goto bye;
 757         }
 758
 759         /*
 760          * Grab some of our basic fundamental operating parameters.
 761          */
 762 #define FW_PARAM_DEV(param) \
 763         (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
 764          V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
 765
 766 #define FW_PARAM_PFVF(param) \
 767         (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
 768          V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param) |  \
 769          V_FW_PARAMS_PARAM_Y(0) | \
 770          V_FW_PARAMS_PARAM_Z(0))
 771
 772         /* If we're running on newer firmware, let it know that we're
 773          * prepared to deal with encapsulated CPL messages.  Older
 774          * firmware won't understand this and we'll just get
 775          * unencapsulated messages ...
 776          */
 777         params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
 778         val[0] = 1;
 779         (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
 780
 781         /*
 782          * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
 783          * capability.  Earlier versions of the firmware didn't have the
 784          * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
 785          * permission to use ULPTX MEMWRITE DSGL.
 786          */
 787         if (is_t4(adap->params.chip)) {
 788                 adap->params.ulptx_memwrite_dsgl = false;
 789         } else {
 790                 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
 791                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
 792                                       1, params, val);
 793                 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
 794         }
 795
 796         /*
 797          * The MTU/MSS Table is initialized by now, so load their values.  If
 798          * we're initializing the adapter, then we'll make any modifications
 799          * we want to the MTU/MSS Table and also initialize the congestion
 800          * parameters.
 801          */
 802         t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
 803         if (state != DEV_STATE_INIT) {
 804                 int i;
 805
 806                 /*
 807                  * The default MTU Table contains values 1492 and 1500.
 808                  * However, for TCP, it's better to have two values which are
 809                  * a multiple of 8 +/- 4 bytes apart near this popular MTU.
 810                  * This allows us to have a TCP Data Payload which is a
 811                  * multiple of 8 regardless of what combination of TCP Options
 812                  * are in use (always a multiple of 4 bytes) which is
 813                  * important for performance reasons.  For instance, if no
 814                  * options are in use, then we have a 20-byte IP header and a
 815                  * 20-byte TCP header.  In this case, a 1500-byte MSS would
 816                  * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
 817                  * which is not a multiple of 8.  So using an MSS of 1488 in
 818                  * this case results in a TCP Data Payload of 1448 bytes which
 819                  * is a multiple of 8.  On the other hand, if 12-byte TCP Time
 820                  * Stamps have been negotiated, then an MTU of 1500 bytes
 821                  * results in a TCP Data Payload of 1448 bytes which, as
 822                  * above, is a multiple of 8 bytes ...
 823                  */
 824                 for (i = 0; i < NMTUS; i++)
 825                         if (adap->params.mtus[i] == 1492) {
 826                                 adap->params.mtus[i] = 1488;
 827                                 break;
 828                         }
 829
 830                 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
 831                              adap->params.b_wnd);
 832         }
 833         t4_init_sge_params(adap);
 834         t4_init_tp_params(adap);
 835         configure_pcie_ext_tag(adap);
 836
 837         adap->params.drv_memwin = MEMWIN_NIC;
 838         adap->flags |= FW_OK;
 839         dev_debug(adap, "%s: returning zero..\n", __func__);
 840         return 0;
 841
 842         /*
 843          * Something bad happened.  If a command timed out or failed with EIO
 844          * FW does not operate within its spec or something catastrophic
 845          * happened to HW/FW, stop issuing commands.
 846          */
 847 bye:
 848         if (ret != -ETIMEDOUT && ret != -EIO)
 849                 t4_fw_bye(adap, adap->mbox);
 850         return ret;
 851 }
 852
 853 /**
 854  * t4_os_portmod_changed - handle port module changes
 855  * @adap: the adapter associated with the module change
 856  * @port_id: the port index whose module status has changed
 857  *
 858  * This is the OS-dependent handler for port module changes.  It is
 859  * invoked when a port module is removed or inserted for any OS-specific
 860  * processing.
 861  */
 862 void t4_os_portmod_changed(const struct adapter *adap, int port_id)
 863 {
 864         static const char * const mod_str[] = {
 865                 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
 866         };
 867
 868         const struct port_info *pi = adap2pinfo(adap, port_id);
 869
 870         if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
 871                 dev_info(adap, "Port%d: port module unplugged\n", pi->port_id);
 872         else if (pi->mod_type < ARRAY_SIZE(mod_str))
 873                 dev_info(adap, "Port%d: %s port module inserted\n", pi->port_id,
 874                          mod_str[pi->mod_type]);
 875         else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
 876                 dev_info(adap, "Port%d: unsupported port module inserted\n",
 877                          pi->port_id);
 878         else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
 879                 dev_info(adap, "Port%d: unknown port module inserted\n",
 880                          pi->port_id);
 881         else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR)
 882                 dev_info(adap, "Port%d: transceiver module error\n",
 883                          pi->port_id);
 884         else
 885                 dev_info(adap, "Port%d: unknown module type %d inserted\n",
 886                          pi->port_id, pi->mod_type);
 887 }
 888
 889 /**
 890  * link_start - enable a port
 891  * @dev: the port to enable
 892  *
 893  * Performs the MAC and PHY actions needed to enable a port.
 894  */
 895 int link_start(struct port_info *pi)
 896 {
 897         struct adapter *adapter = pi->adapter;
 898         int ret;
 899         unsigned int mtu;
 900
 901         mtu = pi->eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 902               (ETHER_HDR_LEN + ETHER_CRC_LEN);
 903
 904         /*
 905          * We do not set address filters and promiscuity here, the stack does
 906          * that step explicitly.
 907          */
 908         ret = t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu, -1, -1,
 909                             -1, 1, true);
 910         if (ret == 0) {
 911                 ret = t4_change_mac(adapter, adapter->mbox, pi->viid,
 912                                     pi->xact_addr_filt,
 913                                     (u8 *)&pi->eth_dev->data->mac_addrs[0],
 914                                     true, true);
 915                 if (ret >= 0) {
 916                         pi->xact_addr_filt = ret;
 917                         ret = 0;
 918                 }
 919         }
 920         if (ret == 0)
 921                 ret = t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,
 922                                     &pi->link_cfg);
 923         if (ret == 0) {
 924                 /*
 925                  * Enabling a Virtual Interface can result in an interrupt
 926                  * during the processing of the VI Enable command and, in some
 927                  * paths, result in an attempt to issue another command in the
 928                  * interrupt context.  Thus, we disable interrupts during the
 929                  * course of the VI Enable command ...
 930                  */
 931                 ret = t4_enable_vi_params(adapter, adapter->mbox, pi->viid,
 932                                           true, true, false);
 933         }
 934         return ret;
 935 }
 936
 937 /**
 938  * cxgbe_write_rss_conf - flash the RSS configuration for a given port
 939  * @pi: the port
 940  * @rss_hf: Hash configuration to apply
 941  */
 942 int cxgbe_write_rss_conf(const struct port_info *pi, uint64_t rss_hf)
 943 {
 944         struct adapter *adapter = pi->adapter;
 945         const struct sge_eth_rxq *rxq;
 946         u64 flags = 0;
 947         u16 rss;
 948         int err;
 949
 950         /*  Should never be called before setting up sge eth rx queues */
 951         if (!(adapter->flags & FULL_INIT_DONE)) {
 952                 dev_err(adap, "%s No RXQs available on port %d\n",
 953                         __func__, pi->port_id);
 954                 return -EINVAL;
 955         }
 956
 957         /* Don't allow unsupported hash functions */
 958         if (rss_hf & ~CXGBE_RSS_HF_ALL)
 959                 return -EINVAL;
 960
 961         if (rss_hf & ETH_RSS_IPV4)
 962                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN;
 963
 964         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
 965                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
 966
 967         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
 968                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
 969                          F_FW_RSS_VI_CONFIG_CMD_UDPEN;
 970
 971         if (rss_hf & ETH_RSS_IPV6)
 972                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN;
 973
 974         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
 975                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
 976
 977         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
 978                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN |
 979                          F_FW_RSS_VI_CONFIG_CMD_UDPEN;
 980
 981         rxq = &adapter->sge.ethrxq[pi->first_qset];
 982         rss = rxq[0].rspq.abs_id;
 983
 984         /* If Tunnel All Lookup isn't specified in the global RSS
 985          * Configuration, then we need to specify a default Ingress
 986          * Queue for any ingress packets which aren't hashed.  We'll
 987          * use our first ingress queue ...
 988          */
 989         err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,
 990                                flags, rss);
 991         return err;
 992 }
 993
 994 /**
 995  * cxgbe_write_rss - write the RSS table for a given port
 996  * @pi: the port
 997  * @queues: array of queue indices for RSS
 998  *
 999  * Sets up the portion of the HW RSS table for the port's VI to distribute
1000  * packets to the Rx queues in @queues.
1001  */
1002 int cxgbe_write_rss(const struct port_info *pi, const u16 *queues)
1003 {
1004         u16 *rss;
1005         int i, err;
1006         struct adapter *adapter = pi->adapter;
1007         const struct sge_eth_rxq *rxq;
1008
1009         /*  Should never be called before setting up sge eth rx queues */
1010         BUG_ON(!(adapter->flags & FULL_INIT_DONE));
1011
1012         rxq = &adapter->sge.ethrxq[pi->first_qset];
1013         rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0);
1014         if (!rss)
1015                 return -ENOMEM;
1016
1017         /* map the queue indices to queue ids */
1018         for (i = 0; i < pi->rss_size; i++, queues++)
1019                 rss[i] = rxq[*queues].rspq.abs_id;
1020
1021         err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0,
1022                                   pi->rss_size, rss, pi->rss_size);
1023         rte_free(rss);
1024         return err;
1025 }
1026
1027 /**
1028  * setup_rss - configure RSS
1029  * @adapter: the adapter
1030  *
1031  * Sets up RSS to distribute packets to multiple receive queues.  We
1032  * configure the RSS CPU lookup table to distribute to the number of HW
1033  * receive queues, and the response queue lookup table to narrow that
1034  * down to the response queues actually configured for each port.
1035  * We always configure the RSS mapping for all ports since the mapping
1036  * table has plenty of entries.
1037  */
1038 int setup_rss(struct port_info *pi)
1039 {
1040         int j, err;
1041         struct adapter *adapter = pi->adapter;
1042
1043         dev_debug(adapter, "%s:  pi->rss_size = %u; pi->n_rx_qsets = %u\n",
1044                   __func__, pi->rss_size, pi->n_rx_qsets);
1045
1046         if (!(pi->flags & PORT_RSS_DONE)) {
1047                 if (adapter->flags & FULL_INIT_DONE) {
1048                         /* Fill default values with equal distribution */
1049                         for (j = 0; j < pi->rss_size; j++)
1050                                 pi->rss[j] = j % pi->n_rx_qsets;
1051
1052                         err = cxgbe_write_rss(pi, pi->rss);
1053                         if (err)
1054                                 return err;
1055
1056                         err = cxgbe_write_rss_conf(pi, pi->rss_hf);
1057                         if (err)
1058                                 return err;
1059                         pi->flags |= PORT_RSS_DONE;
1060                 }
1061         }
1062         return 0;
1063 }
1064
1065 /*
1066  * Enable NAPI scheduling and interrupt generation for all Rx queues.
1067  */
1068 static void enable_rx(struct adapter *adap, struct sge_rspq *q)
1069 {
1070         /* 0-increment GTS to start the timer and enable interrupts */
1071         t4_write_reg(adap, MYPF_REG(A_SGE_PF_GTS),
1072                      V_SEINTARM(q->intr_params) |
1073                      V_INGRESSQID(q->cntxt_id));
1074 }
1075
1076 void cxgbe_enable_rx_queues(struct port_info *pi)
1077 {
1078         struct adapter *adap = pi->adapter;
1079         struct sge *s = &adap->sge;
1080         unsigned int i;
1081
1082         for (i = 0; i < pi->n_rx_qsets; i++)
1083                 enable_rx(adap, &s->ethrxq[pi->first_qset + i].rspq);
1084 }
1085
1086 /**
1087  * fw_caps_to_speed_caps - translate Firmware Port Caps to Speed Caps.
1088  * @port_type: Firmware Port Type
1089  * @fw_caps: Firmware Port Capabilities
1090  * @speed_caps: Device Info Speed Capabilities
1091  *
1092  * Translate a Firmware Port Capabilities specification to Device Info
1093  * Speed Capabilities.
1094  */
1095 static void fw_caps_to_speed_caps(enum fw_port_type port_type,
1096                                   unsigned int fw_caps,
1097                                   u32 *speed_caps)
1098 {
1099 #define SET_SPEED(__speed_name) \
1100         do { \
1101                 *speed_caps |= ETH_LINK_ ## __speed_name; \
1102         } while (0)
1103
1104 #define FW_CAPS_TO_SPEED(__fw_name) \
1105         do { \
1106                 if (fw_caps & FW_PORT_CAP32_ ## __fw_name) \
1107                         SET_SPEED(__fw_name); \
1108         } while (0)
1109
1110         switch (port_type) {
1111         case FW_PORT_TYPE_BT_SGMII:
1112         case FW_PORT_TYPE_BT_XFI:
1113         case FW_PORT_TYPE_BT_XAUI:
1114                 FW_CAPS_TO_SPEED(SPEED_100M);
1115                 FW_CAPS_TO_SPEED(SPEED_1G);
1116                 FW_CAPS_TO_SPEED(SPEED_10G);
1117                 break;
1118
1119         case FW_PORT_TYPE_KX4:
1120         case FW_PORT_TYPE_KX:
1121         case FW_PORT_TYPE_FIBER_XFI:
1122         case FW_PORT_TYPE_FIBER_XAUI:
1123         case FW_PORT_TYPE_SFP:
1124         case FW_PORT_TYPE_QSFP_10G:
1125         case FW_PORT_TYPE_QSA:
1126                 FW_CAPS_TO_SPEED(SPEED_1G);
1127                 FW_CAPS_TO_SPEED(SPEED_10G);
1128                 break;
1129
1130         case FW_PORT_TYPE_KR:
1131                 SET_SPEED(SPEED_10G);
1132                 break;
1133
1134         case FW_PORT_TYPE_BP_AP:
1135         case FW_PORT_TYPE_BP4_AP:
1136                 SET_SPEED(SPEED_1G);
1137                 SET_SPEED(SPEED_10G);
1138                 break;
1139
1140         case FW_PORT_TYPE_BP40_BA:
1141         case FW_PORT_TYPE_QSFP:
1142                 SET_SPEED(SPEED_40G);
1143                 break;
1144
1145         case FW_PORT_TYPE_CR_QSFP:
1146         case FW_PORT_TYPE_SFP28:
1147         case FW_PORT_TYPE_KR_SFP28:
1148                 FW_CAPS_TO_SPEED(SPEED_1G);
1149                 FW_CAPS_TO_SPEED(SPEED_10G);
1150                 FW_CAPS_TO_SPEED(SPEED_25G);
1151                 break;
1152
1153         case FW_PORT_TYPE_CR2_QSFP:
1154                 SET_SPEED(SPEED_50G);
1155                 break;
1156
1157         case FW_PORT_TYPE_KR4_100G:
1158         case FW_PORT_TYPE_CR4_QSFP:
1159                 FW_CAPS_TO_SPEED(SPEED_25G);
1160                 FW_CAPS_TO_SPEED(SPEED_40G);
1161                 FW_CAPS_TO_SPEED(SPEED_50G);
1162                 FW_CAPS_TO_SPEED(SPEED_100G);
1163                 break;
1164
1165         default:
1166                 break;
1167         }
1168
1169 #undef FW_CAPS_TO_SPEED
1170 #undef SET_SPEED
1171 }
1172
1173 /**
1174  * cxgbe_get_speed_caps - Fetch supported speed capabilities
1175  * @pi: Underlying port's info
1176  * @speed_caps: Device Info speed capabilities
1177  *
1178  * Fetch supported speed capabilities of the underlying port.
1179  */
1180 void cxgbe_get_speed_caps(struct port_info *pi, u32 *speed_caps)
1181 {
1182         *speed_caps = 0;
1183
1184         fw_caps_to_speed_caps(pi->port_type, pi->link_cfg.pcaps,
1185                               speed_caps);
1186
1187         if (!(pi->link_cfg.pcaps & FW_PORT_CAP32_ANEG))
1188                 *speed_caps |= ETH_LINK_SPEED_FIXED;
1189 }
1190
1191 /**
1192  * cxgb_up - enable the adapter
1193  * @adap: adapter being enabled
1194  *
1195  * Called when the first port is enabled, this function performs the
1196  * actions necessary to make an adapter operational, such as completing
1197  * the initialization of HW modules, and enabling interrupts.
1198  */
1199 int cxgbe_up(struct adapter *adap)
1200 {
1201         enable_rx(adap, &adap->sge.fw_evtq);
1202         t4_sge_tx_monitor_start(adap);
1203         t4_intr_enable(adap);
1204         adap->flags |= FULL_INIT_DONE;
1205
1206         /* TODO: deadman watchdog ?? */
1207         return 0;
1208 }
1209
1210 /*
1211  * Close the port
1212  */
1213 int cxgbe_down(struct port_info *pi)
1214 {
1215         struct adapter *adapter = pi->adapter;
1216         int err = 0;
1217
1218         err = t4_enable_vi(adapter, adapter->mbox, pi->viid, false, false);
1219         if (err) {
1220                 dev_err(adapter, "%s: disable_vi failed: %d\n", __func__, err);
1221                 return err;
1222         }
1223
1224         t4_reset_link_config(adapter, pi->port_id);
1225         return 0;
1226 }
1227
1228 /*
1229  * Release resources when all the ports have been stopped.
1230  */
1231 void cxgbe_close(struct adapter *adapter)
1232 {
1233         struct port_info *pi;
1234         int i;
1235
1236         if (adapter->flags & FULL_INIT_DONE) {
1237                 t4_intr_disable(adapter);
1238                 t4_sge_tx_monitor_stop(adapter);
1239                 t4_free_sge_resources(adapter);
1240                 for_each_port(adapter, i) {
1241                         pi = adap2pinfo(adapter, i);
1242                         if (pi->viid != 0)
1243                                 t4_free_vi(adapter, adapter->mbox,
1244                                            adapter->pf, 0, pi->viid);
1245                         rte_free(pi->eth_dev->data->mac_addrs);
1246                         /* Skip first port since it'll be freed by DPDK stack */
1247                         if (i) {
1248                                 rte_free(pi->eth_dev->data->dev_private);
1249                                 rte_eth_dev_release_port(pi->eth_dev);
1250                         }
1251                 }
1252                 adapter->flags &= ~FULL_INIT_DONE;
1253         }
1254
1255         if (adapter->flags & FW_OK)
1256                 t4_fw_bye(adapter, adapter->mbox);
1257 }
1258
1259 int cxgbe_probe(struct adapter *adapter)
1260 {
1261         struct port_info *pi;
1262         int chip;
1263         int func, i;
1264         int err = 0;
1265         u32 whoami;
1266
1267         whoami = t4_read_reg(adapter, A_PL_WHOAMI);
1268         chip = t4_get_chip_type(adapter,
1269                         CHELSIO_PCI_ID_VER(adapter->pdev->id.device_id));
1270         if (chip < 0)
1271                 return chip;
1272
1273         func = CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5 ?
1274                G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
1275
1276         adapter->mbox = func;
1277         adapter->pf = func;
1278
1279         t4_os_lock_init(&adapter->mbox_lock);
1280         TAILQ_INIT(&adapter->mbox_list);
1281
1282         err = t4_prep_adapter(adapter);
1283         if (err)
1284                 return err;
1285
1286         setup_memwin(adapter);
1287         err = adap_init0(adapter);
1288         if (err) {
1289                 dev_err(adapter, "%s: Adapter initialization failed, error %d\n",
1290                         __func__, err);
1291                 goto out_free;
1292         }
1293
1294         if (!is_t4(adapter->params.chip)) {
1295                 /*
1296                  * The userspace doorbell BAR is split evenly into doorbell
1297                  * regions, each associated with an egress queue.  If this
1298                  * per-queue region is large enough (at least UDBS_SEG_SIZE)
1299                  * then it can be used to submit a tx work request with an
1300                  * implied doorbell.  Enable write combining on the BAR if
1301                  * there is room for such work requests.
1302                  */
1303                 int s_qpp, qpp, num_seg;
1304
1305                 s_qpp = (S_QUEUESPERPAGEPF0 +
1306                         (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) *
1307                         adapter->pf);
1308                 qpp = 1 << ((t4_read_reg(adapter,
1309                                 A_SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp)
1310                                 & M_QUEUESPERPAGEPF0);
1311                 num_seg = CXGBE_PAGE_SIZE / UDBS_SEG_SIZE;
1312                 if (qpp > num_seg)
1313                         dev_warn(adapter, "Incorrect SGE EGRESS QUEUES_PER_PAGE configuration, continuing in debug mode\n");
1314
1315                 adapter->bar2 = (void *)adapter->pdev->mem_resource[2].addr;
1316                 if (!adapter->bar2) {
1317                         dev_err(adapter, "cannot map device bar2 region\n");
1318                         err = -ENOMEM;
1319                         goto out_free;
1320                 }
1321                 t4_write_reg(adapter, A_SGE_STAT_CFG, V_STATSOURCE_T5(7) |
1322                              V_STATMODE(0));
1323         }
1324
1325         for_each_port(adapter, i) {
1326                 const unsigned int numa_node = rte_socket_id();
1327                 char name[RTE_ETH_NAME_MAX_LEN];
1328                 struct rte_eth_dev *eth_dev;
1329
1330                 snprintf(name, sizeof(name), "%s_%d",
1331                          adapter->pdev->device.name, i);
1332
1333                 if (i == 0) {
1334                         /* First port is already allocated by DPDK */
1335                         eth_dev = adapter->eth_dev;
1336                         goto allocate_mac;
1337                 }
1338
1339                 /*
1340                  * now do all data allocation - for eth_dev structure,
1341                  * and internal (private) data for the remaining ports
1342                  */
1343
1344                 /* reserve an ethdev entry */
1345                 eth_dev = rte_eth_dev_allocate(name);
1346                 if (!eth_dev)
1347                         goto out_free;
1348
1349                 eth_dev->data->dev_private =
1350                         rte_zmalloc_socket(name, sizeof(struct port_info),
1351                                            RTE_CACHE_LINE_SIZE, numa_node);
1352                 if (!eth_dev->data->dev_private)
1353                         goto out_free;
1354
1355 allocate_mac:
1356                 pi = (struct port_info *)eth_dev->data->dev_private;
1357                 adapter->port[i] = pi;
1358                 pi->eth_dev = eth_dev;
1359                 pi->adapter = adapter;
1360                 pi->xact_addr_filt = -1;
1361                 pi->port_id = i;
1362
1363                 pi->eth_dev->device = &adapter->pdev->device;
1364                 pi->eth_dev->dev_ops = adapter->eth_dev->dev_ops;
1365                 pi->eth_dev->tx_pkt_burst = adapter->eth_dev->tx_pkt_burst;
1366                 pi->eth_dev->rx_pkt_burst = adapter->eth_dev->rx_pkt_burst;
1367
1368                 rte_eth_copy_pci_info(pi->eth_dev, adapter->pdev);
1369
1370                 pi->eth_dev->data->mac_addrs = rte_zmalloc(name,
1371                                                            ETHER_ADDR_LEN, 0);
1372                 if (!pi->eth_dev->data->mac_addrs) {
1373                         dev_err(adapter, "%s: Mem allocation failed for storing mac addr, aborting\n",
1374                                 __func__);
1375                         err = -1;
1376                         goto out_free;
1377                 }
1378         }
1379
1380         if (adapter->flags & FW_OK) {
1381                 err = t4_port_init(adapter, adapter->mbox, adapter->pf, 0);
1382                 if (err) {
1383                         dev_err(adapter, "%s: t4_port_init failed with err %d\n",
1384                                 __func__, err);
1385                         goto out_free;
1386                 }
1387         }
1388
1389         cfg_queues(adapter->eth_dev);
1390
1391         print_adapter_info(adapter);
1392         print_port_info(adapter);
1393
1394         err = init_rss(adapter);
1395         if (err)
1396                 goto out_free;
1397
1398         return 0;
1399
1400 out_free:
1401         for_each_port(adapter, i) {
1402                 pi = adap2pinfo(adapter, i);
1403                 if (pi->viid != 0)
1404                         t4_free_vi(adapter, adapter->mbox, adapter->pf,
1405                                    0, pi->viid);
1406                 /* Skip first port since it'll be de-allocated by DPDK */
1407                 if (i == 0)
1408                         continue;
1409                 if (pi->eth_dev) {
1410                         if (pi->eth_dev->data->dev_private)
1411                                 rte_free(pi->eth_dev->data->dev_private);
1412                         rte_eth_dev_release_port(pi->eth_dev);
1413                 }
1414         }
1415
1416         if (adapter->flags & FW_OK)
1417                 t4_fw_bye(adapter, adapter->mbox);
1418         return -err;
1419 }