drivers/net/cxgbe/cxgbe_main.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2014-2017 Chelsio Communications.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Chelsio Communications nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43
  44 #include <rte_byteorder.h>
  45 #include <rte_common.h>
  46 #include <rte_cycles.h>
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_tailq.h>
  56 #include <rte_eal.h>
  57 #include <rte_alarm.h>
  58 #include <rte_ether.h>
  59 #include <rte_ethdev.h>
  60 #include <rte_ethdev_pci.h>
  61 #include <rte_atomic.h>
  62 #include <rte_malloc.h>
  63 #include <rte_random.h>
  64 #include <rte_dev.h>
  65
  66 #include "common.h"
  67 #include "t4_regs.h"
  68 #include "t4_msg.h"
  69 #include "cxgbe.h"
  70
  71 /*
  72  * Response queue handler for the FW event queue.
  73  */
  74 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
  75                           __rte_unused const struct pkt_gl *gl)
  76 {
  77         u8 opcode = ((const struct rss_header *)rsp)->opcode;
  78
  79         rsp++;                                          /* skip RSS header */
  80
  81         /*
  82          * FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
  83          */
  84         if (unlikely(opcode == CPL_FW4_MSG &&
  85                      ((const struct cpl_fw4_msg *)rsp)->type ==
  86                       FW_TYPE_RSSCPL)) {
  87                 rsp++;
  88                 opcode = ((const struct rss_header *)rsp)->opcode;
  89                 rsp++;
  90                 if (opcode != CPL_SGE_EGR_UPDATE) {
  91                         dev_err(q->adapter, "unexpected FW4/CPL %#x on FW event queue\n",
  92                                 opcode);
  93                         goto out;
  94                 }
  95         }
  96
  97         if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
  98                 /* do nothing */
  99         } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
 100                 const struct cpl_fw6_msg *msg = (const void *)rsp;
 101
 102                 t4_handle_fw_rpl(q->adapter, msg->data);
 103         } else {
 104                 dev_err(adapter, "unexpected CPL %#x on FW event queue\n",
 105                         opcode);
 106         }
 107 out:
 108         return 0;
 109 }
 110
 111 int setup_sge_fwevtq(struct adapter *adapter)
 112 {
 113         struct sge *s = &adapter->sge;
 114         int err = 0;
 115         int msi_idx = 0;
 116
 117         err = t4_sge_alloc_rxq(adapter, &s->fw_evtq, true, adapter->eth_dev,
 118                                msi_idx, NULL, fwevtq_handler, -1, NULL, 0,
 119                                rte_socket_id());
 120         return err;
 121 }
 122
 123 static int closest_timer(const struct sge *s, int time)
 124 {
 125         unsigned int i, match = 0;
 126         int delta, min_delta = INT_MAX;
 127
 128         for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
 129                 delta = time - s->timer_val[i];
 130                 if (delta < 0)
 131                         delta = -delta;
 132                 if (delta < min_delta) {
 133                         min_delta = delta;
 134                         match = i;
 135                 }
 136         }
 137         return match;
 138 }
 139
 140 static int closest_thres(const struct sge *s, int thres)
 141 {
 142         unsigned int i, match = 0;
 143         int delta, min_delta = INT_MAX;
 144
 145         for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
 146                 delta = thres - s->counter_val[i];
 147                 if (delta < 0)
 148                         delta = -delta;
 149                 if (delta < min_delta) {
 150                         min_delta = delta;
 151                         match = i;
 152                 }
 153         }
 154         return match;
 155 }
 156
 157 /**
 158  * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters
 159  * @q: the Rx queue
 160  * @us: the hold-off time in us, or 0 to disable timer
 161  * @cnt: the hold-off packet count, or 0 to disable counter
 162  *
 163  * Sets an Rx queue's interrupt hold-off time and packet count.  At least
 164  * one of the two needs to be enabled for the queue to generate interrupts.
 165  */
 166 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
 167                                unsigned int cnt)
 168 {
 169         struct adapter *adap = q->adapter;
 170         unsigned int timer_val;
 171
 172         if (cnt) {
 173                 int err;
 174                 u32 v, new_idx;
 175
 176                 new_idx = closest_thres(&adap->sge, cnt);
 177                 if (q->desc && q->pktcnt_idx != new_idx) {
 178                         /* the queue has already been created, update it */
 179                         v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
 180                             V_FW_PARAMS_PARAM_X(
 181                             FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
 182                             V_FW_PARAMS_PARAM_YZ(q->cntxt_id);
 183                         err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
 184                                             &v, &new_idx);
 185                         if (err)
 186                                 return err;
 187                 }
 188                 q->pktcnt_idx = new_idx;
 189         }
 190
 191         timer_val = (us == 0) ? X_TIMERREG_RESTART_COUNTER :
 192                                 closest_timer(&adap->sge, us);
 193
 194         if ((us | cnt) == 0)
 195                 q->intr_params = V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX);
 196         else
 197                 q->intr_params = V_QINTR_TIMER_IDX(timer_val) |
 198                                  V_QINTR_CNT_EN(cnt > 0);
 199         return 0;
 200 }
 201
 202 static inline bool is_x_1g_port(const struct link_config *lc)
 203 {
 204         return (lc->supported & FW_PORT_CAP_SPEED_1G) != 0;
 205 }
 206
 207 static inline bool is_x_10g_port(const struct link_config *lc)
 208 {
 209         unsigned int speeds, high_speeds;
 210
 211         speeds = V_FW_PORT_CAP_SPEED(G_FW_PORT_CAP_SPEED(lc->supported));
 212         high_speeds = speeds & ~(FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G);
 213
 214         return high_speeds != 0;
 215 }
 216
 217 inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
 218                       unsigned int us, unsigned int cnt,
 219                       unsigned int size, unsigned int iqe_size)
 220 {
 221         q->adapter = adap;
 222         cxgb4_set_rspq_intr_params(q, us, cnt);
 223         q->iqe_len = iqe_size;
 224         q->size = size;
 225 }
 226
 227 int cfg_queue_count(struct rte_eth_dev *eth_dev)
 228 {
 229         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 230         struct adapter *adap = pi->adapter;
 231         struct sge *s = &adap->sge;
 232         unsigned int max_queues = s->max_ethqsets / adap->params.nports;
 233
 234         if ((eth_dev->data->nb_rx_queues < 1) ||
 235             (eth_dev->data->nb_tx_queues < 1))
 236                 return -EINVAL;
 237
 238         if ((eth_dev->data->nb_rx_queues > max_queues) ||
 239             (eth_dev->data->nb_tx_queues > max_queues))
 240                 return -EINVAL;
 241
 242         if (eth_dev->data->nb_rx_queues > pi->rss_size)
 243                 return -EINVAL;
 244
 245         /* We must configure RSS, since config has changed*/
 246         pi->flags &= ~PORT_RSS_DONE;
 247
 248         pi->n_rx_qsets = eth_dev->data->nb_rx_queues;
 249         pi->n_tx_qsets = eth_dev->data->nb_tx_queues;
 250
 251         return 0;
 252 }
 253
 254 void cfg_queues(struct rte_eth_dev *eth_dev)
 255 {
 256         struct rte_config *config = rte_eal_get_configuration();
 257         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 258         struct adapter *adap = pi->adapter;
 259         struct sge *s = &adap->sge;
 260         unsigned int i, nb_ports = 0, qidx = 0;
 261         unsigned int q_per_port = 0;
 262
 263         if (!(adap->flags & CFG_QUEUES)) {
 264                 for_each_port(adap, i) {
 265                         struct port_info *tpi = adap2pinfo(adap, i);
 266
 267                         nb_ports += (is_x_10g_port(&tpi->link_cfg)) ||
 268                                      is_x_1g_port(&tpi->link_cfg) ? 1 : 0;
 269                 }
 270
 271                 /*
 272                  * We default up to # of cores queues per 1G/10G port.
 273                  */
 274                 if (nb_ports)
 275                         q_per_port = (MAX_ETH_QSETS -
 276                                      (adap->params.nports - nb_ports)) /
 277                                      nb_ports;
 278
 279                 if (q_per_port > config->lcore_count)
 280                         q_per_port = config->lcore_count;
 281
 282                 for_each_port(adap, i) {
 283                         struct port_info *pi = adap2pinfo(adap, i);
 284
 285                         pi->first_qset = qidx;
 286
 287                         /* Initially n_rx_qsets == n_tx_qsets */
 288                         pi->n_rx_qsets = (is_x_10g_port(&pi->link_cfg) ||
 289                                           is_x_1g_port(&pi->link_cfg)) ?
 290                                           q_per_port : 1;
 291                         pi->n_tx_qsets = pi->n_rx_qsets;
 292
 293                         if (pi->n_rx_qsets > pi->rss_size)
 294                                 pi->n_rx_qsets = pi->rss_size;
 295
 296                         qidx += pi->n_rx_qsets;
 297                 }
 298
 299                 s->max_ethqsets = qidx;
 300
 301                 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
 302                         struct sge_eth_rxq *r = &s->ethrxq[i];
 303
 304                         init_rspq(adap, &r->rspq, 5, 32, 1024, 64);
 305                         r->usembufs = 1;
 306                         r->fl.size = (r->usembufs ? 1024 : 72);
 307                 }
 308
 309                 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
 310                         s->ethtxq[i].q.size = 1024;
 311
 312                 init_rspq(adap, &adap->sge.fw_evtq, 0, 0, 1024, 64);
 313                 adap->flags |= CFG_QUEUES;
 314         }
 315 }
 316
 317 void cxgbe_stats_get(struct port_info *pi, struct port_stats *stats)
 318 {
 319         t4_get_port_stats_offset(pi->adapter, pi->tx_chan, stats,
 320                                  &pi->stats_base);
 321 }
 322
 323 void cxgbe_stats_reset(struct port_info *pi)
 324 {
 325         t4_clr_port_stats(pi->adapter, pi->tx_chan);
 326 }
 327
 328 static void setup_memwin(struct adapter *adap)
 329 {
 330         u32 mem_win0_base;
 331
 332         /* For T5, only relative offset inside the PCIe BAR is passed */
 333         mem_win0_base = MEMWIN0_BASE;
 334
 335         /*
 336          * Set up memory window for accessing adapter memory ranges.  (Read
 337          * back MA register to ensure that changes propagate before we attempt
 338          * to use the new values.)
 339          */
 340         t4_write_reg(adap,
 341                      PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN,
 342                                          MEMWIN_NIC),
 343                      mem_win0_base | V_BIR(0) |
 344                      V_WINDOW(ilog2(MEMWIN0_APERTURE) - X_WINDOW_SHIFT));
 345         t4_read_reg(adap,
 346                     PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN,
 347                                         MEMWIN_NIC));
 348 }
 349
 350 static int init_rss(struct adapter *adap)
 351 {
 352         unsigned int i;
 353         int err;
 354
 355         err = t4_init_rss_mode(adap, adap->mbox);
 356         if (err)
 357                 return err;
 358
 359         for_each_port(adap, i) {
 360                 struct port_info *pi = adap2pinfo(adap, i);
 361
 362                 pi->rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0);
 363                 if (!pi->rss)
 364                         return -ENOMEM;
 365         }
 366         return 0;
 367 }
 368
 369 /**
 370  * Dump basic information about the adapter.
 371  */
 372 static void print_adapter_info(struct adapter *adap)
 373 {
 374         /**
 375          * Hardware/Firmware/etc. Version/Revision IDs.
 376          */
 377         t4_dump_version_info(adap);
 378 }
 379
 380 static void print_port_info(struct adapter *adap)
 381 {
 382         int i;
 383         char buf[80];
 384         struct rte_pci_addr *loc = &adap->pdev->addr;
 385
 386         for_each_port(adap, i) {
 387                 const struct port_info *pi = &adap->port[i];
 388                 char *bufp = buf;
 389
 390                 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M)
 391                         bufp += sprintf(bufp, "100M/");
 392                 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G)
 393                         bufp += sprintf(bufp, "1G/");
 394                 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G)
 395                         bufp += sprintf(bufp, "10G/");
 396                 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G)
 397                         bufp += sprintf(bufp, "25G/");
 398                 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G)
 399                         bufp += sprintf(bufp, "40G/");
 400                 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G)
 401                         bufp += sprintf(bufp, "100G/");
 402                 if (bufp != buf)
 403                         --bufp;
 404                 sprintf(bufp, "BASE-%s",
 405                         t4_get_port_type_description(
 406                                         (enum fw_port_type)pi->port_type));
 407
 408                 dev_info(adap,
 409                          " " PCI_PRI_FMT " Chelsio rev %d %s %s\n",
 410                          loc->domain, loc->bus, loc->devid, loc->function,
 411                          CHELSIO_CHIP_RELEASE(adap->params.chip), buf,
 412                          (adap->flags & USING_MSIX) ? " MSI-X" :
 413                          (adap->flags & USING_MSI) ? " MSI" : "");
 414         }
 415 }
 416
 417 static void configure_pcie_ext_tag(struct adapter *adapter)
 418 {
 419         u16 v;
 420         int pos = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
 421
 422         if (!pos)
 423                 return;
 424
 425         if (pos > 0) {
 426                 t4_os_pci_read_cfg2(adapter, pos + PCI_EXP_DEVCTL, &v);
 427                 v |= PCI_EXP_DEVCTL_EXT_TAG;
 428                 t4_os_pci_write_cfg2(adapter, pos + PCI_EXP_DEVCTL, v);
 429                 if (is_t6(adapter->params.chip)) {
 430                         t4_set_reg_field(adapter, A_PCIE_CFG2,
 431                                          V_T6_TOTMAXTAG(M_T6_TOTMAXTAG),
 432                                          V_T6_TOTMAXTAG(7));
 433                         t4_set_reg_field(adapter, A_PCIE_CMD_CFG,
 434                                          V_T6_MINTAG(M_T6_MINTAG),
 435                                          V_T6_MINTAG(8));
 436                 } else {
 437                         t4_set_reg_field(adapter, A_PCIE_CFG2,
 438                                          V_TOTMAXTAG(M_TOTMAXTAG),
 439                                          V_TOTMAXTAG(3));
 440                         t4_set_reg_field(adapter, A_PCIE_CMD_CFG,
 441                                          V_MINTAG(M_MINTAG),
 442                                          V_MINTAG(8));
 443                 }
 444         }
 445 }
 446
 447 /*
 448  * Tweak configuration based on system architecture, etc.  Most of these have
 449  * defaults assigned to them by Firmware Configuration Files (if we're using
 450  * them) but need to be explicitly set if we're using hard-coded
 451  * initialization. So these are essentially common tweaks/settings for
 452  * Configuration Files and hard-coded initialization ...
 453  */
 454 static int adap_init0_tweaks(struct adapter *adapter)
 455 {
 456         u8 rx_dma_offset;
 457
 458         /*
 459          * Fix up various Host-Dependent Parameters like Page Size, Cache
 460          * Line Size, etc.  The firmware default is for a 4KB Page Size and
 461          * 64B Cache Line Size ...
 462          */
 463         t4_fixup_host_params_compat(adapter, CXGBE_PAGE_SIZE, L1_CACHE_BYTES,
 464                                     T5_LAST_REV);
 465
 466         /*
 467          * Keep the chip default offset to deliver Ingress packets into our
 468          * DMA buffers to zero
 469          */
 470         rx_dma_offset = 0;
 471         t4_set_reg_field(adapter, A_SGE_CONTROL, V_PKTSHIFT(M_PKTSHIFT),
 472                          V_PKTSHIFT(rx_dma_offset));
 473
 474         t4_set_reg_field(adapter, A_SGE_FLM_CFG,
 475                          V_CREDITCNT(M_CREDITCNT) | M_CREDITCNTPACKING,
 476                          V_CREDITCNT(3) | V_CREDITCNTPACKING(1));
 477
 478         t4_set_reg_field(adapter, A_SGE_INGRESS_RX_THRESHOLD,
 479                          V_THRESHOLD_3(M_THRESHOLD_3), V_THRESHOLD_3(32U));
 480
 481         t4_set_reg_field(adapter, A_SGE_CONTROL2, V_IDMAARBROUNDROBIN(1U),
 482                          V_IDMAARBROUNDROBIN(1U));
 483
 484         /*
 485          * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
 486          * adds the pseudo header itself.
 487          */
 488         t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG,
 489                                F_CSUM_HAS_PSEUDO_HDR, 0);
 490
 491         return 0;
 492 }
 493
 494 /*
 495  * Attempt to initialize the adapter via a Firmware Configuration File.
 496  */
 497 static int adap_init0_config(struct adapter *adapter, int reset)
 498 {
 499         struct fw_caps_config_cmd caps_cmd;
 500         unsigned long mtype = 0, maddr = 0;
 501         u32 finiver, finicsum, cfcsum;
 502         int ret;
 503         int config_issued = 0;
 504         int cfg_addr;
 505         char config_name[20];
 506
 507         /*
 508          * Reset device if necessary.
 509          */
 510         if (reset) {
 511                 ret = t4_fw_reset(adapter, adapter->mbox,
 512                                   F_PIORSTMODE | F_PIORST);
 513                 if (ret < 0) {
 514                         dev_warn(adapter, "Firmware reset failed, error %d\n",
 515                                  -ret);
 516                         goto bye;
 517                 }
 518         }
 519
 520         cfg_addr = t4_flash_cfg_addr(adapter);
 521         if (cfg_addr < 0) {
 522                 ret = cfg_addr;
 523                 dev_warn(adapter, "Finding address for firmware config file in flash failed, error %d\n",
 524                          -ret);
 525                 goto bye;
 526         }
 527
 528         strcpy(config_name, "On Flash");
 529         mtype = FW_MEMTYPE_CF_FLASH;
 530         maddr = cfg_addr;
 531
 532         /*
 533          * Issue a Capability Configuration command to the firmware to get it
 534          * to parse the Configuration File.  We don't use t4_fw_config_file()
 535          * because we want the ability to modify various features after we've
 536          * processed the configuration file ...
 537          */
 538         memset(&caps_cmd, 0, sizeof(caps_cmd));
 539         caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
 540                                            F_FW_CMD_REQUEST | F_FW_CMD_READ);
 541         caps_cmd.cfvalid_to_len16 =
 542                 cpu_to_be32(F_FW_CAPS_CONFIG_CMD_CFVALID |
 543                             V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
 544                             V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) |
 545                             FW_LEN16(caps_cmd));
 546         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
 547                          &caps_cmd);
 548         /*
 549          * If the CAPS_CONFIG failed with an ENOENT (for a Firmware
 550          * Configuration File in FLASH), our last gasp effort is to use the
 551          * Firmware Configuration File which is embedded in the firmware.  A
 552          * very few early versions of the firmware didn't have one embedded
 553          * but we can ignore those.
 554          */
 555         if (ret == -ENOENT) {
 556                 dev_info(adapter, "%s: Going for embedded config in firmware..\n",
 557                          __func__);
 558
 559                 memset(&caps_cmd, 0, sizeof(caps_cmd));
 560                 caps_cmd.op_to_write =
 561                         cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
 562                                     F_FW_CMD_REQUEST | F_FW_CMD_READ);
 563                 caps_cmd.cfvalid_to_len16 = cpu_to_be32(FW_LEN16(caps_cmd));
 564                 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
 565                                  sizeof(caps_cmd), &caps_cmd);
 566                 strcpy(config_name, "Firmware Default");
 567         }
 568
 569         config_issued = 1;
 570         if (ret < 0)
 571                 goto bye;
 572
 573         finiver = be32_to_cpu(caps_cmd.finiver);
 574         finicsum = be32_to_cpu(caps_cmd.finicsum);
 575         cfcsum = be32_to_cpu(caps_cmd.cfcsum);
 576         if (finicsum != cfcsum)
 577                 dev_warn(adapter, "Configuration File checksum mismatch: [fini] csum=%#x, computed csum=%#x\n",
 578                          finicsum, cfcsum);
 579
 580         /*
 581          * If we're a pure NIC driver then disable all offloading facilities.
 582          * This will allow the firmware to optimize aspects of the hardware
 583          * configuration which will result in improved performance.
 584          */
 585         caps_cmd.niccaps &= cpu_to_be16(~(FW_CAPS_CONFIG_NIC_HASHFILTER |
 586                                           FW_CAPS_CONFIG_NIC_ETHOFLD));
 587         caps_cmd.toecaps = 0;
 588         caps_cmd.iscsicaps = 0;
 589         caps_cmd.rdmacaps = 0;
 590         caps_cmd.fcoecaps = 0;
 591
 592         /*
 593          * And now tell the firmware to use the configuration we just loaded.
 594          */
 595         caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
 596                                            F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
 597         caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
 598         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
 599                          NULL);
 600         if (ret < 0) {
 601                 dev_warn(adapter, "Unable to finalize Firmware Capabilities %d\n",
 602                          -ret);
 603                 goto bye;
 604         }
 605
 606         /*
 607          * Tweak configuration based on system architecture, etc.
 608          */
 609         ret = adap_init0_tweaks(adapter);
 610         if (ret < 0) {
 611                 dev_warn(adapter, "Unable to do init0-tweaks %d\n", -ret);
 612                 goto bye;
 613         }
 614
 615         /*
 616          * And finally tell the firmware to initialize itself using the
 617          * parameters from the Configuration File.
 618          */
 619         ret = t4_fw_initialize(adapter, adapter->mbox);
 620         if (ret < 0) {
 621                 dev_warn(adapter, "Initializing Firmware failed, error %d\n",
 622                          -ret);
 623                 goto bye;
 624         }
 625
 626         /*
 627          * Return successfully and note that we're operating with parameters
 628          * not supplied by the driver, rather than from hard-wired
 629          * initialization constants buried in the driver.
 630          */
 631         dev_info(adapter,
 632                  "Successfully configured using Firmware Configuration File \"%s\", version %#x, computed checksum %#x\n",
 633                  config_name, finiver, cfcsum);
 634
 635         return 0;
 636
 637         /*
 638          * Something bad happened.  Return the error ...  (If the "error"
 639          * is that there's no Configuration File on the adapter we don't
 640          * want to issue a warning since this is fairly common.)
 641          */
 642 bye:
 643         if (config_issued && ret != -ENOENT)
 644                 dev_warn(adapter, "\"%s\" configuration file error %d\n",
 645                          config_name, -ret);
 646
 647         dev_debug(adapter, "%s: returning ret = %d ..\n", __func__, ret);
 648         return ret;
 649 }
 650
 651 static int adap_init0(struct adapter *adap)
 652 {
 653         int ret = 0;
 654         u32 v, port_vec;
 655         enum dev_state state;
 656         u32 params[7], val[7];
 657         int reset = 1;
 658         int mbox = adap->mbox;
 659
 660         /*
 661          * Contact FW, advertising Master capability.
 662          */
 663         ret = t4_fw_hello(adap, adap->mbox, adap->mbox, MASTER_MAY, &state);
 664         if (ret < 0) {
 665                 dev_err(adap, "%s: could not connect to FW, error %d\n",
 666                         __func__, -ret);
 667                 goto bye;
 668         }
 669
 670         CXGBE_DEBUG_MBOX(adap, "%s: adap->mbox = %d; ret = %d\n", __func__,
 671                          adap->mbox, ret);
 672
 673         if (ret == mbox)
 674                 adap->flags |= MASTER_PF;
 675
 676         if (state == DEV_STATE_INIT) {
 677                 /*
 678                  * Force halt and reset FW because a previous instance may have
 679                  * exited abnormally without properly shutting down
 680                  */
 681                 ret = t4_fw_halt(adap, adap->mbox, reset);
 682                 if (ret < 0) {
 683                         dev_err(adap, "Failed to halt. Exit.\n");
 684                         goto bye;
 685                 }
 686
 687                 ret = t4_fw_restart(adap, adap->mbox, reset);
 688                 if (ret < 0) {
 689                         dev_err(adap, "Failed to restart. Exit.\n");
 690                         goto bye;
 691                 }
 692                 state = (enum dev_state)((unsigned)state & ~DEV_STATE_INIT);
 693         }
 694
 695         t4_get_version_info(adap);
 696
 697         ret = t4_get_core_clock(adap, &adap->params.vpd);
 698         if (ret < 0) {
 699                 dev_err(adap, "%s: could not get core clock, error %d\n",
 700                         __func__, -ret);
 701                 goto bye;
 702         }
 703
 704         /*
 705          * If the firmware is initialized already (and we're not forcing a
 706          * master initialization), note that we're living with existing
 707          * adapter parameters.  Otherwise, it's time to try initializing the
 708          * adapter ...
 709          */
 710         if (state == DEV_STATE_INIT) {
 711                 dev_info(adap, "Coming up as %s: Adapter already initialized\n",
 712                          adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
 713         } else {
 714                 dev_info(adap, "Coming up as MASTER: Initializing adapter\n");
 715
 716                 ret = adap_init0_config(adap, reset);
 717                 if (ret == -ENOENT) {
 718                         dev_err(adap,
 719                                 "No Configuration File present on adapter. Using hard-wired configuration parameters.\n");
 720                         goto bye;
 721                 }
 722         }
 723         if (ret < 0) {
 724                 dev_err(adap, "could not initialize adapter, error %d\n", -ret);
 725                 goto bye;
 726         }
 727
 728         /* Find out what ports are available to us. */
 729         v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
 730             V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_PORTVEC);
 731         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec);
 732         if (ret < 0) {
 733                 dev_err(adap, "%s: failure in t4_query_params; error = %d\n",
 734                         __func__, ret);
 735                 goto bye;
 736         }
 737
 738         adap->params.nports = hweight32(port_vec);
 739         adap->params.portvec = port_vec;
 740
 741         dev_debug(adap, "%s: adap->params.nports = %u\n", __func__,
 742                   adap->params.nports);
 743
 744         /*
 745          * Give the SGE code a chance to pull in anything that it needs ...
 746          * Note that this must be called after we retrieve our VPD parameters
 747          * in order to know how to convert core ticks to seconds, etc.
 748          */
 749         ret = t4_sge_init(adap);
 750         if (ret < 0) {
 751                 dev_err(adap, "t4_sge_init failed with error %d\n",
 752                         -ret);
 753                 goto bye;
 754         }
 755
 756         /*
 757          * Grab some of our basic fundamental operating parameters.
 758          */
 759 #define FW_PARAM_DEV(param) \
 760         (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
 761          V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
 762
 763 #define FW_PARAM_PFVF(param) \
 764         (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
 765          V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param) |  \
 766          V_FW_PARAMS_PARAM_Y(0) | \
 767          V_FW_PARAMS_PARAM_Z(0))
 768
 769         /* If we're running on newer firmware, let it know that we're
 770          * prepared to deal with encapsulated CPL messages.  Older
 771          * firmware won't understand this and we'll just get
 772          * unencapsulated messages ...
 773          */
 774         params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
 775         val[0] = 1;
 776         (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
 777
 778         /*
 779          * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
 780          * capability.  Earlier versions of the firmware didn't have the
 781          * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
 782          * permission to use ULPTX MEMWRITE DSGL.
 783          */
 784         if (is_t4(adap->params.chip)) {
 785                 adap->params.ulptx_memwrite_dsgl = false;
 786         } else {
 787                 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
 788                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
 789                                       1, params, val);
 790                 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
 791         }
 792
 793         /*
 794          * The MTU/MSS Table is initialized by now, so load their values.  If
 795          * we're initializing the adapter, then we'll make any modifications
 796          * we want to the MTU/MSS Table and also initialize the congestion
 797          * parameters.
 798          */
 799         t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
 800         if (state != DEV_STATE_INIT) {
 801                 int i;
 802
 803                 /*
 804                  * The default MTU Table contains values 1492 and 1500.
 805                  * However, for TCP, it's better to have two values which are
 806                  * a multiple of 8 +/- 4 bytes apart near this popular MTU.
 807                  * This allows us to have a TCP Data Payload which is a
 808                  * multiple of 8 regardless of what combination of TCP Options
 809                  * are in use (always a multiple of 4 bytes) which is
 810                  * important for performance reasons.  For instance, if no
 811                  * options are in use, then we have a 20-byte IP header and a
 812                  * 20-byte TCP header.  In this case, a 1500-byte MSS would
 813                  * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
 814                  * which is not a multiple of 8.  So using an MSS of 1488 in
 815                  * this case results in a TCP Data Payload of 1448 bytes which
 816                  * is a multiple of 8.  On the other hand, if 12-byte TCP Time
 817                  * Stamps have been negotiated, then an MTU of 1500 bytes
 818                  * results in a TCP Data Payload of 1448 bytes which, as
 819                  * above, is a multiple of 8 bytes ...
 820                  */
 821                 for (i = 0; i < NMTUS; i++)
 822                         if (adap->params.mtus[i] == 1492) {
 823                                 adap->params.mtus[i] = 1488;
 824                                 break;
 825                         }
 826
 827                 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
 828                              adap->params.b_wnd);
 829         }
 830         t4_init_sge_params(adap);
 831         t4_init_tp_params(adap);
 832         configure_pcie_ext_tag(adap);
 833
 834         adap->params.drv_memwin = MEMWIN_NIC;
 835         adap->flags |= FW_OK;
 836         dev_debug(adap, "%s: returning zero..\n", __func__);
 837         return 0;
 838
 839         /*
 840          * Something bad happened.  If a command timed out or failed with EIO
 841          * FW does not operate within its spec or something catastrophic
 842          * happened to HW/FW, stop issuing commands.
 843          */
 844 bye:
 845         if (ret != -ETIMEDOUT && ret != -EIO)
 846                 t4_fw_bye(adap, adap->mbox);
 847         return ret;
 848 }
 849
 850 /**
 851  * t4_os_portmod_changed - handle port module changes
 852  * @adap: the adapter associated with the module change
 853  * @port_id: the port index whose module status has changed
 854  *
 855  * This is the OS-dependent handler for port module changes.  It is
 856  * invoked when a port module is removed or inserted for any OS-specific
 857  * processing.
 858  */
 859 void t4_os_portmod_changed(const struct adapter *adap, int port_id)
 860 {
 861         static const char * const mod_str[] = {
 862                 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
 863         };
 864
 865         const struct port_info *pi = &adap->port[port_id];
 866
 867         if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
 868                 dev_info(adap, "Port%d: port module unplugged\n", pi->port_id);
 869         else if (pi->mod_type < ARRAY_SIZE(mod_str))
 870                 dev_info(adap, "Port%d: %s port module inserted\n", pi->port_id,
 871                          mod_str[pi->mod_type]);
 872         else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
 873                 dev_info(adap, "Port%d: unsupported port module inserted\n",
 874                          pi->port_id);
 875         else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
 876                 dev_info(adap, "Port%d: unknown port module inserted\n",
 877                          pi->port_id);
 878         else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR)
 879                 dev_info(adap, "Port%d: transceiver module error\n",
 880                          pi->port_id);
 881         else
 882                 dev_info(adap, "Port%d: unknown module type %d inserted\n",
 883                          pi->port_id, pi->mod_type);
 884 }
 885
 886 /**
 887  * link_start - enable a port
 888  * @dev: the port to enable
 889  *
 890  * Performs the MAC and PHY actions needed to enable a port.
 891  */
 892 int link_start(struct port_info *pi)
 893 {
 894         struct adapter *adapter = pi->adapter;
 895         int ret;
 896         unsigned int mtu;
 897
 898         mtu = pi->eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 899               (ETHER_HDR_LEN + ETHER_CRC_LEN);
 900
 901         /*
 902          * We do not set address filters and promiscuity here, the stack does
 903          * that step explicitly.
 904          */
 905         ret = t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu, -1, -1,
 906                             -1, 1, true);
 907         if (ret == 0) {
 908                 ret = t4_change_mac(adapter, adapter->mbox, pi->viid,
 909                                     pi->xact_addr_filt,
 910                                     (u8 *)&pi->eth_dev->data->mac_addrs[0],
 911                                     true, true);
 912                 if (ret >= 0) {
 913                         pi->xact_addr_filt = ret;
 914                         ret = 0;
 915                 }
 916         }
 917         if (ret == 0)
 918                 ret = t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,
 919                                     &pi->link_cfg);
 920         if (ret == 0) {
 921                 /*
 922                  * Enabling a Virtual Interface can result in an interrupt
 923                  * during the processing of the VI Enable command and, in some
 924                  * paths, result in an attempt to issue another command in the
 925                  * interrupt context.  Thus, we disable interrupts during the
 926                  * course of the VI Enable command ...
 927                  */
 928                 ret = t4_enable_vi_params(adapter, adapter->mbox, pi->viid,
 929                                           true, true, false);
 930         }
 931         return ret;
 932 }
 933
 934 /**
 935  * cxgb4_write_rss - write the RSS table for a given port
 936  * @pi: the port
 937  * @queues: array of queue indices for RSS
 938  *
 939  * Sets up the portion of the HW RSS table for the port's VI to distribute
 940  * packets to the Rx queues in @queues.
 941  */
 942 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues)
 943 {
 944         u16 *rss;
 945         int i, err;
 946         struct adapter *adapter = pi->adapter;
 947         const struct sge_eth_rxq *rxq;
 948
 949         /*  Should never be called before setting up sge eth rx queues */
 950         BUG_ON(!(adapter->flags & FULL_INIT_DONE));
 951
 952         rxq = &adapter->sge.ethrxq[pi->first_qset];
 953         rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0);
 954         if (!rss)
 955                 return -ENOMEM;
 956
 957         /* map the queue indices to queue ids */
 958         for (i = 0; i < pi->rss_size; i++, queues++)
 959                 rss[i] = rxq[*queues].rspq.abs_id;
 960
 961         err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0,
 962                                   pi->rss_size, rss, pi->rss_size);
 963         /*
 964          * If Tunnel All Lookup isn't specified in the global RSS
 965          * Configuration, then we need to specify a default Ingress
 966          * Queue for any ingress packets which aren't hashed.  We'll
 967          * use our first ingress queue ...
 968          */
 969         if (!err)
 970                 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,
 971                                        F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN |
 972                                        F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN |
 973                                        F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
 974                                        F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN |
 975                                        F_FW_RSS_VI_CONFIG_CMD_UDPEN,
 976                                        rss[0]);
 977         rte_free(rss);
 978         return err;
 979 }
 980
 981 /**
 982  * setup_rss - configure RSS
 983  * @adapter: the adapter
 984  *
 985  * Sets up RSS to distribute packets to multiple receive queues.  We
 986  * configure the RSS CPU lookup table to distribute to the number of HW
 987  * receive queues, and the response queue lookup table to narrow that
 988  * down to the response queues actually configured for each port.
 989  * We always configure the RSS mapping for all ports since the mapping
 990  * table has plenty of entries.
 991  */
 992 int setup_rss(struct port_info *pi)
 993 {
 994         int j, err;
 995         struct adapter *adapter = pi->adapter;
 996
 997         dev_debug(adapter, "%s:  pi->rss_size = %u; pi->n_rx_qsets = %u\n",
 998                   __func__, pi->rss_size, pi->n_rx_qsets);
 999
1000         if (!(pi->flags & PORT_RSS_DONE)) {
1001                 if (adapter->flags & FULL_INIT_DONE) {
1002                         /* Fill default values with equal distribution */
1003                         for (j = 0; j < pi->rss_size; j++)
1004                                 pi->rss[j] = j % pi->n_rx_qsets;
1005
1006                         err = cxgb4_write_rss(pi, pi->rss);
1007                         if (err)
1008                                 return err;
1009                         pi->flags |= PORT_RSS_DONE;
1010                 }
1011         }
1012         return 0;
1013 }
1014
1015 /*
1016  * Enable NAPI scheduling and interrupt generation for all Rx queues.
1017  */
1018 static void enable_rx(struct adapter *adap, struct sge_rspq *q)
1019 {
1020         /* 0-increment GTS to start the timer and enable interrupts */
1021         t4_write_reg(adap, MYPF_REG(A_SGE_PF_GTS),
1022                      V_SEINTARM(q->intr_params) |
1023                      V_INGRESSQID(q->cntxt_id));
1024 }
1025
1026 void cxgbe_enable_rx_queues(struct port_info *pi)
1027 {
1028         struct adapter *adap = pi->adapter;
1029         struct sge *s = &adap->sge;
1030         unsigned int i;
1031
1032         for (i = 0; i < pi->n_rx_qsets; i++)
1033                 enable_rx(adap, &s->ethrxq[pi->first_qset + i].rspq);
1034 }
1035
1036 /**
1037  * fw_caps_to_speed_caps - translate Firmware Port Caps to Speed Caps.
1038  * @port_type: Firmware Port Type
1039  * @fw_caps: Firmware Port Capabilities
1040  * @speed_caps: Device Info Speed Capabilities
1041  *
1042  * Translate a Firmware Port Capabilities specification to Device Info
1043  * Speed Capabilities.
1044  */
1045 static void fw_caps_to_speed_caps(enum fw_port_type port_type,
1046                                   unsigned int fw_caps,
1047                                   u32 *speed_caps)
1048 {
1049 #define SET_SPEED(__speed_name) \
1050         do { \
1051                 *speed_caps |= ETH_LINK_ ## __speed_name; \
1052         } while (0)
1053
1054 #define FW_CAPS_TO_SPEED(__fw_name) \
1055         do { \
1056                 if (fw_caps & FW_PORT_CAP_ ## __fw_name) \
1057                         SET_SPEED(__fw_name); \
1058         } while (0)
1059
1060         switch (port_type) {
1061         case FW_PORT_TYPE_BT_SGMII:
1062         case FW_PORT_TYPE_BT_XFI:
1063         case FW_PORT_TYPE_BT_XAUI:
1064                 FW_CAPS_TO_SPEED(SPEED_100M);
1065                 FW_CAPS_TO_SPEED(SPEED_1G);
1066                 FW_CAPS_TO_SPEED(SPEED_10G);
1067                 break;
1068
1069         case FW_PORT_TYPE_KX4:
1070         case FW_PORT_TYPE_KX:
1071         case FW_PORT_TYPE_FIBER_XFI:
1072         case FW_PORT_TYPE_FIBER_XAUI:
1073         case FW_PORT_TYPE_SFP:
1074         case FW_PORT_TYPE_QSFP_10G:
1075         case FW_PORT_TYPE_QSA:
1076                 FW_CAPS_TO_SPEED(SPEED_1G);
1077                 FW_CAPS_TO_SPEED(SPEED_10G);
1078                 break;
1079
1080         case FW_PORT_TYPE_KR:
1081                 SET_SPEED(SPEED_10G);
1082                 break;
1083
1084         case FW_PORT_TYPE_BP_AP:
1085         case FW_PORT_TYPE_BP4_AP:
1086                 SET_SPEED(SPEED_1G);
1087                 SET_SPEED(SPEED_10G);
1088                 break;
1089
1090         case FW_PORT_TYPE_BP40_BA:
1091         case FW_PORT_TYPE_QSFP:
1092                 SET_SPEED(SPEED_40G);
1093                 break;
1094
1095         case FW_PORT_TYPE_CR_QSFP:
1096         case FW_PORT_TYPE_SFP28:
1097         case FW_PORT_TYPE_KR_SFP28:
1098                 FW_CAPS_TO_SPEED(SPEED_1G);
1099                 FW_CAPS_TO_SPEED(SPEED_10G);
1100                 FW_CAPS_TO_SPEED(SPEED_25G);
1101                 break;
1102
1103         case FW_PORT_TYPE_CR2_QSFP:
1104                 SET_SPEED(SPEED_50G);
1105                 break;
1106
1107         case FW_PORT_TYPE_KR4_100G:
1108         case FW_PORT_TYPE_CR4_QSFP:
1109                 FW_CAPS_TO_SPEED(SPEED_25G);
1110                 FW_CAPS_TO_SPEED(SPEED_40G);
1111                 FW_CAPS_TO_SPEED(SPEED_100G);
1112                 break;
1113
1114         default:
1115                 break;
1116         }
1117
1118 #undef FW_CAPS_TO_SPEED
1119 #undef SET_SPEED
1120 }
1121
1122 /**
1123  * cxgbe_get_speed_caps - Fetch supported speed capabilities
1124  * @pi: Underlying port's info
1125  * @speed_caps: Device Info speed capabilities
1126  *
1127  * Fetch supported speed capabilities of the underlying port.
1128  */
1129 void cxgbe_get_speed_caps(struct port_info *pi, u32 *speed_caps)
1130 {
1131         *speed_caps = 0;
1132
1133         fw_caps_to_speed_caps(pi->port_type, pi->link_cfg.supported,
1134                               speed_caps);
1135
1136         if (!(pi->link_cfg.supported & FW_PORT_CAP_ANEG))
1137                 *speed_caps |= ETH_LINK_SPEED_FIXED;
1138 }
1139
1140 /**
1141  * cxgb_up - enable the adapter
1142  * @adap: adapter being enabled
1143  *
1144  * Called when the first port is enabled, this function performs the
1145  * actions necessary to make an adapter operational, such as completing
1146  * the initialization of HW modules, and enabling interrupts.
1147  */
1148 int cxgbe_up(struct adapter *adap)
1149 {
1150         enable_rx(adap, &adap->sge.fw_evtq);
1151         t4_sge_tx_monitor_start(adap);
1152         t4_intr_enable(adap);
1153         adap->flags |= FULL_INIT_DONE;
1154
1155         /* TODO: deadman watchdog ?? */
1156         return 0;
1157 }
1158
1159 /*
1160  * Close the port
1161  */
1162 int cxgbe_down(struct port_info *pi)
1163 {
1164         struct adapter *adapter = pi->adapter;
1165         int err = 0;
1166
1167         err = t4_enable_vi(adapter, adapter->mbox, pi->viid, false, false);
1168         if (err) {
1169                 dev_err(adapter, "%s: disable_vi failed: %d\n", __func__, err);
1170                 return err;
1171         }
1172
1173         t4_reset_link_config(adapter, pi->port_id);
1174         return 0;
1175 }
1176
1177 /*
1178  * Release resources when all the ports have been stopped.
1179  */
1180 void cxgbe_close(struct adapter *adapter)
1181 {
1182         struct port_info *pi;
1183         int i;
1184
1185         if (adapter->flags & FULL_INIT_DONE) {
1186                 t4_intr_disable(adapter);
1187                 t4_sge_tx_monitor_stop(adapter);
1188                 t4_free_sge_resources(adapter);
1189                 for_each_port(adapter, i) {
1190                         pi = adap2pinfo(adapter, i);
1191                         if (pi->viid != 0)
1192                                 t4_free_vi(adapter, adapter->mbox,
1193                                            adapter->pf, 0, pi->viid);
1194                         rte_free(pi->eth_dev->data->mac_addrs);
1195                 }
1196                 adapter->flags &= ~FULL_INIT_DONE;
1197         }
1198
1199         if (adapter->flags & FW_OK)
1200                 t4_fw_bye(adapter, adapter->mbox);
1201 }
1202
1203 int cxgbe_probe(struct adapter *adapter)
1204 {
1205         struct port_info *pi;
1206         int chip;
1207         int func, i;
1208         int err = 0;
1209         u32 whoami;
1210
1211         whoami = t4_read_reg(adapter, A_PL_WHOAMI);
1212         chip = t4_get_chip_type(adapter,
1213                         CHELSIO_PCI_ID_VER(adapter->pdev->id.device_id));
1214         if (chip < 0)
1215                 return chip;
1216
1217         func = CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5 ?
1218                G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
1219
1220         adapter->mbox = func;
1221         adapter->pf = func;
1222
1223         t4_os_lock_init(&adapter->mbox_lock);
1224         TAILQ_INIT(&adapter->mbox_list);
1225
1226         err = t4_prep_adapter(adapter);
1227         if (err)
1228                 return err;
1229
1230         setup_memwin(adapter);
1231         err = adap_init0(adapter);
1232         if (err) {
1233                 dev_err(adapter, "%s: Adapter initialization failed, error %d\n",
1234                         __func__, err);
1235                 goto out_free;
1236         }
1237
1238         if (!is_t4(adapter->params.chip)) {
1239                 /*
1240                  * The userspace doorbell BAR is split evenly into doorbell
1241                  * regions, each associated with an egress queue.  If this
1242                  * per-queue region is large enough (at least UDBS_SEG_SIZE)
1243                  * then it can be used to submit a tx work request with an
1244                  * implied doorbell.  Enable write combining on the BAR if
1245                  * there is room for such work requests.
1246                  */
1247                 int s_qpp, qpp, num_seg;
1248
1249                 s_qpp = (S_QUEUESPERPAGEPF0 +
1250                         (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) *
1251                         adapter->pf);
1252                 qpp = 1 << ((t4_read_reg(adapter,
1253                                 A_SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp)
1254                                 & M_QUEUESPERPAGEPF0);
1255                 num_seg = CXGBE_PAGE_SIZE / UDBS_SEG_SIZE;
1256                 if (qpp > num_seg)
1257                         dev_warn(adapter, "Incorrect SGE EGRESS QUEUES_PER_PAGE configuration, continuing in debug mode\n");
1258
1259                 adapter->bar2 = (void *)adapter->pdev->mem_resource[2].addr;
1260                 if (!adapter->bar2) {
1261                         dev_err(adapter, "cannot map device bar2 region\n");
1262                         err = -ENOMEM;
1263                         goto out_free;
1264                 }
1265                 t4_write_reg(adapter, A_SGE_STAT_CFG, V_STATSOURCE_T5(7) |
1266                              V_STATMODE(0));
1267         }
1268
1269         for_each_port(adapter, i) {
1270                 char name[RTE_ETH_NAME_MAX_LEN];
1271                 struct rte_eth_dev_data *data = NULL;
1272                 const unsigned int numa_node = rte_socket_id();
1273
1274                 pi = &adapter->port[i];
1275                 pi->adapter = adapter;
1276                 pi->xact_addr_filt = -1;
1277                 pi->port_id = i;
1278
1279                 snprintf(name, sizeof(name), "cxgbe%d",
1280                          adapter->eth_dev->data->port_id + i);
1281
1282                 if (i == 0) {
1283                         /* First port is already allocated by DPDK */
1284                         pi->eth_dev = adapter->eth_dev;
1285                         goto allocate_mac;
1286                 }
1287
1288                 /*
1289                  * now do all data allocation - for eth_dev structure,
1290                  * and internal (private) data for the remaining ports
1291                  */
1292
1293                 /* reserve an ethdev entry */
1294                 pi->eth_dev = rte_eth_dev_allocate(name);
1295                 if (!pi->eth_dev)
1296                         goto out_free;
1297
1298                 data = rte_zmalloc_socket(name, sizeof(*data), 0, numa_node);
1299                 if (!data)
1300                         goto out_free;
1301
1302                 data->port_id = adapter->eth_dev->data->port_id + i;
1303
1304                 pi->eth_dev->data = data;
1305
1306 allocate_mac:
1307                 pi->eth_dev->device = &adapter->pdev->device;
1308                 pi->eth_dev->data->dev_private = pi;
1309                 pi->eth_dev->dev_ops = adapter->eth_dev->dev_ops;
1310                 pi->eth_dev->tx_pkt_burst = adapter->eth_dev->tx_pkt_burst;
1311                 pi->eth_dev->rx_pkt_burst = adapter->eth_dev->rx_pkt_burst;
1312
1313                 rte_eth_copy_pci_info(pi->eth_dev, adapter->pdev);
1314
1315                 pi->eth_dev->data->mac_addrs = rte_zmalloc(name,
1316                                                            ETHER_ADDR_LEN, 0);
1317                 if (!pi->eth_dev->data->mac_addrs) {
1318                         dev_err(adapter, "%s: Mem allocation failed for storing mac addr, aborting\n",
1319                                 __func__);
1320                         err = -1;
1321                         goto out_free;
1322                 }
1323         }
1324
1325         if (adapter->flags & FW_OK) {
1326                 err = t4_port_init(adapter, adapter->mbox, adapter->pf, 0);
1327                 if (err) {
1328                         dev_err(adapter, "%s: t4_port_init failed with err %d\n",
1329                                 __func__, err);
1330                         goto out_free;
1331                 }
1332         }
1333
1334         cfg_queues(adapter->eth_dev);
1335
1336         print_adapter_info(adapter);
1337         print_port_info(adapter);
1338
1339         err = init_rss(adapter);
1340         if (err)
1341                 goto out_free;
1342
1343         return 0;
1344
1345 out_free:
1346         for_each_port(adapter, i) {
1347                 pi = adap2pinfo(adapter, i);
1348                 if (pi->viid != 0)
1349                         t4_free_vi(adapter, adapter->mbox, adapter->pf,
1350                                    0, pi->viid);
1351                 /* Skip first port since it'll be de-allocated by DPDK */
1352                 if (i == 0)
1353                         continue;
1354                 if (pi->eth_dev->data)
1355                         rte_free(pi->eth_dev->data);
1356         }
1357
1358         if (adapter->flags & FW_OK)
1359                 t4_fw_bye(adapter, adapter->mbox);
1360         return -err;
1361 }