drivers/net/dpaa/dpaa_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  *   Copyright 2016 Freescale Semiconductor, Inc. All rights reserved.
   4  *   Copyright 2017 NXP
   5  *
   6  */
   7 /* System headers */
   8 #include <stdio.h>
   9 #include <inttypes.h>
  10 #include <unistd.h>
  11 #include <limits.h>
  12 #include <sched.h>
  13 #include <signal.h>
  14 #include <pthread.h>
  15 #include <sys/types.h>
  16 #include <sys/syscall.h>
  17
  18 #include <rte_string_fns.h>
  19 #include <rte_byteorder.h>
  20 #include <rte_common.h>
  21 #include <rte_interrupts.h>
  22 #include <rte_log.h>
  23 #include <rte_debug.h>
  24 #include <rte_pci.h>
  25 #include <rte_atomic.h>
  26 #include <rte_branch_prediction.h>
  27 #include <rte_memory.h>
  28 #include <rte_tailq.h>
  29 #include <rte_eal.h>
  30 #include <rte_alarm.h>
  31 #include <rte_ether.h>
  32 #include <rte_ethdev_driver.h>
  33 #include <rte_malloc.h>
  34 #include <rte_ring.h>
  35
  36 #include <rte_dpaa_bus.h>
  37 #include <rte_dpaa_logs.h>
  38 #include <dpaa_mempool.h>
  39
  40 #include <dpaa_ethdev.h>
  41 #include <dpaa_rxtx.h>
  42 #include <rte_pmd_dpaa.h>
  43
  44 #include <fsl_usd.h>
  45 #include <fsl_qman.h>
  46 #include <fsl_bman.h>
  47 #include <fsl_fman.h>
  48
  49 /* Supported Rx offloads */
  50 static uint64_t dev_rx_offloads_sup =
  51                 DEV_RX_OFFLOAD_JUMBO_FRAME |
  52                 DEV_RX_OFFLOAD_SCATTER;
  53
  54 /* Rx offloads which cannot be disabled */
  55 static uint64_t dev_rx_offloads_nodis =
  56                 DEV_RX_OFFLOAD_IPV4_CKSUM |
  57                 DEV_RX_OFFLOAD_UDP_CKSUM |
  58                 DEV_RX_OFFLOAD_TCP_CKSUM |
  59                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
  60
  61 /* Supported Tx offloads */
  62 static uint64_t dev_tx_offloads_sup;
  63
  64 /* Tx offloads which cannot be disabled */
  65 static uint64_t dev_tx_offloads_nodis =
  66                 DEV_TX_OFFLOAD_IPV4_CKSUM |
  67                 DEV_TX_OFFLOAD_UDP_CKSUM |
  68                 DEV_TX_OFFLOAD_TCP_CKSUM |
  69                 DEV_TX_OFFLOAD_SCTP_CKSUM |
  70                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
  71                 DEV_TX_OFFLOAD_MULTI_SEGS |
  72                 DEV_TX_OFFLOAD_MT_LOCKFREE |
  73                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
  74
  75 /* Keep track of whether QMAN and BMAN have been globally initialized */
  76 static int is_global_init;
  77 static int default_q;   /* use default queue - FMC is not executed*/
  78 /* At present we only allow up to 4 push mode queues as default - as each of
  79  * this queue need dedicated portal and we are short of portals.
  80  */
  81 #define DPAA_MAX_PUSH_MODE_QUEUE       8
  82 #define DPAA_DEFAULT_PUSH_MODE_QUEUE   4
  83
  84 static int dpaa_push_mode_max_queue = DPAA_DEFAULT_PUSH_MODE_QUEUE;
  85 static int dpaa_push_queue_idx; /* Queue index which are in push mode*/
  86
  87
  88 /* Per FQ Taildrop in frame count */
  89 static unsigned int td_threshold = CGR_RX_PERFQ_THRESH;
  90
  91 struct rte_dpaa_xstats_name_off {
  92         char name[RTE_ETH_XSTATS_NAME_SIZE];
  93         uint32_t offset;
  94 };
  95
  96 static const struct rte_dpaa_xstats_name_off dpaa_xstats_strings[] = {
  97         {"rx_align_err",
  98                 offsetof(struct dpaa_if_stats, raln)},
  99         {"rx_valid_pause",
 100                 offsetof(struct dpaa_if_stats, rxpf)},
 101         {"rx_fcs_err",
 102                 offsetof(struct dpaa_if_stats, rfcs)},
 103         {"rx_vlan_frame",
 104                 offsetof(struct dpaa_if_stats, rvlan)},
 105         {"rx_frame_err",
 106                 offsetof(struct dpaa_if_stats, rerr)},
 107         {"rx_drop_err",
 108                 offsetof(struct dpaa_if_stats, rdrp)},
 109         {"rx_undersized",
 110                 offsetof(struct dpaa_if_stats, rund)},
 111         {"rx_oversize_err",
 112                 offsetof(struct dpaa_if_stats, rovr)},
 113         {"rx_fragment_pkt",
 114                 offsetof(struct dpaa_if_stats, rfrg)},
 115         {"tx_valid_pause",
 116                 offsetof(struct dpaa_if_stats, txpf)},
 117         {"tx_fcs_err",
 118                 offsetof(struct dpaa_if_stats, terr)},
 119         {"tx_vlan_frame",
 120                 offsetof(struct dpaa_if_stats, tvlan)},
 121         {"rx_undersized",
 122                 offsetof(struct dpaa_if_stats, tund)},
 123 };
 124
 125 static struct rte_dpaa_driver rte_dpaa_pmd;
 126
 127 static int
 128 dpaa_eth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info);
 129
 130 static inline void
 131 dpaa_poll_queue_default_config(struct qm_mcc_initfq *opts)
 132 {
 133         memset(opts, 0, sizeof(struct qm_mcc_initfq));
 134         opts->we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
 135         opts->fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | QM_FQCTRL_CTXASTASHING |
 136                            QM_FQCTRL_PREFERINCACHE;
 137         opts->fqd.context_a.stashing.exclusive = 0;
 138         if (dpaa_svr_family != SVR_LS1046A_FAMILY)
 139                 opts->fqd.context_a.stashing.annotation_cl =
 140                                                 DPAA_IF_RX_ANNOTATION_STASH;
 141         opts->fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
 142         opts->fqd.context_a.stashing.context_cl = DPAA_IF_RX_CONTEXT_STASH;
 143 }
 144
 145 static int
 146 dpaa_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 147 {
 148         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 149         uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
 150                                 + VLAN_TAG_SIZE;
 151         uint32_t buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
 152
 153         PMD_INIT_FUNC_TRACE();
 154
 155         if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA_MAX_RX_PKT_LEN)
 156                 return -EINVAL;
 157         /*
 158          * Refuse mtu that requires the support of scattered packets
 159          * when this feature has not been enabled before.
 160          */
 161         if (dev->data->min_rx_buf_size &&
 162                 !dev->data->scattered_rx && frame_size > buffsz) {
 163                 DPAA_PMD_ERR("SG not enabled, will not fit in one buffer");
 164                 return -EINVAL;
 165         }
 166
 167         /* check <seg size> * <max_seg>  >= max_frame */
 168         if (dev->data->min_rx_buf_size && dev->data->scattered_rx &&
 169                 (frame_size > buffsz * DPAA_SGT_MAX_ENTRIES)) {
 170                 DPAA_PMD_ERR("Too big to fit for Max SG list %d",
 171                                 buffsz * DPAA_SGT_MAX_ENTRIES);
 172                 return -EINVAL;
 173         }
 174
 175         if (frame_size > RTE_ETHER_MAX_LEN)
 176                 dev->data->dev_conf.rxmode.offloads &=
 177                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 178         else
 179                 dev->data->dev_conf.rxmode.offloads &=
 180                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 181
 182         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 183
 184         fman_if_set_maxfrm(dpaa_intf->fif, frame_size);
 185
 186         return 0;
 187 }
 188
 189 static int
 190 dpaa_eth_dev_configure(struct rte_eth_dev *dev)
 191 {
 192         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 193         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 194         uint64_t rx_offloads = eth_conf->rxmode.offloads;
 195         uint64_t tx_offloads = eth_conf->txmode.offloads;
 196
 197         PMD_INIT_FUNC_TRACE();
 198
 199         /* Rx offloads validation */
 200         if (dev_rx_offloads_nodis & ~rx_offloads) {
 201                 DPAA_PMD_WARN(
 202                 "Rx offloads non configurable - requested 0x%" PRIx64
 203                 " ignored 0x%" PRIx64,
 204                         rx_offloads, dev_rx_offloads_nodis);
 205         }
 206
 207         /* Tx offloads validation */
 208         if (dev_tx_offloads_nodis & ~tx_offloads) {
 209                 DPAA_PMD_WARN(
 210                 "Tx offloads non configurable - requested 0x%" PRIx64
 211                 " ignored 0x%" PRIx64,
 212                         tx_offloads, dev_tx_offloads_nodis);
 213         }
 214
 215         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 216                 uint32_t max_len;
 217
 218                 DPAA_PMD_DEBUG("enabling jumbo");
 219
 220                 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <=
 221                     DPAA_MAX_RX_PKT_LEN)
 222                         max_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
 223                 else {
 224                         DPAA_PMD_INFO("enabling jumbo override conf max len=%d "
 225                                 "supported is %d",
 226                                 dev->data->dev_conf.rxmode.max_rx_pkt_len,
 227                                 DPAA_MAX_RX_PKT_LEN);
 228                         max_len = DPAA_MAX_RX_PKT_LEN;
 229                 }
 230
 231                 fman_if_set_maxfrm(dpaa_intf->fif, max_len);
 232                 dev->data->mtu = max_len
 233                         - RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE;
 234         }
 235
 236         if (rx_offloads & DEV_RX_OFFLOAD_SCATTER) {
 237                 DPAA_PMD_DEBUG("enabling scatter mode");
 238                 fman_if_set_sg(dpaa_intf->fif, 1);
 239                 dev->data->scattered_rx = 1;
 240         }
 241
 242         return 0;
 243 }
 244
 245 static const uint32_t *
 246 dpaa_supported_ptypes_get(struct rte_eth_dev *dev)
 247 {
 248         static const uint32_t ptypes[] = {
 249                 RTE_PTYPE_L2_ETHER,
 250                 RTE_PTYPE_L2_ETHER_VLAN,
 251                 RTE_PTYPE_L2_ETHER_ARP,
 252                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
 253                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
 254                 RTE_PTYPE_L4_ICMP,
 255                 RTE_PTYPE_L4_TCP,
 256                 RTE_PTYPE_L4_UDP,
 257                 RTE_PTYPE_L4_FRAG,
 258                 RTE_PTYPE_L4_TCP,
 259                 RTE_PTYPE_L4_UDP,
 260                 RTE_PTYPE_L4_SCTP
 261         };
 262
 263         PMD_INIT_FUNC_TRACE();
 264
 265         if (dev->rx_pkt_burst == dpaa_eth_queue_rx)
 266                 return ptypes;
 267         return NULL;
 268 }
 269
 270 static int dpaa_eth_dev_start(struct rte_eth_dev *dev)
 271 {
 272         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 273
 274         PMD_INIT_FUNC_TRACE();
 275
 276         /* Change tx callback to the real one */
 277         dev->tx_pkt_burst = dpaa_eth_queue_tx;
 278         fman_if_enable_rx(dpaa_intf->fif);
 279
 280         return 0;
 281 }
 282
 283 static void dpaa_eth_dev_stop(struct rte_eth_dev *dev)
 284 {
 285         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 286
 287         PMD_INIT_FUNC_TRACE();
 288
 289         fman_if_disable_rx(dpaa_intf->fif);
 290         dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
 291 }
 292
 293 static void dpaa_eth_dev_close(struct rte_eth_dev *dev)
 294 {
 295         PMD_INIT_FUNC_TRACE();
 296
 297         dpaa_eth_dev_stop(dev);
 298 }
 299
 300 static int
 301 dpaa_fw_version_get(struct rte_eth_dev *dev __rte_unused,
 302                      char *fw_version,
 303                      size_t fw_size)
 304 {
 305         int ret;
 306         FILE *svr_file = NULL;
 307         unsigned int svr_ver = 0;
 308
 309         PMD_INIT_FUNC_TRACE();
 310
 311         svr_file = fopen(DPAA_SOC_ID_FILE, "r");
 312         if (!svr_file) {
 313                 DPAA_PMD_ERR("Unable to open SoC device");
 314                 return -ENOTSUP; /* Not supported on this infra */
 315         }
 316         if (fscanf(svr_file, "svr:%x", &svr_ver) > 0)
 317                 dpaa_svr_family = svr_ver & SVR_MASK;
 318         else
 319                 DPAA_PMD_ERR("Unable to read SoC device");
 320
 321         fclose(svr_file);
 322
 323         ret = snprintf(fw_version, fw_size, "SVR:%x-fman-v%x",
 324                        svr_ver, fman_ip_rev);
 325         ret += 1; /* add the size of '\0' */
 326
 327         if (fw_size < (uint32_t)ret)
 328                 return ret;
 329         else
 330                 return 0;
 331 }
 332
 333 static int dpaa_eth_dev_info(struct rte_eth_dev *dev,
 334                              struct rte_eth_dev_info *dev_info)
 335 {
 336         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 337
 338         PMD_INIT_FUNC_TRACE();
 339
 340         dev_info->max_rx_queues = dpaa_intf->nb_rx_queues;
 341         dev_info->max_tx_queues = dpaa_intf->nb_tx_queues;
 342         dev_info->max_rx_pktlen = DPAA_MAX_RX_PKT_LEN;
 343         dev_info->max_mac_addrs = DPAA_MAX_MAC_FILTER;
 344         dev_info->max_hash_mac_addrs = 0;
 345         dev_info->max_vfs = 0;
 346         dev_info->max_vmdq_pools = ETH_16_POOLS;
 347         dev_info->flow_type_rss_offloads = DPAA_RSS_OFFLOAD_ALL;
 348
 349         if (dpaa_intf->fif->mac_type == fman_mac_1g) {
 350                 dev_info->speed_capa = ETH_LINK_SPEED_1G;
 351         } else if (dpaa_intf->fif->mac_type == fman_mac_10g) {
 352                 dev_info->speed_capa = (ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G);
 353         } else {
 354                 DPAA_PMD_ERR("invalid link_speed: %s, %d",
 355                              dpaa_intf->name, dpaa_intf->fif->mac_type);
 356                 return -EINVAL;
 357         }
 358
 359         dev_info->rx_offload_capa = dev_rx_offloads_sup |
 360                                         dev_rx_offloads_nodis;
 361         dev_info->tx_offload_capa = dev_tx_offloads_sup |
 362                                         dev_tx_offloads_nodis;
 363         dev_info->default_rxportconf.burst_size = DPAA_DEF_RX_BURST_SIZE;
 364         dev_info->default_txportconf.burst_size = DPAA_DEF_TX_BURST_SIZE;
 365
 366         return 0;
 367 }
 368
 369 static int dpaa_eth_link_update(struct rte_eth_dev *dev,
 370                                 int wait_to_complete __rte_unused)
 371 {
 372         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 373         struct rte_eth_link *link = &dev->data->dev_link;
 374
 375         PMD_INIT_FUNC_TRACE();
 376
 377         if (dpaa_intf->fif->mac_type == fman_mac_1g)
 378                 link->link_speed = ETH_SPEED_NUM_1G;
 379         else if (dpaa_intf->fif->mac_type == fman_mac_10g)
 380                 link->link_speed = ETH_SPEED_NUM_10G;
 381         else
 382                 DPAA_PMD_ERR("invalid link_speed: %s, %d",
 383                              dpaa_intf->name, dpaa_intf->fif->mac_type);
 384
 385         link->link_status = dpaa_intf->valid;
 386         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 387         link->link_autoneg = ETH_LINK_AUTONEG;
 388         return 0;
 389 }
 390
 391 static int dpaa_eth_stats_get(struct rte_eth_dev *dev,
 392                                struct rte_eth_stats *stats)
 393 {
 394         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 395
 396         PMD_INIT_FUNC_TRACE();
 397
 398         fman_if_stats_get(dpaa_intf->fif, stats);
 399         return 0;
 400 }
 401
 402 static int dpaa_eth_stats_reset(struct rte_eth_dev *dev)
 403 {
 404         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 405
 406         PMD_INIT_FUNC_TRACE();
 407
 408         fman_if_stats_reset(dpaa_intf->fif);
 409
 410         return 0;
 411 }
 412
 413 static int
 414 dpaa_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
 415                     unsigned int n)
 416 {
 417         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 418         unsigned int i = 0, num = RTE_DIM(dpaa_xstats_strings);
 419         uint64_t values[sizeof(struct dpaa_if_stats) / 8];
 420
 421         if (n < num)
 422                 return num;
 423
 424         if (xstats == NULL)
 425                 return 0;
 426
 427         fman_if_stats_get_all(dpaa_intf->fif, values,
 428                               sizeof(struct dpaa_if_stats) / 8);
 429
 430         for (i = 0; i < num; i++) {
 431                 xstats[i].id = i;
 432                 xstats[i].value = values[dpaa_xstats_strings[i].offset / 8];
 433         }
 434         return i;
 435 }
 436
 437 static int
 438 dpaa_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 439                       struct rte_eth_xstat_name *xstats_names,
 440                       unsigned int limit)
 441 {
 442         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 443
 444         if (limit < stat_cnt)
 445                 return stat_cnt;
 446
 447         if (xstats_names != NULL)
 448                 for (i = 0; i < stat_cnt; i++)
 449                         strlcpy(xstats_names[i].name,
 450                                 dpaa_xstats_strings[i].name,
 451                                 sizeof(xstats_names[i].name));
 452
 453         return stat_cnt;
 454 }
 455
 456 static int
 457 dpaa_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 458                       uint64_t *values, unsigned int n)
 459 {
 460         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 461         uint64_t values_copy[sizeof(struct dpaa_if_stats) / 8];
 462
 463         if (!ids) {
 464                 struct dpaa_if *dpaa_intf = dev->data->dev_private;
 465
 466                 if (n < stat_cnt)
 467                         return stat_cnt;
 468
 469                 if (!values)
 470                         return 0;
 471
 472                 fman_if_stats_get_all(dpaa_intf->fif, values_copy,
 473                                       sizeof(struct dpaa_if_stats) / 8);
 474
 475                 for (i = 0; i < stat_cnt; i++)
 476                         values[i] =
 477                                 values_copy[dpaa_xstats_strings[i].offset / 8];
 478
 479                 return stat_cnt;
 480         }
 481
 482         dpaa_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
 483
 484         for (i = 0; i < n; i++) {
 485                 if (ids[i] >= stat_cnt) {
 486                         DPAA_PMD_ERR("id value isn't valid");
 487                         return -1;
 488                 }
 489                 values[i] = values_copy[ids[i]];
 490         }
 491         return n;
 492 }
 493
 494 static int
 495 dpaa_xstats_get_names_by_id(
 496         struct rte_eth_dev *dev,
 497         struct rte_eth_xstat_name *xstats_names,
 498         const uint64_t *ids,
 499         unsigned int limit)
 500 {
 501         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 502         struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
 503
 504         if (!ids)
 505                 return dpaa_xstats_get_names(dev, xstats_names, limit);
 506
 507         dpaa_xstats_get_names(dev, xstats_names_copy, limit);
 508
 509         for (i = 0; i < limit; i++) {
 510                 if (ids[i] >= stat_cnt) {
 511                         DPAA_PMD_ERR("id value isn't valid");
 512                         return -1;
 513                 }
 514                 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
 515         }
 516         return limit;
 517 }
 518
 519 static int dpaa_eth_promiscuous_enable(struct rte_eth_dev *dev)
 520 {
 521         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 522
 523         PMD_INIT_FUNC_TRACE();
 524
 525         fman_if_promiscuous_enable(dpaa_intf->fif);
 526
 527         return 0;
 528 }
 529
 530 static int dpaa_eth_promiscuous_disable(struct rte_eth_dev *dev)
 531 {
 532         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 533
 534         PMD_INIT_FUNC_TRACE();
 535
 536         fman_if_promiscuous_disable(dpaa_intf->fif);
 537
 538         return 0;
 539 }
 540
 541 static int dpaa_eth_multicast_enable(struct rte_eth_dev *dev)
 542 {
 543         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 544
 545         PMD_INIT_FUNC_TRACE();
 546
 547         fman_if_set_mcast_filter_table(dpaa_intf->fif);
 548
 549         return 0;
 550 }
 551
 552 static int dpaa_eth_multicast_disable(struct rte_eth_dev *dev)
 553 {
 554         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 555
 556         PMD_INIT_FUNC_TRACE();
 557
 558         fman_if_reset_mcast_filter_table(dpaa_intf->fif);
 559
 560         return 0;
 561 }
 562
 563 static
 564 int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 565                             uint16_t nb_desc,
 566                             unsigned int socket_id __rte_unused,
 567                             const struct rte_eth_rxconf *rx_conf __rte_unused,
 568                             struct rte_mempool *mp)
 569 {
 570         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 571         struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_idx];
 572         struct qm_mcc_initfq opts = {0};
 573         u32 flags = 0;
 574         int ret;
 575         u32 buffsz = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
 576
 577         PMD_INIT_FUNC_TRACE();
 578
 579         if (queue_idx >= dev->data->nb_rx_queues) {
 580                 rte_errno = EOVERFLOW;
 581                 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
 582                       (void *)dev, queue_idx, dev->data->nb_rx_queues);
 583                 return -rte_errno;
 584         }
 585
 586         DPAA_PMD_INFO("Rx queue setup for queue index: %d fq_id (0x%x)",
 587                         queue_idx, rxq->fqid);
 588
 589         /* Max packet can fit in single buffer */
 590         if (dev->data->dev_conf.rxmode.max_rx_pkt_len <= buffsz) {
 591                 ;
 592         } else if (dev->data->dev_conf.rxmode.offloads &
 593                         DEV_RX_OFFLOAD_SCATTER) {
 594                 if (dev->data->dev_conf.rxmode.max_rx_pkt_len >
 595                         buffsz * DPAA_SGT_MAX_ENTRIES) {
 596                         DPAA_PMD_ERR("max RxPkt size %d too big to fit "
 597                                 "MaxSGlist %d",
 598                                 dev->data->dev_conf.rxmode.max_rx_pkt_len,
 599                                 buffsz * DPAA_SGT_MAX_ENTRIES);
 600                         rte_errno = EOVERFLOW;
 601                         return -rte_errno;
 602                 }
 603         } else {
 604                 DPAA_PMD_WARN("The requested maximum Rx packet size (%u) is"
 605                      " larger than a single mbuf (%u) and scattered"
 606                      " mode has not been requested",
 607                      dev->data->dev_conf.rxmode.max_rx_pkt_len,
 608                      buffsz - RTE_PKTMBUF_HEADROOM);
 609         }
 610
 611         if (!dpaa_intf->bp_info || dpaa_intf->bp_info->mp != mp) {
 612                 struct fman_if_ic_params icp;
 613                 uint32_t fd_offset;
 614                 uint32_t bp_size;
 615
 616                 if (!mp->pool_data) {
 617                         DPAA_PMD_ERR("Not an offloaded buffer pool!");
 618                         return -1;
 619                 }
 620                 dpaa_intf->bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp);
 621
 622                 memset(&icp, 0, sizeof(icp));
 623                 /* set ICEOF for to the default value , which is 0*/
 624                 icp.iciof = DEFAULT_ICIOF;
 625                 icp.iceof = DEFAULT_RX_ICEOF;
 626                 icp.icsz = DEFAULT_ICSZ;
 627                 fman_if_set_ic_params(dpaa_intf->fif, &icp);
 628
 629                 fd_offset = RTE_PKTMBUF_HEADROOM + DPAA_HW_BUF_RESERVE;
 630                 fman_if_set_fdoff(dpaa_intf->fif, fd_offset);
 631
 632                 /* Buffer pool size should be equal to Dataroom Size*/
 633                 bp_size = rte_pktmbuf_data_room_size(mp);
 634                 fman_if_set_bp(dpaa_intf->fif, mp->size,
 635                                dpaa_intf->bp_info->bpid, bp_size);
 636                 dpaa_intf->valid = 1;
 637                 DPAA_PMD_DEBUG("if:%s fd_offset = %d offset = %d",
 638                                 dpaa_intf->name, fd_offset,
 639                                 fman_if_get_fdoff(dpaa_intf->fif));
 640         }
 641         DPAA_PMD_DEBUG("if:%s sg_on = %d, max_frm =%d", dpaa_intf->name,
 642                 fman_if_get_sg_enable(dpaa_intf->fif),
 643                 dev->data->dev_conf.rxmode.max_rx_pkt_len);
 644         /* checking if push mode only, no error check for now */
 645         if (dpaa_push_mode_max_queue > dpaa_push_queue_idx) {
 646                 dpaa_push_queue_idx++;
 647                 opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
 648                 opts.fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK |
 649                                    QM_FQCTRL_CTXASTASHING |
 650                                    QM_FQCTRL_PREFERINCACHE;
 651                 opts.fqd.context_a.stashing.exclusive = 0;
 652                 /* In muticore scenario stashing becomes a bottleneck on LS1046.
 653                  * So do not enable stashing in this case
 654                  */
 655                 if (dpaa_svr_family != SVR_LS1046A_FAMILY)
 656                         opts.fqd.context_a.stashing.annotation_cl =
 657                                                 DPAA_IF_RX_ANNOTATION_STASH;
 658                 opts.fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
 659                 opts.fqd.context_a.stashing.context_cl =
 660                                                 DPAA_IF_RX_CONTEXT_STASH;
 661
 662                 /*Create a channel and associate given queue with the channel*/
 663                 qman_alloc_pool_range((u32 *)&rxq->ch_id, 1, 1, 0);
 664                 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
 665                 opts.fqd.dest.channel = rxq->ch_id;
 666                 opts.fqd.dest.wq = DPAA_IF_RX_PRIORITY;
 667                 flags = QMAN_INITFQ_FLAG_SCHED;
 668
 669                 /* Configure tail drop */
 670                 if (dpaa_intf->cgr_rx) {
 671                         opts.we_mask |= QM_INITFQ_WE_CGID;
 672                         opts.fqd.cgid = dpaa_intf->cgr_rx[queue_idx].cgrid;
 673                         opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
 674                 }
 675                 ret = qman_init_fq(rxq, flags, &opts);
 676                 if (ret) {
 677                         DPAA_PMD_ERR("Channel/Q association failed. fqid 0x%x "
 678                                 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
 679                         return ret;
 680                 }
 681                 if (dpaa_svr_family == SVR_LS1043A_FAMILY) {
 682                         rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb_no_prefetch;
 683                 } else {
 684                         rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb;
 685                         rxq->cb.dqrr_prepare = dpaa_rx_cb_prepare;
 686                 }
 687
 688                 rxq->is_static = true;
 689         }
 690         rxq->bp_array = rte_dpaa_bpid_info;
 691         dev->data->rx_queues[queue_idx] = rxq;
 692
 693         /* configure the CGR size as per the desc size */
 694         if (dpaa_intf->cgr_rx) {
 695                 struct qm_mcc_initcgr cgr_opts = {0};
 696
 697                 /* Enable tail drop with cgr on this queue */
 698                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, nb_desc, 0);
 699                 ret = qman_modify_cgr(dpaa_intf->cgr_rx, 0, &cgr_opts);
 700                 if (ret) {
 701                         DPAA_PMD_WARN(
 702                                 "rx taildrop modify fail on fqid %d (ret=%d)",
 703                                 rxq->fqid, ret);
 704                 }
 705         }
 706
 707         return 0;
 708 }
 709
 710 int
 711 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev,
 712                 int eth_rx_queue_id,
 713                 u16 ch_id,
 714                 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
 715 {
 716         int ret;
 717         u32 flags = 0;
 718         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 719         struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
 720         struct qm_mcc_initfq opts = {0};
 721
 722         if (dpaa_push_mode_max_queue)
 723                 DPAA_PMD_WARN("PUSH mode q and EVENTDEV are not compatible\n"
 724                               "PUSH mode already enabled for first %d queues.\n"
 725                               "To disable set DPAA_PUSH_QUEUES_NUMBER to 0\n",
 726                               dpaa_push_mode_max_queue);
 727
 728         dpaa_poll_queue_default_config(&opts);
 729
 730         switch (queue_conf->ev.sched_type) {
 731         case RTE_SCHED_TYPE_ATOMIC:
 732                 opts.fqd.fq_ctrl |= QM_FQCTRL_HOLDACTIVE;
 733                 /* Reset FQCTRL_AVOIDBLOCK bit as it is unnecessary
 734                  * configuration with HOLD_ACTIVE setting
 735                  */
 736                 opts.fqd.fq_ctrl &= (~QM_FQCTRL_AVOIDBLOCK);
 737                 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_atomic;
 738                 break;
 739         case RTE_SCHED_TYPE_ORDERED:
 740                 DPAA_PMD_ERR("Ordered queue schedule type is not supported\n");
 741                 return -1;
 742         default:
 743                 opts.fqd.fq_ctrl |= QM_FQCTRL_AVOIDBLOCK;
 744                 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_parallel;
 745                 break;
 746         }
 747
 748         opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
 749         opts.fqd.dest.channel = ch_id;
 750         opts.fqd.dest.wq = queue_conf->ev.priority;
 751
 752         if (dpaa_intf->cgr_rx) {
 753                 opts.we_mask |= QM_INITFQ_WE_CGID;
 754                 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
 755                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
 756         }
 757
 758         flags = QMAN_INITFQ_FLAG_SCHED;
 759
 760         ret = qman_init_fq(rxq, flags, &opts);
 761         if (ret) {
 762                 DPAA_PMD_ERR("Ev-Channel/Q association failed. fqid 0x%x "
 763                                 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
 764                 return ret;
 765         }
 766
 767         /* copy configuration which needs to be filled during dequeue */
 768         memcpy(&rxq->ev, &queue_conf->ev, sizeof(struct rte_event));
 769         dev->data->rx_queues[eth_rx_queue_id] = rxq;
 770
 771         return ret;
 772 }
 773
 774 int
 775 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev,
 776                 int eth_rx_queue_id)
 777 {
 778         struct qm_mcc_initfq opts;
 779         int ret;
 780         u32 flags = 0;
 781         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 782         struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
 783
 784         dpaa_poll_queue_default_config(&opts);
 785
 786         if (dpaa_intf->cgr_rx) {
 787                 opts.we_mask |= QM_INITFQ_WE_CGID;
 788                 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
 789                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
 790         }
 791
 792         ret = qman_init_fq(rxq, flags, &opts);
 793         if (ret) {
 794                 DPAA_PMD_ERR("init rx fqid %d failed with ret: %d",
 795                              rxq->fqid, ret);
 796         }
 797
 798         rxq->cb.dqrr_dpdk_cb = NULL;
 799         dev->data->rx_queues[eth_rx_queue_id] = NULL;
 800
 801         return 0;
 802 }
 803
 804 static
 805 void dpaa_eth_rx_queue_release(void *rxq __rte_unused)
 806 {
 807         PMD_INIT_FUNC_TRACE();
 808 }
 809
 810 static
 811 int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 812                             uint16_t nb_desc __rte_unused,
 813                 unsigned int socket_id __rte_unused,
 814                 const struct rte_eth_txconf *tx_conf __rte_unused)
 815 {
 816         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 817
 818         PMD_INIT_FUNC_TRACE();
 819
 820         if (queue_idx >= dev->data->nb_tx_queues) {
 821                 rte_errno = EOVERFLOW;
 822                 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
 823                       (void *)dev, queue_idx, dev->data->nb_tx_queues);
 824                 return -rte_errno;
 825         }
 826
 827         DPAA_PMD_INFO("Tx queue setup for queue index: %d fq_id (0x%x)",
 828                         queue_idx, dpaa_intf->tx_queues[queue_idx].fqid);
 829         dev->data->tx_queues[queue_idx] = &dpaa_intf->tx_queues[queue_idx];
 830         return 0;
 831 }
 832
 833 static void dpaa_eth_tx_queue_release(void *txq __rte_unused)
 834 {
 835         PMD_INIT_FUNC_TRACE();
 836 }
 837
 838 static uint32_t
 839 dpaa_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 840 {
 841         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 842         struct qman_fq *rxq = &dpaa_intf->rx_queues[rx_queue_id];
 843         u32 frm_cnt = 0;
 844
 845         PMD_INIT_FUNC_TRACE();
 846
 847         if (qman_query_fq_frm_cnt(rxq, &frm_cnt) == 0) {
 848                 RTE_LOG(DEBUG, PMD, "RX frame count for q(%d) is %u\n",
 849                         rx_queue_id, frm_cnt);
 850         }
 851         return frm_cnt;
 852 }
 853
 854 static int dpaa_link_down(struct rte_eth_dev *dev)
 855 {
 856         PMD_INIT_FUNC_TRACE();
 857
 858         dpaa_eth_dev_stop(dev);
 859         return 0;
 860 }
 861
 862 static int dpaa_link_up(struct rte_eth_dev *dev)
 863 {
 864         PMD_INIT_FUNC_TRACE();
 865
 866         dpaa_eth_dev_start(dev);
 867         return 0;
 868 }
 869
 870 static int
 871 dpaa_flow_ctrl_set(struct rte_eth_dev *dev,
 872                    struct rte_eth_fc_conf *fc_conf)
 873 {
 874         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 875         struct rte_eth_fc_conf *net_fc;
 876
 877         PMD_INIT_FUNC_TRACE();
 878
 879         if (!(dpaa_intf->fc_conf)) {
 880                 dpaa_intf->fc_conf = rte_zmalloc(NULL,
 881                         sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
 882                 if (!dpaa_intf->fc_conf) {
 883                         DPAA_PMD_ERR("unable to save flow control info");
 884                         return -ENOMEM;
 885                 }
 886         }
 887         net_fc = dpaa_intf->fc_conf;
 888
 889         if (fc_conf->high_water < fc_conf->low_water) {
 890                 DPAA_PMD_ERR("Incorrect Flow Control Configuration");
 891                 return -EINVAL;
 892         }
 893
 894         if (fc_conf->mode == RTE_FC_NONE) {
 895                 return 0;
 896         } else if (fc_conf->mode == RTE_FC_TX_PAUSE ||
 897                  fc_conf->mode == RTE_FC_FULL) {
 898                 fman_if_set_fc_threshold(dpaa_intf->fif, fc_conf->high_water,
 899                                          fc_conf->low_water,
 900                                 dpaa_intf->bp_info->bpid);
 901                 if (fc_conf->pause_time)
 902                         fman_if_set_fc_quanta(dpaa_intf->fif,
 903                                               fc_conf->pause_time);
 904         }
 905
 906         /* Save the information in dpaa device */
 907         net_fc->pause_time = fc_conf->pause_time;
 908         net_fc->high_water = fc_conf->high_water;
 909         net_fc->low_water = fc_conf->low_water;
 910         net_fc->send_xon = fc_conf->send_xon;
 911         net_fc->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
 912         net_fc->mode = fc_conf->mode;
 913         net_fc->autoneg = fc_conf->autoneg;
 914
 915         return 0;
 916 }
 917
 918 static int
 919 dpaa_flow_ctrl_get(struct rte_eth_dev *dev,
 920                    struct rte_eth_fc_conf *fc_conf)
 921 {
 922         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 923         struct rte_eth_fc_conf *net_fc = dpaa_intf->fc_conf;
 924         int ret;
 925
 926         PMD_INIT_FUNC_TRACE();
 927
 928         if (net_fc) {
 929                 fc_conf->pause_time = net_fc->pause_time;
 930                 fc_conf->high_water = net_fc->high_water;
 931                 fc_conf->low_water = net_fc->low_water;
 932                 fc_conf->send_xon = net_fc->send_xon;
 933                 fc_conf->mac_ctrl_frame_fwd = net_fc->mac_ctrl_frame_fwd;
 934                 fc_conf->mode = net_fc->mode;
 935                 fc_conf->autoneg = net_fc->autoneg;
 936                 return 0;
 937         }
 938         ret = fman_if_get_fc_threshold(dpaa_intf->fif);
 939         if (ret) {
 940                 fc_conf->mode = RTE_FC_TX_PAUSE;
 941                 fc_conf->pause_time = fman_if_get_fc_quanta(dpaa_intf->fif);
 942         } else {
 943                 fc_conf->mode = RTE_FC_NONE;
 944         }
 945
 946         return 0;
 947 }
 948
 949 static int
 950 dpaa_dev_add_mac_addr(struct rte_eth_dev *dev,
 951                              struct rte_ether_addr *addr,
 952                              uint32_t index,
 953                              __rte_unused uint32_t pool)
 954 {
 955         int ret;
 956         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 957
 958         PMD_INIT_FUNC_TRACE();
 959
 960         ret = fman_if_add_mac_addr(dpaa_intf->fif, addr->addr_bytes, index);
 961
 962         if (ret)
 963                 RTE_LOG(ERR, PMD, "error: Adding the MAC ADDR failed:"
 964                         " err = %d", ret);
 965         return 0;
 966 }
 967
 968 static void
 969 dpaa_dev_remove_mac_addr(struct rte_eth_dev *dev,
 970                           uint32_t index)
 971 {
 972         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 973
 974         PMD_INIT_FUNC_TRACE();
 975
 976         fman_if_clear_mac_addr(dpaa_intf->fif, index);
 977 }
 978
 979 static int
 980 dpaa_dev_set_mac_addr(struct rte_eth_dev *dev,
 981                        struct rte_ether_addr *addr)
 982 {
 983         int ret;
 984         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 985
 986         PMD_INIT_FUNC_TRACE();
 987
 988         ret = fman_if_add_mac_addr(dpaa_intf->fif, addr->addr_bytes, 0);
 989         if (ret)
 990                 RTE_LOG(ERR, PMD, "error: Setting the MAC ADDR failed %d", ret);
 991
 992         return ret;
 993 }
 994
 995 static struct eth_dev_ops dpaa_devops = {
 996         .dev_configure            = dpaa_eth_dev_configure,
 997         .dev_start                = dpaa_eth_dev_start,
 998         .dev_stop                 = dpaa_eth_dev_stop,
 999         .dev_close                = dpaa_eth_dev_close,
1000         .dev_infos_get            = dpaa_eth_dev_info,
1001         .dev_supported_ptypes_get = dpaa_supported_ptypes_get,
1002
1003         .rx_queue_setup           = dpaa_eth_rx_queue_setup,
1004         .tx_queue_setup           = dpaa_eth_tx_queue_setup,
1005         .rx_queue_release         = dpaa_eth_rx_queue_release,
1006         .tx_queue_release         = dpaa_eth_tx_queue_release,
1007         .rx_queue_count           = dpaa_dev_rx_queue_count,
1008
1009         .flow_ctrl_get            = dpaa_flow_ctrl_get,
1010         .flow_ctrl_set            = dpaa_flow_ctrl_set,
1011
1012         .link_update              = dpaa_eth_link_update,
1013         .stats_get                = dpaa_eth_stats_get,
1014         .xstats_get               = dpaa_dev_xstats_get,
1015         .xstats_get_by_id         = dpaa_xstats_get_by_id,
1016         .xstats_get_names_by_id   = dpaa_xstats_get_names_by_id,
1017         .xstats_get_names         = dpaa_xstats_get_names,
1018         .xstats_reset             = dpaa_eth_stats_reset,
1019         .stats_reset              = dpaa_eth_stats_reset,
1020         .promiscuous_enable       = dpaa_eth_promiscuous_enable,
1021         .promiscuous_disable      = dpaa_eth_promiscuous_disable,
1022         .allmulticast_enable      = dpaa_eth_multicast_enable,
1023         .allmulticast_disable     = dpaa_eth_multicast_disable,
1024         .mtu_set                  = dpaa_mtu_set,
1025         .dev_set_link_down        = dpaa_link_down,
1026         .dev_set_link_up          = dpaa_link_up,
1027         .mac_addr_add             = dpaa_dev_add_mac_addr,
1028         .mac_addr_remove          = dpaa_dev_remove_mac_addr,
1029         .mac_addr_set             = dpaa_dev_set_mac_addr,
1030
1031         .fw_version_get           = dpaa_fw_version_get,
1032 };
1033
1034 static bool
1035 is_device_supported(struct rte_eth_dev *dev, struct rte_dpaa_driver *drv)
1036 {
1037         if (strcmp(dev->device->driver->name,
1038                    drv->driver.name))
1039                 return false;
1040
1041         return true;
1042 }
1043
1044 static bool
1045 is_dpaa_supported(struct rte_eth_dev *dev)
1046 {
1047         return is_device_supported(dev, &rte_dpaa_pmd);
1048 }
1049
1050 int
1051 rte_pmd_dpaa_set_tx_loopback(uint8_t port, uint8_t on)
1052 {
1053         struct rte_eth_dev *dev;
1054         struct dpaa_if *dpaa_intf;
1055
1056         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
1057
1058         dev = &rte_eth_devices[port];
1059
1060         if (!is_dpaa_supported(dev))
1061                 return -ENOTSUP;
1062
1063         dpaa_intf = dev->data->dev_private;
1064
1065         if (on)
1066                 fman_if_loopback_enable(dpaa_intf->fif);
1067         else
1068                 fman_if_loopback_disable(dpaa_intf->fif);
1069
1070         return 0;
1071 }
1072
1073 static int dpaa_fc_set_default(struct dpaa_if *dpaa_intf)
1074 {
1075         struct rte_eth_fc_conf *fc_conf;
1076         int ret;
1077
1078         PMD_INIT_FUNC_TRACE();
1079
1080         if (!(dpaa_intf->fc_conf)) {
1081                 dpaa_intf->fc_conf = rte_zmalloc(NULL,
1082                         sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
1083                 if (!dpaa_intf->fc_conf) {
1084                         DPAA_PMD_ERR("unable to save flow control info");
1085                         return -ENOMEM;
1086                 }
1087         }
1088         fc_conf = dpaa_intf->fc_conf;
1089         ret = fman_if_get_fc_threshold(dpaa_intf->fif);
1090         if (ret) {
1091                 fc_conf->mode = RTE_FC_TX_PAUSE;
1092                 fc_conf->pause_time = fman_if_get_fc_quanta(dpaa_intf->fif);
1093         } else {
1094                 fc_conf->mode = RTE_FC_NONE;
1095         }
1096
1097         return 0;
1098 }
1099
1100 /* Initialise an Rx FQ */
1101 static int dpaa_rx_queue_init(struct qman_fq *fq, struct qman_cgr *cgr_rx,
1102                               uint32_t fqid)
1103 {
1104         struct qm_mcc_initfq opts = {0};
1105         int ret;
1106         u32 flags = QMAN_FQ_FLAG_NO_ENQUEUE;
1107         struct qm_mcc_initcgr cgr_opts = {
1108                 .we_mask = QM_CGR_WE_CS_THRES |
1109                                 QM_CGR_WE_CSTD_EN |
1110                                 QM_CGR_WE_MODE,
1111                 .cgr = {
1112                         .cstd_en = QM_CGR_EN,
1113                         .mode = QMAN_CGR_MODE_FRAME
1114                 }
1115         };
1116
1117         PMD_INIT_FUNC_TRACE();
1118
1119         if (fqid) {
1120                 ret = qman_reserve_fqid(fqid);
1121                 if (ret) {
1122                         DPAA_PMD_ERR("reserve rx fqid 0x%x failed with ret: %d",
1123                                      fqid, ret);
1124                         return -EINVAL;
1125                 }
1126         } else {
1127                 flags |= QMAN_FQ_FLAG_DYNAMIC_FQID;
1128         }
1129         DPAA_PMD_DEBUG("creating rx fq %p, fqid 0x%x", fq, fqid);
1130         ret = qman_create_fq(fqid, flags, fq);
1131         if (ret) {
1132                 DPAA_PMD_ERR("create rx fqid 0x%x failed with ret: %d",
1133                         fqid, ret);
1134                 return ret;
1135         }
1136         fq->is_static = false;
1137
1138         dpaa_poll_queue_default_config(&opts);
1139
1140         if (cgr_rx) {
1141                 /* Enable tail drop with cgr on this queue */
1142                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, td_threshold, 0);
1143                 cgr_rx->cb = NULL;
1144                 ret = qman_create_cgr(cgr_rx, QMAN_CGR_FLAG_USE_INIT,
1145                                       &cgr_opts);
1146                 if (ret) {
1147                         DPAA_PMD_WARN(
1148                                 "rx taildrop init fail on rx fqid 0x%x(ret=%d)",
1149                                 fq->fqid, ret);
1150                         goto without_cgr;
1151                 }
1152                 opts.we_mask |= QM_INITFQ_WE_CGID;
1153                 opts.fqd.cgid = cgr_rx->cgrid;
1154                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1155         }
1156 without_cgr:
1157         ret = qman_init_fq(fq, 0, &opts);
1158         if (ret)
1159                 DPAA_PMD_ERR("init rx fqid 0x%x failed with ret:%d", fqid, ret);
1160         return ret;
1161 }
1162
1163 /* Initialise a Tx FQ */
1164 static int dpaa_tx_queue_init(struct qman_fq *fq,
1165                               struct fman_if *fman_intf)
1166 {
1167         struct qm_mcc_initfq opts = {0};
1168         int ret;
1169
1170         PMD_INIT_FUNC_TRACE();
1171
1172         ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID |
1173                              QMAN_FQ_FLAG_TO_DCPORTAL, fq);
1174         if (ret) {
1175                 DPAA_PMD_ERR("create tx fq failed with ret: %d", ret);
1176                 return ret;
1177         }
1178         opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL |
1179                        QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA;
1180         opts.fqd.dest.channel = fman_intf->tx_channel_id;
1181         opts.fqd.dest.wq = DPAA_IF_TX_PRIORITY;
1182         opts.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE;
1183         opts.fqd.context_b = 0;
1184         /* no tx-confirmation */
1185         opts.fqd.context_a.hi = 0x80000000 | fman_dealloc_bufs_mask_hi;
1186         opts.fqd.context_a.lo = 0 | fman_dealloc_bufs_mask_lo;
1187         DPAA_PMD_DEBUG("init tx fq %p, fqid 0x%x", fq, fq->fqid);
1188         ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts);
1189         if (ret)
1190                 DPAA_PMD_ERR("init tx fqid 0x%x failed %d", fq->fqid, ret);
1191         return ret;
1192 }
1193
1194 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1195 /* Initialise a DEBUG FQ ([rt]x_error, rx_default). */
1196 static int dpaa_debug_queue_init(struct qman_fq *fq, uint32_t fqid)
1197 {
1198         struct qm_mcc_initfq opts = {0};
1199         int ret;
1200
1201         PMD_INIT_FUNC_TRACE();
1202
1203         ret = qman_reserve_fqid(fqid);
1204         if (ret) {
1205                 DPAA_PMD_ERR("Reserve debug fqid %d failed with ret: %d",
1206                         fqid, ret);
1207                 return -EINVAL;
1208         }
1209         /* "map" this Rx FQ to one of the interfaces Tx FQID */
1210         DPAA_PMD_DEBUG("Creating debug fq %p, fqid %d", fq, fqid);
1211         ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq);
1212         if (ret) {
1213                 DPAA_PMD_ERR("create debug fqid %d failed with ret: %d",
1214                         fqid, ret);
1215                 return ret;
1216         }
1217         opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL;
1218         opts.fqd.dest.wq = DPAA_IF_DEBUG_PRIORITY;
1219         ret = qman_init_fq(fq, 0, &opts);
1220         if (ret)
1221                 DPAA_PMD_ERR("init debug fqid %d failed with ret: %d",
1222                             fqid, ret);
1223         return ret;
1224 }
1225 #endif
1226
1227 /* Initialise a network interface */
1228 static int
1229 dpaa_dev_init(struct rte_eth_dev *eth_dev)
1230 {
1231         int num_rx_fqs, fqid;
1232         int loop, ret = 0;
1233         int dev_id;
1234         struct rte_dpaa_device *dpaa_device;
1235         struct dpaa_if *dpaa_intf;
1236         struct fm_eth_port_cfg *cfg;
1237         struct fman_if *fman_intf;
1238         struct fman_if_bpool *bp, *tmp_bp;
1239         uint32_t cgrid[DPAA_MAX_NUM_PCD_QUEUES];
1240
1241         PMD_INIT_FUNC_TRACE();
1242
1243         dpaa_intf = eth_dev->data->dev_private;
1244         /* For secondary processes, the primary has done all the work */
1245         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1246                 eth_dev->dev_ops = &dpaa_devops;
1247                 /* Plugging of UCODE burst API not supported in Secondary */
1248                 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
1249                 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx;
1250 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP
1251                 qman_set_fq_lookup_table(
1252                                 dpaa_intf->rx_queues->qman_fq_lookup_table);
1253 #endif
1254                 return 0;
1255         }
1256
1257         dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1258         dev_id = dpaa_device->id.dev_id;
1259         dpaa_intf = eth_dev->data->dev_private;
1260         cfg = &dpaa_netcfg->port_cfg[dev_id];
1261         fman_intf = cfg->fman_if;
1262
1263         dpaa_intf->name = dpaa_device->name;
1264
1265         /* save fman_if & cfg in the interface struture */
1266         dpaa_intf->fif = fman_intf;
1267         dpaa_intf->ifid = dev_id;
1268         dpaa_intf->cfg = cfg;
1269
1270         /* Initialize Rx FQ's */
1271         if (default_q) {
1272                 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES;
1273         } else {
1274                 if (getenv("DPAA_NUM_RX_QUEUES"))
1275                         num_rx_fqs = atoi(getenv("DPAA_NUM_RX_QUEUES"));
1276                 else
1277                         num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES;
1278         }
1279
1280
1281         /* Each device can not have more than DPAA_MAX_NUM_PCD_QUEUES RX
1282          * queues.
1283          */
1284         if (num_rx_fqs <= 0 || num_rx_fqs > DPAA_MAX_NUM_PCD_QUEUES) {
1285                 DPAA_PMD_ERR("Invalid number of RX queues\n");
1286                 return -EINVAL;
1287         }
1288
1289         dpaa_intf->rx_queues = rte_zmalloc(NULL,
1290                 sizeof(struct qman_fq) * num_rx_fqs, MAX_CACHELINE);
1291         if (!dpaa_intf->rx_queues) {
1292                 DPAA_PMD_ERR("Failed to alloc mem for RX queues\n");
1293                 return -ENOMEM;
1294         }
1295
1296         /* If congestion control is enabled globally*/
1297         if (td_threshold) {
1298                 dpaa_intf->cgr_rx = rte_zmalloc(NULL,
1299                         sizeof(struct qman_cgr) * num_rx_fqs, MAX_CACHELINE);
1300                 if (!dpaa_intf->cgr_rx) {
1301                         DPAA_PMD_ERR("Failed to alloc mem for cgr_rx\n");
1302                         ret = -ENOMEM;
1303                         goto free_rx;
1304                 }
1305
1306                 ret = qman_alloc_cgrid_range(&cgrid[0], num_rx_fqs, 1, 0);
1307                 if (ret != num_rx_fqs) {
1308                         DPAA_PMD_WARN("insufficient CGRIDs available");
1309                         ret = -EINVAL;
1310                         goto free_rx;
1311                 }
1312         } else {
1313                 dpaa_intf->cgr_rx = NULL;
1314         }
1315
1316         for (loop = 0; loop < num_rx_fqs; loop++) {
1317                 if (default_q)
1318                         fqid = cfg->rx_def;
1319                 else
1320                         fqid = DPAA_PCD_FQID_START + dpaa_intf->fif->mac_idx *
1321                                 DPAA_PCD_FQID_MULTIPLIER + loop;
1322
1323                 if (dpaa_intf->cgr_rx)
1324                         dpaa_intf->cgr_rx[loop].cgrid = cgrid[loop];
1325
1326                 ret = dpaa_rx_queue_init(&dpaa_intf->rx_queues[loop],
1327                         dpaa_intf->cgr_rx ? &dpaa_intf->cgr_rx[loop] : NULL,
1328                         fqid);
1329                 if (ret)
1330                         goto free_rx;
1331                 dpaa_intf->rx_queues[loop].dpaa_intf = dpaa_intf;
1332         }
1333         dpaa_intf->nb_rx_queues = num_rx_fqs;
1334
1335         /* Initialise Tx FQs.free_rx Have as many Tx FQ's as number of cores */
1336         dpaa_intf->tx_queues = rte_zmalloc(NULL, sizeof(struct qman_fq) *
1337                 MAX_DPAA_CORES, MAX_CACHELINE);
1338         if (!dpaa_intf->tx_queues) {
1339                 DPAA_PMD_ERR("Failed to alloc mem for TX queues\n");
1340                 ret = -ENOMEM;
1341                 goto free_rx;
1342         }
1343
1344         for (loop = 0; loop < MAX_DPAA_CORES; loop++) {
1345                 ret = dpaa_tx_queue_init(&dpaa_intf->tx_queues[loop],
1346                                          fman_intf);
1347                 if (ret)
1348                         goto free_tx;
1349                 dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf;
1350         }
1351         dpaa_intf->nb_tx_queues = MAX_DPAA_CORES;
1352
1353 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1354         dpaa_debug_queue_init(&dpaa_intf->debug_queues[
1355                 DPAA_DEBUG_FQ_RX_ERROR], fman_intf->fqid_rx_err);
1356         dpaa_intf->debug_queues[DPAA_DEBUG_FQ_RX_ERROR].dpaa_intf = dpaa_intf;
1357         dpaa_debug_queue_init(&dpaa_intf->debug_queues[
1358                 DPAA_DEBUG_FQ_TX_ERROR], fman_intf->fqid_tx_err);
1359         dpaa_intf->debug_queues[DPAA_DEBUG_FQ_TX_ERROR].dpaa_intf = dpaa_intf;
1360 #endif
1361
1362         DPAA_PMD_DEBUG("All frame queues created");
1363
1364         /* Get the initial configuration for flow control */
1365         dpaa_fc_set_default(dpaa_intf);
1366
1367         /* reset bpool list, initialize bpool dynamically */
1368         list_for_each_entry_safe(bp, tmp_bp, &cfg->fman_if->bpool_list, node) {
1369                 list_del(&bp->node);
1370                 rte_free(bp);
1371         }
1372
1373         /* Populate ethdev structure */
1374         eth_dev->dev_ops = &dpaa_devops;
1375         eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
1376         eth_dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
1377
1378         /* Allocate memory for storing MAC addresses */
1379         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr",
1380                 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER, 0);
1381         if (eth_dev->data->mac_addrs == NULL) {
1382                 DPAA_PMD_ERR("Failed to allocate %d bytes needed to "
1383                                                 "store MAC addresses",
1384                                 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER);
1385                 ret = -ENOMEM;
1386                 goto free_tx;
1387         }
1388
1389         /* copy the primary mac address */
1390         rte_ether_addr_copy(&fman_intf->mac_addr, &eth_dev->data->mac_addrs[0]);
1391
1392         RTE_LOG(INFO, PMD, "net: dpaa: %s: %02x:%02x:%02x:%02x:%02x:%02x\n",
1393                 dpaa_device->name,
1394                 fman_intf->mac_addr.addr_bytes[0],
1395                 fman_intf->mac_addr.addr_bytes[1],
1396                 fman_intf->mac_addr.addr_bytes[2],
1397                 fman_intf->mac_addr.addr_bytes[3],
1398                 fman_intf->mac_addr.addr_bytes[4],
1399                 fman_intf->mac_addr.addr_bytes[5]);
1400
1401         /* Disable RX mode */
1402         fman_if_discard_rx_errors(fman_intf);
1403         fman_if_disable_rx(fman_intf);
1404         /* Disable promiscuous mode */
1405         fman_if_promiscuous_disable(fman_intf);
1406         /* Disable multicast */
1407         fman_if_reset_mcast_filter_table(fman_intf);
1408         /* Reset interface statistics */
1409         fman_if_stats_reset(fman_intf);
1410         /* Disable SG by default */
1411         fman_if_set_sg(fman_intf, 0);
1412         fman_if_set_maxfrm(fman_intf, RTE_ETHER_MAX_LEN + VLAN_TAG_SIZE);
1413
1414         return 0;
1415
1416 free_tx:
1417         rte_free(dpaa_intf->tx_queues);
1418         dpaa_intf->tx_queues = NULL;
1419         dpaa_intf->nb_tx_queues = 0;
1420
1421 free_rx:
1422         rte_free(dpaa_intf->cgr_rx);
1423         rte_free(dpaa_intf->rx_queues);
1424         dpaa_intf->rx_queues = NULL;
1425         dpaa_intf->nb_rx_queues = 0;
1426         return ret;
1427 }
1428
1429 static int
1430 dpaa_dev_uninit(struct rte_eth_dev *dev)
1431 {
1432         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1433         int loop;
1434
1435         PMD_INIT_FUNC_TRACE();
1436
1437         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1438                 return -EPERM;
1439
1440         if (!dpaa_intf) {
1441                 DPAA_PMD_WARN("Already closed or not started");
1442                 return -1;
1443         }
1444
1445         dpaa_eth_dev_close(dev);
1446
1447         /* release configuration memory */
1448         if (dpaa_intf->fc_conf)
1449                 rte_free(dpaa_intf->fc_conf);
1450
1451         /* Release RX congestion Groups */
1452         if (dpaa_intf->cgr_rx) {
1453                 for (loop = 0; loop < dpaa_intf->nb_rx_queues; loop++)
1454                         qman_delete_cgr(&dpaa_intf->cgr_rx[loop]);
1455
1456                 qman_release_cgrid_range(dpaa_intf->cgr_rx[loop].cgrid,
1457                                          dpaa_intf->nb_rx_queues);
1458         }
1459
1460         rte_free(dpaa_intf->cgr_rx);
1461         dpaa_intf->cgr_rx = NULL;
1462
1463         rte_free(dpaa_intf->rx_queues);
1464         dpaa_intf->rx_queues = NULL;
1465
1466         rte_free(dpaa_intf->tx_queues);
1467         dpaa_intf->tx_queues = NULL;
1468
1469         dev->dev_ops = NULL;
1470         dev->rx_pkt_burst = NULL;
1471         dev->tx_pkt_burst = NULL;
1472
1473         return 0;
1474 }
1475
1476 static int
1477 rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv __rte_unused,
1478                struct rte_dpaa_device *dpaa_dev)
1479 {
1480         int diag;
1481         int ret;
1482         struct rte_eth_dev *eth_dev;
1483
1484         PMD_INIT_FUNC_TRACE();
1485
1486         if ((DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE) >
1487                 RTE_PKTMBUF_HEADROOM) {
1488                 DPAA_PMD_ERR(
1489                 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA Annotation req(%d)",
1490                 RTE_PKTMBUF_HEADROOM,
1491                 DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE);
1492
1493                 return -1;
1494         }
1495
1496         /* In case of secondary process, the device is already configured
1497          * and no further action is required, except portal initialization
1498          * and verifying secondary attachment to port name.
1499          */
1500         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1501                 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name);
1502                 if (!eth_dev)
1503                         return -ENOMEM;
1504                 eth_dev->device = &dpaa_dev->device;
1505                 eth_dev->dev_ops = &dpaa_devops;
1506                 rte_eth_dev_probing_finish(eth_dev);
1507                 return 0;
1508         }
1509
1510         if (!is_global_init && (rte_eal_process_type() == RTE_PROC_PRIMARY)) {
1511                 /* One time load of Qman/Bman drivers */
1512                 ret = qman_global_init();
1513                 if (ret) {
1514                         DPAA_PMD_ERR("QMAN initialization failed: %d",
1515                                      ret);
1516                         return ret;
1517                 }
1518                 ret = bman_global_init();
1519                 if (ret) {
1520                         DPAA_PMD_ERR("BMAN initialization failed: %d",
1521                                      ret);
1522                         return ret;
1523                 }
1524
1525                 if (access("/tmp/fmc.bin", F_OK) == -1) {
1526                         RTE_LOG(INFO, PMD,
1527                                 "* FMC not configured.Enabling default mode\n");
1528                         default_q = 1;
1529                 }
1530
1531                 /* disabling the default push mode for LS1043 */
1532                 if (dpaa_svr_family == SVR_LS1043A_FAMILY)
1533                         dpaa_push_mode_max_queue = 0;
1534
1535                 /* if push mode queues to be enabled. Currenly we are allowing
1536                  * only one queue per thread.
1537                  */
1538                 if (getenv("DPAA_PUSH_QUEUES_NUMBER")) {
1539                         dpaa_push_mode_max_queue =
1540                                         atoi(getenv("DPAA_PUSH_QUEUES_NUMBER"));
1541                         if (dpaa_push_mode_max_queue > DPAA_MAX_PUSH_MODE_QUEUE)
1542                             dpaa_push_mode_max_queue = DPAA_MAX_PUSH_MODE_QUEUE;
1543                 }
1544
1545                 is_global_init = 1;
1546         }
1547
1548         if (unlikely(!RTE_PER_LCORE(dpaa_io))) {
1549                 ret = rte_dpaa_portal_init((void *)1);
1550                 if (ret) {
1551                         DPAA_PMD_ERR("Unable to initialize portal");
1552                         return ret;
1553                 }
1554         }
1555
1556         /* In case of secondary process, the device is already configured
1557          * and no further action is required, except portal initialization
1558          * and verifying secondary attachment to port name.
1559          */
1560         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1561                 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name);
1562                 if (!eth_dev)
1563                         return -ENOMEM;
1564         } else {
1565                 eth_dev = rte_eth_dev_allocate(dpaa_dev->name);
1566                 if (eth_dev == NULL)
1567                         return -ENOMEM;
1568
1569                 eth_dev->data->dev_private = rte_zmalloc(
1570                                                 "ethdev private structure",
1571                                                 sizeof(struct dpaa_if),
1572                                                 RTE_CACHE_LINE_SIZE);
1573                 if (!eth_dev->data->dev_private) {
1574                         DPAA_PMD_ERR("Cannot allocate memzone for port data");
1575                         rte_eth_dev_release_port(eth_dev);
1576                         return -ENOMEM;
1577                 }
1578         }
1579         eth_dev->device = &dpaa_dev->device;
1580         dpaa_dev->eth_dev = eth_dev;
1581
1582         /* Invoke PMD device initialization function */
1583         diag = dpaa_dev_init(eth_dev);
1584         if (diag == 0) {
1585                 rte_eth_dev_probing_finish(eth_dev);
1586                 return 0;
1587         }
1588
1589         rte_eth_dev_release_port(eth_dev);
1590         return diag;
1591 }
1592
1593 static int
1594 rte_dpaa_remove(struct rte_dpaa_device *dpaa_dev)
1595 {
1596         struct rte_eth_dev *eth_dev;
1597
1598         PMD_INIT_FUNC_TRACE();
1599
1600         eth_dev = dpaa_dev->eth_dev;
1601         dpaa_dev_uninit(eth_dev);
1602
1603         rte_eth_dev_release_port(eth_dev);
1604
1605         return 0;
1606 }
1607
1608 static struct rte_dpaa_driver rte_dpaa_pmd = {
1609         .drv_type = FSL_DPAA_ETH,
1610         .probe = rte_dpaa_probe,
1611         .remove = rte_dpaa_remove,
1612 };
1613
1614 RTE_PMD_REGISTER_DPAA(net_dpaa, rte_dpaa_pmd);