drivers/net/dpaa/dpaa_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  *   Copyright 2016 Freescale Semiconductor, Inc. All rights reserved.
   4  *   Copyright 2017-2020 NXP
   5  *
   6  */
   7 /* System headers */
   8 #include <stdio.h>
   9 #include <inttypes.h>
  10 #include <unistd.h>
  11 #include <limits.h>
  12 #include <sched.h>
  13 #include <signal.h>
  14 #include <pthread.h>
  15 #include <sys/types.h>
  16 #include <sys/syscall.h>
  17
  18 #include <rte_string_fns.h>
  19 #include <rte_byteorder.h>
  20 #include <rte_common.h>
  21 #include <rte_interrupts.h>
  22 #include <rte_log.h>
  23 #include <rte_debug.h>
  24 #include <rte_pci.h>
  25 #include <rte_atomic.h>
  26 #include <rte_branch_prediction.h>
  27 #include <rte_memory.h>
  28 #include <rte_tailq.h>
  29 #include <rte_eal.h>
  30 #include <rte_alarm.h>
  31 #include <rte_ether.h>
  32 #include <rte_ethdev_driver.h>
  33 #include <rte_malloc.h>
  34 #include <rte_ring.h>
  35
  36 #include <rte_dpaa_bus.h>
  37 #include <rte_dpaa_logs.h>
  38 #include <dpaa_mempool.h>
  39
  40 #include <dpaa_ethdev.h>
  41 #include <dpaa_rxtx.h>
  42 #include <dpaa_flow.h>
  43 #include <rte_pmd_dpaa.h>
  44
  45 #include <fsl_usd.h>
  46 #include <fsl_qman.h>
  47 #include <fsl_bman.h>
  48 #include <fsl_fman.h>
  49 #include <process.h>
  50 #include <fmlib/fm_ext.h>
  51
  52 /* Supported Rx offloads */
  53 static uint64_t dev_rx_offloads_sup =
  54                 DEV_RX_OFFLOAD_JUMBO_FRAME |
  55                 DEV_RX_OFFLOAD_SCATTER;
  56
  57 /* Rx offloads which cannot be disabled */
  58 static uint64_t dev_rx_offloads_nodis =
  59                 DEV_RX_OFFLOAD_IPV4_CKSUM |
  60                 DEV_RX_OFFLOAD_UDP_CKSUM |
  61                 DEV_RX_OFFLOAD_TCP_CKSUM |
  62                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
  63                 DEV_RX_OFFLOAD_RSS_HASH;
  64
  65 /* Supported Tx offloads */
  66 static uint64_t dev_tx_offloads_sup =
  67                 DEV_TX_OFFLOAD_MT_LOCKFREE |
  68                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
  69
  70 /* Tx offloads which cannot be disabled */
  71 static uint64_t dev_tx_offloads_nodis =
  72                 DEV_TX_OFFLOAD_IPV4_CKSUM |
  73                 DEV_TX_OFFLOAD_UDP_CKSUM |
  74                 DEV_TX_OFFLOAD_TCP_CKSUM |
  75                 DEV_TX_OFFLOAD_SCTP_CKSUM |
  76                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
  77                 DEV_TX_OFFLOAD_MULTI_SEGS;
  78
  79 /* Keep track of whether QMAN and BMAN have been globally initialized */
  80 static int is_global_init;
  81 static int fmc_q = 1;   /* Indicates the use of static fmc for distribution */
  82 static int default_q;   /* use default queue - FMC is not executed*/
  83 /* At present we only allow up to 4 push mode queues as default - as each of
  84  * this queue need dedicated portal and we are short of portals.
  85  */
  86 #define DPAA_MAX_PUSH_MODE_QUEUE       8
  87 #define DPAA_DEFAULT_PUSH_MODE_QUEUE   4
  88
  89 static int dpaa_push_mode_max_queue = DPAA_DEFAULT_PUSH_MODE_QUEUE;
  90 static int dpaa_push_queue_idx; /* Queue index which are in push mode*/
  91
  92
  93 /* Per RX FQ Taildrop in frame count */
  94 static unsigned int td_threshold = CGR_RX_PERFQ_THRESH;
  95
  96 /* Per TX FQ Taildrop in frame count, disabled by default */
  97 static unsigned int td_tx_threshold;
  98
  99 struct rte_dpaa_xstats_name_off {
 100         char name[RTE_ETH_XSTATS_NAME_SIZE];
 101         uint32_t offset;
 102 };
 103
 104 static const struct rte_dpaa_xstats_name_off dpaa_xstats_strings[] = {
 105         {"rx_align_err",
 106                 offsetof(struct dpaa_if_stats, raln)},
 107         {"rx_valid_pause",
 108                 offsetof(struct dpaa_if_stats, rxpf)},
 109         {"rx_fcs_err",
 110                 offsetof(struct dpaa_if_stats, rfcs)},
 111         {"rx_vlan_frame",
 112                 offsetof(struct dpaa_if_stats, rvlan)},
 113         {"rx_frame_err",
 114                 offsetof(struct dpaa_if_stats, rerr)},
 115         {"rx_drop_err",
 116                 offsetof(struct dpaa_if_stats, rdrp)},
 117         {"rx_undersized",
 118                 offsetof(struct dpaa_if_stats, rund)},
 119         {"rx_oversize_err",
 120                 offsetof(struct dpaa_if_stats, rovr)},
 121         {"rx_fragment_pkt",
 122                 offsetof(struct dpaa_if_stats, rfrg)},
 123         {"tx_valid_pause",
 124                 offsetof(struct dpaa_if_stats, txpf)},
 125         {"tx_fcs_err",
 126                 offsetof(struct dpaa_if_stats, terr)},
 127         {"tx_vlan_frame",
 128                 offsetof(struct dpaa_if_stats, tvlan)},
 129         {"rx_undersized",
 130                 offsetof(struct dpaa_if_stats, tund)},
 131 };
 132
 133 static struct rte_dpaa_driver rte_dpaa_pmd;
 134
 135 static int
 136 dpaa_eth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info);
 137
 138 static int dpaa_eth_link_update(struct rte_eth_dev *dev,
 139                                 int wait_to_complete __rte_unused);
 140
 141 static void dpaa_interrupt_handler(void *param);
 142
 143 static inline void
 144 dpaa_poll_queue_default_config(struct qm_mcc_initfq *opts)
 145 {
 146         memset(opts, 0, sizeof(struct qm_mcc_initfq));
 147         opts->we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
 148         opts->fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | QM_FQCTRL_CTXASTASHING |
 149                            QM_FQCTRL_PREFERINCACHE;
 150         opts->fqd.context_a.stashing.exclusive = 0;
 151         if (dpaa_svr_family != SVR_LS1046A_FAMILY)
 152                 opts->fqd.context_a.stashing.annotation_cl =
 153                                                 DPAA_IF_RX_ANNOTATION_STASH;
 154         opts->fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
 155         opts->fqd.context_a.stashing.context_cl = DPAA_IF_RX_CONTEXT_STASH;
 156 }
 157
 158 static int
 159 dpaa_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 160 {
 161         uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
 162                                 + VLAN_TAG_SIZE;
 163         uint32_t buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
 164
 165         PMD_INIT_FUNC_TRACE();
 166
 167         if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA_MAX_RX_PKT_LEN)
 168                 return -EINVAL;
 169         /*
 170          * Refuse mtu that requires the support of scattered packets
 171          * when this feature has not been enabled before.
 172          */
 173         if (dev->data->min_rx_buf_size &&
 174                 !dev->data->scattered_rx && frame_size > buffsz) {
 175                 DPAA_PMD_ERR("SG not enabled, will not fit in one buffer");
 176                 return -EINVAL;
 177         }
 178
 179         /* check <seg size> * <max_seg>  >= max_frame */
 180         if (dev->data->min_rx_buf_size && dev->data->scattered_rx &&
 181                 (frame_size > buffsz * DPAA_SGT_MAX_ENTRIES)) {
 182                 DPAA_PMD_ERR("Too big to fit for Max SG list %d",
 183                                 buffsz * DPAA_SGT_MAX_ENTRIES);
 184                 return -EINVAL;
 185         }
 186
 187         if (frame_size > RTE_ETHER_MAX_LEN)
 188                 dev->data->dev_conf.rxmode.offloads |=
 189                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 190         else
 191                 dev->data->dev_conf.rxmode.offloads &=
 192                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 193
 194         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 195
 196         fman_if_set_maxfrm(dev->process_private, frame_size);
 197
 198         return 0;
 199 }
 200
 201 static int
 202 dpaa_eth_dev_configure(struct rte_eth_dev *dev)
 203 {
 204         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 205         uint64_t rx_offloads = eth_conf->rxmode.offloads;
 206         uint64_t tx_offloads = eth_conf->txmode.offloads;
 207         struct rte_device *rdev = dev->device;
 208         struct rte_eth_link *link = &dev->data->dev_link;
 209         struct rte_dpaa_device *dpaa_dev;
 210         struct fman_if *fif = dev->process_private;
 211         struct __fman_if *__fif;
 212         struct rte_intr_handle *intr_handle;
 213         int speed, duplex;
 214         int ret;
 215
 216         PMD_INIT_FUNC_TRACE();
 217
 218         dpaa_dev = container_of(rdev, struct rte_dpaa_device, device);
 219         intr_handle = &dpaa_dev->intr_handle;
 220         __fif = container_of(fif, struct __fman_if, __if);
 221
 222         /* Rx offloads which are enabled by default */
 223         if (dev_rx_offloads_nodis & ~rx_offloads) {
 224                 DPAA_PMD_INFO(
 225                 "Some of rx offloads enabled by default - requested 0x%" PRIx64
 226                 " fixed are 0x%" PRIx64,
 227                 rx_offloads, dev_rx_offloads_nodis);
 228         }
 229
 230         /* Tx offloads which are enabled by default */
 231         if (dev_tx_offloads_nodis & ~tx_offloads) {
 232                 DPAA_PMD_INFO(
 233                 "Some of tx offloads enabled by default - requested 0x%" PRIx64
 234                 " fixed are 0x%" PRIx64,
 235                 tx_offloads, dev_tx_offloads_nodis);
 236         }
 237
 238         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 239                 uint32_t max_len;
 240
 241                 DPAA_PMD_DEBUG("enabling jumbo");
 242
 243                 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <=
 244                     DPAA_MAX_RX_PKT_LEN)
 245                         max_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
 246                 else {
 247                         DPAA_PMD_INFO("enabling jumbo override conf max len=%d "
 248                                 "supported is %d",
 249                                 dev->data->dev_conf.rxmode.max_rx_pkt_len,
 250                                 DPAA_MAX_RX_PKT_LEN);
 251                         max_len = DPAA_MAX_RX_PKT_LEN;
 252                 }
 253
 254                 fman_if_set_maxfrm(dev->process_private, max_len);
 255                 dev->data->mtu = max_len
 256                         - RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE;
 257         }
 258
 259         if (rx_offloads & DEV_RX_OFFLOAD_SCATTER) {
 260                 DPAA_PMD_DEBUG("enabling scatter mode");
 261                 fman_if_set_sg(dev->process_private, 1);
 262                 dev->data->scattered_rx = 1;
 263         }
 264
 265         if (!(default_q || fmc_q)) {
 266                 if (dpaa_fm_config(dev,
 267                         eth_conf->rx_adv_conf.rss_conf.rss_hf)) {
 268                         dpaa_write_fm_config_to_file();
 269                         DPAA_PMD_ERR("FM port configuration: Failed\n");
 270                         return -1;
 271                 }
 272                 dpaa_write_fm_config_to_file();
 273         }
 274
 275         /* if the interrupts were configured on this devices*/
 276         if (intr_handle && intr_handle->fd) {
 277                 if (dev->data->dev_conf.intr_conf.lsc != 0)
 278                         rte_intr_callback_register(intr_handle,
 279                                            dpaa_interrupt_handler,
 280                                            (void *)dev);
 281
 282                 ret = dpaa_intr_enable(__fif->node_name, intr_handle->fd);
 283                 if (ret) {
 284                         if (dev->data->dev_conf.intr_conf.lsc != 0) {
 285                                 rte_intr_callback_unregister(intr_handle,
 286                                         dpaa_interrupt_handler,
 287                                         (void *)dev);
 288                                 if (ret == EINVAL)
 289                                         printf("Failed to enable interrupt: Not Supported\n");
 290                                 else
 291                                         printf("Failed to enable interrupt\n");
 292                         }
 293                         dev->data->dev_conf.intr_conf.lsc = 0;
 294                         dev->data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC;
 295                 }
 296         }
 297
 298         /* Wait for link status to get updated */
 299         if (!link->link_status)
 300                 sleep(1);
 301
 302         /* Configure link only if link is UP*/
 303         if (link->link_status) {
 304                 if (eth_conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
 305                         /* Start autoneg only if link is not in autoneg mode */
 306                         if (!link->link_autoneg)
 307                                 dpaa_restart_link_autoneg(__fif->node_name);
 308                 } else if (eth_conf->link_speeds & ETH_LINK_SPEED_FIXED) {
 309                         switch (eth_conf->link_speeds & ~ETH_LINK_SPEED_FIXED) {
 310                         case ETH_LINK_SPEED_10M_HD:
 311                                 speed = ETH_SPEED_NUM_10M;
 312                                 duplex = ETH_LINK_HALF_DUPLEX;
 313                                 break;
 314                         case ETH_LINK_SPEED_10M:
 315                                 speed = ETH_SPEED_NUM_10M;
 316                                 duplex = ETH_LINK_FULL_DUPLEX;
 317                                 break;
 318                         case ETH_LINK_SPEED_100M_HD:
 319                                 speed = ETH_SPEED_NUM_100M;
 320                                 duplex = ETH_LINK_HALF_DUPLEX;
 321                                 break;
 322                         case ETH_LINK_SPEED_100M:
 323                                 speed = ETH_SPEED_NUM_100M;
 324                                 duplex = ETH_LINK_FULL_DUPLEX;
 325                                 break;
 326                         case ETH_LINK_SPEED_1G:
 327                                 speed = ETH_SPEED_NUM_1G;
 328                                 duplex = ETH_LINK_FULL_DUPLEX;
 329                                 break;
 330                         case ETH_LINK_SPEED_2_5G:
 331                                 speed = ETH_SPEED_NUM_2_5G;
 332                                 duplex = ETH_LINK_FULL_DUPLEX;
 333                                 break;
 334                         case ETH_LINK_SPEED_10G:
 335                                 speed = ETH_SPEED_NUM_10G;
 336                                 duplex = ETH_LINK_FULL_DUPLEX;
 337                                 break;
 338                         default:
 339                                 speed = ETH_SPEED_NUM_NONE;
 340                                 duplex = ETH_LINK_FULL_DUPLEX;
 341                                 break;
 342                         }
 343                         /* Set link speed */
 344                         dpaa_update_link_speed(__fif->node_name, speed, duplex);
 345                 } else {
 346                         /* Manual autoneg - custom advertisement speed. */
 347                         printf("Custom Advertisement speeds not supported\n");
 348                 }
 349         }
 350
 351         return 0;
 352 }
 353
 354 static const uint32_t *
 355 dpaa_supported_ptypes_get(struct rte_eth_dev *dev)
 356 {
 357         static const uint32_t ptypes[] = {
 358                 RTE_PTYPE_L2_ETHER,
 359                 RTE_PTYPE_L2_ETHER_VLAN,
 360                 RTE_PTYPE_L2_ETHER_ARP,
 361                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
 362                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
 363                 RTE_PTYPE_L4_ICMP,
 364                 RTE_PTYPE_L4_TCP,
 365                 RTE_PTYPE_L4_UDP,
 366                 RTE_PTYPE_L4_FRAG,
 367                 RTE_PTYPE_L4_TCP,
 368                 RTE_PTYPE_L4_UDP,
 369                 RTE_PTYPE_L4_SCTP
 370         };
 371
 372         PMD_INIT_FUNC_TRACE();
 373
 374         if (dev->rx_pkt_burst == dpaa_eth_queue_rx)
 375                 return ptypes;
 376         return NULL;
 377 }
 378
 379 static void dpaa_interrupt_handler(void *param)
 380 {
 381         struct rte_eth_dev *dev = param;
 382         struct rte_device *rdev = dev->device;
 383         struct rte_dpaa_device *dpaa_dev;
 384         struct rte_intr_handle *intr_handle;
 385         uint64_t buf;
 386         int bytes_read;
 387
 388         dpaa_dev = container_of(rdev, struct rte_dpaa_device, device);
 389         intr_handle = &dpaa_dev->intr_handle;
 390
 391         bytes_read = read(intr_handle->fd, &buf, sizeof(uint64_t));
 392         if (bytes_read < 0)
 393                 DPAA_PMD_ERR("Error reading eventfd\n");
 394         dpaa_eth_link_update(dev, 0);
 395         rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
 396 }
 397
 398 static int dpaa_eth_dev_start(struct rte_eth_dev *dev)
 399 {
 400         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 401
 402         PMD_INIT_FUNC_TRACE();
 403
 404         if (!(default_q || fmc_q))
 405                 dpaa_write_fm_config_to_file();
 406
 407         /* Change tx callback to the real one */
 408         if (dpaa_intf->cgr_tx)
 409                 dev->tx_pkt_burst = dpaa_eth_queue_tx_slow;
 410         else
 411                 dev->tx_pkt_burst = dpaa_eth_queue_tx;
 412
 413         fman_if_enable_rx(dev->process_private);
 414
 415         return 0;
 416 }
 417
 418 static void dpaa_eth_dev_stop(struct rte_eth_dev *dev)
 419 {
 420         struct fman_if *fif = dev->process_private;
 421
 422         PMD_INIT_FUNC_TRACE();
 423         dev->data->dev_started = 0;
 424
 425         if (!fif->is_shared_mac)
 426                 fman_if_disable_rx(fif);
 427         dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
 428 }
 429
 430 static int dpaa_eth_dev_close(struct rte_eth_dev *dev)
 431 {
 432         struct fman_if *fif = dev->process_private;
 433         struct __fman_if *__fif;
 434         struct rte_device *rdev = dev->device;
 435         struct rte_dpaa_device *dpaa_dev;
 436         struct rte_intr_handle *intr_handle;
 437         struct rte_eth_link *link = &dev->data->dev_link;
 438         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 439         int loop;
 440
 441         PMD_INIT_FUNC_TRACE();
 442
 443         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 444                 return 0;
 445
 446         if (!dpaa_intf) {
 447                 DPAA_PMD_WARN("Already closed or not started");
 448                 return -1;
 449         }
 450
 451         /* DPAA FM deconfig */
 452         if (!(default_q || fmc_q)) {
 453                 if (dpaa_fm_deconfig(dpaa_intf, dev->process_private))
 454                         DPAA_PMD_WARN("DPAA FM deconfig failed\n");
 455         }
 456
 457         dpaa_dev = container_of(rdev, struct rte_dpaa_device, device);
 458         intr_handle = &dpaa_dev->intr_handle;
 459         __fif = container_of(fif, struct __fman_if, __if);
 460
 461         dpaa_eth_dev_stop(dev);
 462
 463         /* Reset link to autoneg */
 464         if (link->link_status && !link->link_autoneg)
 465                 dpaa_restart_link_autoneg(__fif->node_name);
 466
 467         if (intr_handle && intr_handle->fd &&
 468             dev->data->dev_conf.intr_conf.lsc != 0) {
 469                 dpaa_intr_disable(__fif->node_name);
 470                 rte_intr_callback_unregister(intr_handle,
 471                                              dpaa_interrupt_handler,
 472                                              (void *)dev);
 473         }
 474
 475         /* release configuration memory */
 476         if (dpaa_intf->fc_conf)
 477                 rte_free(dpaa_intf->fc_conf);
 478
 479         /* Release RX congestion Groups */
 480         if (dpaa_intf->cgr_rx) {
 481                 for (loop = 0; loop < dpaa_intf->nb_rx_queues; loop++)
 482                         qman_delete_cgr(&dpaa_intf->cgr_rx[loop]);
 483
 484                 qman_release_cgrid_range(dpaa_intf->cgr_rx[loop].cgrid,
 485                                          dpaa_intf->nb_rx_queues);
 486         }
 487
 488         rte_free(dpaa_intf->cgr_rx);
 489         dpaa_intf->cgr_rx = NULL;
 490         /* Release TX congestion Groups */
 491         if (dpaa_intf->cgr_tx) {
 492                 for (loop = 0; loop < MAX_DPAA_CORES; loop++)
 493                         qman_delete_cgr(&dpaa_intf->cgr_tx[loop]);
 494
 495                 qman_release_cgrid_range(dpaa_intf->cgr_tx[loop].cgrid,
 496                                          MAX_DPAA_CORES);
 497                 rte_free(dpaa_intf->cgr_tx);
 498                 dpaa_intf->cgr_tx = NULL;
 499         }
 500
 501         rte_free(dpaa_intf->rx_queues);
 502         dpaa_intf->rx_queues = NULL;
 503
 504         rte_free(dpaa_intf->tx_queues);
 505         dpaa_intf->tx_queues = NULL;
 506
 507         return 0;
 508 }
 509
 510 static int
 511 dpaa_fw_version_get(struct rte_eth_dev *dev __rte_unused,
 512                      char *fw_version,
 513                      size_t fw_size)
 514 {
 515         int ret;
 516         FILE *svr_file = NULL;
 517         unsigned int svr_ver = 0;
 518
 519         PMD_INIT_FUNC_TRACE();
 520
 521         svr_file = fopen(DPAA_SOC_ID_FILE, "r");
 522         if (!svr_file) {
 523                 DPAA_PMD_ERR("Unable to open SoC device");
 524                 return -ENOTSUP; /* Not supported on this infra */
 525         }
 526         if (fscanf(svr_file, "svr:%x", &svr_ver) > 0)
 527                 dpaa_svr_family = svr_ver & SVR_MASK;
 528         else
 529                 DPAA_PMD_ERR("Unable to read SoC device");
 530
 531         fclose(svr_file);
 532
 533         ret = snprintf(fw_version, fw_size, "SVR:%x-fman-v%x",
 534                        svr_ver, fman_ip_rev);
 535         ret += 1; /* add the size of '\0' */
 536
 537         if (fw_size < (uint32_t)ret)
 538                 return ret;
 539         else
 540                 return 0;
 541 }
 542
 543 static int dpaa_eth_dev_info(struct rte_eth_dev *dev,
 544                              struct rte_eth_dev_info *dev_info)
 545 {
 546         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 547         struct fman_if *fif = dev->process_private;
 548
 549         DPAA_PMD_DEBUG(": %s", dpaa_intf->name);
 550
 551         dev_info->max_rx_queues = dpaa_intf->nb_rx_queues;
 552         dev_info->max_tx_queues = dpaa_intf->nb_tx_queues;
 553         dev_info->max_rx_pktlen = DPAA_MAX_RX_PKT_LEN;
 554         dev_info->max_mac_addrs = DPAA_MAX_MAC_FILTER;
 555         dev_info->max_hash_mac_addrs = 0;
 556         dev_info->max_vfs = 0;
 557         dev_info->max_vmdq_pools = ETH_16_POOLS;
 558         dev_info->flow_type_rss_offloads = DPAA_RSS_OFFLOAD_ALL;
 559
 560         if (fif->mac_type == fman_mac_1g) {
 561                 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD
 562                                         | ETH_LINK_SPEED_10M
 563                                         | ETH_LINK_SPEED_100M_HD
 564                                         | ETH_LINK_SPEED_100M
 565                                         | ETH_LINK_SPEED_1G;
 566         } else if (fif->mac_type == fman_mac_2_5g) {
 567                 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD
 568                                         | ETH_LINK_SPEED_10M
 569                                         | ETH_LINK_SPEED_100M_HD
 570                                         | ETH_LINK_SPEED_100M
 571                                         | ETH_LINK_SPEED_1G
 572                                         | ETH_LINK_SPEED_2_5G;
 573         } else if (fif->mac_type == fman_mac_10g) {
 574                 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD
 575                                         | ETH_LINK_SPEED_10M
 576                                         | ETH_LINK_SPEED_100M_HD
 577                                         | ETH_LINK_SPEED_100M
 578                                         | ETH_LINK_SPEED_1G
 579                                         | ETH_LINK_SPEED_2_5G
 580                                         | ETH_LINK_SPEED_10G;
 581         } else {
 582                 DPAA_PMD_ERR("invalid link_speed: %s, %d",
 583                              dpaa_intf->name, fif->mac_type);
 584                 return -EINVAL;
 585         }
 586
 587         dev_info->rx_offload_capa = dev_rx_offloads_sup |
 588                                         dev_rx_offloads_nodis;
 589         dev_info->tx_offload_capa = dev_tx_offloads_sup |
 590                                         dev_tx_offloads_nodis;
 591         dev_info->default_rxportconf.burst_size = DPAA_DEF_RX_BURST_SIZE;
 592         dev_info->default_txportconf.burst_size = DPAA_DEF_TX_BURST_SIZE;
 593         dev_info->default_rxportconf.nb_queues = 1;
 594         dev_info->default_txportconf.nb_queues = 1;
 595         dev_info->default_txportconf.ring_size = CGR_TX_CGR_THRESH;
 596         dev_info->default_rxportconf.ring_size = CGR_RX_PERFQ_THRESH;
 597
 598         return 0;
 599 }
 600
 601 static int
 602 dpaa_dev_rx_burst_mode_get(struct rte_eth_dev *dev,
 603                         __rte_unused uint16_t queue_id,
 604                         struct rte_eth_burst_mode *mode)
 605 {
 606         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 607         int ret = -EINVAL;
 608         unsigned int i;
 609         const struct burst_info {
 610                 uint64_t flags;
 611                 const char *output;
 612         } rx_offload_map[] = {
 613                         {DEV_RX_OFFLOAD_JUMBO_FRAME, " Jumbo frame,"},
 614                         {DEV_RX_OFFLOAD_SCATTER, " Scattered,"},
 615                         {DEV_RX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"},
 616                         {DEV_RX_OFFLOAD_UDP_CKSUM, " UDP csum,"},
 617                         {DEV_RX_OFFLOAD_TCP_CKSUM, " TCP csum,"},
 618                         {DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
 619                         {DEV_RX_OFFLOAD_RSS_HASH, " RSS,"}
 620         };
 621
 622         /* Update Rx offload info */
 623         for (i = 0; i < RTE_DIM(rx_offload_map); i++) {
 624                 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) {
 625                         snprintf(mode->info, sizeof(mode->info), "%s",
 626                                 rx_offload_map[i].output);
 627                         ret = 0;
 628                         break;
 629                 }
 630         }
 631         return ret;
 632 }
 633
 634 static int
 635 dpaa_dev_tx_burst_mode_get(struct rte_eth_dev *dev,
 636                         __rte_unused uint16_t queue_id,
 637                         struct rte_eth_burst_mode *mode)
 638 {
 639         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 640         int ret = -EINVAL;
 641         unsigned int i;
 642         const struct burst_info {
 643                 uint64_t flags;
 644                 const char *output;
 645         } tx_offload_map[] = {
 646                         {DEV_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"},
 647                         {DEV_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"},
 648                         {DEV_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"},
 649                         {DEV_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"},
 650                         {DEV_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"},
 651                         {DEV_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
 652                         {DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
 653                         {DEV_TX_OFFLOAD_MULTI_SEGS, " Scattered,"}
 654         };
 655
 656         /* Update Tx offload info */
 657         for (i = 0; i < RTE_DIM(tx_offload_map); i++) {
 658                 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) {
 659                         snprintf(mode->info, sizeof(mode->info), "%s",
 660                                 tx_offload_map[i].output);
 661                         ret = 0;
 662                         break;
 663                 }
 664         }
 665         return ret;
 666 }
 667
 668 static int dpaa_eth_link_update(struct rte_eth_dev *dev,
 669                                 int wait_to_complete __rte_unused)
 670 {
 671         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 672         struct rte_eth_link *link = &dev->data->dev_link;
 673         struct fman_if *fif = dev->process_private;
 674         struct __fman_if *__fif = container_of(fif, struct __fman_if, __if);
 675         int ret, ioctl_version;
 676
 677         PMD_INIT_FUNC_TRACE();
 678
 679         ioctl_version = dpaa_get_ioctl_version_number();
 680
 681
 682         if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC) {
 683                 ret = dpaa_get_link_status(__fif->node_name, link);
 684                 if (ret)
 685                         return ret;
 686         } else {
 687                 link->link_status = dpaa_intf->valid;
 688         }
 689
 690         if (ioctl_version < 2) {
 691                 link->link_duplex = ETH_LINK_FULL_DUPLEX;
 692                 link->link_autoneg = ETH_LINK_AUTONEG;
 693
 694                 if (fif->mac_type == fman_mac_1g)
 695                         link->link_speed = ETH_SPEED_NUM_1G;
 696                 else if (fif->mac_type == fman_mac_2_5g)
 697                         link->link_speed = ETH_SPEED_NUM_2_5G;
 698                 else if (fif->mac_type == fman_mac_10g)
 699                         link->link_speed = ETH_SPEED_NUM_10G;
 700                 else
 701                         DPAA_PMD_ERR("invalid link_speed: %s, %d",
 702                                      dpaa_intf->name, fif->mac_type);
 703         }
 704
 705         DPAA_PMD_INFO("Port %d Link is %s\n", dev->data->port_id,
 706                       link->link_status ? "Up" : "Down");
 707         return 0;
 708 }
 709
 710 static int dpaa_eth_stats_get(struct rte_eth_dev *dev,
 711                                struct rte_eth_stats *stats)
 712 {
 713         PMD_INIT_FUNC_TRACE();
 714
 715         fman_if_stats_get(dev->process_private, stats);
 716         return 0;
 717 }
 718
 719 static int dpaa_eth_stats_reset(struct rte_eth_dev *dev)
 720 {
 721         PMD_INIT_FUNC_TRACE();
 722
 723         fman_if_stats_reset(dev->process_private);
 724
 725         return 0;
 726 }
 727
 728 static int
 729 dpaa_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
 730                     unsigned int n)
 731 {
 732         unsigned int i = 0, num = RTE_DIM(dpaa_xstats_strings);
 733         uint64_t values[sizeof(struct dpaa_if_stats) / 8];
 734
 735         if (n < num)
 736                 return num;
 737
 738         if (xstats == NULL)
 739                 return 0;
 740
 741         fman_if_stats_get_all(dev->process_private, values,
 742                               sizeof(struct dpaa_if_stats) / 8);
 743
 744         for (i = 0; i < num; i++) {
 745                 xstats[i].id = i;
 746                 xstats[i].value = values[dpaa_xstats_strings[i].offset / 8];
 747         }
 748         return i;
 749 }
 750
 751 static int
 752 dpaa_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 753                       struct rte_eth_xstat_name *xstats_names,
 754                       unsigned int limit)
 755 {
 756         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 757
 758         if (limit < stat_cnt)
 759                 return stat_cnt;
 760
 761         if (xstats_names != NULL)
 762                 for (i = 0; i < stat_cnt; i++)
 763                         strlcpy(xstats_names[i].name,
 764                                 dpaa_xstats_strings[i].name,
 765                                 sizeof(xstats_names[i].name));
 766
 767         return stat_cnt;
 768 }
 769
 770 static int
 771 dpaa_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 772                       uint64_t *values, unsigned int n)
 773 {
 774         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 775         uint64_t values_copy[sizeof(struct dpaa_if_stats) / 8];
 776
 777         if (!ids) {
 778                 if (n < stat_cnt)
 779                         return stat_cnt;
 780
 781                 if (!values)
 782                         return 0;
 783
 784                 fman_if_stats_get_all(dev->process_private, values_copy,
 785                                       sizeof(struct dpaa_if_stats) / 8);
 786
 787                 for (i = 0; i < stat_cnt; i++)
 788                         values[i] =
 789                                 values_copy[dpaa_xstats_strings[i].offset / 8];
 790
 791                 return stat_cnt;
 792         }
 793
 794         dpaa_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
 795
 796         for (i = 0; i < n; i++) {
 797                 if (ids[i] >= stat_cnt) {
 798                         DPAA_PMD_ERR("id value isn't valid");
 799                         return -1;
 800                 }
 801                 values[i] = values_copy[ids[i]];
 802         }
 803         return n;
 804 }
 805
 806 static int
 807 dpaa_xstats_get_names_by_id(
 808         struct rte_eth_dev *dev,
 809         struct rte_eth_xstat_name *xstats_names,
 810         const uint64_t *ids,
 811         unsigned int limit)
 812 {
 813         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 814         struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
 815
 816         if (!ids)
 817                 return dpaa_xstats_get_names(dev, xstats_names, limit);
 818
 819         dpaa_xstats_get_names(dev, xstats_names_copy, limit);
 820
 821         for (i = 0; i < limit; i++) {
 822                 if (ids[i] >= stat_cnt) {
 823                         DPAA_PMD_ERR("id value isn't valid");
 824                         return -1;
 825                 }
 826                 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
 827         }
 828         return limit;
 829 }
 830
 831 static int dpaa_eth_promiscuous_enable(struct rte_eth_dev *dev)
 832 {
 833         PMD_INIT_FUNC_TRACE();
 834
 835         fman_if_promiscuous_enable(dev->process_private);
 836
 837         return 0;
 838 }
 839
 840 static int dpaa_eth_promiscuous_disable(struct rte_eth_dev *dev)
 841 {
 842         PMD_INIT_FUNC_TRACE();
 843
 844         fman_if_promiscuous_disable(dev->process_private);
 845
 846         return 0;
 847 }
 848
 849 static int dpaa_eth_multicast_enable(struct rte_eth_dev *dev)
 850 {
 851         PMD_INIT_FUNC_TRACE();
 852
 853         fman_if_set_mcast_filter_table(dev->process_private);
 854
 855         return 0;
 856 }
 857
 858 static int dpaa_eth_multicast_disable(struct rte_eth_dev *dev)
 859 {
 860         PMD_INIT_FUNC_TRACE();
 861
 862         fman_if_reset_mcast_filter_table(dev->process_private);
 863
 864         return 0;
 865 }
 866
 867 static void dpaa_fman_if_pool_setup(struct rte_eth_dev *dev)
 868 {
 869         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 870         struct fman_if_ic_params icp;
 871         uint32_t fd_offset;
 872         uint32_t bp_size;
 873
 874         memset(&icp, 0, sizeof(icp));
 875         /* set ICEOF for to the default value , which is 0*/
 876         icp.iciof = DEFAULT_ICIOF;
 877         icp.iceof = DEFAULT_RX_ICEOF;
 878         icp.icsz = DEFAULT_ICSZ;
 879         fman_if_set_ic_params(dev->process_private, &icp);
 880
 881         fd_offset = RTE_PKTMBUF_HEADROOM + DPAA_HW_BUF_RESERVE;
 882         fman_if_set_fdoff(dev->process_private, fd_offset);
 883
 884         /* Buffer pool size should be equal to Dataroom Size*/
 885         bp_size = rte_pktmbuf_data_room_size(dpaa_intf->bp_info->mp);
 886
 887         fman_if_set_bp(dev->process_private,
 888                        dpaa_intf->bp_info->mp->size,
 889                        dpaa_intf->bp_info->bpid, bp_size);
 890 }
 891
 892 static inline int dpaa_eth_rx_queue_bp_check(struct rte_eth_dev *dev,
 893                                              int8_t vsp_id, uint32_t bpid)
 894 {
 895         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 896         struct fman_if *fif = dev->process_private;
 897
 898         if (fif->num_profiles) {
 899                 if (vsp_id < 0)
 900                         vsp_id = fif->base_profile_id;
 901         } else {
 902                 if (vsp_id < 0)
 903                         vsp_id = 0;
 904         }
 905
 906         if (dpaa_intf->vsp_bpid[vsp_id] &&
 907                 bpid != dpaa_intf->vsp_bpid[vsp_id]) {
 908                 DPAA_PMD_ERR("Various MPs are assigned to RXQs with same VSP");
 909
 910                 return -1;
 911         }
 912
 913         return 0;
 914 }
 915
 916 static
 917 int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 918                             uint16_t nb_desc,
 919                             unsigned int socket_id __rte_unused,
 920                             const struct rte_eth_rxconf *rx_conf,
 921                             struct rte_mempool *mp)
 922 {
 923         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 924         struct fman_if *fif = dev->process_private;
 925         struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_idx];
 926         struct qm_mcc_initfq opts = {0};
 927         u32 flags = 0;
 928         int ret;
 929         u32 buffsz = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
 930
 931         PMD_INIT_FUNC_TRACE();
 932
 933         if (queue_idx >= dev->data->nb_rx_queues) {
 934                 rte_errno = EOVERFLOW;
 935                 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
 936                       (void *)dev, queue_idx, dev->data->nb_rx_queues);
 937                 return -rte_errno;
 938         }
 939
 940         /* Rx deferred start is not supported */
 941         if (rx_conf->rx_deferred_start) {
 942                 DPAA_PMD_ERR("%p:Rx deferred start not supported", (void *)dev);
 943                 return -EINVAL;
 944         }
 945         rxq->nb_desc = UINT16_MAX;
 946         rxq->offloads = rx_conf->offloads;
 947
 948         DPAA_PMD_INFO("Rx queue setup for queue index: %d fq_id (0x%x)",
 949                         queue_idx, rxq->fqid);
 950
 951         if (!fif->num_profiles) {
 952                 if (dpaa_intf->bp_info && dpaa_intf->bp_info->bp &&
 953                         dpaa_intf->bp_info->mp != mp) {
 954                         DPAA_PMD_WARN("Multiple pools on same interface not"
 955                                       " supported");
 956                         return -EINVAL;
 957                 }
 958         } else {
 959                 if (dpaa_eth_rx_queue_bp_check(dev, rxq->vsp_id,
 960                         DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid)) {
 961                         return -EINVAL;
 962                 }
 963         }
 964
 965         /* Max packet can fit in single buffer */
 966         if (dev->data->dev_conf.rxmode.max_rx_pkt_len <= buffsz) {
 967                 ;
 968         } else if (dev->data->dev_conf.rxmode.offloads &
 969                         DEV_RX_OFFLOAD_SCATTER) {
 970                 if (dev->data->dev_conf.rxmode.max_rx_pkt_len >
 971                         buffsz * DPAA_SGT_MAX_ENTRIES) {
 972                         DPAA_PMD_ERR("max RxPkt size %d too big to fit "
 973                                 "MaxSGlist %d",
 974                                 dev->data->dev_conf.rxmode.max_rx_pkt_len,
 975                                 buffsz * DPAA_SGT_MAX_ENTRIES);
 976                         rte_errno = EOVERFLOW;
 977                         return -rte_errno;
 978                 }
 979         } else {
 980                 DPAA_PMD_WARN("The requested maximum Rx packet size (%u) is"
 981                      " larger than a single mbuf (%u) and scattered"
 982                      " mode has not been requested",
 983                      dev->data->dev_conf.rxmode.max_rx_pkt_len,
 984                      buffsz - RTE_PKTMBUF_HEADROOM);
 985         }
 986
 987         dpaa_intf->bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp);
 988
 989         /* For shared interface, it's done in kernel, skip.*/
 990         if (!fif->is_shared_mac)
 991                 dpaa_fman_if_pool_setup(dev);
 992
 993         if (fif->num_profiles) {
 994                 int8_t vsp_id = rxq->vsp_id;
 995
 996                 if (vsp_id >= 0) {
 997                         ret = dpaa_port_vsp_update(dpaa_intf, fmc_q, vsp_id,
 998                                         DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid,
 999                                         fif);
1000                         if (ret) {
1001                                 DPAA_PMD_ERR("dpaa_port_vsp_update failed");
1002                                 return ret;
1003                         }
1004                 } else {
1005                         DPAA_PMD_INFO("Base profile is associated to"
1006                                 " RXQ fqid:%d\r\n", rxq->fqid);
1007                         if (fif->is_shared_mac) {
1008                                 DPAA_PMD_ERR("Fatal: Base profile is associated"
1009                                              " to shared interface on DPDK.");
1010                                 return -EINVAL;
1011                         }
1012                         dpaa_intf->vsp_bpid[fif->base_profile_id] =
1013                                 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid;
1014                 }
1015         } else {
1016                 dpaa_intf->vsp_bpid[0] =
1017                         DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid;
1018         }
1019
1020         dpaa_intf->valid = 1;
1021         DPAA_PMD_DEBUG("if:%s sg_on = %d, max_frm =%d", dpaa_intf->name,
1022                 fman_if_get_sg_enable(fif),
1023                 dev->data->dev_conf.rxmode.max_rx_pkt_len);
1024         /* checking if push mode only, no error check for now */
1025         if (!rxq->is_static &&
1026             dpaa_push_mode_max_queue > dpaa_push_queue_idx) {
1027                 struct qman_portal *qp;
1028                 int q_fd;
1029
1030                 dpaa_push_queue_idx++;
1031                 opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
1032                 opts.fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK |
1033                                    QM_FQCTRL_CTXASTASHING |
1034                                    QM_FQCTRL_PREFERINCACHE;
1035                 opts.fqd.context_a.stashing.exclusive = 0;
1036                 /* In muticore scenario stashing becomes a bottleneck on LS1046.
1037                  * So do not enable stashing in this case
1038                  */
1039                 if (dpaa_svr_family != SVR_LS1046A_FAMILY)
1040                         opts.fqd.context_a.stashing.annotation_cl =
1041                                                 DPAA_IF_RX_ANNOTATION_STASH;
1042                 opts.fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
1043                 opts.fqd.context_a.stashing.context_cl =
1044                                                 DPAA_IF_RX_CONTEXT_STASH;
1045
1046                 /*Create a channel and associate given queue with the channel*/
1047                 qman_alloc_pool_range((u32 *)&rxq->ch_id, 1, 1, 0);
1048                 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
1049                 opts.fqd.dest.channel = rxq->ch_id;
1050                 opts.fqd.dest.wq = DPAA_IF_RX_PRIORITY;
1051                 flags = QMAN_INITFQ_FLAG_SCHED;
1052
1053                 /* Configure tail drop */
1054                 if (dpaa_intf->cgr_rx) {
1055                         opts.we_mask |= QM_INITFQ_WE_CGID;
1056                         opts.fqd.cgid = dpaa_intf->cgr_rx[queue_idx].cgrid;
1057                         opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1058                 }
1059                 ret = qman_init_fq(rxq, flags, &opts);
1060                 if (ret) {
1061                         DPAA_PMD_ERR("Channel/Q association failed. fqid 0x%x "
1062                                 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
1063                         return ret;
1064                 }
1065                 if (dpaa_svr_family == SVR_LS1043A_FAMILY) {
1066                         rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb_no_prefetch;
1067                 } else {
1068                         rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb;
1069                         rxq->cb.dqrr_prepare = dpaa_rx_cb_prepare;
1070                 }
1071
1072                 rxq->is_static = true;
1073
1074                 /* Allocate qman specific portals */
1075                 qp = fsl_qman_fq_portal_create(&q_fd);
1076                 if (!qp) {
1077                         DPAA_PMD_ERR("Unable to alloc fq portal");
1078                         return -1;
1079                 }
1080                 rxq->qp = qp;
1081
1082                 /* Set up the device interrupt handler */
1083                 if (!dev->intr_handle) {
1084                         struct rte_dpaa_device *dpaa_dev;
1085                         struct rte_device *rdev = dev->device;
1086
1087                         dpaa_dev = container_of(rdev, struct rte_dpaa_device,
1088                                                 device);
1089                         dev->intr_handle = &dpaa_dev->intr_handle;
1090                         dev->intr_handle->intr_vec = rte_zmalloc(NULL,
1091                                         dpaa_push_mode_max_queue, 0);
1092                         if (!dev->intr_handle->intr_vec) {
1093                                 DPAA_PMD_ERR("intr_vec alloc failed");
1094                                 return -ENOMEM;
1095                         }
1096                         dev->intr_handle->nb_efd = dpaa_push_mode_max_queue;
1097                         dev->intr_handle->max_intr = dpaa_push_mode_max_queue;
1098                 }
1099
1100                 dev->intr_handle->type = RTE_INTR_HANDLE_EXT;
1101                 dev->intr_handle->intr_vec[queue_idx] = queue_idx + 1;
1102                 dev->intr_handle->efds[queue_idx] = q_fd;
1103                 rxq->q_fd = q_fd;
1104         }
1105         rxq->bp_array = rte_dpaa_bpid_info;
1106         dev->data->rx_queues[queue_idx] = rxq;
1107
1108         /* configure the CGR size as per the desc size */
1109         if (dpaa_intf->cgr_rx) {
1110                 struct qm_mcc_initcgr cgr_opts = {0};
1111
1112                 rxq->nb_desc = nb_desc;
1113                 /* Enable tail drop with cgr on this queue */
1114                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, nb_desc, 0);
1115                 ret = qman_modify_cgr(dpaa_intf->cgr_rx, 0, &cgr_opts);
1116                 if (ret) {
1117                         DPAA_PMD_WARN(
1118                                 "rx taildrop modify fail on fqid %d (ret=%d)",
1119                                 rxq->fqid, ret);
1120                 }
1121         }
1122         /* Enable main queue to receive error packets also by default */
1123         fman_if_set_err_fqid(fif, rxq->fqid);
1124         return 0;
1125 }
1126
1127 int
1128 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev,
1129                 int eth_rx_queue_id,
1130                 u16 ch_id,
1131                 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
1132 {
1133         int ret;
1134         u32 flags = 0;
1135         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1136         struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
1137         struct qm_mcc_initfq opts = {0};
1138
1139         if (dpaa_push_mode_max_queue)
1140                 DPAA_PMD_WARN("PUSH mode q and EVENTDEV are not compatible\n"
1141                               "PUSH mode already enabled for first %d queues.\n"
1142                               "To disable set DPAA_PUSH_QUEUES_NUMBER to 0\n",
1143                               dpaa_push_mode_max_queue);
1144
1145         dpaa_poll_queue_default_config(&opts);
1146
1147         switch (queue_conf->ev.sched_type) {
1148         case RTE_SCHED_TYPE_ATOMIC:
1149                 opts.fqd.fq_ctrl |= QM_FQCTRL_HOLDACTIVE;
1150                 /* Reset FQCTRL_AVOIDBLOCK bit as it is unnecessary
1151                  * configuration with HOLD_ACTIVE setting
1152                  */
1153                 opts.fqd.fq_ctrl &= (~QM_FQCTRL_AVOIDBLOCK);
1154                 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_atomic;
1155                 break;
1156         case RTE_SCHED_TYPE_ORDERED:
1157                 DPAA_PMD_ERR("Ordered queue schedule type is not supported\n");
1158                 return -1;
1159         default:
1160                 opts.fqd.fq_ctrl |= QM_FQCTRL_AVOIDBLOCK;
1161                 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_parallel;
1162                 break;
1163         }
1164
1165         opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
1166         opts.fqd.dest.channel = ch_id;
1167         opts.fqd.dest.wq = queue_conf->ev.priority;
1168
1169         if (dpaa_intf->cgr_rx) {
1170                 opts.we_mask |= QM_INITFQ_WE_CGID;
1171                 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
1172                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1173         }
1174
1175         flags = QMAN_INITFQ_FLAG_SCHED;
1176
1177         ret = qman_init_fq(rxq, flags, &opts);
1178         if (ret) {
1179                 DPAA_PMD_ERR("Ev-Channel/Q association failed. fqid 0x%x "
1180                                 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
1181                 return ret;
1182         }
1183
1184         /* copy configuration which needs to be filled during dequeue */
1185         memcpy(&rxq->ev, &queue_conf->ev, sizeof(struct rte_event));
1186         dev->data->rx_queues[eth_rx_queue_id] = rxq;
1187
1188         return ret;
1189 }
1190
1191 int
1192 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev,
1193                 int eth_rx_queue_id)
1194 {
1195         struct qm_mcc_initfq opts;
1196         int ret;
1197         u32 flags = 0;
1198         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1199         struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
1200
1201         dpaa_poll_queue_default_config(&opts);
1202
1203         if (dpaa_intf->cgr_rx) {
1204                 opts.we_mask |= QM_INITFQ_WE_CGID;
1205                 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
1206                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1207         }
1208
1209         ret = qman_init_fq(rxq, flags, &opts);
1210         if (ret) {
1211                 DPAA_PMD_ERR("init rx fqid %d failed with ret: %d",
1212                              rxq->fqid, ret);
1213         }
1214
1215         rxq->cb.dqrr_dpdk_cb = NULL;
1216         dev->data->rx_queues[eth_rx_queue_id] = NULL;
1217
1218         return 0;
1219 }
1220
1221 static
1222 void dpaa_eth_rx_queue_release(void *rxq __rte_unused)
1223 {
1224         PMD_INIT_FUNC_TRACE();
1225 }
1226
1227 static
1228 int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1229                             uint16_t nb_desc __rte_unused,
1230                 unsigned int socket_id __rte_unused,
1231                 const struct rte_eth_txconf *tx_conf)
1232 {
1233         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1234         struct qman_fq *txq = &dpaa_intf->tx_queues[queue_idx];
1235
1236         PMD_INIT_FUNC_TRACE();
1237
1238         /* Tx deferred start is not supported */
1239         if (tx_conf->tx_deferred_start) {
1240                 DPAA_PMD_ERR("%p:Tx deferred start not supported", (void *)dev);
1241                 return -EINVAL;
1242         }
1243         txq->nb_desc = UINT16_MAX;
1244         txq->offloads = tx_conf->offloads;
1245
1246         if (queue_idx >= dev->data->nb_tx_queues) {
1247                 rte_errno = EOVERFLOW;
1248                 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
1249                       (void *)dev, queue_idx, dev->data->nb_tx_queues);
1250                 return -rte_errno;
1251         }
1252
1253         DPAA_PMD_INFO("Tx queue setup for queue index: %d fq_id (0x%x)",
1254                         queue_idx, txq->fqid);
1255         dev->data->tx_queues[queue_idx] = txq;
1256
1257         return 0;
1258 }
1259
1260 static void dpaa_eth_tx_queue_release(void *txq __rte_unused)
1261 {
1262         PMD_INIT_FUNC_TRACE();
1263 }
1264
1265 static uint32_t
1266 dpaa_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1267 {
1268         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1269         struct qman_fq *rxq = &dpaa_intf->rx_queues[rx_queue_id];
1270         u32 frm_cnt = 0;
1271
1272         PMD_INIT_FUNC_TRACE();
1273
1274         if (qman_query_fq_frm_cnt(rxq, &frm_cnt) == 0) {
1275                 DPAA_PMD_DEBUG("RX frame count for q(%d) is %u",
1276                                rx_queue_id, frm_cnt);
1277         }
1278         return frm_cnt;
1279 }
1280
1281 static int dpaa_link_down(struct rte_eth_dev *dev)
1282 {
1283         struct fman_if *fif = dev->process_private;
1284         struct __fman_if *__fif;
1285
1286         PMD_INIT_FUNC_TRACE();
1287
1288         __fif = container_of(fif, struct __fman_if, __if);
1289
1290         if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC)
1291                 dpaa_update_link_status(__fif->node_name, ETH_LINK_DOWN);
1292         else
1293                 dpaa_eth_dev_stop(dev);
1294         return 0;
1295 }
1296
1297 static int dpaa_link_up(struct rte_eth_dev *dev)
1298 {
1299         struct fman_if *fif = dev->process_private;
1300         struct __fman_if *__fif;
1301
1302         PMD_INIT_FUNC_TRACE();
1303
1304         __fif = container_of(fif, struct __fman_if, __if);
1305
1306         if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC)
1307                 dpaa_update_link_status(__fif->node_name, ETH_LINK_UP);
1308         else
1309                 dpaa_eth_dev_start(dev);
1310         return 0;
1311 }
1312
1313 static int
1314 dpaa_flow_ctrl_set(struct rte_eth_dev *dev,
1315                    struct rte_eth_fc_conf *fc_conf)
1316 {
1317         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1318         struct rte_eth_fc_conf *net_fc;
1319
1320         PMD_INIT_FUNC_TRACE();
1321
1322         if (!(dpaa_intf->fc_conf)) {
1323                 dpaa_intf->fc_conf = rte_zmalloc(NULL,
1324                         sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
1325                 if (!dpaa_intf->fc_conf) {
1326                         DPAA_PMD_ERR("unable to save flow control info");
1327                         return -ENOMEM;
1328                 }
1329         }
1330         net_fc = dpaa_intf->fc_conf;
1331
1332         if (fc_conf->high_water < fc_conf->low_water) {
1333                 DPAA_PMD_ERR("Incorrect Flow Control Configuration");
1334                 return -EINVAL;
1335         }
1336
1337         if (fc_conf->mode == RTE_FC_NONE) {
1338                 return 0;
1339         } else if (fc_conf->mode == RTE_FC_TX_PAUSE ||
1340                  fc_conf->mode == RTE_FC_FULL) {
1341                 fman_if_set_fc_threshold(dev->process_private,
1342                                          fc_conf->high_water,
1343                                          fc_conf->low_water,
1344                                          dpaa_intf->bp_info->bpid);
1345                 if (fc_conf->pause_time)
1346                         fman_if_set_fc_quanta(dev->process_private,
1347                                               fc_conf->pause_time);
1348         }
1349
1350         /* Save the information in dpaa device */
1351         net_fc->pause_time = fc_conf->pause_time;
1352         net_fc->high_water = fc_conf->high_water;
1353         net_fc->low_water = fc_conf->low_water;
1354         net_fc->send_xon = fc_conf->send_xon;
1355         net_fc->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
1356         net_fc->mode = fc_conf->mode;
1357         net_fc->autoneg = fc_conf->autoneg;
1358
1359         return 0;
1360 }
1361
1362 static int
1363 dpaa_flow_ctrl_get(struct rte_eth_dev *dev,
1364                    struct rte_eth_fc_conf *fc_conf)
1365 {
1366         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1367         struct rte_eth_fc_conf *net_fc = dpaa_intf->fc_conf;
1368         int ret;
1369
1370         PMD_INIT_FUNC_TRACE();
1371
1372         if (net_fc) {
1373                 fc_conf->pause_time = net_fc->pause_time;
1374                 fc_conf->high_water = net_fc->high_water;
1375                 fc_conf->low_water = net_fc->low_water;
1376                 fc_conf->send_xon = net_fc->send_xon;
1377                 fc_conf->mac_ctrl_frame_fwd = net_fc->mac_ctrl_frame_fwd;
1378                 fc_conf->mode = net_fc->mode;
1379                 fc_conf->autoneg = net_fc->autoneg;
1380                 return 0;
1381         }
1382         ret = fman_if_get_fc_threshold(dev->process_private);
1383         if (ret) {
1384                 fc_conf->mode = RTE_FC_TX_PAUSE;
1385                 fc_conf->pause_time =
1386                         fman_if_get_fc_quanta(dev->process_private);
1387         } else {
1388                 fc_conf->mode = RTE_FC_NONE;
1389         }
1390
1391         return 0;
1392 }
1393
1394 static int
1395 dpaa_dev_add_mac_addr(struct rte_eth_dev *dev,
1396                              struct rte_ether_addr *addr,
1397                              uint32_t index,
1398                              __rte_unused uint32_t pool)
1399 {
1400         int ret;
1401
1402         PMD_INIT_FUNC_TRACE();
1403
1404         ret = fman_if_add_mac_addr(dev->process_private,
1405                                    addr->addr_bytes, index);
1406
1407         if (ret)
1408                 DPAA_PMD_ERR("Adding the MAC ADDR failed: err = %d", ret);
1409         return 0;
1410 }
1411
1412 static void
1413 dpaa_dev_remove_mac_addr(struct rte_eth_dev *dev,
1414                           uint32_t index)
1415 {
1416         PMD_INIT_FUNC_TRACE();
1417
1418         fman_if_clear_mac_addr(dev->process_private, index);
1419 }
1420
1421 static int
1422 dpaa_dev_set_mac_addr(struct rte_eth_dev *dev,
1423                        struct rte_ether_addr *addr)
1424 {
1425         int ret;
1426
1427         PMD_INIT_FUNC_TRACE();
1428
1429         ret = fman_if_add_mac_addr(dev->process_private, addr->addr_bytes, 0);
1430         if (ret)
1431                 DPAA_PMD_ERR("Setting the MAC ADDR failed %d", ret);
1432
1433         return ret;
1434 }
1435
1436 static int
1437 dpaa_dev_rss_hash_update(struct rte_eth_dev *dev,
1438                          struct rte_eth_rss_conf *rss_conf)
1439 {
1440         struct rte_eth_dev_data *data = dev->data;
1441         struct rte_eth_conf *eth_conf = &data->dev_conf;
1442
1443         PMD_INIT_FUNC_TRACE();
1444
1445         if (!(default_q || fmc_q)) {
1446                 if (dpaa_fm_config(dev, rss_conf->rss_hf)) {
1447                         DPAA_PMD_ERR("FM port configuration: Failed\n");
1448                         return -1;
1449                 }
1450                 eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf;
1451         } else {
1452                 DPAA_PMD_ERR("Function not supported\n");
1453                 return -ENOTSUP;
1454         }
1455         return 0;
1456 }
1457
1458 static int
1459 dpaa_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
1460                            struct rte_eth_rss_conf *rss_conf)
1461 {
1462         struct rte_eth_dev_data *data = dev->data;
1463         struct rte_eth_conf *eth_conf = &data->dev_conf;
1464
1465         /* dpaa does not support rss_key, so length should be 0*/
1466         rss_conf->rss_key_len = 0;
1467         rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf;
1468         return 0;
1469 }
1470
1471 static int dpaa_dev_queue_intr_enable(struct rte_eth_dev *dev,
1472                                       uint16_t queue_id)
1473 {
1474         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1475         struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id];
1476
1477         if (!rxq->is_static)
1478                 return -EINVAL;
1479
1480         return qman_fq_portal_irqsource_add(rxq->qp, QM_PIRQ_DQRI);
1481 }
1482
1483 static int dpaa_dev_queue_intr_disable(struct rte_eth_dev *dev,
1484                                        uint16_t queue_id)
1485 {
1486         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1487         struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id];
1488         uint32_t temp;
1489         ssize_t temp1;
1490
1491         if (!rxq->is_static)
1492                 return -EINVAL;
1493
1494         qman_fq_portal_irqsource_remove(rxq->qp, ~0);
1495
1496         temp1 = read(rxq->q_fd, &temp, sizeof(temp));
1497         if (temp1 != sizeof(temp))
1498                 DPAA_PMD_ERR("irq read error");
1499
1500         qman_fq_portal_thread_irq(rxq->qp);
1501
1502         return 0;
1503 }
1504
1505 static void
1506 dpaa_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1507         struct rte_eth_rxq_info *qinfo)
1508 {
1509         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1510         struct qman_fq *rxq;
1511
1512         rxq = dev->data->rx_queues[queue_id];
1513
1514         qinfo->mp = dpaa_intf->bp_info->mp;
1515         qinfo->scattered_rx = dev->data->scattered_rx;
1516         qinfo->nb_desc = rxq->nb_desc;
1517         qinfo->conf.rx_free_thresh = 1;
1518         qinfo->conf.rx_drop_en = 1;
1519         qinfo->conf.rx_deferred_start = 0;
1520         qinfo->conf.offloads = rxq->offloads;
1521 }
1522
1523 static void
1524 dpaa_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1525         struct rte_eth_txq_info *qinfo)
1526 {
1527         struct qman_fq *txq;
1528
1529         txq = dev->data->tx_queues[queue_id];
1530
1531         qinfo->nb_desc = txq->nb_desc;
1532         qinfo->conf.tx_thresh.pthresh = 0;
1533         qinfo->conf.tx_thresh.hthresh = 0;
1534         qinfo->conf.tx_thresh.wthresh = 0;
1535
1536         qinfo->conf.tx_free_thresh = 0;
1537         qinfo->conf.tx_rs_thresh = 0;
1538         qinfo->conf.offloads = txq->offloads;
1539         qinfo->conf.tx_deferred_start = 0;
1540 }
1541
1542 static struct eth_dev_ops dpaa_devops = {
1543         .dev_configure            = dpaa_eth_dev_configure,
1544         .dev_start                = dpaa_eth_dev_start,
1545         .dev_stop                 = dpaa_eth_dev_stop,
1546         .dev_close                = dpaa_eth_dev_close,
1547         .dev_infos_get            = dpaa_eth_dev_info,
1548         .dev_supported_ptypes_get = dpaa_supported_ptypes_get,
1549
1550         .rx_queue_setup           = dpaa_eth_rx_queue_setup,
1551         .tx_queue_setup           = dpaa_eth_tx_queue_setup,
1552         .rx_queue_release         = dpaa_eth_rx_queue_release,
1553         .tx_queue_release         = dpaa_eth_tx_queue_release,
1554         .rx_burst_mode_get        = dpaa_dev_rx_burst_mode_get,
1555         .tx_burst_mode_get        = dpaa_dev_tx_burst_mode_get,
1556         .rxq_info_get             = dpaa_rxq_info_get,
1557         .txq_info_get             = dpaa_txq_info_get,
1558
1559         .flow_ctrl_get            = dpaa_flow_ctrl_get,
1560         .flow_ctrl_set            = dpaa_flow_ctrl_set,
1561
1562         .link_update              = dpaa_eth_link_update,
1563         .stats_get                = dpaa_eth_stats_get,
1564         .xstats_get               = dpaa_dev_xstats_get,
1565         .xstats_get_by_id         = dpaa_xstats_get_by_id,
1566         .xstats_get_names_by_id   = dpaa_xstats_get_names_by_id,
1567         .xstats_get_names         = dpaa_xstats_get_names,
1568         .xstats_reset             = dpaa_eth_stats_reset,
1569         .stats_reset              = dpaa_eth_stats_reset,
1570         .promiscuous_enable       = dpaa_eth_promiscuous_enable,
1571         .promiscuous_disable      = dpaa_eth_promiscuous_disable,
1572         .allmulticast_enable      = dpaa_eth_multicast_enable,
1573         .allmulticast_disable     = dpaa_eth_multicast_disable,
1574         .mtu_set                  = dpaa_mtu_set,
1575         .dev_set_link_down        = dpaa_link_down,
1576         .dev_set_link_up          = dpaa_link_up,
1577         .mac_addr_add             = dpaa_dev_add_mac_addr,
1578         .mac_addr_remove          = dpaa_dev_remove_mac_addr,
1579         .mac_addr_set             = dpaa_dev_set_mac_addr,
1580
1581         .fw_version_get           = dpaa_fw_version_get,
1582
1583         .rx_queue_intr_enable     = dpaa_dev_queue_intr_enable,
1584         .rx_queue_intr_disable    = dpaa_dev_queue_intr_disable,
1585         .rss_hash_update          = dpaa_dev_rss_hash_update,
1586         .rss_hash_conf_get        = dpaa_dev_rss_hash_conf_get,
1587 };
1588
1589 static bool
1590 is_device_supported(struct rte_eth_dev *dev, struct rte_dpaa_driver *drv)
1591 {
1592         if (strcmp(dev->device->driver->name,
1593                    drv->driver.name))
1594                 return false;
1595
1596         return true;
1597 }
1598
1599 static bool
1600 is_dpaa_supported(struct rte_eth_dev *dev)
1601 {
1602         return is_device_supported(dev, &rte_dpaa_pmd);
1603 }
1604
1605 int
1606 rte_pmd_dpaa_set_tx_loopback(uint16_t port, uint8_t on)
1607 {
1608         struct rte_eth_dev *dev;
1609
1610         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
1611
1612         dev = &rte_eth_devices[port];
1613
1614         if (!is_dpaa_supported(dev))
1615                 return -ENOTSUP;
1616
1617         if (on)
1618                 fman_if_loopback_enable(dev->process_private);
1619         else
1620                 fman_if_loopback_disable(dev->process_private);
1621
1622         return 0;
1623 }
1624
1625 static int dpaa_fc_set_default(struct dpaa_if *dpaa_intf,
1626                                struct fman_if *fman_intf)
1627 {
1628         struct rte_eth_fc_conf *fc_conf;
1629         int ret;
1630
1631         PMD_INIT_FUNC_TRACE();
1632
1633         if (!(dpaa_intf->fc_conf)) {
1634                 dpaa_intf->fc_conf = rte_zmalloc(NULL,
1635                         sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
1636                 if (!dpaa_intf->fc_conf) {
1637                         DPAA_PMD_ERR("unable to save flow control info");
1638                         return -ENOMEM;
1639                 }
1640         }
1641         fc_conf = dpaa_intf->fc_conf;
1642         ret = fman_if_get_fc_threshold(fman_intf);
1643         if (ret) {
1644                 fc_conf->mode = RTE_FC_TX_PAUSE;
1645                 fc_conf->pause_time = fman_if_get_fc_quanta(fman_intf);
1646         } else {
1647                 fc_conf->mode = RTE_FC_NONE;
1648         }
1649
1650         return 0;
1651 }
1652
1653 /* Initialise an Rx FQ */
1654 static int dpaa_rx_queue_init(struct qman_fq *fq, struct qman_cgr *cgr_rx,
1655                               uint32_t fqid)
1656 {
1657         struct qm_mcc_initfq opts = {0};
1658         int ret;
1659         u32 flags = QMAN_FQ_FLAG_NO_ENQUEUE;
1660         struct qm_mcc_initcgr cgr_opts = {
1661                 .we_mask = QM_CGR_WE_CS_THRES |
1662                                 QM_CGR_WE_CSTD_EN |
1663                                 QM_CGR_WE_MODE,
1664                 .cgr = {
1665                         .cstd_en = QM_CGR_EN,
1666                         .mode = QMAN_CGR_MODE_FRAME
1667                 }
1668         };
1669
1670         if (fmc_q || default_q) {
1671                 ret = qman_reserve_fqid(fqid);
1672                 if (ret) {
1673                         DPAA_PMD_ERR("reserve rx fqid 0x%x failed, ret: %d",
1674                                      fqid, ret);
1675                         return -EINVAL;
1676                 }
1677         }
1678
1679         DPAA_PMD_DEBUG("creating rx fq %p, fqid 0x%x", fq, fqid);
1680         ret = qman_create_fq(fqid, flags, fq);
1681         if (ret) {
1682                 DPAA_PMD_ERR("create rx fqid 0x%x failed with ret: %d",
1683                         fqid, ret);
1684                 return ret;
1685         }
1686         fq->is_static = false;
1687
1688         dpaa_poll_queue_default_config(&opts);
1689
1690         if (cgr_rx) {
1691                 /* Enable tail drop with cgr on this queue */
1692                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, td_threshold, 0);
1693                 cgr_rx->cb = NULL;
1694                 ret = qman_create_cgr(cgr_rx, QMAN_CGR_FLAG_USE_INIT,
1695                                       &cgr_opts);
1696                 if (ret) {
1697                         DPAA_PMD_WARN(
1698                                 "rx taildrop init fail on rx fqid 0x%x(ret=%d)",
1699                                 fq->fqid, ret);
1700                         goto without_cgr;
1701                 }
1702                 opts.we_mask |= QM_INITFQ_WE_CGID;
1703                 opts.fqd.cgid = cgr_rx->cgrid;
1704                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1705         }
1706 without_cgr:
1707         ret = qman_init_fq(fq, 0, &opts);
1708         if (ret)
1709                 DPAA_PMD_ERR("init rx fqid 0x%x failed with ret:%d", fqid, ret);
1710         return ret;
1711 }
1712
1713 /* Initialise a Tx FQ */
1714 static int dpaa_tx_queue_init(struct qman_fq *fq,
1715                               struct fman_if *fman_intf,
1716                               struct qman_cgr *cgr_tx)
1717 {
1718         struct qm_mcc_initfq opts = {0};
1719         struct qm_mcc_initcgr cgr_opts = {
1720                 .we_mask = QM_CGR_WE_CS_THRES |
1721                                 QM_CGR_WE_CSTD_EN |
1722                                 QM_CGR_WE_MODE,
1723                 .cgr = {
1724                         .cstd_en = QM_CGR_EN,
1725                         .mode = QMAN_CGR_MODE_FRAME
1726                 }
1727         };
1728         int ret;
1729
1730         ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID |
1731                              QMAN_FQ_FLAG_TO_DCPORTAL, fq);
1732         if (ret) {
1733                 DPAA_PMD_ERR("create tx fq failed with ret: %d", ret);
1734                 return ret;
1735         }
1736         opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL |
1737                        QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA;
1738         opts.fqd.dest.channel = fman_intf->tx_channel_id;
1739         opts.fqd.dest.wq = DPAA_IF_TX_PRIORITY;
1740         opts.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE;
1741         opts.fqd.context_b = 0;
1742         /* no tx-confirmation */
1743         opts.fqd.context_a.hi = 0x80000000 | fman_dealloc_bufs_mask_hi;
1744         opts.fqd.context_a.lo = 0 | fman_dealloc_bufs_mask_lo;
1745         DPAA_PMD_DEBUG("init tx fq %p, fqid 0x%x", fq, fq->fqid);
1746
1747         if (cgr_tx) {
1748                 /* Enable tail drop with cgr on this queue */
1749                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres,
1750                                       td_tx_threshold, 0);
1751                 cgr_tx->cb = NULL;
1752                 ret = qman_create_cgr(cgr_tx, QMAN_CGR_FLAG_USE_INIT,
1753                                       &cgr_opts);
1754                 if (ret) {
1755                         DPAA_PMD_WARN(
1756                                 "rx taildrop init fail on rx fqid 0x%x(ret=%d)",
1757                                 fq->fqid, ret);
1758                         goto without_cgr;
1759                 }
1760                 opts.we_mask |= QM_INITFQ_WE_CGID;
1761                 opts.fqd.cgid = cgr_tx->cgrid;
1762                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1763                 DPAA_PMD_DEBUG("Tx FQ tail drop enabled, threshold = %d\n",
1764                                 td_tx_threshold);
1765         }
1766 without_cgr:
1767         ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts);
1768         if (ret)
1769                 DPAA_PMD_ERR("init tx fqid 0x%x failed %d", fq->fqid, ret);
1770         return ret;
1771 }
1772
1773 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1774 /* Initialise a DEBUG FQ ([rt]x_error, rx_default). */
1775 static int dpaa_debug_queue_init(struct qman_fq *fq, uint32_t fqid)
1776 {
1777         struct qm_mcc_initfq opts = {0};
1778         int ret;
1779
1780         PMD_INIT_FUNC_TRACE();
1781
1782         ret = qman_reserve_fqid(fqid);
1783         if (ret) {
1784                 DPAA_PMD_ERR("Reserve debug fqid %d failed with ret: %d",
1785                         fqid, ret);
1786                 return -EINVAL;
1787         }
1788         /* "map" this Rx FQ to one of the interfaces Tx FQID */
1789         DPAA_PMD_DEBUG("Creating debug fq %p, fqid %d", fq, fqid);
1790         ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq);
1791         if (ret) {
1792                 DPAA_PMD_ERR("create debug fqid %d failed with ret: %d",
1793                         fqid, ret);
1794                 return ret;
1795         }
1796         opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL;
1797         opts.fqd.dest.wq = DPAA_IF_DEBUG_PRIORITY;
1798         ret = qman_init_fq(fq, 0, &opts);
1799         if (ret)
1800                 DPAA_PMD_ERR("init debug fqid %d failed with ret: %d",
1801                             fqid, ret);
1802         return ret;
1803 }
1804 #endif
1805
1806 /* Initialise a network interface */
1807 static int
1808 dpaa_dev_init_secondary(struct rte_eth_dev *eth_dev)
1809 {
1810         struct rte_dpaa_device *dpaa_device;
1811         struct fm_eth_port_cfg *cfg;
1812         struct dpaa_if *dpaa_intf;
1813         struct fman_if *fman_intf;
1814         int dev_id;
1815
1816         PMD_INIT_FUNC_TRACE();
1817
1818         dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1819         dev_id = dpaa_device->id.dev_id;
1820         cfg = dpaa_get_eth_port_cfg(dev_id);
1821         fman_intf = cfg->fman_if;
1822         eth_dev->process_private = fman_intf;
1823
1824         /* Plugging of UCODE burst API not supported in Secondary */
1825         dpaa_intf = eth_dev->data->dev_private;
1826         eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
1827         if (dpaa_intf->cgr_tx)
1828                 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx_slow;
1829         else
1830                 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx;
1831 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP
1832         qman_set_fq_lookup_table(
1833                 dpaa_intf->rx_queues->qman_fq_lookup_table);
1834 #endif
1835
1836         return 0;
1837 }
1838
1839 /* Initialise a network interface */
1840 static int
1841 dpaa_dev_init(struct rte_eth_dev *eth_dev)
1842 {
1843         int num_rx_fqs, fqid;
1844         int loop, ret = 0;
1845         int dev_id;
1846         struct rte_dpaa_device *dpaa_device;
1847         struct dpaa_if *dpaa_intf;
1848         struct fm_eth_port_cfg *cfg;
1849         struct fman_if *fman_intf;
1850         struct fman_if_bpool *bp, *tmp_bp;
1851         uint32_t cgrid[DPAA_MAX_NUM_PCD_QUEUES];
1852         uint32_t cgrid_tx[MAX_DPAA_CORES];
1853         uint32_t dev_rx_fqids[DPAA_MAX_NUM_PCD_QUEUES];
1854         int8_t dev_vspids[DPAA_MAX_NUM_PCD_QUEUES];
1855         int8_t vsp_id = -1;
1856
1857         PMD_INIT_FUNC_TRACE();
1858
1859         dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1860         dev_id = dpaa_device->id.dev_id;
1861         dpaa_intf = eth_dev->data->dev_private;
1862         cfg = dpaa_get_eth_port_cfg(dev_id);
1863         fman_intf = cfg->fman_if;
1864
1865         dpaa_intf->name = dpaa_device->name;
1866
1867         /* save fman_if & cfg in the interface struture */
1868         eth_dev->process_private = fman_intf;
1869         dpaa_intf->ifid = dev_id;
1870         dpaa_intf->cfg = cfg;
1871
1872         memset((char *)dev_rx_fqids, 0,
1873                 sizeof(uint32_t) * DPAA_MAX_NUM_PCD_QUEUES);
1874
1875         memset(dev_vspids, -1, DPAA_MAX_NUM_PCD_QUEUES);
1876
1877         /* Initialize Rx FQ's */
1878         if (default_q) {
1879                 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES;
1880         } else if (fmc_q) {
1881                 num_rx_fqs = dpaa_port_fmc_init(fman_intf, dev_rx_fqids,
1882                                                 dev_vspids,
1883                                                 DPAA_MAX_NUM_PCD_QUEUES);
1884                 if (num_rx_fqs < 0) {
1885                         DPAA_PMD_ERR("%s FMC initializes failed!",
1886                                 dpaa_intf->name);
1887                         goto free_rx;
1888                 }
1889                 if (!num_rx_fqs) {
1890                         DPAA_PMD_WARN("%s is not configured by FMC.",
1891                                 dpaa_intf->name);
1892                 }
1893         } else {
1894                 /* FMCLESS mode, load balance to multiple cores.*/
1895                 num_rx_fqs = rte_lcore_count();
1896         }
1897
1898         /* Each device can not have more than DPAA_MAX_NUM_PCD_QUEUES RX
1899          * queues.
1900          */
1901         if (num_rx_fqs < 0 || num_rx_fqs > DPAA_MAX_NUM_PCD_QUEUES) {
1902                 DPAA_PMD_ERR("Invalid number of RX queues\n");
1903                 return -EINVAL;
1904         }
1905
1906         if (num_rx_fqs > 0) {
1907                 dpaa_intf->rx_queues = rte_zmalloc(NULL,
1908                         sizeof(struct qman_fq) * num_rx_fqs, MAX_CACHELINE);
1909                 if (!dpaa_intf->rx_queues) {
1910                         DPAA_PMD_ERR("Failed to alloc mem for RX queues\n");
1911                         return -ENOMEM;
1912                 }
1913         } else {
1914                 dpaa_intf->rx_queues = NULL;
1915         }
1916
1917         memset(cgrid, 0, sizeof(cgrid));
1918         memset(cgrid_tx, 0, sizeof(cgrid_tx));
1919
1920         /* if DPAA_TX_TAILDROP_THRESHOLD is set, use that value; if 0, it means
1921          * Tx tail drop is disabled.
1922          */
1923         if (getenv("DPAA_TX_TAILDROP_THRESHOLD")) {
1924                 td_tx_threshold = atoi(getenv("DPAA_TX_TAILDROP_THRESHOLD"));
1925                 DPAA_PMD_DEBUG("Tail drop threshold env configured: %u",
1926                                td_tx_threshold);
1927                 /* if a very large value is being configured */
1928                 if (td_tx_threshold > UINT16_MAX)
1929                         td_tx_threshold = CGR_RX_PERFQ_THRESH;
1930         }
1931
1932         /* If congestion control is enabled globally*/
1933         if (num_rx_fqs > 0 && td_threshold) {
1934                 dpaa_intf->cgr_rx = rte_zmalloc(NULL,
1935                         sizeof(struct qman_cgr) * num_rx_fqs, MAX_CACHELINE);
1936                 if (!dpaa_intf->cgr_rx) {
1937                         DPAA_PMD_ERR("Failed to alloc mem for cgr_rx\n");
1938                         ret = -ENOMEM;
1939                         goto free_rx;
1940                 }
1941
1942                 ret = qman_alloc_cgrid_range(&cgrid[0], num_rx_fqs, 1, 0);
1943                 if (ret != num_rx_fqs) {
1944                         DPAA_PMD_WARN("insufficient CGRIDs available");
1945                         ret = -EINVAL;
1946                         goto free_rx;
1947                 }
1948         } else {
1949                 dpaa_intf->cgr_rx = NULL;
1950         }
1951
1952         if (!fmc_q && !default_q) {
1953                 ret = qman_alloc_fqid_range(dev_rx_fqids, num_rx_fqs,
1954                                             num_rx_fqs, 0);
1955                 if (ret < 0) {
1956                         DPAA_PMD_ERR("Failed to alloc rx fqid's\n");
1957                         goto free_rx;
1958                 }
1959         }
1960
1961         for (loop = 0; loop < num_rx_fqs; loop++) {
1962                 if (default_q)
1963                         fqid = cfg->rx_def;
1964                 else
1965                         fqid = dev_rx_fqids[loop];
1966
1967                 vsp_id = dev_vspids[loop];
1968
1969                 if (dpaa_intf->cgr_rx)
1970                         dpaa_intf->cgr_rx[loop].cgrid = cgrid[loop];
1971
1972                 ret = dpaa_rx_queue_init(&dpaa_intf->rx_queues[loop],
1973                         dpaa_intf->cgr_rx ? &dpaa_intf->cgr_rx[loop] : NULL,
1974                         fqid);
1975                 if (ret)
1976                         goto free_rx;
1977                 dpaa_intf->rx_queues[loop].vsp_id = vsp_id;
1978                 dpaa_intf->rx_queues[loop].dpaa_intf = dpaa_intf;
1979         }
1980         dpaa_intf->nb_rx_queues = num_rx_fqs;
1981
1982         /* Initialise Tx FQs.free_rx Have as many Tx FQ's as number of cores */
1983         dpaa_intf->tx_queues = rte_zmalloc(NULL, sizeof(struct qman_fq) *
1984                 MAX_DPAA_CORES, MAX_CACHELINE);
1985         if (!dpaa_intf->tx_queues) {
1986                 DPAA_PMD_ERR("Failed to alloc mem for TX queues\n");
1987                 ret = -ENOMEM;
1988                 goto free_rx;
1989         }
1990
1991         /* If congestion control is enabled globally*/
1992         if (td_tx_threshold) {
1993                 dpaa_intf->cgr_tx = rte_zmalloc(NULL,
1994                         sizeof(struct qman_cgr) * MAX_DPAA_CORES,
1995                         MAX_CACHELINE);
1996                 if (!dpaa_intf->cgr_tx) {
1997                         DPAA_PMD_ERR("Failed to alloc mem for cgr_tx\n");
1998                         ret = -ENOMEM;
1999                         goto free_rx;
2000                 }
2001
2002                 ret = qman_alloc_cgrid_range(&cgrid_tx[0], MAX_DPAA_CORES,
2003                                              1, 0);
2004                 if (ret != MAX_DPAA_CORES) {
2005                         DPAA_PMD_WARN("insufficient CGRIDs available");
2006                         ret = -EINVAL;
2007                         goto free_rx;
2008                 }
2009         } else {
2010                 dpaa_intf->cgr_tx = NULL;
2011         }
2012
2013
2014         for (loop = 0; loop < MAX_DPAA_CORES; loop++) {
2015                 if (dpaa_intf->cgr_tx)
2016                         dpaa_intf->cgr_tx[loop].cgrid = cgrid_tx[loop];
2017
2018                 ret = dpaa_tx_queue_init(&dpaa_intf->tx_queues[loop],
2019                         fman_intf,
2020                         dpaa_intf->cgr_tx ? &dpaa_intf->cgr_tx[loop] : NULL);
2021                 if (ret)
2022                         goto free_tx;
2023                 dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf;
2024         }
2025         dpaa_intf->nb_tx_queues = MAX_DPAA_CORES;
2026
2027 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
2028         ret = dpaa_debug_queue_init(&dpaa_intf->debug_queues
2029                         [DPAA_DEBUG_FQ_RX_ERROR], fman_intf->fqid_rx_err);
2030         if (ret) {
2031                 DPAA_PMD_ERR("DPAA RX ERROR queue init failed!");
2032                 goto free_tx;
2033         }
2034         dpaa_intf->debug_queues[DPAA_DEBUG_FQ_RX_ERROR].dpaa_intf = dpaa_intf;
2035         ret = dpaa_debug_queue_init(&dpaa_intf->debug_queues
2036                         [DPAA_DEBUG_FQ_TX_ERROR], fman_intf->fqid_tx_err);
2037         if (ret) {
2038                 DPAA_PMD_ERR("DPAA TX ERROR queue init failed!");
2039                 goto free_tx;
2040         }
2041         dpaa_intf->debug_queues[DPAA_DEBUG_FQ_TX_ERROR].dpaa_intf = dpaa_intf;
2042 #endif
2043
2044         DPAA_PMD_DEBUG("All frame queues created");
2045
2046         /* Get the initial configuration for flow control */
2047         dpaa_fc_set_default(dpaa_intf, fman_intf);
2048
2049         /* reset bpool list, initialize bpool dynamically */
2050         list_for_each_entry_safe(bp, tmp_bp, &cfg->fman_if->bpool_list, node) {
2051                 list_del(&bp->node);
2052                 rte_free(bp);
2053         }
2054
2055         /* Populate ethdev structure */
2056         eth_dev->dev_ops = &dpaa_devops;
2057         eth_dev->rx_queue_count = dpaa_dev_rx_queue_count;
2058         eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
2059         eth_dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
2060
2061         /* Allocate memory for storing MAC addresses */
2062         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr",
2063                 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER, 0);
2064         if (eth_dev->data->mac_addrs == NULL) {
2065                 DPAA_PMD_ERR("Failed to allocate %d bytes needed to "
2066                                                 "store MAC addresses",
2067                                 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER);
2068                 ret = -ENOMEM;
2069                 goto free_tx;
2070         }
2071
2072         /* copy the primary mac address */
2073         rte_ether_addr_copy(&fman_intf->mac_addr, &eth_dev->data->mac_addrs[0]);
2074
2075         RTE_LOG(INFO, PMD, "net: dpaa: %s: %02x:%02x:%02x:%02x:%02x:%02x\n",
2076                 dpaa_device->name,
2077                 fman_intf->mac_addr.addr_bytes[0],
2078                 fman_intf->mac_addr.addr_bytes[1],
2079                 fman_intf->mac_addr.addr_bytes[2],
2080                 fman_intf->mac_addr.addr_bytes[3],
2081                 fman_intf->mac_addr.addr_bytes[4],
2082                 fman_intf->mac_addr.addr_bytes[5]);
2083
2084         if (!fman_intf->is_shared_mac) {
2085                 /* Configure error packet handling */
2086                 fman_if_receive_rx_errors(fman_intf,
2087                         FM_FD_RX_STATUS_ERR_MASK);
2088                 /* Disable RX mode */
2089                 fman_if_disable_rx(fman_intf);
2090                 /* Disable promiscuous mode */
2091                 fman_if_promiscuous_disable(fman_intf);
2092                 /* Disable multicast */
2093                 fman_if_reset_mcast_filter_table(fman_intf);
2094                 /* Reset interface statistics */
2095                 fman_if_stats_reset(fman_intf);
2096                 /* Disable SG by default */
2097                 fman_if_set_sg(fman_intf, 0);
2098                 fman_if_set_maxfrm(fman_intf,
2099                                    RTE_ETHER_MAX_LEN + VLAN_TAG_SIZE);
2100         }
2101
2102         return 0;
2103
2104 free_tx:
2105         rte_free(dpaa_intf->tx_queues);
2106         dpaa_intf->tx_queues = NULL;
2107         dpaa_intf->nb_tx_queues = 0;
2108
2109 free_rx:
2110         rte_free(dpaa_intf->cgr_rx);
2111         rte_free(dpaa_intf->cgr_tx);
2112         rte_free(dpaa_intf->rx_queues);
2113         dpaa_intf->rx_queues = NULL;
2114         dpaa_intf->nb_rx_queues = 0;
2115         return ret;
2116 }
2117
2118 static int
2119 rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv,
2120                struct rte_dpaa_device *dpaa_dev)
2121 {
2122         int diag;
2123         int ret;
2124         struct rte_eth_dev *eth_dev;
2125
2126         PMD_INIT_FUNC_TRACE();
2127
2128         if ((DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE) >
2129                 RTE_PKTMBUF_HEADROOM) {
2130                 DPAA_PMD_ERR(
2131                 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA Annotation req(%d)",
2132                 RTE_PKTMBUF_HEADROOM,
2133                 DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE);
2134
2135                 return -1;
2136         }
2137
2138         /* In case of secondary process, the device is already configured
2139          * and no further action is required, except portal initialization
2140          * and verifying secondary attachment to port name.
2141          */
2142         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2143                 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name);
2144                 if (!eth_dev)
2145                         return -ENOMEM;
2146                 eth_dev->device = &dpaa_dev->device;
2147                 eth_dev->dev_ops = &dpaa_devops;
2148
2149                 ret = dpaa_dev_init_secondary(eth_dev);
2150                 if (ret != 0) {
2151                         RTE_LOG(ERR, PMD, "secondary dev init failed\n");
2152                         return ret;
2153                 }
2154
2155                 rte_eth_dev_probing_finish(eth_dev);
2156                 return 0;
2157         }
2158
2159         if (!is_global_init && (rte_eal_process_type() == RTE_PROC_PRIMARY)) {
2160                 if (access("/tmp/fmc.bin", F_OK) == -1) {
2161                         DPAA_PMD_INFO("* FMC not configured.Enabling default mode");
2162                         default_q = 1;
2163                 }
2164
2165                 if (!(default_q || fmc_q)) {
2166                         if (dpaa_fm_init()) {
2167                                 DPAA_PMD_ERR("FM init failed\n");
2168                                 return -1;
2169                         }
2170                 }
2171
2172                 /* disabling the default push mode for LS1043 */
2173                 if (dpaa_svr_family == SVR_LS1043A_FAMILY)
2174                         dpaa_push_mode_max_queue = 0;
2175
2176                 /* if push mode queues to be enabled. Currenly we are allowing
2177                  * only one queue per thread.
2178                  */
2179                 if (getenv("DPAA_PUSH_QUEUES_NUMBER")) {
2180                         dpaa_push_mode_max_queue =
2181                                         atoi(getenv("DPAA_PUSH_QUEUES_NUMBER"));
2182                         if (dpaa_push_mode_max_queue > DPAA_MAX_PUSH_MODE_QUEUE)
2183                             dpaa_push_mode_max_queue = DPAA_MAX_PUSH_MODE_QUEUE;
2184                 }
2185
2186                 is_global_init = 1;
2187         }
2188
2189         if (unlikely(!DPAA_PER_LCORE_PORTAL)) {
2190                 ret = rte_dpaa_portal_init((void *)1);
2191                 if (ret) {
2192                         DPAA_PMD_ERR("Unable to initialize portal");
2193                         return ret;
2194                 }
2195         }
2196
2197         eth_dev = rte_eth_dev_allocate(dpaa_dev->name);
2198         if (!eth_dev)
2199                 return -ENOMEM;
2200
2201         eth_dev->data->dev_private =
2202                         rte_zmalloc("ethdev private structure",
2203                                         sizeof(struct dpaa_if),
2204                                         RTE_CACHE_LINE_SIZE);
2205         if (!eth_dev->data->dev_private) {
2206                 DPAA_PMD_ERR("Cannot allocate memzone for port data");
2207                 rte_eth_dev_release_port(eth_dev);
2208                 return -ENOMEM;
2209         }
2210
2211         eth_dev->device = &dpaa_dev->device;
2212         dpaa_dev->eth_dev = eth_dev;
2213
2214         qman_ern_register_cb(dpaa_free_mbuf);
2215
2216         if (dpaa_drv->drv_flags & RTE_DPAA_DRV_INTR_LSC)
2217                 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;
2218
2219         /* Invoke PMD device initialization function */
2220         diag = dpaa_dev_init(eth_dev);
2221         if (diag == 0) {
2222                 rte_eth_dev_probing_finish(eth_dev);
2223                 return 0;
2224         }
2225
2226         rte_eth_dev_release_port(eth_dev);
2227         return diag;
2228 }
2229
2230 static int
2231 rte_dpaa_remove(struct rte_dpaa_device *dpaa_dev)
2232 {
2233         struct rte_eth_dev *eth_dev;
2234         int ret;
2235
2236         PMD_INIT_FUNC_TRACE();
2237
2238         eth_dev = dpaa_dev->eth_dev;
2239         dpaa_eth_dev_close(eth_dev);
2240         ret = rte_eth_dev_release_port(eth_dev);
2241
2242         return ret;
2243 }
2244
2245 static void __attribute__((destructor(102))) dpaa_finish(void)
2246 {
2247         /* For secondary, primary will do all the cleanup */
2248         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2249                 return;
2250
2251         if (!(default_q || fmc_q)) {
2252                 unsigned int i;
2253
2254                 for (i = 0; i < RTE_MAX_ETHPORTS; i++) {
2255                         if (rte_eth_devices[i].dev_ops == &dpaa_devops) {
2256                                 struct rte_eth_dev *dev = &rte_eth_devices[i];
2257                                 struct dpaa_if *dpaa_intf =
2258                                         dev->data->dev_private;
2259                                 struct fman_if *fif =
2260                                         dev->process_private;
2261                                 if (dpaa_intf->port_handle)
2262                                         if (dpaa_fm_deconfig(dpaa_intf, fif))
2263                                                 DPAA_PMD_WARN("DPAA FM "
2264                                                         "deconfig failed\n");
2265                                 if (fif->num_profiles) {
2266                                         if (dpaa_port_vsp_cleanup(dpaa_intf,
2267                                                                   fif))
2268                                                 DPAA_PMD_WARN("DPAA FM vsp cleanup failed\n");
2269                                 }
2270                         }
2271                 }
2272                 if (is_global_init)
2273                         if (dpaa_fm_term())
2274                                 DPAA_PMD_WARN("DPAA FM term failed\n");
2275
2276                 is_global_init = 0;
2277
2278                 DPAA_PMD_INFO("DPAA fman cleaned up");
2279         }
2280 }
2281
2282 static struct rte_dpaa_driver rte_dpaa_pmd = {
2283         .drv_flags = RTE_DPAA_DRV_INTR_LSC,
2284         .drv_type = FSL_DPAA_ETH,
2285         .probe = rte_dpaa_probe,
2286         .remove = rte_dpaa_remove,
2287 };
2288
2289 RTE_PMD_REGISTER_DPAA(net_dpaa, rte_dpaa_pmd);
2290 RTE_LOG_REGISTER(dpaa_logtype_pmd, pmd.net.dpaa, NOTICE);