drivers/net/dpaa/dpaa_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  *   Copyright 2016 Freescale Semiconductor, Inc. All rights reserved.
   4  *   Copyright 2017 NXP
   5  *
   6  */
   7 /* System headers */
   8 #include <stdio.h>
   9 #include <inttypes.h>
  10 #include <unistd.h>
  11 #include <limits.h>
  12 #include <sched.h>
  13 #include <signal.h>
  14 #include <pthread.h>
  15 #include <sys/types.h>
  16 #include <sys/syscall.h>
  17
  18 #include <rte_string_fns.h>
  19 #include <rte_byteorder.h>
  20 #include <rte_common.h>
  21 #include <rte_interrupts.h>
  22 #include <rte_log.h>
  23 #include <rte_debug.h>
  24 #include <rte_pci.h>
  25 #include <rte_atomic.h>
  26 #include <rte_branch_prediction.h>
  27 #include <rte_memory.h>
  28 #include <rte_tailq.h>
  29 #include <rte_eal.h>
  30 #include <rte_alarm.h>
  31 #include <rte_ether.h>
  32 #include <rte_ethdev_driver.h>
  33 #include <rte_malloc.h>
  34 #include <rte_ring.h>
  35
  36 #include <rte_dpaa_bus.h>
  37 #include <rte_dpaa_logs.h>
  38 #include <dpaa_mempool.h>
  39
  40 #include <dpaa_ethdev.h>
  41 #include <dpaa_rxtx.h>
  42 #include <rte_pmd_dpaa.h>
  43
  44 #include <fsl_usd.h>
  45 #include <fsl_qman.h>
  46 #include <fsl_bman.h>
  47 #include <fsl_fman.h>
  48
  49 /* Supported Rx offloads */
  50 static uint64_t dev_rx_offloads_sup =
  51                 DEV_RX_OFFLOAD_JUMBO_FRAME |
  52                 DEV_RX_OFFLOAD_SCATTER;
  53
  54 /* Rx offloads which cannot be disabled */
  55 static uint64_t dev_rx_offloads_nodis =
  56                 DEV_RX_OFFLOAD_IPV4_CKSUM |
  57                 DEV_RX_OFFLOAD_UDP_CKSUM |
  58                 DEV_RX_OFFLOAD_TCP_CKSUM |
  59                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
  60
  61 /* Supported Tx offloads */
  62 static uint64_t dev_tx_offloads_sup;
  63
  64 /* Tx offloads which cannot be disabled */
  65 static uint64_t dev_tx_offloads_nodis =
  66                 DEV_TX_OFFLOAD_IPV4_CKSUM |
  67                 DEV_TX_OFFLOAD_UDP_CKSUM |
  68                 DEV_TX_OFFLOAD_TCP_CKSUM |
  69                 DEV_TX_OFFLOAD_SCTP_CKSUM |
  70                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
  71                 DEV_TX_OFFLOAD_MULTI_SEGS |
  72                 DEV_TX_OFFLOAD_MT_LOCKFREE |
  73                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
  74
  75 /* Keep track of whether QMAN and BMAN have been globally initialized */
  76 static int is_global_init;
  77 static int default_q;   /* use default queue - FMC is not executed*/
  78 /* At present we only allow up to 4 push mode queues as default - as each of
  79  * this queue need dedicated portal and we are short of portals.
  80  */
  81 #define DPAA_MAX_PUSH_MODE_QUEUE       8
  82 #define DPAA_DEFAULT_PUSH_MODE_QUEUE   4
  83
  84 static int dpaa_push_mode_max_queue = DPAA_DEFAULT_PUSH_MODE_QUEUE;
  85 static int dpaa_push_queue_idx; /* Queue index which are in push mode*/
  86
  87
  88 /* Per FQ Taildrop in frame count */
  89 static unsigned int td_threshold = CGR_RX_PERFQ_THRESH;
  90
  91 struct rte_dpaa_xstats_name_off {
  92         char name[RTE_ETH_XSTATS_NAME_SIZE];
  93         uint32_t offset;
  94 };
  95
  96 static const struct rte_dpaa_xstats_name_off dpaa_xstats_strings[] = {
  97         {"rx_align_err",
  98                 offsetof(struct dpaa_if_stats, raln)},
  99         {"rx_valid_pause",
 100                 offsetof(struct dpaa_if_stats, rxpf)},
 101         {"rx_fcs_err",
 102                 offsetof(struct dpaa_if_stats, rfcs)},
 103         {"rx_vlan_frame",
 104                 offsetof(struct dpaa_if_stats, rvlan)},
 105         {"rx_frame_err",
 106                 offsetof(struct dpaa_if_stats, rerr)},
 107         {"rx_drop_err",
 108                 offsetof(struct dpaa_if_stats, rdrp)},
 109         {"rx_undersized",
 110                 offsetof(struct dpaa_if_stats, rund)},
 111         {"rx_oversize_err",
 112                 offsetof(struct dpaa_if_stats, rovr)},
 113         {"rx_fragment_pkt",
 114                 offsetof(struct dpaa_if_stats, rfrg)},
 115         {"tx_valid_pause",
 116                 offsetof(struct dpaa_if_stats, txpf)},
 117         {"tx_fcs_err",
 118                 offsetof(struct dpaa_if_stats, terr)},
 119         {"tx_vlan_frame",
 120                 offsetof(struct dpaa_if_stats, tvlan)},
 121         {"rx_undersized",
 122                 offsetof(struct dpaa_if_stats, tund)},
 123 };
 124
 125 static struct rte_dpaa_driver rte_dpaa_pmd;
 126
 127 static int
 128 dpaa_eth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info);
 129
 130 static inline void
 131 dpaa_poll_queue_default_config(struct qm_mcc_initfq *opts)
 132 {
 133         memset(opts, 0, sizeof(struct qm_mcc_initfq));
 134         opts->we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
 135         opts->fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | QM_FQCTRL_CTXASTASHING |
 136                            QM_FQCTRL_PREFERINCACHE;
 137         opts->fqd.context_a.stashing.exclusive = 0;
 138         if (dpaa_svr_family != SVR_LS1046A_FAMILY)
 139                 opts->fqd.context_a.stashing.annotation_cl =
 140                                                 DPAA_IF_RX_ANNOTATION_STASH;
 141         opts->fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
 142         opts->fqd.context_a.stashing.context_cl = DPAA_IF_RX_CONTEXT_STASH;
 143 }
 144
 145 static int
 146 dpaa_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 147 {
 148         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 149         uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
 150                                 + VLAN_TAG_SIZE;
 151         uint32_t buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
 152
 153         PMD_INIT_FUNC_TRACE();
 154
 155         if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA_MAX_RX_PKT_LEN)
 156                 return -EINVAL;
 157         /*
 158          * Refuse mtu that requires the support of scattered packets
 159          * when this feature has not been enabled before.
 160          */
 161         if (dev->data->min_rx_buf_size &&
 162                 !dev->data->scattered_rx && frame_size > buffsz) {
 163                 DPAA_PMD_ERR("SG not enabled, will not fit in one buffer");
 164                 return -EINVAL;
 165         }
 166
 167         /* check <seg size> * <max_seg>  >= max_frame */
 168         if (dev->data->min_rx_buf_size && dev->data->scattered_rx &&
 169                 (frame_size > buffsz * DPAA_SGT_MAX_ENTRIES)) {
 170                 DPAA_PMD_ERR("Too big to fit for Max SG list %d",
 171                                 buffsz * DPAA_SGT_MAX_ENTRIES);
 172                 return -EINVAL;
 173         }
 174
 175         if (frame_size > RTE_ETHER_MAX_LEN)
 176                 dev->data->dev_conf.rxmode.offloads &=
 177                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 178         else
 179                 dev->data->dev_conf.rxmode.offloads &=
 180                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 181
 182         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 183
 184         fman_if_set_maxfrm(dpaa_intf->fif, frame_size);
 185
 186         return 0;
 187 }
 188
 189 static int
 190 dpaa_eth_dev_configure(struct rte_eth_dev *dev)
 191 {
 192         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 193         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 194         uint64_t rx_offloads = eth_conf->rxmode.offloads;
 195         uint64_t tx_offloads = eth_conf->txmode.offloads;
 196
 197         PMD_INIT_FUNC_TRACE();
 198
 199         /* Rx offloads validation */
 200         if (dev_rx_offloads_nodis & ~rx_offloads) {
 201                 DPAA_PMD_WARN(
 202                 "Rx offloads non configurable - requested 0x%" PRIx64
 203                 " ignored 0x%" PRIx64,
 204                         rx_offloads, dev_rx_offloads_nodis);
 205         }
 206
 207         /* Tx offloads validation */
 208         if (dev_tx_offloads_nodis & ~tx_offloads) {
 209                 DPAA_PMD_WARN(
 210                 "Tx offloads non configurable - requested 0x%" PRIx64
 211                 " ignored 0x%" PRIx64,
 212                         tx_offloads, dev_tx_offloads_nodis);
 213         }
 214
 215         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 216                 uint32_t max_len;
 217
 218                 DPAA_PMD_DEBUG("enabling jumbo");
 219
 220                 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <=
 221                     DPAA_MAX_RX_PKT_LEN)
 222                         max_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
 223                 else {
 224                         DPAA_PMD_INFO("enabling jumbo override conf max len=%d "
 225                                 "supported is %d",
 226                                 dev->data->dev_conf.rxmode.max_rx_pkt_len,
 227                                 DPAA_MAX_RX_PKT_LEN);
 228                         max_len = DPAA_MAX_RX_PKT_LEN;
 229                 }
 230
 231                 fman_if_set_maxfrm(dpaa_intf->fif, max_len);
 232                 dev->data->mtu = max_len
 233                         - RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE;
 234         }
 235
 236         if (rx_offloads & DEV_RX_OFFLOAD_SCATTER) {
 237                 DPAA_PMD_DEBUG("enabling scatter mode");
 238                 fman_if_set_sg(dpaa_intf->fif, 1);
 239                 dev->data->scattered_rx = 1;
 240         }
 241
 242         return 0;
 243 }
 244
 245 static const uint32_t *
 246 dpaa_supported_ptypes_get(struct rte_eth_dev *dev)
 247 {
 248         static const uint32_t ptypes[] = {
 249                 RTE_PTYPE_L2_ETHER,
 250                 RTE_PTYPE_L2_ETHER_VLAN,
 251                 RTE_PTYPE_L2_ETHER_ARP,
 252                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
 253                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
 254                 RTE_PTYPE_L4_ICMP,
 255                 RTE_PTYPE_L4_TCP,
 256                 RTE_PTYPE_L4_UDP,
 257                 RTE_PTYPE_L4_FRAG,
 258                 RTE_PTYPE_L4_TCP,
 259                 RTE_PTYPE_L4_UDP,
 260                 RTE_PTYPE_L4_SCTP
 261         };
 262
 263         PMD_INIT_FUNC_TRACE();
 264
 265         if (dev->rx_pkt_burst == dpaa_eth_queue_rx)
 266                 return ptypes;
 267         return NULL;
 268 }
 269
 270 static int dpaa_eth_dev_start(struct rte_eth_dev *dev)
 271 {
 272         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 273
 274         PMD_INIT_FUNC_TRACE();
 275
 276         /* Change tx callback to the real one */
 277         dev->tx_pkt_burst = dpaa_eth_queue_tx;
 278         fman_if_enable_rx(dpaa_intf->fif);
 279
 280         return 0;
 281 }
 282
 283 static void dpaa_eth_dev_stop(struct rte_eth_dev *dev)
 284 {
 285         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 286
 287         PMD_INIT_FUNC_TRACE();
 288
 289         fman_if_disable_rx(dpaa_intf->fif);
 290         dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
 291 }
 292
 293 static void dpaa_eth_dev_close(struct rte_eth_dev *dev)
 294 {
 295         PMD_INIT_FUNC_TRACE();
 296
 297         dpaa_eth_dev_stop(dev);
 298 }
 299
 300 static int
 301 dpaa_fw_version_get(struct rte_eth_dev *dev __rte_unused,
 302                      char *fw_version,
 303                      size_t fw_size)
 304 {
 305         int ret;
 306         FILE *svr_file = NULL;
 307         unsigned int svr_ver = 0;
 308
 309         PMD_INIT_FUNC_TRACE();
 310
 311         svr_file = fopen(DPAA_SOC_ID_FILE, "r");
 312         if (!svr_file) {
 313                 DPAA_PMD_ERR("Unable to open SoC device");
 314                 return -ENOTSUP; /* Not supported on this infra */
 315         }
 316         if (fscanf(svr_file, "svr:%x", &svr_ver) > 0)
 317                 dpaa_svr_family = svr_ver & SVR_MASK;
 318         else
 319                 DPAA_PMD_ERR("Unable to read SoC device");
 320
 321         fclose(svr_file);
 322
 323         ret = snprintf(fw_version, fw_size, "SVR:%x-fman-v%x",
 324                        svr_ver, fman_ip_rev);
 325         ret += 1; /* add the size of '\0' */
 326
 327         if (fw_size < (uint32_t)ret)
 328                 return ret;
 329         else
 330                 return 0;
 331 }
 332
 333 static int dpaa_eth_dev_info(struct rte_eth_dev *dev,
 334                              struct rte_eth_dev_info *dev_info)
 335 {
 336         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 337
 338         PMD_INIT_FUNC_TRACE();
 339
 340         dev_info->max_rx_queues = dpaa_intf->nb_rx_queues;
 341         dev_info->max_tx_queues = dpaa_intf->nb_tx_queues;
 342         dev_info->max_rx_pktlen = DPAA_MAX_RX_PKT_LEN;
 343         dev_info->max_mac_addrs = DPAA_MAX_MAC_FILTER;
 344         dev_info->max_hash_mac_addrs = 0;
 345         dev_info->max_vfs = 0;
 346         dev_info->max_vmdq_pools = ETH_16_POOLS;
 347         dev_info->flow_type_rss_offloads = DPAA_RSS_OFFLOAD_ALL;
 348
 349         if (dpaa_intf->fif->mac_type == fman_mac_1g) {
 350                 dev_info->speed_capa = ETH_LINK_SPEED_1G;
 351         } else if (dpaa_intf->fif->mac_type == fman_mac_10g) {
 352                 dev_info->speed_capa = (ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G);
 353         } else {
 354                 DPAA_PMD_ERR("invalid link_speed: %s, %d",
 355                              dpaa_intf->name, dpaa_intf->fif->mac_type);
 356                 return -EINVAL;
 357         }
 358
 359         dev_info->rx_offload_capa = dev_rx_offloads_sup |
 360                                         dev_rx_offloads_nodis;
 361         dev_info->tx_offload_capa = dev_tx_offloads_sup |
 362                                         dev_tx_offloads_nodis;
 363         dev_info->default_rxportconf.burst_size = DPAA_DEF_RX_BURST_SIZE;
 364         dev_info->default_txportconf.burst_size = DPAA_DEF_TX_BURST_SIZE;
 365
 366         return 0;
 367 }
 368
 369 static int dpaa_eth_link_update(struct rte_eth_dev *dev,
 370                                 int wait_to_complete __rte_unused)
 371 {
 372         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 373         struct rte_eth_link *link = &dev->data->dev_link;
 374
 375         PMD_INIT_FUNC_TRACE();
 376
 377         if (dpaa_intf->fif->mac_type == fman_mac_1g)
 378                 link->link_speed = ETH_SPEED_NUM_1G;
 379         else if (dpaa_intf->fif->mac_type == fman_mac_10g)
 380                 link->link_speed = ETH_SPEED_NUM_10G;
 381         else
 382                 DPAA_PMD_ERR("invalid link_speed: %s, %d",
 383                              dpaa_intf->name, dpaa_intf->fif->mac_type);
 384
 385         link->link_status = dpaa_intf->valid;
 386         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 387         link->link_autoneg = ETH_LINK_AUTONEG;
 388         return 0;
 389 }
 390
 391 static int dpaa_eth_stats_get(struct rte_eth_dev *dev,
 392                                struct rte_eth_stats *stats)
 393 {
 394         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 395
 396         PMD_INIT_FUNC_TRACE();
 397
 398         fman_if_stats_get(dpaa_intf->fif, stats);
 399         return 0;
 400 }
 401
 402 static int dpaa_eth_stats_reset(struct rte_eth_dev *dev)
 403 {
 404         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 405
 406         PMD_INIT_FUNC_TRACE();
 407
 408         fman_if_stats_reset(dpaa_intf->fif);
 409
 410         return 0;
 411 }
 412
 413 static int
 414 dpaa_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
 415                     unsigned int n)
 416 {
 417         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 418         unsigned int i = 0, num = RTE_DIM(dpaa_xstats_strings);
 419         uint64_t values[sizeof(struct dpaa_if_stats) / 8];
 420
 421         if (n < num)
 422                 return num;
 423
 424         if (xstats == NULL)
 425                 return 0;
 426
 427         fman_if_stats_get_all(dpaa_intf->fif, values,
 428                               sizeof(struct dpaa_if_stats) / 8);
 429
 430         for (i = 0; i < num; i++) {
 431                 xstats[i].id = i;
 432                 xstats[i].value = values[dpaa_xstats_strings[i].offset / 8];
 433         }
 434         return i;
 435 }
 436
 437 static int
 438 dpaa_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 439                       struct rte_eth_xstat_name *xstats_names,
 440                       unsigned int limit)
 441 {
 442         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 443
 444         if (limit < stat_cnt)
 445                 return stat_cnt;
 446
 447         if (xstats_names != NULL)
 448                 for (i = 0; i < stat_cnt; i++)
 449                         strlcpy(xstats_names[i].name,
 450                                 dpaa_xstats_strings[i].name,
 451                                 sizeof(xstats_names[i].name));
 452
 453         return stat_cnt;
 454 }
 455
 456 static int
 457 dpaa_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 458                       uint64_t *values, unsigned int n)
 459 {
 460         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 461         uint64_t values_copy[sizeof(struct dpaa_if_stats) / 8];
 462
 463         if (!ids) {
 464                 struct dpaa_if *dpaa_intf = dev->data->dev_private;
 465
 466                 if (n < stat_cnt)
 467                         return stat_cnt;
 468
 469                 if (!values)
 470                         return 0;
 471
 472                 fman_if_stats_get_all(dpaa_intf->fif, values_copy,
 473                                       sizeof(struct dpaa_if_stats) / 8);
 474
 475                 for (i = 0; i < stat_cnt; i++)
 476                         values[i] =
 477                                 values_copy[dpaa_xstats_strings[i].offset / 8];
 478
 479                 return stat_cnt;
 480         }
 481
 482         dpaa_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
 483
 484         for (i = 0; i < n; i++) {
 485                 if (ids[i] >= stat_cnt) {
 486                         DPAA_PMD_ERR("id value isn't valid");
 487                         return -1;
 488                 }
 489                 values[i] = values_copy[ids[i]];
 490         }
 491         return n;
 492 }
 493
 494 static int
 495 dpaa_xstats_get_names_by_id(
 496         struct rte_eth_dev *dev,
 497         struct rte_eth_xstat_name *xstats_names,
 498         const uint64_t *ids,
 499         unsigned int limit)
 500 {
 501         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 502         struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
 503
 504         if (!ids)
 505                 return dpaa_xstats_get_names(dev, xstats_names, limit);
 506
 507         dpaa_xstats_get_names(dev, xstats_names_copy, limit);
 508
 509         for (i = 0; i < limit; i++) {
 510                 if (ids[i] >= stat_cnt) {
 511                         DPAA_PMD_ERR("id value isn't valid");
 512                         return -1;
 513                 }
 514                 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
 515         }
 516         return limit;
 517 }
 518
 519 static int dpaa_eth_promiscuous_enable(struct rte_eth_dev *dev)
 520 {
 521         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 522
 523         PMD_INIT_FUNC_TRACE();
 524
 525         fman_if_promiscuous_enable(dpaa_intf->fif);
 526
 527         return 0;
 528 }
 529
 530 static int dpaa_eth_promiscuous_disable(struct rte_eth_dev *dev)
 531 {
 532         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 533
 534         PMD_INIT_FUNC_TRACE();
 535
 536         fman_if_promiscuous_disable(dpaa_intf->fif);
 537
 538         return 0;
 539 }
 540
 541 static void dpaa_eth_multicast_enable(struct rte_eth_dev *dev)
 542 {
 543         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 544
 545         PMD_INIT_FUNC_TRACE();
 546
 547         fman_if_set_mcast_filter_table(dpaa_intf->fif);
 548 }
 549
 550 static void dpaa_eth_multicast_disable(struct rte_eth_dev *dev)
 551 {
 552         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 553
 554         PMD_INIT_FUNC_TRACE();
 555
 556         fman_if_reset_mcast_filter_table(dpaa_intf->fif);
 557 }
 558
 559 static
 560 int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 561                             uint16_t nb_desc,
 562                             unsigned int socket_id __rte_unused,
 563                             const struct rte_eth_rxconf *rx_conf __rte_unused,
 564                             struct rte_mempool *mp)
 565 {
 566         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 567         struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_idx];
 568         struct qm_mcc_initfq opts = {0};
 569         u32 flags = 0;
 570         int ret;
 571         u32 buffsz = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
 572
 573         PMD_INIT_FUNC_TRACE();
 574
 575         if (queue_idx >= dev->data->nb_rx_queues) {
 576                 rte_errno = EOVERFLOW;
 577                 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
 578                       (void *)dev, queue_idx, dev->data->nb_rx_queues);
 579                 return -rte_errno;
 580         }
 581
 582         DPAA_PMD_INFO("Rx queue setup for queue index: %d fq_id (0x%x)",
 583                         queue_idx, rxq->fqid);
 584
 585         /* Max packet can fit in single buffer */
 586         if (dev->data->dev_conf.rxmode.max_rx_pkt_len <= buffsz) {
 587                 ;
 588         } else if (dev->data->dev_conf.rxmode.offloads &
 589                         DEV_RX_OFFLOAD_SCATTER) {
 590                 if (dev->data->dev_conf.rxmode.max_rx_pkt_len >
 591                         buffsz * DPAA_SGT_MAX_ENTRIES) {
 592                         DPAA_PMD_ERR("max RxPkt size %d too big to fit "
 593                                 "MaxSGlist %d",
 594                                 dev->data->dev_conf.rxmode.max_rx_pkt_len,
 595                                 buffsz * DPAA_SGT_MAX_ENTRIES);
 596                         rte_errno = EOVERFLOW;
 597                         return -rte_errno;
 598                 }
 599         } else {
 600                 DPAA_PMD_WARN("The requested maximum Rx packet size (%u) is"
 601                      " larger than a single mbuf (%u) and scattered"
 602                      " mode has not been requested",
 603                      dev->data->dev_conf.rxmode.max_rx_pkt_len,
 604                      buffsz - RTE_PKTMBUF_HEADROOM);
 605         }
 606
 607         if (!dpaa_intf->bp_info || dpaa_intf->bp_info->mp != mp) {
 608                 struct fman_if_ic_params icp;
 609                 uint32_t fd_offset;
 610                 uint32_t bp_size;
 611
 612                 if (!mp->pool_data) {
 613                         DPAA_PMD_ERR("Not an offloaded buffer pool!");
 614                         return -1;
 615                 }
 616                 dpaa_intf->bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp);
 617
 618                 memset(&icp, 0, sizeof(icp));
 619                 /* set ICEOF for to the default value , which is 0*/
 620                 icp.iciof = DEFAULT_ICIOF;
 621                 icp.iceof = DEFAULT_RX_ICEOF;
 622                 icp.icsz = DEFAULT_ICSZ;
 623                 fman_if_set_ic_params(dpaa_intf->fif, &icp);
 624
 625                 fd_offset = RTE_PKTMBUF_HEADROOM + DPAA_HW_BUF_RESERVE;
 626                 fman_if_set_fdoff(dpaa_intf->fif, fd_offset);
 627
 628                 /* Buffer pool size should be equal to Dataroom Size*/
 629                 bp_size = rte_pktmbuf_data_room_size(mp);
 630                 fman_if_set_bp(dpaa_intf->fif, mp->size,
 631                                dpaa_intf->bp_info->bpid, bp_size);
 632                 dpaa_intf->valid = 1;
 633                 DPAA_PMD_DEBUG("if:%s fd_offset = %d offset = %d",
 634                                 dpaa_intf->name, fd_offset,
 635                                 fman_if_get_fdoff(dpaa_intf->fif));
 636         }
 637         DPAA_PMD_DEBUG("if:%s sg_on = %d, max_frm =%d", dpaa_intf->name,
 638                 fman_if_get_sg_enable(dpaa_intf->fif),
 639                 dev->data->dev_conf.rxmode.max_rx_pkt_len);
 640         /* checking if push mode only, no error check for now */
 641         if (dpaa_push_mode_max_queue > dpaa_push_queue_idx) {
 642                 dpaa_push_queue_idx++;
 643                 opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
 644                 opts.fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK |
 645                                    QM_FQCTRL_CTXASTASHING |
 646                                    QM_FQCTRL_PREFERINCACHE;
 647                 opts.fqd.context_a.stashing.exclusive = 0;
 648                 /* In muticore scenario stashing becomes a bottleneck on LS1046.
 649                  * So do not enable stashing in this case
 650                  */
 651                 if (dpaa_svr_family != SVR_LS1046A_FAMILY)
 652                         opts.fqd.context_a.stashing.annotation_cl =
 653                                                 DPAA_IF_RX_ANNOTATION_STASH;
 654                 opts.fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
 655                 opts.fqd.context_a.stashing.context_cl =
 656                                                 DPAA_IF_RX_CONTEXT_STASH;
 657
 658                 /*Create a channel and associate given queue with the channel*/
 659                 qman_alloc_pool_range((u32 *)&rxq->ch_id, 1, 1, 0);
 660                 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
 661                 opts.fqd.dest.channel = rxq->ch_id;
 662                 opts.fqd.dest.wq = DPAA_IF_RX_PRIORITY;
 663                 flags = QMAN_INITFQ_FLAG_SCHED;
 664
 665                 /* Configure tail drop */
 666                 if (dpaa_intf->cgr_rx) {
 667                         opts.we_mask |= QM_INITFQ_WE_CGID;
 668                         opts.fqd.cgid = dpaa_intf->cgr_rx[queue_idx].cgrid;
 669                         opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
 670                 }
 671                 ret = qman_init_fq(rxq, flags, &opts);
 672                 if (ret) {
 673                         DPAA_PMD_ERR("Channel/Q association failed. fqid 0x%x "
 674                                 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
 675                         return ret;
 676                 }
 677                 if (dpaa_svr_family == SVR_LS1043A_FAMILY) {
 678                         rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb_no_prefetch;
 679                 } else {
 680                         rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb;
 681                         rxq->cb.dqrr_prepare = dpaa_rx_cb_prepare;
 682                 }
 683
 684                 rxq->is_static = true;
 685         }
 686         rxq->bp_array = rte_dpaa_bpid_info;
 687         dev->data->rx_queues[queue_idx] = rxq;
 688
 689         /* configure the CGR size as per the desc size */
 690         if (dpaa_intf->cgr_rx) {
 691                 struct qm_mcc_initcgr cgr_opts = {0};
 692
 693                 /* Enable tail drop with cgr on this queue */
 694                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, nb_desc, 0);
 695                 ret = qman_modify_cgr(dpaa_intf->cgr_rx, 0, &cgr_opts);
 696                 if (ret) {
 697                         DPAA_PMD_WARN(
 698                                 "rx taildrop modify fail on fqid %d (ret=%d)",
 699                                 rxq->fqid, ret);
 700                 }
 701         }
 702
 703         return 0;
 704 }
 705
 706 int
 707 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev,
 708                 int eth_rx_queue_id,
 709                 u16 ch_id,
 710                 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
 711 {
 712         int ret;
 713         u32 flags = 0;
 714         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 715         struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
 716         struct qm_mcc_initfq opts = {0};
 717
 718         if (dpaa_push_mode_max_queue)
 719                 DPAA_PMD_WARN("PUSH mode q and EVENTDEV are not compatible\n"
 720                               "PUSH mode already enabled for first %d queues.\n"
 721                               "To disable set DPAA_PUSH_QUEUES_NUMBER to 0\n",
 722                               dpaa_push_mode_max_queue);
 723
 724         dpaa_poll_queue_default_config(&opts);
 725
 726         switch (queue_conf->ev.sched_type) {
 727         case RTE_SCHED_TYPE_ATOMIC:
 728                 opts.fqd.fq_ctrl |= QM_FQCTRL_HOLDACTIVE;
 729                 /* Reset FQCTRL_AVOIDBLOCK bit as it is unnecessary
 730                  * configuration with HOLD_ACTIVE setting
 731                  */
 732                 opts.fqd.fq_ctrl &= (~QM_FQCTRL_AVOIDBLOCK);
 733                 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_atomic;
 734                 break;
 735         case RTE_SCHED_TYPE_ORDERED:
 736                 DPAA_PMD_ERR("Ordered queue schedule type is not supported\n");
 737                 return -1;
 738         default:
 739                 opts.fqd.fq_ctrl |= QM_FQCTRL_AVOIDBLOCK;
 740                 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_parallel;
 741                 break;
 742         }
 743
 744         opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
 745         opts.fqd.dest.channel = ch_id;
 746         opts.fqd.dest.wq = queue_conf->ev.priority;
 747
 748         if (dpaa_intf->cgr_rx) {
 749                 opts.we_mask |= QM_INITFQ_WE_CGID;
 750                 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
 751                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
 752         }
 753
 754         flags = QMAN_INITFQ_FLAG_SCHED;
 755
 756         ret = qman_init_fq(rxq, flags, &opts);
 757         if (ret) {
 758                 DPAA_PMD_ERR("Ev-Channel/Q association failed. fqid 0x%x "
 759                                 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
 760                 return ret;
 761         }
 762
 763         /* copy configuration which needs to be filled during dequeue */
 764         memcpy(&rxq->ev, &queue_conf->ev, sizeof(struct rte_event));
 765         dev->data->rx_queues[eth_rx_queue_id] = rxq;
 766
 767         return ret;
 768 }
 769
 770 int
 771 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev,
 772                 int eth_rx_queue_id)
 773 {
 774         struct qm_mcc_initfq opts;
 775         int ret;
 776         u32 flags = 0;
 777         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 778         struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
 779
 780         dpaa_poll_queue_default_config(&opts);
 781
 782         if (dpaa_intf->cgr_rx) {
 783                 opts.we_mask |= QM_INITFQ_WE_CGID;
 784                 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
 785                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
 786         }
 787
 788         ret = qman_init_fq(rxq, flags, &opts);
 789         if (ret) {
 790                 DPAA_PMD_ERR("init rx fqid %d failed with ret: %d",
 791                              rxq->fqid, ret);
 792         }
 793
 794         rxq->cb.dqrr_dpdk_cb = NULL;
 795         dev->data->rx_queues[eth_rx_queue_id] = NULL;
 796
 797         return 0;
 798 }
 799
 800 static
 801 void dpaa_eth_rx_queue_release(void *rxq __rte_unused)
 802 {
 803         PMD_INIT_FUNC_TRACE();
 804 }
 805
 806 static
 807 int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 808                             uint16_t nb_desc __rte_unused,
 809                 unsigned int socket_id __rte_unused,
 810                 const struct rte_eth_txconf *tx_conf __rte_unused)
 811 {
 812         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 813
 814         PMD_INIT_FUNC_TRACE();
 815
 816         if (queue_idx >= dev->data->nb_tx_queues) {
 817                 rte_errno = EOVERFLOW;
 818                 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
 819                       (void *)dev, queue_idx, dev->data->nb_tx_queues);
 820                 return -rte_errno;
 821         }
 822
 823         DPAA_PMD_INFO("Tx queue setup for queue index: %d fq_id (0x%x)",
 824                         queue_idx, dpaa_intf->tx_queues[queue_idx].fqid);
 825         dev->data->tx_queues[queue_idx] = &dpaa_intf->tx_queues[queue_idx];
 826         return 0;
 827 }
 828
 829 static void dpaa_eth_tx_queue_release(void *txq __rte_unused)
 830 {
 831         PMD_INIT_FUNC_TRACE();
 832 }
 833
 834 static uint32_t
 835 dpaa_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 836 {
 837         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 838         struct qman_fq *rxq = &dpaa_intf->rx_queues[rx_queue_id];
 839         u32 frm_cnt = 0;
 840
 841         PMD_INIT_FUNC_TRACE();
 842
 843         if (qman_query_fq_frm_cnt(rxq, &frm_cnt) == 0) {
 844                 RTE_LOG(DEBUG, PMD, "RX frame count for q(%d) is %u\n",
 845                         rx_queue_id, frm_cnt);
 846         }
 847         return frm_cnt;
 848 }
 849
 850 static int dpaa_link_down(struct rte_eth_dev *dev)
 851 {
 852         PMD_INIT_FUNC_TRACE();
 853
 854         dpaa_eth_dev_stop(dev);
 855         return 0;
 856 }
 857
 858 static int dpaa_link_up(struct rte_eth_dev *dev)
 859 {
 860         PMD_INIT_FUNC_TRACE();
 861
 862         dpaa_eth_dev_start(dev);
 863         return 0;
 864 }
 865
 866 static int
 867 dpaa_flow_ctrl_set(struct rte_eth_dev *dev,
 868                    struct rte_eth_fc_conf *fc_conf)
 869 {
 870         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 871         struct rte_eth_fc_conf *net_fc;
 872
 873         PMD_INIT_FUNC_TRACE();
 874
 875         if (!(dpaa_intf->fc_conf)) {
 876                 dpaa_intf->fc_conf = rte_zmalloc(NULL,
 877                         sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
 878                 if (!dpaa_intf->fc_conf) {
 879                         DPAA_PMD_ERR("unable to save flow control info");
 880                         return -ENOMEM;
 881                 }
 882         }
 883         net_fc = dpaa_intf->fc_conf;
 884
 885         if (fc_conf->high_water < fc_conf->low_water) {
 886                 DPAA_PMD_ERR("Incorrect Flow Control Configuration");
 887                 return -EINVAL;
 888         }
 889
 890         if (fc_conf->mode == RTE_FC_NONE) {
 891                 return 0;
 892         } else if (fc_conf->mode == RTE_FC_TX_PAUSE ||
 893                  fc_conf->mode == RTE_FC_FULL) {
 894                 fman_if_set_fc_threshold(dpaa_intf->fif, fc_conf->high_water,
 895                                          fc_conf->low_water,
 896                                 dpaa_intf->bp_info->bpid);
 897                 if (fc_conf->pause_time)
 898                         fman_if_set_fc_quanta(dpaa_intf->fif,
 899                                               fc_conf->pause_time);
 900         }
 901
 902         /* Save the information in dpaa device */
 903         net_fc->pause_time = fc_conf->pause_time;
 904         net_fc->high_water = fc_conf->high_water;
 905         net_fc->low_water = fc_conf->low_water;
 906         net_fc->send_xon = fc_conf->send_xon;
 907         net_fc->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
 908         net_fc->mode = fc_conf->mode;
 909         net_fc->autoneg = fc_conf->autoneg;
 910
 911         return 0;
 912 }
 913
 914 static int
 915 dpaa_flow_ctrl_get(struct rte_eth_dev *dev,
 916                    struct rte_eth_fc_conf *fc_conf)
 917 {
 918         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 919         struct rte_eth_fc_conf *net_fc = dpaa_intf->fc_conf;
 920         int ret;
 921
 922         PMD_INIT_FUNC_TRACE();
 923
 924         if (net_fc) {
 925                 fc_conf->pause_time = net_fc->pause_time;
 926                 fc_conf->high_water = net_fc->high_water;
 927                 fc_conf->low_water = net_fc->low_water;
 928                 fc_conf->send_xon = net_fc->send_xon;
 929                 fc_conf->mac_ctrl_frame_fwd = net_fc->mac_ctrl_frame_fwd;
 930                 fc_conf->mode = net_fc->mode;
 931                 fc_conf->autoneg = net_fc->autoneg;
 932                 return 0;
 933         }
 934         ret = fman_if_get_fc_threshold(dpaa_intf->fif);
 935         if (ret) {
 936                 fc_conf->mode = RTE_FC_TX_PAUSE;
 937                 fc_conf->pause_time = fman_if_get_fc_quanta(dpaa_intf->fif);
 938         } else {
 939                 fc_conf->mode = RTE_FC_NONE;
 940         }
 941
 942         return 0;
 943 }
 944
 945 static int
 946 dpaa_dev_add_mac_addr(struct rte_eth_dev *dev,
 947                              struct rte_ether_addr *addr,
 948                              uint32_t index,
 949                              __rte_unused uint32_t pool)
 950 {
 951         int ret;
 952         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 953
 954         PMD_INIT_FUNC_TRACE();
 955
 956         ret = fman_if_add_mac_addr(dpaa_intf->fif, addr->addr_bytes, index);
 957
 958         if (ret)
 959                 RTE_LOG(ERR, PMD, "error: Adding the MAC ADDR failed:"
 960                         " err = %d", ret);
 961         return 0;
 962 }
 963
 964 static void
 965 dpaa_dev_remove_mac_addr(struct rte_eth_dev *dev,
 966                           uint32_t index)
 967 {
 968         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 969
 970         PMD_INIT_FUNC_TRACE();
 971
 972         fman_if_clear_mac_addr(dpaa_intf->fif, index);
 973 }
 974
 975 static int
 976 dpaa_dev_set_mac_addr(struct rte_eth_dev *dev,
 977                        struct rte_ether_addr *addr)
 978 {
 979         int ret;
 980         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 981
 982         PMD_INIT_FUNC_TRACE();
 983
 984         ret = fman_if_add_mac_addr(dpaa_intf->fif, addr->addr_bytes, 0);
 985         if (ret)
 986                 RTE_LOG(ERR, PMD, "error: Setting the MAC ADDR failed %d", ret);
 987
 988         return ret;
 989 }
 990
 991 static struct eth_dev_ops dpaa_devops = {
 992         .dev_configure            = dpaa_eth_dev_configure,
 993         .dev_start                = dpaa_eth_dev_start,
 994         .dev_stop                 = dpaa_eth_dev_stop,
 995         .dev_close                = dpaa_eth_dev_close,
 996         .dev_infos_get            = dpaa_eth_dev_info,
 997         .dev_supported_ptypes_get = dpaa_supported_ptypes_get,
 998
 999         .rx_queue_setup           = dpaa_eth_rx_queue_setup,
1000         .tx_queue_setup           = dpaa_eth_tx_queue_setup,
1001         .rx_queue_release         = dpaa_eth_rx_queue_release,
1002         .tx_queue_release         = dpaa_eth_tx_queue_release,
1003         .rx_queue_count           = dpaa_dev_rx_queue_count,
1004
1005         .flow_ctrl_get            = dpaa_flow_ctrl_get,
1006         .flow_ctrl_set            = dpaa_flow_ctrl_set,
1007
1008         .link_update              = dpaa_eth_link_update,
1009         .stats_get                = dpaa_eth_stats_get,
1010         .xstats_get               = dpaa_dev_xstats_get,
1011         .xstats_get_by_id         = dpaa_xstats_get_by_id,
1012         .xstats_get_names_by_id   = dpaa_xstats_get_names_by_id,
1013         .xstats_get_names         = dpaa_xstats_get_names,
1014         .xstats_reset             = dpaa_eth_stats_reset,
1015         .stats_reset              = dpaa_eth_stats_reset,
1016         .promiscuous_enable       = dpaa_eth_promiscuous_enable,
1017         .promiscuous_disable      = dpaa_eth_promiscuous_disable,
1018         .allmulticast_enable      = dpaa_eth_multicast_enable,
1019         .allmulticast_disable     = dpaa_eth_multicast_disable,
1020         .mtu_set                  = dpaa_mtu_set,
1021         .dev_set_link_down        = dpaa_link_down,
1022         .dev_set_link_up          = dpaa_link_up,
1023         .mac_addr_add             = dpaa_dev_add_mac_addr,
1024         .mac_addr_remove          = dpaa_dev_remove_mac_addr,
1025         .mac_addr_set             = dpaa_dev_set_mac_addr,
1026
1027         .fw_version_get           = dpaa_fw_version_get,
1028 };
1029
1030 static bool
1031 is_device_supported(struct rte_eth_dev *dev, struct rte_dpaa_driver *drv)
1032 {
1033         if (strcmp(dev->device->driver->name,
1034                    drv->driver.name))
1035                 return false;
1036
1037         return true;
1038 }
1039
1040 static bool
1041 is_dpaa_supported(struct rte_eth_dev *dev)
1042 {
1043         return is_device_supported(dev, &rte_dpaa_pmd);
1044 }
1045
1046 int
1047 rte_pmd_dpaa_set_tx_loopback(uint8_t port, uint8_t on)
1048 {
1049         struct rte_eth_dev *dev;
1050         struct dpaa_if *dpaa_intf;
1051
1052         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
1053
1054         dev = &rte_eth_devices[port];
1055
1056         if (!is_dpaa_supported(dev))
1057                 return -ENOTSUP;
1058
1059         dpaa_intf = dev->data->dev_private;
1060
1061         if (on)
1062                 fman_if_loopback_enable(dpaa_intf->fif);
1063         else
1064                 fman_if_loopback_disable(dpaa_intf->fif);
1065
1066         return 0;
1067 }
1068
1069 static int dpaa_fc_set_default(struct dpaa_if *dpaa_intf)
1070 {
1071         struct rte_eth_fc_conf *fc_conf;
1072         int ret;
1073
1074         PMD_INIT_FUNC_TRACE();
1075
1076         if (!(dpaa_intf->fc_conf)) {
1077                 dpaa_intf->fc_conf = rte_zmalloc(NULL,
1078                         sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
1079                 if (!dpaa_intf->fc_conf) {
1080                         DPAA_PMD_ERR("unable to save flow control info");
1081                         return -ENOMEM;
1082                 }
1083         }
1084         fc_conf = dpaa_intf->fc_conf;
1085         ret = fman_if_get_fc_threshold(dpaa_intf->fif);
1086         if (ret) {
1087                 fc_conf->mode = RTE_FC_TX_PAUSE;
1088                 fc_conf->pause_time = fman_if_get_fc_quanta(dpaa_intf->fif);
1089         } else {
1090                 fc_conf->mode = RTE_FC_NONE;
1091         }
1092
1093         return 0;
1094 }
1095
1096 /* Initialise an Rx FQ */
1097 static int dpaa_rx_queue_init(struct qman_fq *fq, struct qman_cgr *cgr_rx,
1098                               uint32_t fqid)
1099 {
1100         struct qm_mcc_initfq opts = {0};
1101         int ret;
1102         u32 flags = QMAN_FQ_FLAG_NO_ENQUEUE;
1103         struct qm_mcc_initcgr cgr_opts = {
1104                 .we_mask = QM_CGR_WE_CS_THRES |
1105                                 QM_CGR_WE_CSTD_EN |
1106                                 QM_CGR_WE_MODE,
1107                 .cgr = {
1108                         .cstd_en = QM_CGR_EN,
1109                         .mode = QMAN_CGR_MODE_FRAME
1110                 }
1111         };
1112
1113         PMD_INIT_FUNC_TRACE();
1114
1115         if (fqid) {
1116                 ret = qman_reserve_fqid(fqid);
1117                 if (ret) {
1118                         DPAA_PMD_ERR("reserve rx fqid 0x%x failed with ret: %d",
1119                                      fqid, ret);
1120                         return -EINVAL;
1121                 }
1122         } else {
1123                 flags |= QMAN_FQ_FLAG_DYNAMIC_FQID;
1124         }
1125         DPAA_PMD_DEBUG("creating rx fq %p, fqid 0x%x", fq, fqid);
1126         ret = qman_create_fq(fqid, flags, fq);
1127         if (ret) {
1128                 DPAA_PMD_ERR("create rx fqid 0x%x failed with ret: %d",
1129                         fqid, ret);
1130                 return ret;
1131         }
1132         fq->is_static = false;
1133
1134         dpaa_poll_queue_default_config(&opts);
1135
1136         if (cgr_rx) {
1137                 /* Enable tail drop with cgr on this queue */
1138                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, td_threshold, 0);
1139                 cgr_rx->cb = NULL;
1140                 ret = qman_create_cgr(cgr_rx, QMAN_CGR_FLAG_USE_INIT,
1141                                       &cgr_opts);
1142                 if (ret) {
1143                         DPAA_PMD_WARN(
1144                                 "rx taildrop init fail on rx fqid 0x%x(ret=%d)",
1145                                 fq->fqid, ret);
1146                         goto without_cgr;
1147                 }
1148                 opts.we_mask |= QM_INITFQ_WE_CGID;
1149                 opts.fqd.cgid = cgr_rx->cgrid;
1150                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1151         }
1152 without_cgr:
1153         ret = qman_init_fq(fq, 0, &opts);
1154         if (ret)
1155                 DPAA_PMD_ERR("init rx fqid 0x%x failed with ret:%d", fqid, ret);
1156         return ret;
1157 }
1158
1159 /* Initialise a Tx FQ */
1160 static int dpaa_tx_queue_init(struct qman_fq *fq,
1161                               struct fman_if *fman_intf)
1162 {
1163         struct qm_mcc_initfq opts = {0};
1164         int ret;
1165
1166         PMD_INIT_FUNC_TRACE();
1167
1168         ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID |
1169                              QMAN_FQ_FLAG_TO_DCPORTAL, fq);
1170         if (ret) {
1171                 DPAA_PMD_ERR("create tx fq failed with ret: %d", ret);
1172                 return ret;
1173         }
1174         opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL |
1175                        QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA;
1176         opts.fqd.dest.channel = fman_intf->tx_channel_id;
1177         opts.fqd.dest.wq = DPAA_IF_TX_PRIORITY;
1178         opts.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE;
1179         opts.fqd.context_b = 0;
1180         /* no tx-confirmation */
1181         opts.fqd.context_a.hi = 0x80000000 | fman_dealloc_bufs_mask_hi;
1182         opts.fqd.context_a.lo = 0 | fman_dealloc_bufs_mask_lo;
1183         DPAA_PMD_DEBUG("init tx fq %p, fqid 0x%x", fq, fq->fqid);
1184         ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts);
1185         if (ret)
1186                 DPAA_PMD_ERR("init tx fqid 0x%x failed %d", fq->fqid, ret);
1187         return ret;
1188 }
1189
1190 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1191 /* Initialise a DEBUG FQ ([rt]x_error, rx_default). */
1192 static int dpaa_debug_queue_init(struct qman_fq *fq, uint32_t fqid)
1193 {
1194         struct qm_mcc_initfq opts = {0};
1195         int ret;
1196
1197         PMD_INIT_FUNC_TRACE();
1198
1199         ret = qman_reserve_fqid(fqid);
1200         if (ret) {
1201                 DPAA_PMD_ERR("Reserve debug fqid %d failed with ret: %d",
1202                         fqid, ret);
1203                 return -EINVAL;
1204         }
1205         /* "map" this Rx FQ to one of the interfaces Tx FQID */
1206         DPAA_PMD_DEBUG("Creating debug fq %p, fqid %d", fq, fqid);
1207         ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq);
1208         if (ret) {
1209                 DPAA_PMD_ERR("create debug fqid %d failed with ret: %d",
1210                         fqid, ret);
1211                 return ret;
1212         }
1213         opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL;
1214         opts.fqd.dest.wq = DPAA_IF_DEBUG_PRIORITY;
1215         ret = qman_init_fq(fq, 0, &opts);
1216         if (ret)
1217                 DPAA_PMD_ERR("init debug fqid %d failed with ret: %d",
1218                             fqid, ret);
1219         return ret;
1220 }
1221 #endif
1222
1223 /* Initialise a network interface */
1224 static int
1225 dpaa_dev_init(struct rte_eth_dev *eth_dev)
1226 {
1227         int num_rx_fqs, fqid;
1228         int loop, ret = 0;
1229         int dev_id;
1230         struct rte_dpaa_device *dpaa_device;
1231         struct dpaa_if *dpaa_intf;
1232         struct fm_eth_port_cfg *cfg;
1233         struct fman_if *fman_intf;
1234         struct fman_if_bpool *bp, *tmp_bp;
1235         uint32_t cgrid[DPAA_MAX_NUM_PCD_QUEUES];
1236
1237         PMD_INIT_FUNC_TRACE();
1238
1239         dpaa_intf = eth_dev->data->dev_private;
1240         /* For secondary processes, the primary has done all the work */
1241         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1242                 eth_dev->dev_ops = &dpaa_devops;
1243                 /* Plugging of UCODE burst API not supported in Secondary */
1244                 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
1245                 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx;
1246 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP
1247                 qman_set_fq_lookup_table(
1248                                 dpaa_intf->rx_queues->qman_fq_lookup_table);
1249 #endif
1250                 return 0;
1251         }
1252
1253         dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1254         dev_id = dpaa_device->id.dev_id;
1255         dpaa_intf = eth_dev->data->dev_private;
1256         cfg = &dpaa_netcfg->port_cfg[dev_id];
1257         fman_intf = cfg->fman_if;
1258
1259         dpaa_intf->name = dpaa_device->name;
1260
1261         /* save fman_if & cfg in the interface struture */
1262         dpaa_intf->fif = fman_intf;
1263         dpaa_intf->ifid = dev_id;
1264         dpaa_intf->cfg = cfg;
1265
1266         /* Initialize Rx FQ's */
1267         if (default_q) {
1268                 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES;
1269         } else {
1270                 if (getenv("DPAA_NUM_RX_QUEUES"))
1271                         num_rx_fqs = atoi(getenv("DPAA_NUM_RX_QUEUES"));
1272                 else
1273                         num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES;
1274         }
1275
1276
1277         /* Each device can not have more than DPAA_MAX_NUM_PCD_QUEUES RX
1278          * queues.
1279          */
1280         if (num_rx_fqs <= 0 || num_rx_fqs > DPAA_MAX_NUM_PCD_QUEUES) {
1281                 DPAA_PMD_ERR("Invalid number of RX queues\n");
1282                 return -EINVAL;
1283         }
1284
1285         dpaa_intf->rx_queues = rte_zmalloc(NULL,
1286                 sizeof(struct qman_fq) * num_rx_fqs, MAX_CACHELINE);
1287         if (!dpaa_intf->rx_queues) {
1288                 DPAA_PMD_ERR("Failed to alloc mem for RX queues\n");
1289                 return -ENOMEM;
1290         }
1291
1292         /* If congestion control is enabled globally*/
1293         if (td_threshold) {
1294                 dpaa_intf->cgr_rx = rte_zmalloc(NULL,
1295                         sizeof(struct qman_cgr) * num_rx_fqs, MAX_CACHELINE);
1296                 if (!dpaa_intf->cgr_rx) {
1297                         DPAA_PMD_ERR("Failed to alloc mem for cgr_rx\n");
1298                         ret = -ENOMEM;
1299                         goto free_rx;
1300                 }
1301
1302                 ret = qman_alloc_cgrid_range(&cgrid[0], num_rx_fqs, 1, 0);
1303                 if (ret != num_rx_fqs) {
1304                         DPAA_PMD_WARN("insufficient CGRIDs available");
1305                         ret = -EINVAL;
1306                         goto free_rx;
1307                 }
1308         } else {
1309                 dpaa_intf->cgr_rx = NULL;
1310         }
1311
1312         for (loop = 0; loop < num_rx_fqs; loop++) {
1313                 if (default_q)
1314                         fqid = cfg->rx_def;
1315                 else
1316                         fqid = DPAA_PCD_FQID_START + dpaa_intf->fif->mac_idx *
1317                                 DPAA_PCD_FQID_MULTIPLIER + loop;
1318
1319                 if (dpaa_intf->cgr_rx)
1320                         dpaa_intf->cgr_rx[loop].cgrid = cgrid[loop];
1321
1322                 ret = dpaa_rx_queue_init(&dpaa_intf->rx_queues[loop],
1323                         dpaa_intf->cgr_rx ? &dpaa_intf->cgr_rx[loop] : NULL,
1324                         fqid);
1325                 if (ret)
1326                         goto free_rx;
1327                 dpaa_intf->rx_queues[loop].dpaa_intf = dpaa_intf;
1328         }
1329         dpaa_intf->nb_rx_queues = num_rx_fqs;
1330
1331         /* Initialise Tx FQs.free_rx Have as many Tx FQ's as number of cores */
1332         dpaa_intf->tx_queues = rte_zmalloc(NULL, sizeof(struct qman_fq) *
1333                 MAX_DPAA_CORES, MAX_CACHELINE);
1334         if (!dpaa_intf->tx_queues) {
1335                 DPAA_PMD_ERR("Failed to alloc mem for TX queues\n");
1336                 ret = -ENOMEM;
1337                 goto free_rx;
1338         }
1339
1340         for (loop = 0; loop < MAX_DPAA_CORES; loop++) {
1341                 ret = dpaa_tx_queue_init(&dpaa_intf->tx_queues[loop],
1342                                          fman_intf);
1343                 if (ret)
1344                         goto free_tx;
1345                 dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf;
1346         }
1347         dpaa_intf->nb_tx_queues = MAX_DPAA_CORES;
1348
1349 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1350         dpaa_debug_queue_init(&dpaa_intf->debug_queues[
1351                 DPAA_DEBUG_FQ_RX_ERROR], fman_intf->fqid_rx_err);
1352         dpaa_intf->debug_queues[DPAA_DEBUG_FQ_RX_ERROR].dpaa_intf = dpaa_intf;
1353         dpaa_debug_queue_init(&dpaa_intf->debug_queues[
1354                 DPAA_DEBUG_FQ_TX_ERROR], fman_intf->fqid_tx_err);
1355         dpaa_intf->debug_queues[DPAA_DEBUG_FQ_TX_ERROR].dpaa_intf = dpaa_intf;
1356 #endif
1357
1358         DPAA_PMD_DEBUG("All frame queues created");
1359
1360         /* Get the initial configuration for flow control */
1361         dpaa_fc_set_default(dpaa_intf);
1362
1363         /* reset bpool list, initialize bpool dynamically */
1364         list_for_each_entry_safe(bp, tmp_bp, &cfg->fman_if->bpool_list, node) {
1365                 list_del(&bp->node);
1366                 rte_free(bp);
1367         }
1368
1369         /* Populate ethdev structure */
1370         eth_dev->dev_ops = &dpaa_devops;
1371         eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
1372         eth_dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
1373
1374         /* Allocate memory for storing MAC addresses */
1375         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr",
1376                 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER, 0);
1377         if (eth_dev->data->mac_addrs == NULL) {
1378                 DPAA_PMD_ERR("Failed to allocate %d bytes needed to "
1379                                                 "store MAC addresses",
1380                                 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER);
1381                 ret = -ENOMEM;
1382                 goto free_tx;
1383         }
1384
1385         /* copy the primary mac address */
1386         rte_ether_addr_copy(&fman_intf->mac_addr, &eth_dev->data->mac_addrs[0]);
1387
1388         RTE_LOG(INFO, PMD, "net: dpaa: %s: %02x:%02x:%02x:%02x:%02x:%02x\n",
1389                 dpaa_device->name,
1390                 fman_intf->mac_addr.addr_bytes[0],
1391                 fman_intf->mac_addr.addr_bytes[1],
1392                 fman_intf->mac_addr.addr_bytes[2],
1393                 fman_intf->mac_addr.addr_bytes[3],
1394                 fman_intf->mac_addr.addr_bytes[4],
1395                 fman_intf->mac_addr.addr_bytes[5]);
1396
1397         /* Disable RX mode */
1398         fman_if_discard_rx_errors(fman_intf);
1399         fman_if_disable_rx(fman_intf);
1400         /* Disable promiscuous mode */
1401         fman_if_promiscuous_disable(fman_intf);
1402         /* Disable multicast */
1403         fman_if_reset_mcast_filter_table(fman_intf);
1404         /* Reset interface statistics */
1405         fman_if_stats_reset(fman_intf);
1406         /* Disable SG by default */
1407         fman_if_set_sg(fman_intf, 0);
1408         fman_if_set_maxfrm(fman_intf, RTE_ETHER_MAX_LEN + VLAN_TAG_SIZE);
1409
1410         return 0;
1411
1412 free_tx:
1413         rte_free(dpaa_intf->tx_queues);
1414         dpaa_intf->tx_queues = NULL;
1415         dpaa_intf->nb_tx_queues = 0;
1416
1417 free_rx:
1418         rte_free(dpaa_intf->cgr_rx);
1419         rte_free(dpaa_intf->rx_queues);
1420         dpaa_intf->rx_queues = NULL;
1421         dpaa_intf->nb_rx_queues = 0;
1422         return ret;
1423 }
1424
1425 static int
1426 dpaa_dev_uninit(struct rte_eth_dev *dev)
1427 {
1428         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1429         int loop;
1430
1431         PMD_INIT_FUNC_TRACE();
1432
1433         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1434                 return -EPERM;
1435
1436         if (!dpaa_intf) {
1437                 DPAA_PMD_WARN("Already closed or not started");
1438                 return -1;
1439         }
1440
1441         dpaa_eth_dev_close(dev);
1442
1443         /* release configuration memory */
1444         if (dpaa_intf->fc_conf)
1445                 rte_free(dpaa_intf->fc_conf);
1446
1447         /* Release RX congestion Groups */
1448         if (dpaa_intf->cgr_rx) {
1449                 for (loop = 0; loop < dpaa_intf->nb_rx_queues; loop++)
1450                         qman_delete_cgr(&dpaa_intf->cgr_rx[loop]);
1451
1452                 qman_release_cgrid_range(dpaa_intf->cgr_rx[loop].cgrid,
1453                                          dpaa_intf->nb_rx_queues);
1454         }
1455
1456         rte_free(dpaa_intf->cgr_rx);
1457         dpaa_intf->cgr_rx = NULL;
1458
1459         rte_free(dpaa_intf->rx_queues);
1460         dpaa_intf->rx_queues = NULL;
1461
1462         rte_free(dpaa_intf->tx_queues);
1463         dpaa_intf->tx_queues = NULL;
1464
1465         dev->dev_ops = NULL;
1466         dev->rx_pkt_burst = NULL;
1467         dev->tx_pkt_burst = NULL;
1468
1469         return 0;
1470 }
1471
1472 static int
1473 rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv __rte_unused,
1474                struct rte_dpaa_device *dpaa_dev)
1475 {
1476         int diag;
1477         int ret;
1478         struct rte_eth_dev *eth_dev;
1479
1480         PMD_INIT_FUNC_TRACE();
1481
1482         if ((DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE) >
1483                 RTE_PKTMBUF_HEADROOM) {
1484                 DPAA_PMD_ERR(
1485                 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA Annotation req(%d)",
1486                 RTE_PKTMBUF_HEADROOM,
1487                 DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE);
1488
1489                 return -1;
1490         }
1491
1492         /* In case of secondary process, the device is already configured
1493          * and no further action is required, except portal initialization
1494          * and verifying secondary attachment to port name.
1495          */
1496         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1497                 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name);
1498                 if (!eth_dev)
1499                         return -ENOMEM;
1500                 eth_dev->device = &dpaa_dev->device;
1501                 eth_dev->dev_ops = &dpaa_devops;
1502                 rte_eth_dev_probing_finish(eth_dev);
1503                 return 0;
1504         }
1505
1506         if (!is_global_init && (rte_eal_process_type() == RTE_PROC_PRIMARY)) {
1507                 /* One time load of Qman/Bman drivers */
1508                 ret = qman_global_init();
1509                 if (ret) {
1510                         DPAA_PMD_ERR("QMAN initialization failed: %d",
1511                                      ret);
1512                         return ret;
1513                 }
1514                 ret = bman_global_init();
1515                 if (ret) {
1516                         DPAA_PMD_ERR("BMAN initialization failed: %d",
1517                                      ret);
1518                         return ret;
1519                 }
1520
1521                 if (access("/tmp/fmc.bin", F_OK) == -1) {
1522                         RTE_LOG(INFO, PMD,
1523                                 "* FMC not configured.Enabling default mode\n");
1524                         default_q = 1;
1525                 }
1526
1527                 /* disabling the default push mode for LS1043 */
1528                 if (dpaa_svr_family == SVR_LS1043A_FAMILY)
1529                         dpaa_push_mode_max_queue = 0;
1530
1531                 /* if push mode queues to be enabled. Currenly we are allowing
1532                  * only one queue per thread.
1533                  */
1534                 if (getenv("DPAA_PUSH_QUEUES_NUMBER")) {
1535                         dpaa_push_mode_max_queue =
1536                                         atoi(getenv("DPAA_PUSH_QUEUES_NUMBER"));
1537                         if (dpaa_push_mode_max_queue > DPAA_MAX_PUSH_MODE_QUEUE)
1538                             dpaa_push_mode_max_queue = DPAA_MAX_PUSH_MODE_QUEUE;
1539                 }
1540
1541                 is_global_init = 1;
1542         }
1543
1544         if (unlikely(!RTE_PER_LCORE(dpaa_io))) {
1545                 ret = rte_dpaa_portal_init((void *)1);
1546                 if (ret) {
1547                         DPAA_PMD_ERR("Unable to initialize portal");
1548                         return ret;
1549                 }
1550         }
1551
1552         /* In case of secondary process, the device is already configured
1553          * and no further action is required, except portal initialization
1554          * and verifying secondary attachment to port name.
1555          */
1556         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1557                 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name);
1558                 if (!eth_dev)
1559                         return -ENOMEM;
1560         } else {
1561                 eth_dev = rte_eth_dev_allocate(dpaa_dev->name);
1562                 if (eth_dev == NULL)
1563                         return -ENOMEM;
1564
1565                 eth_dev->data->dev_private = rte_zmalloc(
1566                                                 "ethdev private structure",
1567                                                 sizeof(struct dpaa_if),
1568                                                 RTE_CACHE_LINE_SIZE);
1569                 if (!eth_dev->data->dev_private) {
1570                         DPAA_PMD_ERR("Cannot allocate memzone for port data");
1571                         rte_eth_dev_release_port(eth_dev);
1572                         return -ENOMEM;
1573                 }
1574         }
1575         eth_dev->device = &dpaa_dev->device;
1576         dpaa_dev->eth_dev = eth_dev;
1577
1578         /* Invoke PMD device initialization function */
1579         diag = dpaa_dev_init(eth_dev);
1580         if (diag == 0) {
1581                 rte_eth_dev_probing_finish(eth_dev);
1582                 return 0;
1583         }
1584
1585         rte_eth_dev_release_port(eth_dev);
1586         return diag;
1587 }
1588
1589 static int
1590 rte_dpaa_remove(struct rte_dpaa_device *dpaa_dev)
1591 {
1592         struct rte_eth_dev *eth_dev;
1593
1594         PMD_INIT_FUNC_TRACE();
1595
1596         eth_dev = dpaa_dev->eth_dev;
1597         dpaa_dev_uninit(eth_dev);
1598
1599         rte_eth_dev_release_port(eth_dev);
1600
1601         return 0;
1602 }
1603
1604 static struct rte_dpaa_driver rte_dpaa_pmd = {
1605         .drv_type = FSL_DPAA_ETH,
1606         .probe = rte_dpaa_probe,
1607         .remove = rte_dpaa_remove,
1608 };
1609
1610 RTE_PMD_REGISTER_DPAA(net_dpaa, rte_dpaa_pmd);