drivers/net/dpaa/dpaa_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  *   Copyright 2016 Freescale Semiconductor, Inc. All rights reserved.
   4  *   Copyright 2017-2020 NXP
   5  *
   6  */
   7 /* System headers */
   8 #include <stdio.h>
   9 #include <inttypes.h>
  10 #include <unistd.h>
  11 #include <limits.h>
  12 #include <sched.h>
  13 #include <signal.h>
  14 #include <pthread.h>
  15 #include <sys/types.h>
  16 #include <sys/syscall.h>
  17
  18 #include <rte_string_fns.h>
  19 #include <rte_byteorder.h>
  20 #include <rte_common.h>
  21 #include <rte_interrupts.h>
  22 #include <rte_log.h>
  23 #include <rte_debug.h>
  24 #include <rte_pci.h>
  25 #include <rte_atomic.h>
  26 #include <rte_branch_prediction.h>
  27 #include <rte_memory.h>
  28 #include <rte_tailq.h>
  29 #include <rte_eal.h>
  30 #include <rte_alarm.h>
  31 #include <rte_ether.h>
  32 #include <rte_ethdev_driver.h>
  33 #include <rte_malloc.h>
  34 #include <rte_ring.h>
  35
  36 #include <rte_dpaa_bus.h>
  37 #include <rte_dpaa_logs.h>
  38 #include <dpaa_mempool.h>
  39
  40 #include <dpaa_ethdev.h>
  41 #include <dpaa_rxtx.h>
  42 #include <dpaa_flow.h>
  43 #include <rte_pmd_dpaa.h>
  44
  45 #include <fsl_usd.h>
  46 #include <fsl_qman.h>
  47 #include <fsl_bman.h>
  48 #include <fsl_fman.h>
  49 #include <process.h>
  50 #include <fmlib/fm_ext.h>
  51
  52 /* Supported Rx offloads */
  53 static uint64_t dev_rx_offloads_sup =
  54                 DEV_RX_OFFLOAD_JUMBO_FRAME |
  55                 DEV_RX_OFFLOAD_SCATTER;
  56
  57 /* Rx offloads which cannot be disabled */
  58 static uint64_t dev_rx_offloads_nodis =
  59                 DEV_RX_OFFLOAD_IPV4_CKSUM |
  60                 DEV_RX_OFFLOAD_UDP_CKSUM |
  61                 DEV_RX_OFFLOAD_TCP_CKSUM |
  62                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
  63                 DEV_RX_OFFLOAD_RSS_HASH;
  64
  65 /* Supported Tx offloads */
  66 static uint64_t dev_tx_offloads_sup =
  67                 DEV_TX_OFFLOAD_MT_LOCKFREE |
  68                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
  69
  70 /* Tx offloads which cannot be disabled */
  71 static uint64_t dev_tx_offloads_nodis =
  72                 DEV_TX_OFFLOAD_IPV4_CKSUM |
  73                 DEV_TX_OFFLOAD_UDP_CKSUM |
  74                 DEV_TX_OFFLOAD_TCP_CKSUM |
  75                 DEV_TX_OFFLOAD_SCTP_CKSUM |
  76                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
  77                 DEV_TX_OFFLOAD_MULTI_SEGS;
  78
  79 /* Keep track of whether QMAN and BMAN have been globally initialized */
  80 static int is_global_init;
  81 static int fmc_q = 1;   /* Indicates the use of static fmc for distribution */
  82 static int default_q;   /* use default queue - FMC is not executed*/
  83 /* At present we only allow up to 4 push mode queues as default - as each of
  84  * this queue need dedicated portal and we are short of portals.
  85  */
  86 #define DPAA_MAX_PUSH_MODE_QUEUE       8
  87 #define DPAA_DEFAULT_PUSH_MODE_QUEUE   4
  88
  89 static int dpaa_push_mode_max_queue = DPAA_DEFAULT_PUSH_MODE_QUEUE;
  90 static int dpaa_push_queue_idx; /* Queue index which are in push mode*/
  91
  92
  93 /* Per RX FQ Taildrop in frame count */
  94 static unsigned int td_threshold = CGR_RX_PERFQ_THRESH;
  95
  96 /* Per TX FQ Taildrop in frame count, disabled by default */
  97 static unsigned int td_tx_threshold;
  98
  99 struct rte_dpaa_xstats_name_off {
 100         char name[RTE_ETH_XSTATS_NAME_SIZE];
 101         uint32_t offset;
 102 };
 103
 104 static const struct rte_dpaa_xstats_name_off dpaa_xstats_strings[] = {
 105         {"rx_align_err",
 106                 offsetof(struct dpaa_if_stats, raln)},
 107         {"rx_valid_pause",
 108                 offsetof(struct dpaa_if_stats, rxpf)},
 109         {"rx_fcs_err",
 110                 offsetof(struct dpaa_if_stats, rfcs)},
 111         {"rx_vlan_frame",
 112                 offsetof(struct dpaa_if_stats, rvlan)},
 113         {"rx_frame_err",
 114                 offsetof(struct dpaa_if_stats, rerr)},
 115         {"rx_drop_err",
 116                 offsetof(struct dpaa_if_stats, rdrp)},
 117         {"rx_undersized",
 118                 offsetof(struct dpaa_if_stats, rund)},
 119         {"rx_oversize_err",
 120                 offsetof(struct dpaa_if_stats, rovr)},
 121         {"rx_fragment_pkt",
 122                 offsetof(struct dpaa_if_stats, rfrg)},
 123         {"tx_valid_pause",
 124                 offsetof(struct dpaa_if_stats, txpf)},
 125         {"tx_fcs_err",
 126                 offsetof(struct dpaa_if_stats, terr)},
 127         {"tx_vlan_frame",
 128                 offsetof(struct dpaa_if_stats, tvlan)},
 129         {"rx_undersized",
 130                 offsetof(struct dpaa_if_stats, tund)},
 131 };
 132
 133 static struct rte_dpaa_driver rte_dpaa_pmd;
 134
 135 static int
 136 dpaa_eth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info);
 137
 138 static int dpaa_eth_link_update(struct rte_eth_dev *dev,
 139                                 int wait_to_complete __rte_unused);
 140
 141 static void dpaa_interrupt_handler(void *param);
 142
 143 static inline void
 144 dpaa_poll_queue_default_config(struct qm_mcc_initfq *opts)
 145 {
 146         memset(opts, 0, sizeof(struct qm_mcc_initfq));
 147         opts->we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
 148         opts->fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | QM_FQCTRL_CTXASTASHING |
 149                            QM_FQCTRL_PREFERINCACHE;
 150         opts->fqd.context_a.stashing.exclusive = 0;
 151         if (dpaa_svr_family != SVR_LS1046A_FAMILY)
 152                 opts->fqd.context_a.stashing.annotation_cl =
 153                                                 DPAA_IF_RX_ANNOTATION_STASH;
 154         opts->fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
 155         opts->fqd.context_a.stashing.context_cl = DPAA_IF_RX_CONTEXT_STASH;
 156 }
 157
 158 static int
 159 dpaa_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 160 {
 161         uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
 162                                 + VLAN_TAG_SIZE;
 163         uint32_t buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
 164
 165         PMD_INIT_FUNC_TRACE();
 166
 167         if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA_MAX_RX_PKT_LEN)
 168                 return -EINVAL;
 169         /*
 170          * Refuse mtu that requires the support of scattered packets
 171          * when this feature has not been enabled before.
 172          */
 173         if (dev->data->min_rx_buf_size &&
 174                 !dev->data->scattered_rx && frame_size > buffsz) {
 175                 DPAA_PMD_ERR("SG not enabled, will not fit in one buffer");
 176                 return -EINVAL;
 177         }
 178
 179         /* check <seg size> * <max_seg>  >= max_frame */
 180         if (dev->data->min_rx_buf_size && dev->data->scattered_rx &&
 181                 (frame_size > buffsz * DPAA_SGT_MAX_ENTRIES)) {
 182                 DPAA_PMD_ERR("Too big to fit for Max SG list %d",
 183                                 buffsz * DPAA_SGT_MAX_ENTRIES);
 184                 return -EINVAL;
 185         }
 186
 187         if (frame_size > RTE_ETHER_MAX_LEN)
 188                 dev->data->dev_conf.rxmode.offloads |=
 189                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 190         else
 191                 dev->data->dev_conf.rxmode.offloads &=
 192                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 193
 194         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 195
 196         fman_if_set_maxfrm(dev->process_private, frame_size);
 197
 198         return 0;
 199 }
 200
 201 static int
 202 dpaa_eth_dev_configure(struct rte_eth_dev *dev)
 203 {
 204         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 205         uint64_t rx_offloads = eth_conf->rxmode.offloads;
 206         uint64_t tx_offloads = eth_conf->txmode.offloads;
 207         struct rte_device *rdev = dev->device;
 208         struct rte_eth_link *link = &dev->data->dev_link;
 209         struct rte_dpaa_device *dpaa_dev;
 210         struct fman_if *fif = dev->process_private;
 211         struct __fman_if *__fif;
 212         struct rte_intr_handle *intr_handle;
 213         int speed, duplex;
 214         int ret;
 215
 216         PMD_INIT_FUNC_TRACE();
 217
 218         dpaa_dev = container_of(rdev, struct rte_dpaa_device, device);
 219         intr_handle = &dpaa_dev->intr_handle;
 220         __fif = container_of(fif, struct __fman_if, __if);
 221
 222         /* Rx offloads which are enabled by default */
 223         if (dev_rx_offloads_nodis & ~rx_offloads) {
 224                 DPAA_PMD_INFO(
 225                 "Some of rx offloads enabled by default - requested 0x%" PRIx64
 226                 " fixed are 0x%" PRIx64,
 227                 rx_offloads, dev_rx_offloads_nodis);
 228         }
 229
 230         /* Tx offloads which are enabled by default */
 231         if (dev_tx_offloads_nodis & ~tx_offloads) {
 232                 DPAA_PMD_INFO(
 233                 "Some of tx offloads enabled by default - requested 0x%" PRIx64
 234                 " fixed are 0x%" PRIx64,
 235                 tx_offloads, dev_tx_offloads_nodis);
 236         }
 237
 238         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 239                 uint32_t max_len;
 240
 241                 DPAA_PMD_DEBUG("enabling jumbo");
 242
 243                 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <=
 244                     DPAA_MAX_RX_PKT_LEN)
 245                         max_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
 246                 else {
 247                         DPAA_PMD_INFO("enabling jumbo override conf max len=%d "
 248                                 "supported is %d",
 249                                 dev->data->dev_conf.rxmode.max_rx_pkt_len,
 250                                 DPAA_MAX_RX_PKT_LEN);
 251                         max_len = DPAA_MAX_RX_PKT_LEN;
 252                 }
 253
 254                 fman_if_set_maxfrm(dev->process_private, max_len);
 255                 dev->data->mtu = max_len
 256                         - RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE;
 257         }
 258
 259         if (rx_offloads & DEV_RX_OFFLOAD_SCATTER) {
 260                 DPAA_PMD_DEBUG("enabling scatter mode");
 261                 fman_if_set_sg(dev->process_private, 1);
 262                 dev->data->scattered_rx = 1;
 263         }
 264
 265         if (!(default_q || fmc_q)) {
 266                 if (dpaa_fm_config(dev,
 267                         eth_conf->rx_adv_conf.rss_conf.rss_hf)) {
 268                         dpaa_write_fm_config_to_file();
 269                         DPAA_PMD_ERR("FM port configuration: Failed\n");
 270                         return -1;
 271                 }
 272                 dpaa_write_fm_config_to_file();
 273         }
 274
 275         /* if the interrupts were configured on this devices*/
 276         if (intr_handle && intr_handle->fd) {
 277                 if (dev->data->dev_conf.intr_conf.lsc != 0)
 278                         rte_intr_callback_register(intr_handle,
 279                                            dpaa_interrupt_handler,
 280                                            (void *)dev);
 281
 282                 ret = dpaa_intr_enable(__fif->node_name, intr_handle->fd);
 283                 if (ret) {
 284                         if (dev->data->dev_conf.intr_conf.lsc != 0) {
 285                                 rte_intr_callback_unregister(intr_handle,
 286                                         dpaa_interrupt_handler,
 287                                         (void *)dev);
 288                                 if (ret == EINVAL)
 289                                         printf("Failed to enable interrupt: Not Supported\n");
 290                                 else
 291                                         printf("Failed to enable interrupt\n");
 292                         }
 293                         dev->data->dev_conf.intr_conf.lsc = 0;
 294                         dev->data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC;
 295                 }
 296         }
 297
 298         /* Wait for link status to get updated */
 299         if (!link->link_status)
 300                 sleep(1);
 301
 302         /* Configure link only if link is UP*/
 303         if (link->link_status) {
 304                 if (eth_conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
 305                         /* Start autoneg only if link is not in autoneg mode */
 306                         if (!link->link_autoneg)
 307                                 dpaa_restart_link_autoneg(__fif->node_name);
 308                 } else if (eth_conf->link_speeds & ETH_LINK_SPEED_FIXED) {
 309                         switch (eth_conf->link_speeds & ~ETH_LINK_SPEED_FIXED) {
 310                         case ETH_LINK_SPEED_10M_HD:
 311                                 speed = ETH_SPEED_NUM_10M;
 312                                 duplex = ETH_LINK_HALF_DUPLEX;
 313                                 break;
 314                         case ETH_LINK_SPEED_10M:
 315                                 speed = ETH_SPEED_NUM_10M;
 316                                 duplex = ETH_LINK_FULL_DUPLEX;
 317                                 break;
 318                         case ETH_LINK_SPEED_100M_HD:
 319                                 speed = ETH_SPEED_NUM_100M;
 320                                 duplex = ETH_LINK_HALF_DUPLEX;
 321                                 break;
 322                         case ETH_LINK_SPEED_100M:
 323                                 speed = ETH_SPEED_NUM_100M;
 324                                 duplex = ETH_LINK_FULL_DUPLEX;
 325                                 break;
 326                         case ETH_LINK_SPEED_1G:
 327                                 speed = ETH_SPEED_NUM_1G;
 328                                 duplex = ETH_LINK_FULL_DUPLEX;
 329                                 break;
 330                         case ETH_LINK_SPEED_2_5G:
 331                                 speed = ETH_SPEED_NUM_2_5G;
 332                                 duplex = ETH_LINK_FULL_DUPLEX;
 333                                 break;
 334                         case ETH_LINK_SPEED_10G:
 335                                 speed = ETH_SPEED_NUM_10G;
 336                                 duplex = ETH_LINK_FULL_DUPLEX;
 337                                 break;
 338                         default:
 339                                 speed = ETH_SPEED_NUM_NONE;
 340                                 duplex = ETH_LINK_FULL_DUPLEX;
 341                                 break;
 342                         }
 343                         /* Set link speed */
 344                         dpaa_update_link_speed(__fif->node_name, speed, duplex);
 345                 } else {
 346                         /* Manual autoneg - custom advertisement speed. */
 347                         printf("Custom Advertisement speeds not supported\n");
 348                 }
 349         }
 350
 351         return 0;
 352 }
 353
 354 static const uint32_t *
 355 dpaa_supported_ptypes_get(struct rte_eth_dev *dev)
 356 {
 357         static const uint32_t ptypes[] = {
 358                 RTE_PTYPE_L2_ETHER,
 359                 RTE_PTYPE_L2_ETHER_VLAN,
 360                 RTE_PTYPE_L2_ETHER_ARP,
 361                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
 362                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
 363                 RTE_PTYPE_L4_ICMP,
 364                 RTE_PTYPE_L4_TCP,
 365                 RTE_PTYPE_L4_UDP,
 366                 RTE_PTYPE_L4_FRAG,
 367                 RTE_PTYPE_L4_TCP,
 368                 RTE_PTYPE_L4_UDP,
 369                 RTE_PTYPE_L4_SCTP
 370         };
 371
 372         PMD_INIT_FUNC_TRACE();
 373
 374         if (dev->rx_pkt_burst == dpaa_eth_queue_rx)
 375                 return ptypes;
 376         return NULL;
 377 }
 378
 379 static void dpaa_interrupt_handler(void *param)
 380 {
 381         struct rte_eth_dev *dev = param;
 382         struct rte_device *rdev = dev->device;
 383         struct rte_dpaa_device *dpaa_dev;
 384         struct rte_intr_handle *intr_handle;
 385         uint64_t buf;
 386         int bytes_read;
 387
 388         dpaa_dev = container_of(rdev, struct rte_dpaa_device, device);
 389         intr_handle = &dpaa_dev->intr_handle;
 390
 391         bytes_read = read(intr_handle->fd, &buf, sizeof(uint64_t));
 392         if (bytes_read < 0)
 393                 DPAA_PMD_ERR("Error reading eventfd\n");
 394         dpaa_eth_link_update(dev, 0);
 395         rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
 396 }
 397
 398 static int dpaa_eth_dev_start(struct rte_eth_dev *dev)
 399 {
 400         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 401
 402         PMD_INIT_FUNC_TRACE();
 403
 404         if (!(default_q || fmc_q))
 405                 dpaa_write_fm_config_to_file();
 406
 407         /* Change tx callback to the real one */
 408         if (dpaa_intf->cgr_tx)
 409                 dev->tx_pkt_burst = dpaa_eth_queue_tx_slow;
 410         else
 411                 dev->tx_pkt_burst = dpaa_eth_queue_tx;
 412
 413         fman_if_enable_rx(dev->process_private);
 414
 415         return 0;
 416 }
 417
 418 static void dpaa_eth_dev_stop(struct rte_eth_dev *dev)
 419 {
 420         struct fman_if *fif = dev->process_private;
 421
 422         PMD_INIT_FUNC_TRACE();
 423         dev->data->dev_started = 0;
 424
 425         if (!fif->is_shared_mac)
 426                 fman_if_disable_rx(fif);
 427         dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
 428 }
 429
 430 static int dpaa_eth_dev_close(struct rte_eth_dev *dev)
 431 {
 432         struct fman_if *fif = dev->process_private;
 433         struct __fman_if *__fif;
 434         struct rte_device *rdev = dev->device;
 435         struct rte_dpaa_device *dpaa_dev;
 436         struct rte_intr_handle *intr_handle;
 437         struct rte_eth_link *link = &dev->data->dev_link;
 438         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 439         int loop;
 440
 441         PMD_INIT_FUNC_TRACE();
 442
 443         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 444                 return 0;
 445
 446         if (!dpaa_intf) {
 447                 DPAA_PMD_WARN("Already closed or not started");
 448                 return -1;
 449         }
 450
 451         /* DPAA FM deconfig */
 452         if (!(default_q || fmc_q)) {
 453                 if (dpaa_fm_deconfig(dpaa_intf, dev->process_private))
 454                         DPAA_PMD_WARN("DPAA FM deconfig failed\n");
 455         }
 456
 457         dpaa_dev = container_of(rdev, struct rte_dpaa_device, device);
 458         intr_handle = &dpaa_dev->intr_handle;
 459         __fif = container_of(fif, struct __fman_if, __if);
 460
 461         dpaa_eth_dev_stop(dev);
 462
 463         /* Reset link to autoneg */
 464         if (link->link_status && !link->link_autoneg)
 465                 dpaa_restart_link_autoneg(__fif->node_name);
 466
 467         if (intr_handle && intr_handle->fd &&
 468             dev->data->dev_conf.intr_conf.lsc != 0) {
 469                 dpaa_intr_disable(__fif->node_name);
 470                 rte_intr_callback_unregister(intr_handle,
 471                                              dpaa_interrupt_handler,
 472                                              (void *)dev);
 473         }
 474
 475         /* release configuration memory */
 476         if (dpaa_intf->fc_conf)
 477                 rte_free(dpaa_intf->fc_conf);
 478
 479         /* Release RX congestion Groups */
 480         if (dpaa_intf->cgr_rx) {
 481                 for (loop = 0; loop < dpaa_intf->nb_rx_queues; loop++)
 482                         qman_delete_cgr(&dpaa_intf->cgr_rx[loop]);
 483
 484                 qman_release_cgrid_range(dpaa_intf->cgr_rx[loop].cgrid,
 485                                          dpaa_intf->nb_rx_queues);
 486         }
 487
 488         rte_free(dpaa_intf->cgr_rx);
 489         dpaa_intf->cgr_rx = NULL;
 490         /* Release TX congestion Groups */
 491         if (dpaa_intf->cgr_tx) {
 492                 for (loop = 0; loop < MAX_DPAA_CORES; loop++)
 493                         qman_delete_cgr(&dpaa_intf->cgr_tx[loop]);
 494
 495                 qman_release_cgrid_range(dpaa_intf->cgr_tx[loop].cgrid,
 496                                          MAX_DPAA_CORES);
 497                 rte_free(dpaa_intf->cgr_tx);
 498                 dpaa_intf->cgr_tx = NULL;
 499         }
 500
 501         rte_free(dpaa_intf->rx_queues);
 502         dpaa_intf->rx_queues = NULL;
 503
 504         rte_free(dpaa_intf->tx_queues);
 505         dpaa_intf->tx_queues = NULL;
 506
 507         dev->dev_ops = NULL;
 508         dev->rx_pkt_burst = NULL;
 509         dev->tx_pkt_burst = NULL;
 510
 511         return 0;
 512 }
 513
 514 static int
 515 dpaa_fw_version_get(struct rte_eth_dev *dev __rte_unused,
 516                      char *fw_version,
 517                      size_t fw_size)
 518 {
 519         int ret;
 520         FILE *svr_file = NULL;
 521         unsigned int svr_ver = 0;
 522
 523         PMD_INIT_FUNC_TRACE();
 524
 525         svr_file = fopen(DPAA_SOC_ID_FILE, "r");
 526         if (!svr_file) {
 527                 DPAA_PMD_ERR("Unable to open SoC device");
 528                 return -ENOTSUP; /* Not supported on this infra */
 529         }
 530         if (fscanf(svr_file, "svr:%x", &svr_ver) > 0)
 531                 dpaa_svr_family = svr_ver & SVR_MASK;
 532         else
 533                 DPAA_PMD_ERR("Unable to read SoC device");
 534
 535         fclose(svr_file);
 536
 537         ret = snprintf(fw_version, fw_size, "SVR:%x-fman-v%x",
 538                        svr_ver, fman_ip_rev);
 539         ret += 1; /* add the size of '\0' */
 540
 541         if (fw_size < (uint32_t)ret)
 542                 return ret;
 543         else
 544                 return 0;
 545 }
 546
 547 static int dpaa_eth_dev_info(struct rte_eth_dev *dev,
 548                              struct rte_eth_dev_info *dev_info)
 549 {
 550         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 551         struct fman_if *fif = dev->process_private;
 552
 553         DPAA_PMD_DEBUG(": %s", dpaa_intf->name);
 554
 555         dev_info->max_rx_queues = dpaa_intf->nb_rx_queues;
 556         dev_info->max_tx_queues = dpaa_intf->nb_tx_queues;
 557         dev_info->max_rx_pktlen = DPAA_MAX_RX_PKT_LEN;
 558         dev_info->max_mac_addrs = DPAA_MAX_MAC_FILTER;
 559         dev_info->max_hash_mac_addrs = 0;
 560         dev_info->max_vfs = 0;
 561         dev_info->max_vmdq_pools = ETH_16_POOLS;
 562         dev_info->flow_type_rss_offloads = DPAA_RSS_OFFLOAD_ALL;
 563
 564         if (fif->mac_type == fman_mac_1g) {
 565                 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD
 566                                         | ETH_LINK_SPEED_10M
 567                                         | ETH_LINK_SPEED_100M_HD
 568                                         | ETH_LINK_SPEED_100M
 569                                         | ETH_LINK_SPEED_1G;
 570         } else if (fif->mac_type == fman_mac_2_5g) {
 571                 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD
 572                                         | ETH_LINK_SPEED_10M
 573                                         | ETH_LINK_SPEED_100M_HD
 574                                         | ETH_LINK_SPEED_100M
 575                                         | ETH_LINK_SPEED_1G
 576                                         | ETH_LINK_SPEED_2_5G;
 577         } else if (fif->mac_type == fman_mac_10g) {
 578                 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD
 579                                         | ETH_LINK_SPEED_10M
 580                                         | ETH_LINK_SPEED_100M_HD
 581                                         | ETH_LINK_SPEED_100M
 582                                         | ETH_LINK_SPEED_1G
 583                                         | ETH_LINK_SPEED_2_5G
 584                                         | ETH_LINK_SPEED_10G;
 585         } else {
 586                 DPAA_PMD_ERR("invalid link_speed: %s, %d",
 587                              dpaa_intf->name, fif->mac_type);
 588                 return -EINVAL;
 589         }
 590
 591         dev_info->rx_offload_capa = dev_rx_offloads_sup |
 592                                         dev_rx_offloads_nodis;
 593         dev_info->tx_offload_capa = dev_tx_offloads_sup |
 594                                         dev_tx_offloads_nodis;
 595         dev_info->default_rxportconf.burst_size = DPAA_DEF_RX_BURST_SIZE;
 596         dev_info->default_txportconf.burst_size = DPAA_DEF_TX_BURST_SIZE;
 597         dev_info->default_rxportconf.nb_queues = 1;
 598         dev_info->default_txportconf.nb_queues = 1;
 599         dev_info->default_txportconf.ring_size = CGR_TX_CGR_THRESH;
 600         dev_info->default_rxportconf.ring_size = CGR_RX_PERFQ_THRESH;
 601
 602         return 0;
 603 }
 604
 605 static int
 606 dpaa_dev_rx_burst_mode_get(struct rte_eth_dev *dev,
 607                         __rte_unused uint16_t queue_id,
 608                         struct rte_eth_burst_mode *mode)
 609 {
 610         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 611         int ret = -EINVAL;
 612         unsigned int i;
 613         const struct burst_info {
 614                 uint64_t flags;
 615                 const char *output;
 616         } rx_offload_map[] = {
 617                         {DEV_RX_OFFLOAD_JUMBO_FRAME, " Jumbo frame,"},
 618                         {DEV_RX_OFFLOAD_SCATTER, " Scattered,"},
 619                         {DEV_RX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"},
 620                         {DEV_RX_OFFLOAD_UDP_CKSUM, " UDP csum,"},
 621                         {DEV_RX_OFFLOAD_TCP_CKSUM, " TCP csum,"},
 622                         {DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
 623                         {DEV_RX_OFFLOAD_RSS_HASH, " RSS,"}
 624         };
 625
 626         /* Update Rx offload info */
 627         for (i = 0; i < RTE_DIM(rx_offload_map); i++) {
 628                 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) {
 629                         snprintf(mode->info, sizeof(mode->info), "%s",
 630                                 rx_offload_map[i].output);
 631                         ret = 0;
 632                         break;
 633                 }
 634         }
 635         return ret;
 636 }
 637
 638 static int
 639 dpaa_dev_tx_burst_mode_get(struct rte_eth_dev *dev,
 640                         __rte_unused uint16_t queue_id,
 641                         struct rte_eth_burst_mode *mode)
 642 {
 643         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 644         int ret = -EINVAL;
 645         unsigned int i;
 646         const struct burst_info {
 647                 uint64_t flags;
 648                 const char *output;
 649         } tx_offload_map[] = {
 650                         {DEV_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"},
 651                         {DEV_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"},
 652                         {DEV_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"},
 653                         {DEV_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"},
 654                         {DEV_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"},
 655                         {DEV_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
 656                         {DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
 657                         {DEV_TX_OFFLOAD_MULTI_SEGS, " Scattered,"}
 658         };
 659
 660         /* Update Tx offload info */
 661         for (i = 0; i < RTE_DIM(tx_offload_map); i++) {
 662                 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) {
 663                         snprintf(mode->info, sizeof(mode->info), "%s",
 664                                 tx_offload_map[i].output);
 665                         ret = 0;
 666                         break;
 667                 }
 668         }
 669         return ret;
 670 }
 671
 672 static int dpaa_eth_link_update(struct rte_eth_dev *dev,
 673                                 int wait_to_complete __rte_unused)
 674 {
 675         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 676         struct rte_eth_link *link = &dev->data->dev_link;
 677         struct fman_if *fif = dev->process_private;
 678         struct __fman_if *__fif = container_of(fif, struct __fman_if, __if);
 679         int ret, ioctl_version;
 680
 681         PMD_INIT_FUNC_TRACE();
 682
 683         ioctl_version = dpaa_get_ioctl_version_number();
 684
 685
 686         if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC) {
 687                 ret = dpaa_get_link_status(__fif->node_name, link);
 688                 if (ret)
 689                         return ret;
 690         } else {
 691                 link->link_status = dpaa_intf->valid;
 692         }
 693
 694         if (ioctl_version < 2) {
 695                 link->link_duplex = ETH_LINK_FULL_DUPLEX;
 696                 link->link_autoneg = ETH_LINK_AUTONEG;
 697
 698                 if (fif->mac_type == fman_mac_1g)
 699                         link->link_speed = ETH_SPEED_NUM_1G;
 700                 else if (fif->mac_type == fman_mac_2_5g)
 701                         link->link_speed = ETH_SPEED_NUM_2_5G;
 702                 else if (fif->mac_type == fman_mac_10g)
 703                         link->link_speed = ETH_SPEED_NUM_10G;
 704                 else
 705                         DPAA_PMD_ERR("invalid link_speed: %s, %d",
 706                                      dpaa_intf->name, fif->mac_type);
 707         }
 708
 709         DPAA_PMD_INFO("Port %d Link is %s\n", dev->data->port_id,
 710                       link->link_status ? "Up" : "Down");
 711         return 0;
 712 }
 713
 714 static int dpaa_eth_stats_get(struct rte_eth_dev *dev,
 715                                struct rte_eth_stats *stats)
 716 {
 717         PMD_INIT_FUNC_TRACE();
 718
 719         fman_if_stats_get(dev->process_private, stats);
 720         return 0;
 721 }
 722
 723 static int dpaa_eth_stats_reset(struct rte_eth_dev *dev)
 724 {
 725         PMD_INIT_FUNC_TRACE();
 726
 727         fman_if_stats_reset(dev->process_private);
 728
 729         return 0;
 730 }
 731
 732 static int
 733 dpaa_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
 734                     unsigned int n)
 735 {
 736         unsigned int i = 0, num = RTE_DIM(dpaa_xstats_strings);
 737         uint64_t values[sizeof(struct dpaa_if_stats) / 8];
 738
 739         if (n < num)
 740                 return num;
 741
 742         if (xstats == NULL)
 743                 return 0;
 744
 745         fman_if_stats_get_all(dev->process_private, values,
 746                               sizeof(struct dpaa_if_stats) / 8);
 747
 748         for (i = 0; i < num; i++) {
 749                 xstats[i].id = i;
 750                 xstats[i].value = values[dpaa_xstats_strings[i].offset / 8];
 751         }
 752         return i;
 753 }
 754
 755 static int
 756 dpaa_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 757                       struct rte_eth_xstat_name *xstats_names,
 758                       unsigned int limit)
 759 {
 760         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 761
 762         if (limit < stat_cnt)
 763                 return stat_cnt;
 764
 765         if (xstats_names != NULL)
 766                 for (i = 0; i < stat_cnt; i++)
 767                         strlcpy(xstats_names[i].name,
 768                                 dpaa_xstats_strings[i].name,
 769                                 sizeof(xstats_names[i].name));
 770
 771         return stat_cnt;
 772 }
 773
 774 static int
 775 dpaa_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 776                       uint64_t *values, unsigned int n)
 777 {
 778         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 779         uint64_t values_copy[sizeof(struct dpaa_if_stats) / 8];
 780
 781         if (!ids) {
 782                 if (n < stat_cnt)
 783                         return stat_cnt;
 784
 785                 if (!values)
 786                         return 0;
 787
 788                 fman_if_stats_get_all(dev->process_private, values_copy,
 789                                       sizeof(struct dpaa_if_stats) / 8);
 790
 791                 for (i = 0; i < stat_cnt; i++)
 792                         values[i] =
 793                                 values_copy[dpaa_xstats_strings[i].offset / 8];
 794
 795                 return stat_cnt;
 796         }
 797
 798         dpaa_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
 799
 800         for (i = 0; i < n; i++) {
 801                 if (ids[i] >= stat_cnt) {
 802                         DPAA_PMD_ERR("id value isn't valid");
 803                         return -1;
 804                 }
 805                 values[i] = values_copy[ids[i]];
 806         }
 807         return n;
 808 }
 809
 810 static int
 811 dpaa_xstats_get_names_by_id(
 812         struct rte_eth_dev *dev,
 813         struct rte_eth_xstat_name *xstats_names,
 814         const uint64_t *ids,
 815         unsigned int limit)
 816 {
 817         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 818         struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
 819
 820         if (!ids)
 821                 return dpaa_xstats_get_names(dev, xstats_names, limit);
 822
 823         dpaa_xstats_get_names(dev, xstats_names_copy, limit);
 824
 825         for (i = 0; i < limit; i++) {
 826                 if (ids[i] >= stat_cnt) {
 827                         DPAA_PMD_ERR("id value isn't valid");
 828                         return -1;
 829                 }
 830                 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
 831         }
 832         return limit;
 833 }
 834
 835 static int dpaa_eth_promiscuous_enable(struct rte_eth_dev *dev)
 836 {
 837         PMD_INIT_FUNC_TRACE();
 838
 839         fman_if_promiscuous_enable(dev->process_private);
 840
 841         return 0;
 842 }
 843
 844 static int dpaa_eth_promiscuous_disable(struct rte_eth_dev *dev)
 845 {
 846         PMD_INIT_FUNC_TRACE();
 847
 848         fman_if_promiscuous_disable(dev->process_private);
 849
 850         return 0;
 851 }
 852
 853 static int dpaa_eth_multicast_enable(struct rte_eth_dev *dev)
 854 {
 855         PMD_INIT_FUNC_TRACE();
 856
 857         fman_if_set_mcast_filter_table(dev->process_private);
 858
 859         return 0;
 860 }
 861
 862 static int dpaa_eth_multicast_disable(struct rte_eth_dev *dev)
 863 {
 864         PMD_INIT_FUNC_TRACE();
 865
 866         fman_if_reset_mcast_filter_table(dev->process_private);
 867
 868         return 0;
 869 }
 870
 871 static void dpaa_fman_if_pool_setup(struct rte_eth_dev *dev)
 872 {
 873         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 874         struct fman_if_ic_params icp;
 875         uint32_t fd_offset;
 876         uint32_t bp_size;
 877
 878         memset(&icp, 0, sizeof(icp));
 879         /* set ICEOF for to the default value , which is 0*/
 880         icp.iciof = DEFAULT_ICIOF;
 881         icp.iceof = DEFAULT_RX_ICEOF;
 882         icp.icsz = DEFAULT_ICSZ;
 883         fman_if_set_ic_params(dev->process_private, &icp);
 884
 885         fd_offset = RTE_PKTMBUF_HEADROOM + DPAA_HW_BUF_RESERVE;
 886         fman_if_set_fdoff(dev->process_private, fd_offset);
 887
 888         /* Buffer pool size should be equal to Dataroom Size*/
 889         bp_size = rte_pktmbuf_data_room_size(dpaa_intf->bp_info->mp);
 890
 891         fman_if_set_bp(dev->process_private,
 892                        dpaa_intf->bp_info->mp->size,
 893                        dpaa_intf->bp_info->bpid, bp_size);
 894 }
 895
 896 static inline int dpaa_eth_rx_queue_bp_check(struct rte_eth_dev *dev,
 897                                              int8_t vsp_id, uint32_t bpid)
 898 {
 899         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 900         struct fman_if *fif = dev->process_private;
 901
 902         if (fif->num_profiles) {
 903                 if (vsp_id < 0)
 904                         vsp_id = fif->base_profile_id;
 905         } else {
 906                 if (vsp_id < 0)
 907                         vsp_id = 0;
 908         }
 909
 910         if (dpaa_intf->vsp_bpid[vsp_id] &&
 911                 bpid != dpaa_intf->vsp_bpid[vsp_id]) {
 912                 DPAA_PMD_ERR("Various MPs are assigned to RXQs with same VSP");
 913
 914                 return -1;
 915         }
 916
 917         return 0;
 918 }
 919
 920 static
 921 int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 922                             uint16_t nb_desc,
 923                             unsigned int socket_id __rte_unused,
 924                             const struct rte_eth_rxconf *rx_conf,
 925                             struct rte_mempool *mp)
 926 {
 927         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 928         struct fman_if *fif = dev->process_private;
 929         struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_idx];
 930         struct qm_mcc_initfq opts = {0};
 931         u32 flags = 0;
 932         int ret;
 933         u32 buffsz = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
 934
 935         PMD_INIT_FUNC_TRACE();
 936
 937         if (queue_idx >= dev->data->nb_rx_queues) {
 938                 rte_errno = EOVERFLOW;
 939                 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
 940                       (void *)dev, queue_idx, dev->data->nb_rx_queues);
 941                 return -rte_errno;
 942         }
 943
 944         /* Rx deferred start is not supported */
 945         if (rx_conf->rx_deferred_start) {
 946                 DPAA_PMD_ERR("%p:Rx deferred start not supported", (void *)dev);
 947                 return -EINVAL;
 948         }
 949         rxq->nb_desc = UINT16_MAX;
 950         rxq->offloads = rx_conf->offloads;
 951
 952         DPAA_PMD_INFO("Rx queue setup for queue index: %d fq_id (0x%x)",
 953                         queue_idx, rxq->fqid);
 954
 955         if (!fif->num_profiles) {
 956                 if (dpaa_intf->bp_info && dpaa_intf->bp_info->bp &&
 957                         dpaa_intf->bp_info->mp != mp) {
 958                         DPAA_PMD_WARN("Multiple pools on same interface not"
 959                                       " supported");
 960                         return -EINVAL;
 961                 }
 962         } else {
 963                 if (dpaa_eth_rx_queue_bp_check(dev, rxq->vsp_id,
 964                         DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid)) {
 965                         return -EINVAL;
 966                 }
 967         }
 968
 969         /* Max packet can fit in single buffer */
 970         if (dev->data->dev_conf.rxmode.max_rx_pkt_len <= buffsz) {
 971                 ;
 972         } else if (dev->data->dev_conf.rxmode.offloads &
 973                         DEV_RX_OFFLOAD_SCATTER) {
 974                 if (dev->data->dev_conf.rxmode.max_rx_pkt_len >
 975                         buffsz * DPAA_SGT_MAX_ENTRIES) {
 976                         DPAA_PMD_ERR("max RxPkt size %d too big to fit "
 977                                 "MaxSGlist %d",
 978                                 dev->data->dev_conf.rxmode.max_rx_pkt_len,
 979                                 buffsz * DPAA_SGT_MAX_ENTRIES);
 980                         rte_errno = EOVERFLOW;
 981                         return -rte_errno;
 982                 }
 983         } else {
 984                 DPAA_PMD_WARN("The requested maximum Rx packet size (%u) is"
 985                      " larger than a single mbuf (%u) and scattered"
 986                      " mode has not been requested",
 987                      dev->data->dev_conf.rxmode.max_rx_pkt_len,
 988                      buffsz - RTE_PKTMBUF_HEADROOM);
 989         }
 990
 991         dpaa_intf->bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp);
 992
 993         /* For shared interface, it's done in kernel, skip.*/
 994         if (!fif->is_shared_mac)
 995                 dpaa_fman_if_pool_setup(dev);
 996
 997         if (fif->num_profiles) {
 998                 int8_t vsp_id = rxq->vsp_id;
 999
1000                 if (vsp_id >= 0) {
1001                         ret = dpaa_port_vsp_update(dpaa_intf, fmc_q, vsp_id,
1002                                         DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid,
1003                                         fif);
1004                         if (ret) {
1005                                 DPAA_PMD_ERR("dpaa_port_vsp_update failed");
1006                                 return ret;
1007                         }
1008                 } else {
1009                         DPAA_PMD_INFO("Base profile is associated to"
1010                                 " RXQ fqid:%d\r\n", rxq->fqid);
1011                         if (fif->is_shared_mac) {
1012                                 DPAA_PMD_ERR("Fatal: Base profile is associated"
1013                                              " to shared interface on DPDK.");
1014                                 return -EINVAL;
1015                         }
1016                         dpaa_intf->vsp_bpid[fif->base_profile_id] =
1017                                 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid;
1018                 }
1019         } else {
1020                 dpaa_intf->vsp_bpid[0] =
1021                         DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid;
1022         }
1023
1024         dpaa_intf->valid = 1;
1025         DPAA_PMD_DEBUG("if:%s sg_on = %d, max_frm =%d", dpaa_intf->name,
1026                 fman_if_get_sg_enable(fif),
1027                 dev->data->dev_conf.rxmode.max_rx_pkt_len);
1028         /* checking if push mode only, no error check for now */
1029         if (!rxq->is_static &&
1030             dpaa_push_mode_max_queue > dpaa_push_queue_idx) {
1031                 struct qman_portal *qp;
1032                 int q_fd;
1033
1034                 dpaa_push_queue_idx++;
1035                 opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
1036                 opts.fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK |
1037                                    QM_FQCTRL_CTXASTASHING |
1038                                    QM_FQCTRL_PREFERINCACHE;
1039                 opts.fqd.context_a.stashing.exclusive = 0;
1040                 /* In muticore scenario stashing becomes a bottleneck on LS1046.
1041                  * So do not enable stashing in this case
1042                  */
1043                 if (dpaa_svr_family != SVR_LS1046A_FAMILY)
1044                         opts.fqd.context_a.stashing.annotation_cl =
1045                                                 DPAA_IF_RX_ANNOTATION_STASH;
1046                 opts.fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
1047                 opts.fqd.context_a.stashing.context_cl =
1048                                                 DPAA_IF_RX_CONTEXT_STASH;
1049
1050                 /*Create a channel and associate given queue with the channel*/
1051                 qman_alloc_pool_range((u32 *)&rxq->ch_id, 1, 1, 0);
1052                 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
1053                 opts.fqd.dest.channel = rxq->ch_id;
1054                 opts.fqd.dest.wq = DPAA_IF_RX_PRIORITY;
1055                 flags = QMAN_INITFQ_FLAG_SCHED;
1056
1057                 /* Configure tail drop */
1058                 if (dpaa_intf->cgr_rx) {
1059                         opts.we_mask |= QM_INITFQ_WE_CGID;
1060                         opts.fqd.cgid = dpaa_intf->cgr_rx[queue_idx].cgrid;
1061                         opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1062                 }
1063                 ret = qman_init_fq(rxq, flags, &opts);
1064                 if (ret) {
1065                         DPAA_PMD_ERR("Channel/Q association failed. fqid 0x%x "
1066                                 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
1067                         return ret;
1068                 }
1069                 if (dpaa_svr_family == SVR_LS1043A_FAMILY) {
1070                         rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb_no_prefetch;
1071                 } else {
1072                         rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb;
1073                         rxq->cb.dqrr_prepare = dpaa_rx_cb_prepare;
1074                 }
1075
1076                 rxq->is_static = true;
1077
1078                 /* Allocate qman specific portals */
1079                 qp = fsl_qman_fq_portal_create(&q_fd);
1080                 if (!qp) {
1081                         DPAA_PMD_ERR("Unable to alloc fq portal");
1082                         return -1;
1083                 }
1084                 rxq->qp = qp;
1085
1086                 /* Set up the device interrupt handler */
1087                 if (!dev->intr_handle) {
1088                         struct rte_dpaa_device *dpaa_dev;
1089                         struct rte_device *rdev = dev->device;
1090
1091                         dpaa_dev = container_of(rdev, struct rte_dpaa_device,
1092                                                 device);
1093                         dev->intr_handle = &dpaa_dev->intr_handle;
1094                         dev->intr_handle->intr_vec = rte_zmalloc(NULL,
1095                                         dpaa_push_mode_max_queue, 0);
1096                         if (!dev->intr_handle->intr_vec) {
1097                                 DPAA_PMD_ERR("intr_vec alloc failed");
1098                                 return -ENOMEM;
1099                         }
1100                         dev->intr_handle->nb_efd = dpaa_push_mode_max_queue;
1101                         dev->intr_handle->max_intr = dpaa_push_mode_max_queue;
1102                 }
1103
1104                 dev->intr_handle->type = RTE_INTR_HANDLE_EXT;
1105                 dev->intr_handle->intr_vec[queue_idx] = queue_idx + 1;
1106                 dev->intr_handle->efds[queue_idx] = q_fd;
1107                 rxq->q_fd = q_fd;
1108         }
1109         rxq->bp_array = rte_dpaa_bpid_info;
1110         dev->data->rx_queues[queue_idx] = rxq;
1111
1112         /* configure the CGR size as per the desc size */
1113         if (dpaa_intf->cgr_rx) {
1114                 struct qm_mcc_initcgr cgr_opts = {0};
1115
1116                 rxq->nb_desc = nb_desc;
1117                 /* Enable tail drop with cgr on this queue */
1118                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, nb_desc, 0);
1119                 ret = qman_modify_cgr(dpaa_intf->cgr_rx, 0, &cgr_opts);
1120                 if (ret) {
1121                         DPAA_PMD_WARN(
1122                                 "rx taildrop modify fail on fqid %d (ret=%d)",
1123                                 rxq->fqid, ret);
1124                 }
1125         }
1126         /* Enable main queue to receive error packets also by default */
1127         fman_if_set_err_fqid(fif, rxq->fqid);
1128         return 0;
1129 }
1130
1131 int
1132 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev,
1133                 int eth_rx_queue_id,
1134                 u16 ch_id,
1135                 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
1136 {
1137         int ret;
1138         u32 flags = 0;
1139         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1140         struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
1141         struct qm_mcc_initfq opts = {0};
1142
1143         if (dpaa_push_mode_max_queue)
1144                 DPAA_PMD_WARN("PUSH mode q and EVENTDEV are not compatible\n"
1145                               "PUSH mode already enabled for first %d queues.\n"
1146                               "To disable set DPAA_PUSH_QUEUES_NUMBER to 0\n",
1147                               dpaa_push_mode_max_queue);
1148
1149         dpaa_poll_queue_default_config(&opts);
1150
1151         switch (queue_conf->ev.sched_type) {
1152         case RTE_SCHED_TYPE_ATOMIC:
1153                 opts.fqd.fq_ctrl |= QM_FQCTRL_HOLDACTIVE;
1154                 /* Reset FQCTRL_AVOIDBLOCK bit as it is unnecessary
1155                  * configuration with HOLD_ACTIVE setting
1156                  */
1157                 opts.fqd.fq_ctrl &= (~QM_FQCTRL_AVOIDBLOCK);
1158                 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_atomic;
1159                 break;
1160         case RTE_SCHED_TYPE_ORDERED:
1161                 DPAA_PMD_ERR("Ordered queue schedule type is not supported\n");
1162                 return -1;
1163         default:
1164                 opts.fqd.fq_ctrl |= QM_FQCTRL_AVOIDBLOCK;
1165                 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_parallel;
1166                 break;
1167         }
1168
1169         opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
1170         opts.fqd.dest.channel = ch_id;
1171         opts.fqd.dest.wq = queue_conf->ev.priority;
1172
1173         if (dpaa_intf->cgr_rx) {
1174                 opts.we_mask |= QM_INITFQ_WE_CGID;
1175                 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
1176                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1177         }
1178
1179         flags = QMAN_INITFQ_FLAG_SCHED;
1180
1181         ret = qman_init_fq(rxq, flags, &opts);
1182         if (ret) {
1183                 DPAA_PMD_ERR("Ev-Channel/Q association failed. fqid 0x%x "
1184                                 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
1185                 return ret;
1186         }
1187
1188         /* copy configuration which needs to be filled during dequeue */
1189         memcpy(&rxq->ev, &queue_conf->ev, sizeof(struct rte_event));
1190         dev->data->rx_queues[eth_rx_queue_id] = rxq;
1191
1192         return ret;
1193 }
1194
1195 int
1196 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev,
1197                 int eth_rx_queue_id)
1198 {
1199         struct qm_mcc_initfq opts;
1200         int ret;
1201         u32 flags = 0;
1202         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1203         struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
1204
1205         dpaa_poll_queue_default_config(&opts);
1206
1207         if (dpaa_intf->cgr_rx) {
1208                 opts.we_mask |= QM_INITFQ_WE_CGID;
1209                 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
1210                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1211         }
1212
1213         ret = qman_init_fq(rxq, flags, &opts);
1214         if (ret) {
1215                 DPAA_PMD_ERR("init rx fqid %d failed with ret: %d",
1216                              rxq->fqid, ret);
1217         }
1218
1219         rxq->cb.dqrr_dpdk_cb = NULL;
1220         dev->data->rx_queues[eth_rx_queue_id] = NULL;
1221
1222         return 0;
1223 }
1224
1225 static
1226 void dpaa_eth_rx_queue_release(void *rxq __rte_unused)
1227 {
1228         PMD_INIT_FUNC_TRACE();
1229 }
1230
1231 static
1232 int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1233                             uint16_t nb_desc __rte_unused,
1234                 unsigned int socket_id __rte_unused,
1235                 const struct rte_eth_txconf *tx_conf)
1236 {
1237         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1238         struct qman_fq *txq = &dpaa_intf->tx_queues[queue_idx];
1239
1240         PMD_INIT_FUNC_TRACE();
1241
1242         /* Tx deferred start is not supported */
1243         if (tx_conf->tx_deferred_start) {
1244                 DPAA_PMD_ERR("%p:Tx deferred start not supported", (void *)dev);
1245                 return -EINVAL;
1246         }
1247         txq->nb_desc = UINT16_MAX;
1248         txq->offloads = tx_conf->offloads;
1249
1250         if (queue_idx >= dev->data->nb_tx_queues) {
1251                 rte_errno = EOVERFLOW;
1252                 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
1253                       (void *)dev, queue_idx, dev->data->nb_tx_queues);
1254                 return -rte_errno;
1255         }
1256
1257         DPAA_PMD_INFO("Tx queue setup for queue index: %d fq_id (0x%x)",
1258                         queue_idx, txq->fqid);
1259         dev->data->tx_queues[queue_idx] = txq;
1260
1261         return 0;
1262 }
1263
1264 static void dpaa_eth_tx_queue_release(void *txq __rte_unused)
1265 {
1266         PMD_INIT_FUNC_TRACE();
1267 }
1268
1269 static uint32_t
1270 dpaa_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1271 {
1272         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1273         struct qman_fq *rxq = &dpaa_intf->rx_queues[rx_queue_id];
1274         u32 frm_cnt = 0;
1275
1276         PMD_INIT_FUNC_TRACE();
1277
1278         if (qman_query_fq_frm_cnt(rxq, &frm_cnt) == 0) {
1279                 DPAA_PMD_DEBUG("RX frame count for q(%d) is %u",
1280                                rx_queue_id, frm_cnt);
1281         }
1282         return frm_cnt;
1283 }
1284
1285 static int dpaa_link_down(struct rte_eth_dev *dev)
1286 {
1287         struct fman_if *fif = dev->process_private;
1288         struct __fman_if *__fif;
1289
1290         PMD_INIT_FUNC_TRACE();
1291
1292         __fif = container_of(fif, struct __fman_if, __if);
1293
1294         if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC)
1295                 dpaa_update_link_status(__fif->node_name, ETH_LINK_DOWN);
1296         else
1297                 dpaa_eth_dev_stop(dev);
1298         return 0;
1299 }
1300
1301 static int dpaa_link_up(struct rte_eth_dev *dev)
1302 {
1303         struct fman_if *fif = dev->process_private;
1304         struct __fman_if *__fif;
1305
1306         PMD_INIT_FUNC_TRACE();
1307
1308         __fif = container_of(fif, struct __fman_if, __if);
1309
1310         if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC)
1311                 dpaa_update_link_status(__fif->node_name, ETH_LINK_UP);
1312         else
1313                 dpaa_eth_dev_start(dev);
1314         return 0;
1315 }
1316
1317 static int
1318 dpaa_flow_ctrl_set(struct rte_eth_dev *dev,
1319                    struct rte_eth_fc_conf *fc_conf)
1320 {
1321         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1322         struct rte_eth_fc_conf *net_fc;
1323
1324         PMD_INIT_FUNC_TRACE();
1325
1326         if (!(dpaa_intf->fc_conf)) {
1327                 dpaa_intf->fc_conf = rte_zmalloc(NULL,
1328                         sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
1329                 if (!dpaa_intf->fc_conf) {
1330                         DPAA_PMD_ERR("unable to save flow control info");
1331                         return -ENOMEM;
1332                 }
1333         }
1334         net_fc = dpaa_intf->fc_conf;
1335
1336         if (fc_conf->high_water < fc_conf->low_water) {
1337                 DPAA_PMD_ERR("Incorrect Flow Control Configuration");
1338                 return -EINVAL;
1339         }
1340
1341         if (fc_conf->mode == RTE_FC_NONE) {
1342                 return 0;
1343         } else if (fc_conf->mode == RTE_FC_TX_PAUSE ||
1344                  fc_conf->mode == RTE_FC_FULL) {
1345                 fman_if_set_fc_threshold(dev->process_private,
1346                                          fc_conf->high_water,
1347                                          fc_conf->low_water,
1348                                          dpaa_intf->bp_info->bpid);
1349                 if (fc_conf->pause_time)
1350                         fman_if_set_fc_quanta(dev->process_private,
1351                                               fc_conf->pause_time);
1352         }
1353
1354         /* Save the information in dpaa device */
1355         net_fc->pause_time = fc_conf->pause_time;
1356         net_fc->high_water = fc_conf->high_water;
1357         net_fc->low_water = fc_conf->low_water;
1358         net_fc->send_xon = fc_conf->send_xon;
1359         net_fc->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
1360         net_fc->mode = fc_conf->mode;
1361         net_fc->autoneg = fc_conf->autoneg;
1362
1363         return 0;
1364 }
1365
1366 static int
1367 dpaa_flow_ctrl_get(struct rte_eth_dev *dev,
1368                    struct rte_eth_fc_conf *fc_conf)
1369 {
1370         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1371         struct rte_eth_fc_conf *net_fc = dpaa_intf->fc_conf;
1372         int ret;
1373
1374         PMD_INIT_FUNC_TRACE();
1375
1376         if (net_fc) {
1377                 fc_conf->pause_time = net_fc->pause_time;
1378                 fc_conf->high_water = net_fc->high_water;
1379                 fc_conf->low_water = net_fc->low_water;
1380                 fc_conf->send_xon = net_fc->send_xon;
1381                 fc_conf->mac_ctrl_frame_fwd = net_fc->mac_ctrl_frame_fwd;
1382                 fc_conf->mode = net_fc->mode;
1383                 fc_conf->autoneg = net_fc->autoneg;
1384                 return 0;
1385         }
1386         ret = fman_if_get_fc_threshold(dev->process_private);
1387         if (ret) {
1388                 fc_conf->mode = RTE_FC_TX_PAUSE;
1389                 fc_conf->pause_time =
1390                         fman_if_get_fc_quanta(dev->process_private);
1391         } else {
1392                 fc_conf->mode = RTE_FC_NONE;
1393         }
1394
1395         return 0;
1396 }
1397
1398 static int
1399 dpaa_dev_add_mac_addr(struct rte_eth_dev *dev,
1400                              struct rte_ether_addr *addr,
1401                              uint32_t index,
1402                              __rte_unused uint32_t pool)
1403 {
1404         int ret;
1405
1406         PMD_INIT_FUNC_TRACE();
1407
1408         ret = fman_if_add_mac_addr(dev->process_private,
1409                                    addr->addr_bytes, index);
1410
1411         if (ret)
1412                 DPAA_PMD_ERR("Adding the MAC ADDR failed: err = %d", ret);
1413         return 0;
1414 }
1415
1416 static void
1417 dpaa_dev_remove_mac_addr(struct rte_eth_dev *dev,
1418                           uint32_t index)
1419 {
1420         PMD_INIT_FUNC_TRACE();
1421
1422         fman_if_clear_mac_addr(dev->process_private, index);
1423 }
1424
1425 static int
1426 dpaa_dev_set_mac_addr(struct rte_eth_dev *dev,
1427                        struct rte_ether_addr *addr)
1428 {
1429         int ret;
1430
1431         PMD_INIT_FUNC_TRACE();
1432
1433         ret = fman_if_add_mac_addr(dev->process_private, addr->addr_bytes, 0);
1434         if (ret)
1435                 DPAA_PMD_ERR("Setting the MAC ADDR failed %d", ret);
1436
1437         return ret;
1438 }
1439
1440 static int
1441 dpaa_dev_rss_hash_update(struct rte_eth_dev *dev,
1442                          struct rte_eth_rss_conf *rss_conf)
1443 {
1444         struct rte_eth_dev_data *data = dev->data;
1445         struct rte_eth_conf *eth_conf = &data->dev_conf;
1446
1447         PMD_INIT_FUNC_TRACE();
1448
1449         if (!(default_q || fmc_q)) {
1450                 if (dpaa_fm_config(dev, rss_conf->rss_hf)) {
1451                         DPAA_PMD_ERR("FM port configuration: Failed\n");
1452                         return -1;
1453                 }
1454                 eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf;
1455         } else {
1456                 DPAA_PMD_ERR("Function not supported\n");
1457                 return -ENOTSUP;
1458         }
1459         return 0;
1460 }
1461
1462 static int
1463 dpaa_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
1464                            struct rte_eth_rss_conf *rss_conf)
1465 {
1466         struct rte_eth_dev_data *data = dev->data;
1467         struct rte_eth_conf *eth_conf = &data->dev_conf;
1468
1469         /* dpaa does not support rss_key, so length should be 0*/
1470         rss_conf->rss_key_len = 0;
1471         rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf;
1472         return 0;
1473 }
1474
1475 static int dpaa_dev_queue_intr_enable(struct rte_eth_dev *dev,
1476                                       uint16_t queue_id)
1477 {
1478         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1479         struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id];
1480
1481         if (!rxq->is_static)
1482                 return -EINVAL;
1483
1484         return qman_fq_portal_irqsource_add(rxq->qp, QM_PIRQ_DQRI);
1485 }
1486
1487 static int dpaa_dev_queue_intr_disable(struct rte_eth_dev *dev,
1488                                        uint16_t queue_id)
1489 {
1490         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1491         struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id];
1492         uint32_t temp;
1493         ssize_t temp1;
1494
1495         if (!rxq->is_static)
1496                 return -EINVAL;
1497
1498         qman_fq_portal_irqsource_remove(rxq->qp, ~0);
1499
1500         temp1 = read(rxq->q_fd, &temp, sizeof(temp));
1501         if (temp1 != sizeof(temp))
1502                 DPAA_PMD_ERR("irq read error");
1503
1504         qman_fq_portal_thread_irq(rxq->qp);
1505
1506         return 0;
1507 }
1508
1509 static void
1510 dpaa_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1511         struct rte_eth_rxq_info *qinfo)
1512 {
1513         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1514         struct qman_fq *rxq;
1515
1516         rxq = dev->data->rx_queues[queue_id];
1517
1518         qinfo->mp = dpaa_intf->bp_info->mp;
1519         qinfo->scattered_rx = dev->data->scattered_rx;
1520         qinfo->nb_desc = rxq->nb_desc;
1521         qinfo->conf.rx_free_thresh = 1;
1522         qinfo->conf.rx_drop_en = 1;
1523         qinfo->conf.rx_deferred_start = 0;
1524         qinfo->conf.offloads = rxq->offloads;
1525 }
1526
1527 static void
1528 dpaa_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1529         struct rte_eth_txq_info *qinfo)
1530 {
1531         struct qman_fq *txq;
1532
1533         txq = dev->data->tx_queues[queue_id];
1534
1535         qinfo->nb_desc = txq->nb_desc;
1536         qinfo->conf.tx_thresh.pthresh = 0;
1537         qinfo->conf.tx_thresh.hthresh = 0;
1538         qinfo->conf.tx_thresh.wthresh = 0;
1539
1540         qinfo->conf.tx_free_thresh = 0;
1541         qinfo->conf.tx_rs_thresh = 0;
1542         qinfo->conf.offloads = txq->offloads;
1543         qinfo->conf.tx_deferred_start = 0;
1544 }
1545
1546 static struct eth_dev_ops dpaa_devops = {
1547         .dev_configure            = dpaa_eth_dev_configure,
1548         .dev_start                = dpaa_eth_dev_start,
1549         .dev_stop                 = dpaa_eth_dev_stop,
1550         .dev_close                = dpaa_eth_dev_close,
1551         .dev_infos_get            = dpaa_eth_dev_info,
1552         .dev_supported_ptypes_get = dpaa_supported_ptypes_get,
1553
1554         .rx_queue_setup           = dpaa_eth_rx_queue_setup,
1555         .tx_queue_setup           = dpaa_eth_tx_queue_setup,
1556         .rx_queue_release         = dpaa_eth_rx_queue_release,
1557         .tx_queue_release         = dpaa_eth_tx_queue_release,
1558         .rx_burst_mode_get        = dpaa_dev_rx_burst_mode_get,
1559         .tx_burst_mode_get        = dpaa_dev_tx_burst_mode_get,
1560         .rxq_info_get             = dpaa_rxq_info_get,
1561         .txq_info_get             = dpaa_txq_info_get,
1562
1563         .flow_ctrl_get            = dpaa_flow_ctrl_get,
1564         .flow_ctrl_set            = dpaa_flow_ctrl_set,
1565
1566         .link_update              = dpaa_eth_link_update,
1567         .stats_get                = dpaa_eth_stats_get,
1568         .xstats_get               = dpaa_dev_xstats_get,
1569         .xstats_get_by_id         = dpaa_xstats_get_by_id,
1570         .xstats_get_names_by_id   = dpaa_xstats_get_names_by_id,
1571         .xstats_get_names         = dpaa_xstats_get_names,
1572         .xstats_reset             = dpaa_eth_stats_reset,
1573         .stats_reset              = dpaa_eth_stats_reset,
1574         .promiscuous_enable       = dpaa_eth_promiscuous_enable,
1575         .promiscuous_disable      = dpaa_eth_promiscuous_disable,
1576         .allmulticast_enable      = dpaa_eth_multicast_enable,
1577         .allmulticast_disable     = dpaa_eth_multicast_disable,
1578         .mtu_set                  = dpaa_mtu_set,
1579         .dev_set_link_down        = dpaa_link_down,
1580         .dev_set_link_up          = dpaa_link_up,
1581         .mac_addr_add             = dpaa_dev_add_mac_addr,
1582         .mac_addr_remove          = dpaa_dev_remove_mac_addr,
1583         .mac_addr_set             = dpaa_dev_set_mac_addr,
1584
1585         .fw_version_get           = dpaa_fw_version_get,
1586
1587         .rx_queue_intr_enable     = dpaa_dev_queue_intr_enable,
1588         .rx_queue_intr_disable    = dpaa_dev_queue_intr_disable,
1589         .rss_hash_update          = dpaa_dev_rss_hash_update,
1590         .rss_hash_conf_get        = dpaa_dev_rss_hash_conf_get,
1591 };
1592
1593 static bool
1594 is_device_supported(struct rte_eth_dev *dev, struct rte_dpaa_driver *drv)
1595 {
1596         if (strcmp(dev->device->driver->name,
1597                    drv->driver.name))
1598                 return false;
1599
1600         return true;
1601 }
1602
1603 static bool
1604 is_dpaa_supported(struct rte_eth_dev *dev)
1605 {
1606         return is_device_supported(dev, &rte_dpaa_pmd);
1607 }
1608
1609 int
1610 rte_pmd_dpaa_set_tx_loopback(uint16_t port, uint8_t on)
1611 {
1612         struct rte_eth_dev *dev;
1613
1614         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
1615
1616         dev = &rte_eth_devices[port];
1617
1618         if (!is_dpaa_supported(dev))
1619                 return -ENOTSUP;
1620
1621         if (on)
1622                 fman_if_loopback_enable(dev->process_private);
1623         else
1624                 fman_if_loopback_disable(dev->process_private);
1625
1626         return 0;
1627 }
1628
1629 static int dpaa_fc_set_default(struct dpaa_if *dpaa_intf,
1630                                struct fman_if *fman_intf)
1631 {
1632         struct rte_eth_fc_conf *fc_conf;
1633         int ret;
1634
1635         PMD_INIT_FUNC_TRACE();
1636
1637         if (!(dpaa_intf->fc_conf)) {
1638                 dpaa_intf->fc_conf = rte_zmalloc(NULL,
1639                         sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
1640                 if (!dpaa_intf->fc_conf) {
1641                         DPAA_PMD_ERR("unable to save flow control info");
1642                         return -ENOMEM;
1643                 }
1644         }
1645         fc_conf = dpaa_intf->fc_conf;
1646         ret = fman_if_get_fc_threshold(fman_intf);
1647         if (ret) {
1648                 fc_conf->mode = RTE_FC_TX_PAUSE;
1649                 fc_conf->pause_time = fman_if_get_fc_quanta(fman_intf);
1650         } else {
1651                 fc_conf->mode = RTE_FC_NONE;
1652         }
1653
1654         return 0;
1655 }
1656
1657 /* Initialise an Rx FQ */
1658 static int dpaa_rx_queue_init(struct qman_fq *fq, struct qman_cgr *cgr_rx,
1659                               uint32_t fqid)
1660 {
1661         struct qm_mcc_initfq opts = {0};
1662         int ret;
1663         u32 flags = QMAN_FQ_FLAG_NO_ENQUEUE;
1664         struct qm_mcc_initcgr cgr_opts = {
1665                 .we_mask = QM_CGR_WE_CS_THRES |
1666                                 QM_CGR_WE_CSTD_EN |
1667                                 QM_CGR_WE_MODE,
1668                 .cgr = {
1669                         .cstd_en = QM_CGR_EN,
1670                         .mode = QMAN_CGR_MODE_FRAME
1671                 }
1672         };
1673
1674         if (fmc_q || default_q) {
1675                 ret = qman_reserve_fqid(fqid);
1676                 if (ret) {
1677                         DPAA_PMD_ERR("reserve rx fqid 0x%x failed, ret: %d",
1678                                      fqid, ret);
1679                         return -EINVAL;
1680                 }
1681         }
1682
1683         DPAA_PMD_DEBUG("creating rx fq %p, fqid 0x%x", fq, fqid);
1684         ret = qman_create_fq(fqid, flags, fq);
1685         if (ret) {
1686                 DPAA_PMD_ERR("create rx fqid 0x%x failed with ret: %d",
1687                         fqid, ret);
1688                 return ret;
1689         }
1690         fq->is_static = false;
1691
1692         dpaa_poll_queue_default_config(&opts);
1693
1694         if (cgr_rx) {
1695                 /* Enable tail drop with cgr on this queue */
1696                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, td_threshold, 0);
1697                 cgr_rx->cb = NULL;
1698                 ret = qman_create_cgr(cgr_rx, QMAN_CGR_FLAG_USE_INIT,
1699                                       &cgr_opts);
1700                 if (ret) {
1701                         DPAA_PMD_WARN(
1702                                 "rx taildrop init fail on rx fqid 0x%x(ret=%d)",
1703                                 fq->fqid, ret);
1704                         goto without_cgr;
1705                 }
1706                 opts.we_mask |= QM_INITFQ_WE_CGID;
1707                 opts.fqd.cgid = cgr_rx->cgrid;
1708                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1709         }
1710 without_cgr:
1711         ret = qman_init_fq(fq, 0, &opts);
1712         if (ret)
1713                 DPAA_PMD_ERR("init rx fqid 0x%x failed with ret:%d", fqid, ret);
1714         return ret;
1715 }
1716
1717 /* Initialise a Tx FQ */
1718 static int dpaa_tx_queue_init(struct qman_fq *fq,
1719                               struct fman_if *fman_intf,
1720                               struct qman_cgr *cgr_tx)
1721 {
1722         struct qm_mcc_initfq opts = {0};
1723         struct qm_mcc_initcgr cgr_opts = {
1724                 .we_mask = QM_CGR_WE_CS_THRES |
1725                                 QM_CGR_WE_CSTD_EN |
1726                                 QM_CGR_WE_MODE,
1727                 .cgr = {
1728                         .cstd_en = QM_CGR_EN,
1729                         .mode = QMAN_CGR_MODE_FRAME
1730                 }
1731         };
1732         int ret;
1733
1734         ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID |
1735                              QMAN_FQ_FLAG_TO_DCPORTAL, fq);
1736         if (ret) {
1737                 DPAA_PMD_ERR("create tx fq failed with ret: %d", ret);
1738                 return ret;
1739         }
1740         opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL |
1741                        QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA;
1742         opts.fqd.dest.channel = fman_intf->tx_channel_id;
1743         opts.fqd.dest.wq = DPAA_IF_TX_PRIORITY;
1744         opts.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE;
1745         opts.fqd.context_b = 0;
1746         /* no tx-confirmation */
1747         opts.fqd.context_a.hi = 0x80000000 | fman_dealloc_bufs_mask_hi;
1748         opts.fqd.context_a.lo = 0 | fman_dealloc_bufs_mask_lo;
1749         DPAA_PMD_DEBUG("init tx fq %p, fqid 0x%x", fq, fq->fqid);
1750
1751         if (cgr_tx) {
1752                 /* Enable tail drop with cgr on this queue */
1753                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres,
1754                                       td_tx_threshold, 0);
1755                 cgr_tx->cb = NULL;
1756                 ret = qman_create_cgr(cgr_tx, QMAN_CGR_FLAG_USE_INIT,
1757                                       &cgr_opts);
1758                 if (ret) {
1759                         DPAA_PMD_WARN(
1760                                 "rx taildrop init fail on rx fqid 0x%x(ret=%d)",
1761                                 fq->fqid, ret);
1762                         goto without_cgr;
1763                 }
1764                 opts.we_mask |= QM_INITFQ_WE_CGID;
1765                 opts.fqd.cgid = cgr_tx->cgrid;
1766                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1767                 DPAA_PMD_DEBUG("Tx FQ tail drop enabled, threshold = %d\n",
1768                                 td_tx_threshold);
1769         }
1770 without_cgr:
1771         ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts);
1772         if (ret)
1773                 DPAA_PMD_ERR("init tx fqid 0x%x failed %d", fq->fqid, ret);
1774         return ret;
1775 }
1776
1777 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1778 /* Initialise a DEBUG FQ ([rt]x_error, rx_default). */
1779 static int dpaa_debug_queue_init(struct qman_fq *fq, uint32_t fqid)
1780 {
1781         struct qm_mcc_initfq opts = {0};
1782         int ret;
1783
1784         PMD_INIT_FUNC_TRACE();
1785
1786         ret = qman_reserve_fqid(fqid);
1787         if (ret) {
1788                 DPAA_PMD_ERR("Reserve debug fqid %d failed with ret: %d",
1789                         fqid, ret);
1790                 return -EINVAL;
1791         }
1792         /* "map" this Rx FQ to one of the interfaces Tx FQID */
1793         DPAA_PMD_DEBUG("Creating debug fq %p, fqid %d", fq, fqid);
1794         ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq);
1795         if (ret) {
1796                 DPAA_PMD_ERR("create debug fqid %d failed with ret: %d",
1797                         fqid, ret);
1798                 return ret;
1799         }
1800         opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL;
1801         opts.fqd.dest.wq = DPAA_IF_DEBUG_PRIORITY;
1802         ret = qman_init_fq(fq, 0, &opts);
1803         if (ret)
1804                 DPAA_PMD_ERR("init debug fqid %d failed with ret: %d",
1805                             fqid, ret);
1806         return ret;
1807 }
1808 #endif
1809
1810 /* Initialise a network interface */
1811 static int
1812 dpaa_dev_init_secondary(struct rte_eth_dev *eth_dev)
1813 {
1814         struct rte_dpaa_device *dpaa_device;
1815         struct fm_eth_port_cfg *cfg;
1816         struct dpaa_if *dpaa_intf;
1817         struct fman_if *fman_intf;
1818         int dev_id;
1819
1820         PMD_INIT_FUNC_TRACE();
1821
1822         dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1823         dev_id = dpaa_device->id.dev_id;
1824         cfg = dpaa_get_eth_port_cfg(dev_id);
1825         fman_intf = cfg->fman_if;
1826         eth_dev->process_private = fman_intf;
1827
1828         /* Plugging of UCODE burst API not supported in Secondary */
1829         dpaa_intf = eth_dev->data->dev_private;
1830         eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
1831         if (dpaa_intf->cgr_tx)
1832                 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx_slow;
1833         else
1834                 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx;
1835 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP
1836         qman_set_fq_lookup_table(
1837                 dpaa_intf->rx_queues->qman_fq_lookup_table);
1838 #endif
1839
1840         return 0;
1841 }
1842
1843 /* Initialise a network interface */
1844 static int
1845 dpaa_dev_init(struct rte_eth_dev *eth_dev)
1846 {
1847         int num_rx_fqs, fqid;
1848         int loop, ret = 0;
1849         int dev_id;
1850         struct rte_dpaa_device *dpaa_device;
1851         struct dpaa_if *dpaa_intf;
1852         struct fm_eth_port_cfg *cfg;
1853         struct fman_if *fman_intf;
1854         struct fman_if_bpool *bp, *tmp_bp;
1855         uint32_t cgrid[DPAA_MAX_NUM_PCD_QUEUES];
1856         uint32_t cgrid_tx[MAX_DPAA_CORES];
1857         uint32_t dev_rx_fqids[DPAA_MAX_NUM_PCD_QUEUES];
1858         int8_t dev_vspids[DPAA_MAX_NUM_PCD_QUEUES];
1859         int8_t vsp_id = -1;
1860
1861         PMD_INIT_FUNC_TRACE();
1862
1863         dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1864         dev_id = dpaa_device->id.dev_id;
1865         dpaa_intf = eth_dev->data->dev_private;
1866         cfg = dpaa_get_eth_port_cfg(dev_id);
1867         fman_intf = cfg->fman_if;
1868
1869         dpaa_intf->name = dpaa_device->name;
1870
1871         /* save fman_if & cfg in the interface struture */
1872         eth_dev->process_private = fman_intf;
1873         dpaa_intf->ifid = dev_id;
1874         dpaa_intf->cfg = cfg;
1875
1876         memset((char *)dev_rx_fqids, 0,
1877                 sizeof(uint32_t) * DPAA_MAX_NUM_PCD_QUEUES);
1878
1879         memset(dev_vspids, -1, DPAA_MAX_NUM_PCD_QUEUES);
1880
1881         /* Initialize Rx FQ's */
1882         if (default_q) {
1883                 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES;
1884         } else if (fmc_q) {
1885                 num_rx_fqs = dpaa_port_fmc_init(fman_intf, dev_rx_fqids,
1886                                                 dev_vspids,
1887                                                 DPAA_MAX_NUM_PCD_QUEUES);
1888                 if (num_rx_fqs < 0) {
1889                         DPAA_PMD_ERR("%s FMC initializes failed!",
1890                                 dpaa_intf->name);
1891                         goto free_rx;
1892                 }
1893                 if (!num_rx_fqs) {
1894                         DPAA_PMD_WARN("%s is not configured by FMC.",
1895                                 dpaa_intf->name);
1896                 }
1897         } else {
1898                 /* FMCLESS mode, load balance to multiple cores.*/
1899                 num_rx_fqs = rte_lcore_count();
1900         }
1901
1902         /* Each device can not have more than DPAA_MAX_NUM_PCD_QUEUES RX
1903          * queues.
1904          */
1905         if (num_rx_fqs < 0 || num_rx_fqs > DPAA_MAX_NUM_PCD_QUEUES) {
1906                 DPAA_PMD_ERR("Invalid number of RX queues\n");
1907                 return -EINVAL;
1908         }
1909
1910         if (num_rx_fqs > 0) {
1911                 dpaa_intf->rx_queues = rte_zmalloc(NULL,
1912                         sizeof(struct qman_fq) * num_rx_fqs, MAX_CACHELINE);
1913                 if (!dpaa_intf->rx_queues) {
1914                         DPAA_PMD_ERR("Failed to alloc mem for RX queues\n");
1915                         return -ENOMEM;
1916                 }
1917         } else {
1918                 dpaa_intf->rx_queues = NULL;
1919         }
1920
1921         memset(cgrid, 0, sizeof(cgrid));
1922         memset(cgrid_tx, 0, sizeof(cgrid_tx));
1923
1924         /* if DPAA_TX_TAILDROP_THRESHOLD is set, use that value; if 0, it means
1925          * Tx tail drop is disabled.
1926          */
1927         if (getenv("DPAA_TX_TAILDROP_THRESHOLD")) {
1928                 td_tx_threshold = atoi(getenv("DPAA_TX_TAILDROP_THRESHOLD"));
1929                 DPAA_PMD_DEBUG("Tail drop threshold env configured: %u",
1930                                td_tx_threshold);
1931                 /* if a very large value is being configured */
1932                 if (td_tx_threshold > UINT16_MAX)
1933                         td_tx_threshold = CGR_RX_PERFQ_THRESH;
1934         }
1935
1936         /* If congestion control is enabled globally*/
1937         if (num_rx_fqs > 0 && td_threshold) {
1938                 dpaa_intf->cgr_rx = rte_zmalloc(NULL,
1939                         sizeof(struct qman_cgr) * num_rx_fqs, MAX_CACHELINE);
1940                 if (!dpaa_intf->cgr_rx) {
1941                         DPAA_PMD_ERR("Failed to alloc mem for cgr_rx\n");
1942                         ret = -ENOMEM;
1943                         goto free_rx;
1944                 }
1945
1946                 ret = qman_alloc_cgrid_range(&cgrid[0], num_rx_fqs, 1, 0);
1947                 if (ret != num_rx_fqs) {
1948                         DPAA_PMD_WARN("insufficient CGRIDs available");
1949                         ret = -EINVAL;
1950                         goto free_rx;
1951                 }
1952         } else {
1953                 dpaa_intf->cgr_rx = NULL;
1954         }
1955
1956         if (!fmc_q && !default_q) {
1957                 ret = qman_alloc_fqid_range(dev_rx_fqids, num_rx_fqs,
1958                                             num_rx_fqs, 0);
1959                 if (ret < 0) {
1960                         DPAA_PMD_ERR("Failed to alloc rx fqid's\n");
1961                         goto free_rx;
1962                 }
1963         }
1964
1965         for (loop = 0; loop < num_rx_fqs; loop++) {
1966                 if (default_q)
1967                         fqid = cfg->rx_def;
1968                 else
1969                         fqid = dev_rx_fqids[loop];
1970
1971                 vsp_id = dev_vspids[loop];
1972
1973                 if (dpaa_intf->cgr_rx)
1974                         dpaa_intf->cgr_rx[loop].cgrid = cgrid[loop];
1975
1976                 ret = dpaa_rx_queue_init(&dpaa_intf->rx_queues[loop],
1977                         dpaa_intf->cgr_rx ? &dpaa_intf->cgr_rx[loop] : NULL,
1978                         fqid);
1979                 if (ret)
1980                         goto free_rx;
1981                 dpaa_intf->rx_queues[loop].vsp_id = vsp_id;
1982                 dpaa_intf->rx_queues[loop].dpaa_intf = dpaa_intf;
1983         }
1984         dpaa_intf->nb_rx_queues = num_rx_fqs;
1985
1986         /* Initialise Tx FQs.free_rx Have as many Tx FQ's as number of cores */
1987         dpaa_intf->tx_queues = rte_zmalloc(NULL, sizeof(struct qman_fq) *
1988                 MAX_DPAA_CORES, MAX_CACHELINE);
1989         if (!dpaa_intf->tx_queues) {
1990                 DPAA_PMD_ERR("Failed to alloc mem for TX queues\n");
1991                 ret = -ENOMEM;
1992                 goto free_rx;
1993         }
1994
1995         /* If congestion control is enabled globally*/
1996         if (td_tx_threshold) {
1997                 dpaa_intf->cgr_tx = rte_zmalloc(NULL,
1998                         sizeof(struct qman_cgr) * MAX_DPAA_CORES,
1999                         MAX_CACHELINE);
2000                 if (!dpaa_intf->cgr_tx) {
2001                         DPAA_PMD_ERR("Failed to alloc mem for cgr_tx\n");
2002                         ret = -ENOMEM;
2003                         goto free_rx;
2004                 }
2005
2006                 ret = qman_alloc_cgrid_range(&cgrid_tx[0], MAX_DPAA_CORES,
2007                                              1, 0);
2008                 if (ret != MAX_DPAA_CORES) {
2009                         DPAA_PMD_WARN("insufficient CGRIDs available");
2010                         ret = -EINVAL;
2011                         goto free_rx;
2012                 }
2013         } else {
2014                 dpaa_intf->cgr_tx = NULL;
2015         }
2016
2017
2018         for (loop = 0; loop < MAX_DPAA_CORES; loop++) {
2019                 if (dpaa_intf->cgr_tx)
2020                         dpaa_intf->cgr_tx[loop].cgrid = cgrid_tx[loop];
2021
2022                 ret = dpaa_tx_queue_init(&dpaa_intf->tx_queues[loop],
2023                         fman_intf,
2024                         dpaa_intf->cgr_tx ? &dpaa_intf->cgr_tx[loop] : NULL);
2025                 if (ret)
2026                         goto free_tx;
2027                 dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf;
2028         }
2029         dpaa_intf->nb_tx_queues = MAX_DPAA_CORES;
2030
2031 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
2032         ret = dpaa_debug_queue_init(&dpaa_intf->debug_queues
2033                         [DPAA_DEBUG_FQ_RX_ERROR], fman_intf->fqid_rx_err);
2034         if (ret) {
2035                 DPAA_PMD_ERR("DPAA RX ERROR queue init failed!");
2036                 goto free_tx;
2037         }
2038         dpaa_intf->debug_queues[DPAA_DEBUG_FQ_RX_ERROR].dpaa_intf = dpaa_intf;
2039         ret = dpaa_debug_queue_init(&dpaa_intf->debug_queues
2040                         [DPAA_DEBUG_FQ_TX_ERROR], fman_intf->fqid_tx_err);
2041         if (ret) {
2042                 DPAA_PMD_ERR("DPAA TX ERROR queue init failed!");
2043                 goto free_tx;
2044         }
2045         dpaa_intf->debug_queues[DPAA_DEBUG_FQ_TX_ERROR].dpaa_intf = dpaa_intf;
2046 #endif
2047
2048         DPAA_PMD_DEBUG("All frame queues created");
2049
2050         /* Get the initial configuration for flow control */
2051         dpaa_fc_set_default(dpaa_intf, fman_intf);
2052
2053         /* reset bpool list, initialize bpool dynamically */
2054         list_for_each_entry_safe(bp, tmp_bp, &cfg->fman_if->bpool_list, node) {
2055                 list_del(&bp->node);
2056                 rte_free(bp);
2057         }
2058
2059         /* Populate ethdev structure */
2060         eth_dev->dev_ops = &dpaa_devops;
2061         eth_dev->rx_queue_count = dpaa_dev_rx_queue_count;
2062         eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
2063         eth_dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
2064
2065         /* Allocate memory for storing MAC addresses */
2066         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr",
2067                 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER, 0);
2068         if (eth_dev->data->mac_addrs == NULL) {
2069                 DPAA_PMD_ERR("Failed to allocate %d bytes needed to "
2070                                                 "store MAC addresses",
2071                                 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER);
2072                 ret = -ENOMEM;
2073                 goto free_tx;
2074         }
2075
2076         /* copy the primary mac address */
2077         rte_ether_addr_copy(&fman_intf->mac_addr, &eth_dev->data->mac_addrs[0]);
2078
2079         RTE_LOG(INFO, PMD, "net: dpaa: %s: %02x:%02x:%02x:%02x:%02x:%02x\n",
2080                 dpaa_device->name,
2081                 fman_intf->mac_addr.addr_bytes[0],
2082                 fman_intf->mac_addr.addr_bytes[1],
2083                 fman_intf->mac_addr.addr_bytes[2],
2084                 fman_intf->mac_addr.addr_bytes[3],
2085                 fman_intf->mac_addr.addr_bytes[4],
2086                 fman_intf->mac_addr.addr_bytes[5]);
2087
2088         if (!fman_intf->is_shared_mac) {
2089                 /* Configure error packet handling */
2090                 fman_if_receive_rx_errors(fman_intf,
2091                         FM_FD_RX_STATUS_ERR_MASK);
2092                 /* Disable RX mode */
2093                 fman_if_disable_rx(fman_intf);
2094                 /* Disable promiscuous mode */
2095                 fman_if_promiscuous_disable(fman_intf);
2096                 /* Disable multicast */
2097                 fman_if_reset_mcast_filter_table(fman_intf);
2098                 /* Reset interface statistics */
2099                 fman_if_stats_reset(fman_intf);
2100                 /* Disable SG by default */
2101                 fman_if_set_sg(fman_intf, 0);
2102                 fman_if_set_maxfrm(fman_intf,
2103                                    RTE_ETHER_MAX_LEN + VLAN_TAG_SIZE);
2104         }
2105
2106         return 0;
2107
2108 free_tx:
2109         rte_free(dpaa_intf->tx_queues);
2110         dpaa_intf->tx_queues = NULL;
2111         dpaa_intf->nb_tx_queues = 0;
2112
2113 free_rx:
2114         rte_free(dpaa_intf->cgr_rx);
2115         rte_free(dpaa_intf->cgr_tx);
2116         rte_free(dpaa_intf->rx_queues);
2117         dpaa_intf->rx_queues = NULL;
2118         dpaa_intf->nb_rx_queues = 0;
2119         return ret;
2120 }
2121
2122 static int
2123 rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv,
2124                struct rte_dpaa_device *dpaa_dev)
2125 {
2126         int diag;
2127         int ret;
2128         struct rte_eth_dev *eth_dev;
2129
2130         PMD_INIT_FUNC_TRACE();
2131
2132         if ((DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE) >
2133                 RTE_PKTMBUF_HEADROOM) {
2134                 DPAA_PMD_ERR(
2135                 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA Annotation req(%d)",
2136                 RTE_PKTMBUF_HEADROOM,
2137                 DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE);
2138
2139                 return -1;
2140         }
2141
2142         /* In case of secondary process, the device is already configured
2143          * and no further action is required, except portal initialization
2144          * and verifying secondary attachment to port name.
2145          */
2146         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2147                 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name);
2148                 if (!eth_dev)
2149                         return -ENOMEM;
2150                 eth_dev->device = &dpaa_dev->device;
2151                 eth_dev->dev_ops = &dpaa_devops;
2152
2153                 ret = dpaa_dev_init_secondary(eth_dev);
2154                 if (ret != 0) {
2155                         RTE_LOG(ERR, PMD, "secondary dev init failed\n");
2156                         return ret;
2157                 }
2158
2159                 rte_eth_dev_probing_finish(eth_dev);
2160                 return 0;
2161         }
2162
2163         if (!is_global_init && (rte_eal_process_type() == RTE_PROC_PRIMARY)) {
2164                 if (access("/tmp/fmc.bin", F_OK) == -1) {
2165                         DPAA_PMD_INFO("* FMC not configured.Enabling default mode");
2166                         default_q = 1;
2167                 }
2168
2169                 if (!(default_q || fmc_q)) {
2170                         if (dpaa_fm_init()) {
2171                                 DPAA_PMD_ERR("FM init failed\n");
2172                                 return -1;
2173                         }
2174                 }
2175
2176                 /* disabling the default push mode for LS1043 */
2177                 if (dpaa_svr_family == SVR_LS1043A_FAMILY)
2178                         dpaa_push_mode_max_queue = 0;
2179
2180                 /* if push mode queues to be enabled. Currenly we are allowing
2181                  * only one queue per thread.
2182                  */
2183                 if (getenv("DPAA_PUSH_QUEUES_NUMBER")) {
2184                         dpaa_push_mode_max_queue =
2185                                         atoi(getenv("DPAA_PUSH_QUEUES_NUMBER"));
2186                         if (dpaa_push_mode_max_queue > DPAA_MAX_PUSH_MODE_QUEUE)
2187                             dpaa_push_mode_max_queue = DPAA_MAX_PUSH_MODE_QUEUE;
2188                 }
2189
2190                 is_global_init = 1;
2191         }
2192
2193         if (unlikely(!DPAA_PER_LCORE_PORTAL)) {
2194                 ret = rte_dpaa_portal_init((void *)1);
2195                 if (ret) {
2196                         DPAA_PMD_ERR("Unable to initialize portal");
2197                         return ret;
2198                 }
2199         }
2200
2201         eth_dev = rte_eth_dev_allocate(dpaa_dev->name);
2202         if (!eth_dev)
2203                 return -ENOMEM;
2204
2205         eth_dev->data->dev_private =
2206                         rte_zmalloc("ethdev private structure",
2207                                         sizeof(struct dpaa_if),
2208                                         RTE_CACHE_LINE_SIZE);
2209         if (!eth_dev->data->dev_private) {
2210                 DPAA_PMD_ERR("Cannot allocate memzone for port data");
2211                 rte_eth_dev_release_port(eth_dev);
2212                 return -ENOMEM;
2213         }
2214
2215         eth_dev->device = &dpaa_dev->device;
2216         dpaa_dev->eth_dev = eth_dev;
2217
2218         qman_ern_register_cb(dpaa_free_mbuf);
2219
2220         if (dpaa_drv->drv_flags & RTE_DPAA_DRV_INTR_LSC)
2221                 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;
2222
2223         /* Invoke PMD device initialization function */
2224         diag = dpaa_dev_init(eth_dev);
2225         if (diag == 0) {
2226                 rte_eth_dev_probing_finish(eth_dev);
2227                 return 0;
2228         }
2229
2230         rte_eth_dev_release_port(eth_dev);
2231         return diag;
2232 }
2233
2234 static int
2235 rte_dpaa_remove(struct rte_dpaa_device *dpaa_dev)
2236 {
2237         struct rte_eth_dev *eth_dev;
2238         int ret;
2239
2240         PMD_INIT_FUNC_TRACE();
2241
2242         eth_dev = dpaa_dev->eth_dev;
2243         dpaa_eth_dev_close(eth_dev);
2244         ret = rte_eth_dev_release_port(eth_dev);
2245
2246         return ret;
2247 }
2248
2249 static void __attribute__((destructor(102))) dpaa_finish(void)
2250 {
2251         /* For secondary, primary will do all the cleanup */
2252         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2253                 return;
2254
2255         if (!(default_q || fmc_q)) {
2256                 unsigned int i;
2257
2258                 for (i = 0; i < RTE_MAX_ETHPORTS; i++) {
2259                         if (rte_eth_devices[i].dev_ops == &dpaa_devops) {
2260                                 struct rte_eth_dev *dev = &rte_eth_devices[i];
2261                                 struct dpaa_if *dpaa_intf =
2262                                         dev->data->dev_private;
2263                                 struct fman_if *fif =
2264                                         dev->process_private;
2265                                 if (dpaa_intf->port_handle)
2266                                         if (dpaa_fm_deconfig(dpaa_intf, fif))
2267                                                 DPAA_PMD_WARN("DPAA FM "
2268                                                         "deconfig failed\n");
2269                                 if (fif->num_profiles) {
2270                                         if (dpaa_port_vsp_cleanup(dpaa_intf,
2271                                                                   fif))
2272                                                 DPAA_PMD_WARN("DPAA FM vsp cleanup failed\n");
2273                                 }
2274                         }
2275                 }
2276                 if (is_global_init)
2277                         if (dpaa_fm_term())
2278                                 DPAA_PMD_WARN("DPAA FM term failed\n");
2279
2280                 is_global_init = 0;
2281
2282                 DPAA_PMD_INFO("DPAA fman cleaned up");
2283         }
2284 }
2285
2286 static struct rte_dpaa_driver rte_dpaa_pmd = {
2287         .drv_flags = RTE_DPAA_DRV_INTR_LSC,
2288         .drv_type = FSL_DPAA_ETH,
2289         .probe = rte_dpaa_probe,
2290         .remove = rte_dpaa_remove,
2291 };
2292
2293 RTE_PMD_REGISTER_DPAA(net_dpaa, rte_dpaa_pmd);
2294 RTE_LOG_REGISTER(dpaa_logtype_pmd, pmd.net.dpaa, NOTICE);