drivers/net/dpaa/dpaa_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  *   Copyright 2016 Freescale Semiconductor, Inc. All rights reserved.
   4  *   Copyright 2017-2020 NXP
   5  *
   6  */
   7 /* System headers */
   8 #include <stdio.h>
   9 #include <inttypes.h>
  10 #include <unistd.h>
  11 #include <limits.h>
  12 #include <sched.h>
  13 #include <signal.h>
  14 #include <pthread.h>
  15 #include <sys/types.h>
  16 #include <sys/syscall.h>
  17
  18 #include <rte_string_fns.h>
  19 #include <rte_byteorder.h>
  20 #include <rte_common.h>
  21 #include <rte_interrupts.h>
  22 #include <rte_log.h>
  23 #include <rte_debug.h>
  24 #include <rte_pci.h>
  25 #include <rte_atomic.h>
  26 #include <rte_branch_prediction.h>
  27 #include <rte_memory.h>
  28 #include <rte_tailq.h>
  29 #include <rte_eal.h>
  30 #include <rte_alarm.h>
  31 #include <rte_ether.h>
  32 #include <rte_ethdev_driver.h>
  33 #include <rte_malloc.h>
  34 #include <rte_ring.h>
  35
  36 #include <rte_dpaa_bus.h>
  37 #include <rte_dpaa_logs.h>
  38 #include <dpaa_mempool.h>
  39
  40 #include <dpaa_ethdev.h>
  41 #include <dpaa_rxtx.h>
  42 #include <dpaa_flow.h>
  43 #include <rte_pmd_dpaa.h>
  44
  45 #include <fsl_usd.h>
  46 #include <fsl_qman.h>
  47 #include <fsl_bman.h>
  48 #include <fsl_fman.h>
  49 #include <process.h>
  50 #include <fmlib/fm_ext.h>
  51
  52 /* Supported Rx offloads */
  53 static uint64_t dev_rx_offloads_sup =
  54                 DEV_RX_OFFLOAD_JUMBO_FRAME |
  55                 DEV_RX_OFFLOAD_SCATTER;
  56
  57 /* Rx offloads which cannot be disabled */
  58 static uint64_t dev_rx_offloads_nodis =
  59                 DEV_RX_OFFLOAD_IPV4_CKSUM |
  60                 DEV_RX_OFFLOAD_UDP_CKSUM |
  61                 DEV_RX_OFFLOAD_TCP_CKSUM |
  62                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
  63                 DEV_RX_OFFLOAD_RSS_HASH;
  64
  65 /* Supported Tx offloads */
  66 static uint64_t dev_tx_offloads_sup =
  67                 DEV_TX_OFFLOAD_MT_LOCKFREE |
  68                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
  69
  70 /* Tx offloads which cannot be disabled */
  71 static uint64_t dev_tx_offloads_nodis =
  72                 DEV_TX_OFFLOAD_IPV4_CKSUM |
  73                 DEV_TX_OFFLOAD_UDP_CKSUM |
  74                 DEV_TX_OFFLOAD_TCP_CKSUM |
  75                 DEV_TX_OFFLOAD_SCTP_CKSUM |
  76                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
  77                 DEV_TX_OFFLOAD_MULTI_SEGS;
  78
  79 /* Keep track of whether QMAN and BMAN have been globally initialized */
  80 static int is_global_init;
  81 static int fmc_q = 1;   /* Indicates the use of static fmc for distribution */
  82 static int default_q;   /* use default queue - FMC is not executed*/
  83 /* At present we only allow up to 4 push mode queues as default - as each of
  84  * this queue need dedicated portal and we are short of portals.
  85  */
  86 #define DPAA_MAX_PUSH_MODE_QUEUE       8
  87 #define DPAA_DEFAULT_PUSH_MODE_QUEUE   4
  88
  89 static int dpaa_push_mode_max_queue = DPAA_DEFAULT_PUSH_MODE_QUEUE;
  90 static int dpaa_push_queue_idx; /* Queue index which are in push mode*/
  91
  92
  93 /* Per RX FQ Taildrop in frame count */
  94 static unsigned int td_threshold = CGR_RX_PERFQ_THRESH;
  95
  96 /* Per TX FQ Taildrop in frame count, disabled by default */
  97 static unsigned int td_tx_threshold;
  98
  99 struct rte_dpaa_xstats_name_off {
 100         char name[RTE_ETH_XSTATS_NAME_SIZE];
 101         uint32_t offset;
 102 };
 103
 104 static const struct rte_dpaa_xstats_name_off dpaa_xstats_strings[] = {
 105         {"rx_align_err",
 106                 offsetof(struct dpaa_if_stats, raln)},
 107         {"rx_valid_pause",
 108                 offsetof(struct dpaa_if_stats, rxpf)},
 109         {"rx_fcs_err",
 110                 offsetof(struct dpaa_if_stats, rfcs)},
 111         {"rx_vlan_frame",
 112                 offsetof(struct dpaa_if_stats, rvlan)},
 113         {"rx_frame_err",
 114                 offsetof(struct dpaa_if_stats, rerr)},
 115         {"rx_drop_err",
 116                 offsetof(struct dpaa_if_stats, rdrp)},
 117         {"rx_undersized",
 118                 offsetof(struct dpaa_if_stats, rund)},
 119         {"rx_oversize_err",
 120                 offsetof(struct dpaa_if_stats, rovr)},
 121         {"rx_fragment_pkt",
 122                 offsetof(struct dpaa_if_stats, rfrg)},
 123         {"tx_valid_pause",
 124                 offsetof(struct dpaa_if_stats, txpf)},
 125         {"tx_fcs_err",
 126                 offsetof(struct dpaa_if_stats, terr)},
 127         {"tx_vlan_frame",
 128                 offsetof(struct dpaa_if_stats, tvlan)},
 129         {"rx_undersized",
 130                 offsetof(struct dpaa_if_stats, tund)},
 131 };
 132
 133 static struct rte_dpaa_driver rte_dpaa_pmd;
 134
 135 static int
 136 dpaa_eth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info);
 137
 138 static int dpaa_eth_link_update(struct rte_eth_dev *dev,
 139                                 int wait_to_complete __rte_unused);
 140
 141 static void dpaa_interrupt_handler(void *param);
 142
 143 static inline void
 144 dpaa_poll_queue_default_config(struct qm_mcc_initfq *opts)
 145 {
 146         memset(opts, 0, sizeof(struct qm_mcc_initfq));
 147         opts->we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
 148         opts->fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | QM_FQCTRL_CTXASTASHING |
 149                            QM_FQCTRL_PREFERINCACHE;
 150         opts->fqd.context_a.stashing.exclusive = 0;
 151         if (dpaa_svr_family != SVR_LS1046A_FAMILY)
 152                 opts->fqd.context_a.stashing.annotation_cl =
 153                                                 DPAA_IF_RX_ANNOTATION_STASH;
 154         opts->fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
 155         opts->fqd.context_a.stashing.context_cl = DPAA_IF_RX_CONTEXT_STASH;
 156 }
 157
 158 static int
 159 dpaa_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 160 {
 161         uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
 162                                 + VLAN_TAG_SIZE;
 163         uint32_t buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
 164
 165         PMD_INIT_FUNC_TRACE();
 166
 167         if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA_MAX_RX_PKT_LEN)
 168                 return -EINVAL;
 169         /*
 170          * Refuse mtu that requires the support of scattered packets
 171          * when this feature has not been enabled before.
 172          */
 173         if (dev->data->min_rx_buf_size &&
 174                 !dev->data->scattered_rx && frame_size > buffsz) {
 175                 DPAA_PMD_ERR("SG not enabled, will not fit in one buffer");
 176                 return -EINVAL;
 177         }
 178
 179         /* check <seg size> * <max_seg>  >= max_frame */
 180         if (dev->data->min_rx_buf_size && dev->data->scattered_rx &&
 181                 (frame_size > buffsz * DPAA_SGT_MAX_ENTRIES)) {
 182                 DPAA_PMD_ERR("Too big to fit for Max SG list %d",
 183                                 buffsz * DPAA_SGT_MAX_ENTRIES);
 184                 return -EINVAL;
 185         }
 186
 187         if (frame_size > RTE_ETHER_MAX_LEN)
 188                 dev->data->dev_conf.rxmode.offloads |=
 189                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 190         else
 191                 dev->data->dev_conf.rxmode.offloads &=
 192                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 193
 194         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 195
 196         fman_if_set_maxfrm(dev->process_private, frame_size);
 197
 198         return 0;
 199 }
 200
 201 static int
 202 dpaa_eth_dev_configure(struct rte_eth_dev *dev)
 203 {
 204         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 205         uint64_t rx_offloads = eth_conf->rxmode.offloads;
 206         uint64_t tx_offloads = eth_conf->txmode.offloads;
 207         struct rte_device *rdev = dev->device;
 208         struct rte_eth_link *link = &dev->data->dev_link;
 209         struct rte_dpaa_device *dpaa_dev;
 210         struct fman_if *fif = dev->process_private;
 211         struct __fman_if *__fif;
 212         struct rte_intr_handle *intr_handle;
 213         int speed, duplex;
 214         int ret;
 215
 216         PMD_INIT_FUNC_TRACE();
 217
 218         dpaa_dev = container_of(rdev, struct rte_dpaa_device, device);
 219         intr_handle = &dpaa_dev->intr_handle;
 220         __fif = container_of(fif, struct __fman_if, __if);
 221
 222         /* Rx offloads which are enabled by default */
 223         if (dev_rx_offloads_nodis & ~rx_offloads) {
 224                 DPAA_PMD_INFO(
 225                 "Some of rx offloads enabled by default - requested 0x%" PRIx64
 226                 " fixed are 0x%" PRIx64,
 227                 rx_offloads, dev_rx_offloads_nodis);
 228         }
 229
 230         /* Tx offloads which are enabled by default */
 231         if (dev_tx_offloads_nodis & ~tx_offloads) {
 232                 DPAA_PMD_INFO(
 233                 "Some of tx offloads enabled by default - requested 0x%" PRIx64
 234                 " fixed are 0x%" PRIx64,
 235                 tx_offloads, dev_tx_offloads_nodis);
 236         }
 237
 238         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 239                 uint32_t max_len;
 240
 241                 DPAA_PMD_DEBUG("enabling jumbo");
 242
 243                 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <=
 244                     DPAA_MAX_RX_PKT_LEN)
 245                         max_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
 246                 else {
 247                         DPAA_PMD_INFO("enabling jumbo override conf max len=%d "
 248                                 "supported is %d",
 249                                 dev->data->dev_conf.rxmode.max_rx_pkt_len,
 250                                 DPAA_MAX_RX_PKT_LEN);
 251                         max_len = DPAA_MAX_RX_PKT_LEN;
 252                 }
 253
 254                 fman_if_set_maxfrm(dev->process_private, max_len);
 255                 dev->data->mtu = max_len
 256                         - RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE;
 257         }
 258
 259         if (rx_offloads & DEV_RX_OFFLOAD_SCATTER) {
 260                 DPAA_PMD_DEBUG("enabling scatter mode");
 261                 fman_if_set_sg(dev->process_private, 1);
 262                 dev->data->scattered_rx = 1;
 263         }
 264
 265         if (!(default_q || fmc_q)) {
 266                 if (dpaa_fm_config(dev,
 267                         eth_conf->rx_adv_conf.rss_conf.rss_hf)) {
 268                         dpaa_write_fm_config_to_file();
 269                         DPAA_PMD_ERR("FM port configuration: Failed\n");
 270                         return -1;
 271                 }
 272                 dpaa_write_fm_config_to_file();
 273         }
 274
 275         /* if the interrupts were configured on this devices*/
 276         if (intr_handle && intr_handle->fd) {
 277                 if (dev->data->dev_conf.intr_conf.lsc != 0)
 278                         rte_intr_callback_register(intr_handle,
 279                                            dpaa_interrupt_handler,
 280                                            (void *)dev);
 281
 282                 ret = dpaa_intr_enable(__fif->node_name, intr_handle->fd);
 283                 if (ret) {
 284                         if (dev->data->dev_conf.intr_conf.lsc != 0) {
 285                                 rte_intr_callback_unregister(intr_handle,
 286                                         dpaa_interrupt_handler,
 287                                         (void *)dev);
 288                                 if (ret == EINVAL)
 289                                         printf("Failed to enable interrupt: Not Supported\n");
 290                                 else
 291                                         printf("Failed to enable interrupt\n");
 292                         }
 293                         dev->data->dev_conf.intr_conf.lsc = 0;
 294                         dev->data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC;
 295                 }
 296         }
 297
 298         /* Wait for link status to get updated */
 299         if (!link->link_status)
 300                 sleep(1);
 301
 302         /* Configure link only if link is UP*/
 303         if (link->link_status) {
 304                 if (eth_conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
 305                         /* Start autoneg only if link is not in autoneg mode */
 306                         if (!link->link_autoneg)
 307                                 dpaa_restart_link_autoneg(__fif->node_name);
 308                 } else if (eth_conf->link_speeds & ETH_LINK_SPEED_FIXED) {
 309                         switch (eth_conf->link_speeds & ~ETH_LINK_SPEED_FIXED) {
 310                         case ETH_LINK_SPEED_10M_HD:
 311                                 speed = ETH_SPEED_NUM_10M;
 312                                 duplex = ETH_LINK_HALF_DUPLEX;
 313                                 break;
 314                         case ETH_LINK_SPEED_10M:
 315                                 speed = ETH_SPEED_NUM_10M;
 316                                 duplex = ETH_LINK_FULL_DUPLEX;
 317                                 break;
 318                         case ETH_LINK_SPEED_100M_HD:
 319                                 speed = ETH_SPEED_NUM_100M;
 320                                 duplex = ETH_LINK_HALF_DUPLEX;
 321                                 break;
 322                         case ETH_LINK_SPEED_100M:
 323                                 speed = ETH_SPEED_NUM_100M;
 324                                 duplex = ETH_LINK_FULL_DUPLEX;
 325                                 break;
 326                         case ETH_LINK_SPEED_1G:
 327                                 speed = ETH_SPEED_NUM_1G;
 328                                 duplex = ETH_LINK_FULL_DUPLEX;
 329                                 break;
 330                         case ETH_LINK_SPEED_2_5G:
 331                                 speed = ETH_SPEED_NUM_2_5G;
 332                                 duplex = ETH_LINK_FULL_DUPLEX;
 333                                 break;
 334                         case ETH_LINK_SPEED_10G:
 335                                 speed = ETH_SPEED_NUM_10G;
 336                                 duplex = ETH_LINK_FULL_DUPLEX;
 337                                 break;
 338                         default:
 339                                 speed = ETH_SPEED_NUM_NONE;
 340                                 duplex = ETH_LINK_FULL_DUPLEX;
 341                                 break;
 342                         }
 343                         /* Set link speed */
 344                         dpaa_update_link_speed(__fif->node_name, speed, duplex);
 345                 } else {
 346                         /* Manual autoneg - custom advertisement speed. */
 347                         printf("Custom Advertisement speeds not supported\n");
 348                 }
 349         }
 350
 351         return 0;
 352 }
 353
 354 static const uint32_t *
 355 dpaa_supported_ptypes_get(struct rte_eth_dev *dev)
 356 {
 357         static const uint32_t ptypes[] = {
 358                 RTE_PTYPE_L2_ETHER,
 359                 RTE_PTYPE_L2_ETHER_VLAN,
 360                 RTE_PTYPE_L2_ETHER_ARP,
 361                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
 362                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
 363                 RTE_PTYPE_L4_ICMP,
 364                 RTE_PTYPE_L4_TCP,
 365                 RTE_PTYPE_L4_UDP,
 366                 RTE_PTYPE_L4_FRAG,
 367                 RTE_PTYPE_L4_TCP,
 368                 RTE_PTYPE_L4_UDP,
 369                 RTE_PTYPE_L4_SCTP
 370         };
 371
 372         PMD_INIT_FUNC_TRACE();
 373
 374         if (dev->rx_pkt_burst == dpaa_eth_queue_rx)
 375                 return ptypes;
 376         return NULL;
 377 }
 378
 379 static void dpaa_interrupt_handler(void *param)
 380 {
 381         struct rte_eth_dev *dev = param;
 382         struct rte_device *rdev = dev->device;
 383         struct rte_dpaa_device *dpaa_dev;
 384         struct rte_intr_handle *intr_handle;
 385         uint64_t buf;
 386         int bytes_read;
 387
 388         dpaa_dev = container_of(rdev, struct rte_dpaa_device, device);
 389         intr_handle = &dpaa_dev->intr_handle;
 390
 391         bytes_read = read(intr_handle->fd, &buf, sizeof(uint64_t));
 392         if (bytes_read < 0)
 393                 DPAA_PMD_ERR("Error reading eventfd\n");
 394         dpaa_eth_link_update(dev, 0);
 395         rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
 396 }
 397
 398 static int dpaa_eth_dev_start(struct rte_eth_dev *dev)
 399 {
 400         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 401
 402         PMD_INIT_FUNC_TRACE();
 403
 404         if (!(default_q || fmc_q))
 405                 dpaa_write_fm_config_to_file();
 406
 407         /* Change tx callback to the real one */
 408         if (dpaa_intf->cgr_tx)
 409                 dev->tx_pkt_burst = dpaa_eth_queue_tx_slow;
 410         else
 411                 dev->tx_pkt_burst = dpaa_eth_queue_tx;
 412
 413         fman_if_enable_rx(dev->process_private);
 414
 415         return 0;
 416 }
 417
 418 static void dpaa_eth_dev_stop(struct rte_eth_dev *dev)
 419 {
 420         struct fman_if *fif = dev->process_private;
 421
 422         PMD_INIT_FUNC_TRACE();
 423
 424         if (!fif->is_shared_mac)
 425                 fman_if_disable_rx(fif);
 426         dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
 427 }
 428
 429 static int dpaa_eth_dev_close(struct rte_eth_dev *dev)
 430 {
 431         struct fman_if *fif = dev->process_private;
 432         struct __fman_if *__fif;
 433         struct rte_device *rdev = dev->device;
 434         struct rte_dpaa_device *dpaa_dev;
 435         struct rte_intr_handle *intr_handle;
 436         struct rte_eth_link *link = &dev->data->dev_link;
 437         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 438         int loop;
 439
 440         PMD_INIT_FUNC_TRACE();
 441
 442         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 443                 return 0;
 444
 445         if (!dpaa_intf) {
 446                 DPAA_PMD_WARN("Already closed or not started");
 447                 return -1;
 448         }
 449
 450         /* DPAA FM deconfig */
 451         if (!(default_q || fmc_q)) {
 452                 if (dpaa_fm_deconfig(dpaa_intf, dev->process_private))
 453                         DPAA_PMD_WARN("DPAA FM deconfig failed\n");
 454         }
 455
 456         dpaa_dev = container_of(rdev, struct rte_dpaa_device, device);
 457         intr_handle = &dpaa_dev->intr_handle;
 458         __fif = container_of(fif, struct __fman_if, __if);
 459
 460         dpaa_eth_dev_stop(dev);
 461
 462         /* Reset link to autoneg */
 463         if (link->link_status && !link->link_autoneg)
 464                 dpaa_restart_link_autoneg(__fif->node_name);
 465
 466         if (intr_handle && intr_handle->fd &&
 467             dev->data->dev_conf.intr_conf.lsc != 0) {
 468                 dpaa_intr_disable(__fif->node_name);
 469                 rte_intr_callback_unregister(intr_handle,
 470                                              dpaa_interrupt_handler,
 471                                              (void *)dev);
 472         }
 473
 474         /* release configuration memory */
 475         if (dpaa_intf->fc_conf)
 476                 rte_free(dpaa_intf->fc_conf);
 477
 478         /* Release RX congestion Groups */
 479         if (dpaa_intf->cgr_rx) {
 480                 for (loop = 0; loop < dpaa_intf->nb_rx_queues; loop++)
 481                         qman_delete_cgr(&dpaa_intf->cgr_rx[loop]);
 482
 483                 qman_release_cgrid_range(dpaa_intf->cgr_rx[loop].cgrid,
 484                                          dpaa_intf->nb_rx_queues);
 485         }
 486
 487         rte_free(dpaa_intf->cgr_rx);
 488         dpaa_intf->cgr_rx = NULL;
 489         /* Release TX congestion Groups */
 490         if (dpaa_intf->cgr_tx) {
 491                 for (loop = 0; loop < MAX_DPAA_CORES; loop++)
 492                         qman_delete_cgr(&dpaa_intf->cgr_tx[loop]);
 493
 494                 qman_release_cgrid_range(dpaa_intf->cgr_tx[loop].cgrid,
 495                                          MAX_DPAA_CORES);
 496                 rte_free(dpaa_intf->cgr_tx);
 497                 dpaa_intf->cgr_tx = NULL;
 498         }
 499
 500         rte_free(dpaa_intf->rx_queues);
 501         dpaa_intf->rx_queues = NULL;
 502
 503         rte_free(dpaa_intf->tx_queues);
 504         dpaa_intf->tx_queues = NULL;
 505
 506         dev->dev_ops = NULL;
 507         dev->rx_pkt_burst = NULL;
 508         dev->tx_pkt_burst = NULL;
 509
 510         return 0;
 511 }
 512
 513 static int
 514 dpaa_fw_version_get(struct rte_eth_dev *dev __rte_unused,
 515                      char *fw_version,
 516                      size_t fw_size)
 517 {
 518         int ret;
 519         FILE *svr_file = NULL;
 520         unsigned int svr_ver = 0;
 521
 522         PMD_INIT_FUNC_TRACE();
 523
 524         svr_file = fopen(DPAA_SOC_ID_FILE, "r");
 525         if (!svr_file) {
 526                 DPAA_PMD_ERR("Unable to open SoC device");
 527                 return -ENOTSUP; /* Not supported on this infra */
 528         }
 529         if (fscanf(svr_file, "svr:%x", &svr_ver) > 0)
 530                 dpaa_svr_family = svr_ver & SVR_MASK;
 531         else
 532                 DPAA_PMD_ERR("Unable to read SoC device");
 533
 534         fclose(svr_file);
 535
 536         ret = snprintf(fw_version, fw_size, "SVR:%x-fman-v%x",
 537                        svr_ver, fman_ip_rev);
 538         ret += 1; /* add the size of '\0' */
 539
 540         if (fw_size < (uint32_t)ret)
 541                 return ret;
 542         else
 543                 return 0;
 544 }
 545
 546 static int dpaa_eth_dev_info(struct rte_eth_dev *dev,
 547                              struct rte_eth_dev_info *dev_info)
 548 {
 549         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 550         struct fman_if *fif = dev->process_private;
 551
 552         DPAA_PMD_DEBUG(": %s", dpaa_intf->name);
 553
 554         dev_info->max_rx_queues = dpaa_intf->nb_rx_queues;
 555         dev_info->max_tx_queues = dpaa_intf->nb_tx_queues;
 556         dev_info->max_rx_pktlen = DPAA_MAX_RX_PKT_LEN;
 557         dev_info->max_mac_addrs = DPAA_MAX_MAC_FILTER;
 558         dev_info->max_hash_mac_addrs = 0;
 559         dev_info->max_vfs = 0;
 560         dev_info->max_vmdq_pools = ETH_16_POOLS;
 561         dev_info->flow_type_rss_offloads = DPAA_RSS_OFFLOAD_ALL;
 562
 563         if (fif->mac_type == fman_mac_1g) {
 564                 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD
 565                                         | ETH_LINK_SPEED_10M
 566                                         | ETH_LINK_SPEED_100M_HD
 567                                         | ETH_LINK_SPEED_100M
 568                                         | ETH_LINK_SPEED_1G;
 569         } else if (fif->mac_type == fman_mac_2_5g) {
 570                 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD
 571                                         | ETH_LINK_SPEED_10M
 572                                         | ETH_LINK_SPEED_100M_HD
 573                                         | ETH_LINK_SPEED_100M
 574                                         | ETH_LINK_SPEED_1G
 575                                         | ETH_LINK_SPEED_2_5G;
 576         } else if (fif->mac_type == fman_mac_10g) {
 577                 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD
 578                                         | ETH_LINK_SPEED_10M
 579                                         | ETH_LINK_SPEED_100M_HD
 580                                         | ETH_LINK_SPEED_100M
 581                                         | ETH_LINK_SPEED_1G
 582                                         | ETH_LINK_SPEED_2_5G
 583                                         | ETH_LINK_SPEED_10G;
 584         } else {
 585                 DPAA_PMD_ERR("invalid link_speed: %s, %d",
 586                              dpaa_intf->name, fif->mac_type);
 587                 return -EINVAL;
 588         }
 589
 590         dev_info->rx_offload_capa = dev_rx_offloads_sup |
 591                                         dev_rx_offloads_nodis;
 592         dev_info->tx_offload_capa = dev_tx_offloads_sup |
 593                                         dev_tx_offloads_nodis;
 594         dev_info->default_rxportconf.burst_size = DPAA_DEF_RX_BURST_SIZE;
 595         dev_info->default_txportconf.burst_size = DPAA_DEF_TX_BURST_SIZE;
 596         dev_info->default_rxportconf.nb_queues = 1;
 597         dev_info->default_txportconf.nb_queues = 1;
 598         dev_info->default_txportconf.ring_size = CGR_TX_CGR_THRESH;
 599         dev_info->default_rxportconf.ring_size = CGR_RX_PERFQ_THRESH;
 600
 601         return 0;
 602 }
 603
 604 static int
 605 dpaa_dev_rx_burst_mode_get(struct rte_eth_dev *dev,
 606                         __rte_unused uint16_t queue_id,
 607                         struct rte_eth_burst_mode *mode)
 608 {
 609         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 610         int ret = -EINVAL;
 611         unsigned int i;
 612         const struct burst_info {
 613                 uint64_t flags;
 614                 const char *output;
 615         } rx_offload_map[] = {
 616                         {DEV_RX_OFFLOAD_JUMBO_FRAME, " Jumbo frame,"},
 617                         {DEV_RX_OFFLOAD_SCATTER, " Scattered,"},
 618                         {DEV_RX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"},
 619                         {DEV_RX_OFFLOAD_UDP_CKSUM, " UDP csum,"},
 620                         {DEV_RX_OFFLOAD_TCP_CKSUM, " TCP csum,"},
 621                         {DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
 622                         {DEV_RX_OFFLOAD_RSS_HASH, " RSS,"}
 623         };
 624
 625         /* Update Rx offload info */
 626         for (i = 0; i < RTE_DIM(rx_offload_map); i++) {
 627                 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) {
 628                         snprintf(mode->info, sizeof(mode->info), "%s",
 629                                 rx_offload_map[i].output);
 630                         ret = 0;
 631                         break;
 632                 }
 633         }
 634         return ret;
 635 }
 636
 637 static int
 638 dpaa_dev_tx_burst_mode_get(struct rte_eth_dev *dev,
 639                         __rte_unused uint16_t queue_id,
 640                         struct rte_eth_burst_mode *mode)
 641 {
 642         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 643         int ret = -EINVAL;
 644         unsigned int i;
 645         const struct burst_info {
 646                 uint64_t flags;
 647                 const char *output;
 648         } tx_offload_map[] = {
 649                         {DEV_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"},
 650                         {DEV_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"},
 651                         {DEV_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"},
 652                         {DEV_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"},
 653                         {DEV_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"},
 654                         {DEV_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
 655                         {DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
 656                         {DEV_TX_OFFLOAD_MULTI_SEGS, " Scattered,"}
 657         };
 658
 659         /* Update Tx offload info */
 660         for (i = 0; i < RTE_DIM(tx_offload_map); i++) {
 661                 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) {
 662                         snprintf(mode->info, sizeof(mode->info), "%s",
 663                                 tx_offload_map[i].output);
 664                         ret = 0;
 665                         break;
 666                 }
 667         }
 668         return ret;
 669 }
 670
 671 static int dpaa_eth_link_update(struct rte_eth_dev *dev,
 672                                 int wait_to_complete __rte_unused)
 673 {
 674         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 675         struct rte_eth_link *link = &dev->data->dev_link;
 676         struct fman_if *fif = dev->process_private;
 677         struct __fman_if *__fif = container_of(fif, struct __fman_if, __if);
 678         int ret, ioctl_version;
 679
 680         PMD_INIT_FUNC_TRACE();
 681
 682         ioctl_version = dpaa_get_ioctl_version_number();
 683
 684
 685         if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC) {
 686                 ret = dpaa_get_link_status(__fif->node_name, link);
 687                 if (ret)
 688                         return ret;
 689         } else {
 690                 link->link_status = dpaa_intf->valid;
 691         }
 692
 693         if (ioctl_version < 2) {
 694                 link->link_duplex = ETH_LINK_FULL_DUPLEX;
 695                 link->link_autoneg = ETH_LINK_AUTONEG;
 696
 697                 if (fif->mac_type == fman_mac_1g)
 698                         link->link_speed = ETH_SPEED_NUM_1G;
 699                 else if (fif->mac_type == fman_mac_2_5g)
 700                         link->link_speed = ETH_SPEED_NUM_2_5G;
 701                 else if (fif->mac_type == fman_mac_10g)
 702                         link->link_speed = ETH_SPEED_NUM_10G;
 703                 else
 704                         DPAA_PMD_ERR("invalid link_speed: %s, %d",
 705                                      dpaa_intf->name, fif->mac_type);
 706         }
 707
 708         DPAA_PMD_INFO("Port %d Link is %s\n", dev->data->port_id,
 709                       link->link_status ? "Up" : "Down");
 710         return 0;
 711 }
 712
 713 static int dpaa_eth_stats_get(struct rte_eth_dev *dev,
 714                                struct rte_eth_stats *stats)
 715 {
 716         PMD_INIT_FUNC_TRACE();
 717
 718         fman_if_stats_get(dev->process_private, stats);
 719         return 0;
 720 }
 721
 722 static int dpaa_eth_stats_reset(struct rte_eth_dev *dev)
 723 {
 724         PMD_INIT_FUNC_TRACE();
 725
 726         fman_if_stats_reset(dev->process_private);
 727
 728         return 0;
 729 }
 730
 731 static int
 732 dpaa_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
 733                     unsigned int n)
 734 {
 735         unsigned int i = 0, num = RTE_DIM(dpaa_xstats_strings);
 736         uint64_t values[sizeof(struct dpaa_if_stats) / 8];
 737
 738         if (n < num)
 739                 return num;
 740
 741         if (xstats == NULL)
 742                 return 0;
 743
 744         fman_if_stats_get_all(dev->process_private, values,
 745                               sizeof(struct dpaa_if_stats) / 8);
 746
 747         for (i = 0; i < num; i++) {
 748                 xstats[i].id = i;
 749                 xstats[i].value = values[dpaa_xstats_strings[i].offset / 8];
 750         }
 751         return i;
 752 }
 753
 754 static int
 755 dpaa_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 756                       struct rte_eth_xstat_name *xstats_names,
 757                       unsigned int limit)
 758 {
 759         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 760
 761         if (limit < stat_cnt)
 762                 return stat_cnt;
 763
 764         if (xstats_names != NULL)
 765                 for (i = 0; i < stat_cnt; i++)
 766                         strlcpy(xstats_names[i].name,
 767                                 dpaa_xstats_strings[i].name,
 768                                 sizeof(xstats_names[i].name));
 769
 770         return stat_cnt;
 771 }
 772
 773 static int
 774 dpaa_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 775                       uint64_t *values, unsigned int n)
 776 {
 777         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 778         uint64_t values_copy[sizeof(struct dpaa_if_stats) / 8];
 779
 780         if (!ids) {
 781                 if (n < stat_cnt)
 782                         return stat_cnt;
 783
 784                 if (!values)
 785                         return 0;
 786
 787                 fman_if_stats_get_all(dev->process_private, values_copy,
 788                                       sizeof(struct dpaa_if_stats) / 8);
 789
 790                 for (i = 0; i < stat_cnt; i++)
 791                         values[i] =
 792                                 values_copy[dpaa_xstats_strings[i].offset / 8];
 793
 794                 return stat_cnt;
 795         }
 796
 797         dpaa_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
 798
 799         for (i = 0; i < n; i++) {
 800                 if (ids[i] >= stat_cnt) {
 801                         DPAA_PMD_ERR("id value isn't valid");
 802                         return -1;
 803                 }
 804                 values[i] = values_copy[ids[i]];
 805         }
 806         return n;
 807 }
 808
 809 static int
 810 dpaa_xstats_get_names_by_id(
 811         struct rte_eth_dev *dev,
 812         struct rte_eth_xstat_name *xstats_names,
 813         const uint64_t *ids,
 814         unsigned int limit)
 815 {
 816         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 817         struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
 818
 819         if (!ids)
 820                 return dpaa_xstats_get_names(dev, xstats_names, limit);
 821
 822         dpaa_xstats_get_names(dev, xstats_names_copy, limit);
 823
 824         for (i = 0; i < limit; i++) {
 825                 if (ids[i] >= stat_cnt) {
 826                         DPAA_PMD_ERR("id value isn't valid");
 827                         return -1;
 828                 }
 829                 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
 830         }
 831         return limit;
 832 }
 833
 834 static int dpaa_eth_promiscuous_enable(struct rte_eth_dev *dev)
 835 {
 836         PMD_INIT_FUNC_TRACE();
 837
 838         fman_if_promiscuous_enable(dev->process_private);
 839
 840         return 0;
 841 }
 842
 843 static int dpaa_eth_promiscuous_disable(struct rte_eth_dev *dev)
 844 {
 845         PMD_INIT_FUNC_TRACE();
 846
 847         fman_if_promiscuous_disable(dev->process_private);
 848
 849         return 0;
 850 }
 851
 852 static int dpaa_eth_multicast_enable(struct rte_eth_dev *dev)
 853 {
 854         PMD_INIT_FUNC_TRACE();
 855
 856         fman_if_set_mcast_filter_table(dev->process_private);
 857
 858         return 0;
 859 }
 860
 861 static int dpaa_eth_multicast_disable(struct rte_eth_dev *dev)
 862 {
 863         PMD_INIT_FUNC_TRACE();
 864
 865         fman_if_reset_mcast_filter_table(dev->process_private);
 866
 867         return 0;
 868 }
 869
 870 static void dpaa_fman_if_pool_setup(struct rte_eth_dev *dev)
 871 {
 872         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 873         struct fman_if_ic_params icp;
 874         uint32_t fd_offset;
 875         uint32_t bp_size;
 876
 877         memset(&icp, 0, sizeof(icp));
 878         /* set ICEOF for to the default value , which is 0*/
 879         icp.iciof = DEFAULT_ICIOF;
 880         icp.iceof = DEFAULT_RX_ICEOF;
 881         icp.icsz = DEFAULT_ICSZ;
 882         fman_if_set_ic_params(dev->process_private, &icp);
 883
 884         fd_offset = RTE_PKTMBUF_HEADROOM + DPAA_HW_BUF_RESERVE;
 885         fman_if_set_fdoff(dev->process_private, fd_offset);
 886
 887         /* Buffer pool size should be equal to Dataroom Size*/
 888         bp_size = rte_pktmbuf_data_room_size(dpaa_intf->bp_info->mp);
 889
 890         fman_if_set_bp(dev->process_private,
 891                        dpaa_intf->bp_info->mp->size,
 892                        dpaa_intf->bp_info->bpid, bp_size);
 893 }
 894
 895 static inline int dpaa_eth_rx_queue_bp_check(struct rte_eth_dev *dev,
 896                                              int8_t vsp_id, uint32_t bpid)
 897 {
 898         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 899         struct fman_if *fif = dev->process_private;
 900
 901         if (fif->num_profiles) {
 902                 if (vsp_id < 0)
 903                         vsp_id = fif->base_profile_id;
 904         } else {
 905                 if (vsp_id < 0)
 906                         vsp_id = 0;
 907         }
 908
 909         if (dpaa_intf->vsp_bpid[vsp_id] &&
 910                 bpid != dpaa_intf->vsp_bpid[vsp_id]) {
 911                 DPAA_PMD_ERR("Various MPs are assigned to RXQs with same VSP");
 912
 913                 return -1;
 914         }
 915
 916         return 0;
 917 }
 918
 919 static
 920 int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 921                             uint16_t nb_desc,
 922                             unsigned int socket_id __rte_unused,
 923                             const struct rte_eth_rxconf *rx_conf,
 924                             struct rte_mempool *mp)
 925 {
 926         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 927         struct fman_if *fif = dev->process_private;
 928         struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_idx];
 929         struct qm_mcc_initfq opts = {0};
 930         u32 flags = 0;
 931         int ret;
 932         u32 buffsz = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
 933
 934         PMD_INIT_FUNC_TRACE();
 935
 936         if (queue_idx >= dev->data->nb_rx_queues) {
 937                 rte_errno = EOVERFLOW;
 938                 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
 939                       (void *)dev, queue_idx, dev->data->nb_rx_queues);
 940                 return -rte_errno;
 941         }
 942
 943         /* Rx deferred start is not supported */
 944         if (rx_conf->rx_deferred_start) {
 945                 DPAA_PMD_ERR("%p:Rx deferred start not supported", (void *)dev);
 946                 return -EINVAL;
 947         }
 948         rxq->nb_desc = UINT16_MAX;
 949         rxq->offloads = rx_conf->offloads;
 950
 951         DPAA_PMD_INFO("Rx queue setup for queue index: %d fq_id (0x%x)",
 952                         queue_idx, rxq->fqid);
 953
 954         if (!fif->num_profiles) {
 955                 if (dpaa_intf->bp_info && dpaa_intf->bp_info->bp &&
 956                         dpaa_intf->bp_info->mp != mp) {
 957                         DPAA_PMD_WARN("Multiple pools on same interface not"
 958                                       " supported");
 959                         return -EINVAL;
 960                 }
 961         } else {
 962                 if (dpaa_eth_rx_queue_bp_check(dev, rxq->vsp_id,
 963                         DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid)) {
 964                         return -EINVAL;
 965                 }
 966         }
 967
 968         /* Max packet can fit in single buffer */
 969         if (dev->data->dev_conf.rxmode.max_rx_pkt_len <= buffsz) {
 970                 ;
 971         } else if (dev->data->dev_conf.rxmode.offloads &
 972                         DEV_RX_OFFLOAD_SCATTER) {
 973                 if (dev->data->dev_conf.rxmode.max_rx_pkt_len >
 974                         buffsz * DPAA_SGT_MAX_ENTRIES) {
 975                         DPAA_PMD_ERR("max RxPkt size %d too big to fit "
 976                                 "MaxSGlist %d",
 977                                 dev->data->dev_conf.rxmode.max_rx_pkt_len,
 978                                 buffsz * DPAA_SGT_MAX_ENTRIES);
 979                         rte_errno = EOVERFLOW;
 980                         return -rte_errno;
 981                 }
 982         } else {
 983                 DPAA_PMD_WARN("The requested maximum Rx packet size (%u) is"
 984                      " larger than a single mbuf (%u) and scattered"
 985                      " mode has not been requested",
 986                      dev->data->dev_conf.rxmode.max_rx_pkt_len,
 987                      buffsz - RTE_PKTMBUF_HEADROOM);
 988         }
 989
 990         dpaa_intf->bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp);
 991
 992         /* For shared interface, it's done in kernel, skip.*/
 993         if (!fif->is_shared_mac)
 994                 dpaa_fman_if_pool_setup(dev);
 995
 996         if (fif->num_profiles) {
 997                 int8_t vsp_id = rxq->vsp_id;
 998
 999                 if (vsp_id >= 0) {
1000                         ret = dpaa_port_vsp_update(dpaa_intf, fmc_q, vsp_id,
1001                                         DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid,
1002                                         fif);
1003                         if (ret) {
1004                                 DPAA_PMD_ERR("dpaa_port_vsp_update failed");
1005                                 return ret;
1006                         }
1007                 } else {
1008                         DPAA_PMD_INFO("Base profile is associated to"
1009                                 " RXQ fqid:%d\r\n", rxq->fqid);
1010                         if (fif->is_shared_mac) {
1011                                 DPAA_PMD_ERR("Fatal: Base profile is associated"
1012                                              " to shared interface on DPDK.");
1013                                 return -EINVAL;
1014                         }
1015                         dpaa_intf->vsp_bpid[fif->base_profile_id] =
1016                                 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid;
1017                 }
1018         } else {
1019                 dpaa_intf->vsp_bpid[0] =
1020                         DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid;
1021         }
1022
1023         dpaa_intf->valid = 1;
1024         DPAA_PMD_DEBUG("if:%s sg_on = %d, max_frm =%d", dpaa_intf->name,
1025                 fman_if_get_sg_enable(fif),
1026                 dev->data->dev_conf.rxmode.max_rx_pkt_len);
1027         /* checking if push mode only, no error check for now */
1028         if (!rxq->is_static &&
1029             dpaa_push_mode_max_queue > dpaa_push_queue_idx) {
1030                 struct qman_portal *qp;
1031                 int q_fd;
1032
1033                 dpaa_push_queue_idx++;
1034                 opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
1035                 opts.fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK |
1036                                    QM_FQCTRL_CTXASTASHING |
1037                                    QM_FQCTRL_PREFERINCACHE;
1038                 opts.fqd.context_a.stashing.exclusive = 0;
1039                 /* In muticore scenario stashing becomes a bottleneck on LS1046.
1040                  * So do not enable stashing in this case
1041                  */
1042                 if (dpaa_svr_family != SVR_LS1046A_FAMILY)
1043                         opts.fqd.context_a.stashing.annotation_cl =
1044                                                 DPAA_IF_RX_ANNOTATION_STASH;
1045                 opts.fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
1046                 opts.fqd.context_a.stashing.context_cl =
1047                                                 DPAA_IF_RX_CONTEXT_STASH;
1048
1049                 /*Create a channel and associate given queue with the channel*/
1050                 qman_alloc_pool_range((u32 *)&rxq->ch_id, 1, 1, 0);
1051                 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
1052                 opts.fqd.dest.channel = rxq->ch_id;
1053                 opts.fqd.dest.wq = DPAA_IF_RX_PRIORITY;
1054                 flags = QMAN_INITFQ_FLAG_SCHED;
1055
1056                 /* Configure tail drop */
1057                 if (dpaa_intf->cgr_rx) {
1058                         opts.we_mask |= QM_INITFQ_WE_CGID;
1059                         opts.fqd.cgid = dpaa_intf->cgr_rx[queue_idx].cgrid;
1060                         opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1061                 }
1062                 ret = qman_init_fq(rxq, flags, &opts);
1063                 if (ret) {
1064                         DPAA_PMD_ERR("Channel/Q association failed. fqid 0x%x "
1065                                 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
1066                         return ret;
1067                 }
1068                 if (dpaa_svr_family == SVR_LS1043A_FAMILY) {
1069                         rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb_no_prefetch;
1070                 } else {
1071                         rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb;
1072                         rxq->cb.dqrr_prepare = dpaa_rx_cb_prepare;
1073                 }
1074
1075                 rxq->is_static = true;
1076
1077                 /* Allocate qman specific portals */
1078                 qp = fsl_qman_fq_portal_create(&q_fd);
1079                 if (!qp) {
1080                         DPAA_PMD_ERR("Unable to alloc fq portal");
1081                         return -1;
1082                 }
1083                 rxq->qp = qp;
1084
1085                 /* Set up the device interrupt handler */
1086                 if (!dev->intr_handle) {
1087                         struct rte_dpaa_device *dpaa_dev;
1088                         struct rte_device *rdev = dev->device;
1089
1090                         dpaa_dev = container_of(rdev, struct rte_dpaa_device,
1091                                                 device);
1092                         dev->intr_handle = &dpaa_dev->intr_handle;
1093                         dev->intr_handle->intr_vec = rte_zmalloc(NULL,
1094                                         dpaa_push_mode_max_queue, 0);
1095                         if (!dev->intr_handle->intr_vec) {
1096                                 DPAA_PMD_ERR("intr_vec alloc failed");
1097                                 return -ENOMEM;
1098                         }
1099                         dev->intr_handle->nb_efd = dpaa_push_mode_max_queue;
1100                         dev->intr_handle->max_intr = dpaa_push_mode_max_queue;
1101                 }
1102
1103                 dev->intr_handle->type = RTE_INTR_HANDLE_EXT;
1104                 dev->intr_handle->intr_vec[queue_idx] = queue_idx + 1;
1105                 dev->intr_handle->efds[queue_idx] = q_fd;
1106                 rxq->q_fd = q_fd;
1107         }
1108         rxq->bp_array = rte_dpaa_bpid_info;
1109         dev->data->rx_queues[queue_idx] = rxq;
1110
1111         /* configure the CGR size as per the desc size */
1112         if (dpaa_intf->cgr_rx) {
1113                 struct qm_mcc_initcgr cgr_opts = {0};
1114
1115                 rxq->nb_desc = nb_desc;
1116                 /* Enable tail drop with cgr on this queue */
1117                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, nb_desc, 0);
1118                 ret = qman_modify_cgr(dpaa_intf->cgr_rx, 0, &cgr_opts);
1119                 if (ret) {
1120                         DPAA_PMD_WARN(
1121                                 "rx taildrop modify fail on fqid %d (ret=%d)",
1122                                 rxq->fqid, ret);
1123                 }
1124         }
1125         /* Enable main queue to receive error packets also by default */
1126         fman_if_set_err_fqid(fif, rxq->fqid);
1127         return 0;
1128 }
1129
1130 int
1131 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev,
1132                 int eth_rx_queue_id,
1133                 u16 ch_id,
1134                 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
1135 {
1136         int ret;
1137         u32 flags = 0;
1138         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1139         struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
1140         struct qm_mcc_initfq opts = {0};
1141
1142         if (dpaa_push_mode_max_queue)
1143                 DPAA_PMD_WARN("PUSH mode q and EVENTDEV are not compatible\n"
1144                               "PUSH mode already enabled for first %d queues.\n"
1145                               "To disable set DPAA_PUSH_QUEUES_NUMBER to 0\n",
1146                               dpaa_push_mode_max_queue);
1147
1148         dpaa_poll_queue_default_config(&opts);
1149
1150         switch (queue_conf->ev.sched_type) {
1151         case RTE_SCHED_TYPE_ATOMIC:
1152                 opts.fqd.fq_ctrl |= QM_FQCTRL_HOLDACTIVE;
1153                 /* Reset FQCTRL_AVOIDBLOCK bit as it is unnecessary
1154                  * configuration with HOLD_ACTIVE setting
1155                  */
1156                 opts.fqd.fq_ctrl &= (~QM_FQCTRL_AVOIDBLOCK);
1157                 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_atomic;
1158                 break;
1159         case RTE_SCHED_TYPE_ORDERED:
1160                 DPAA_PMD_ERR("Ordered queue schedule type is not supported\n");
1161                 return -1;
1162         default:
1163                 opts.fqd.fq_ctrl |= QM_FQCTRL_AVOIDBLOCK;
1164                 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_parallel;
1165                 break;
1166         }
1167
1168         opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
1169         opts.fqd.dest.channel = ch_id;
1170         opts.fqd.dest.wq = queue_conf->ev.priority;
1171
1172         if (dpaa_intf->cgr_rx) {
1173                 opts.we_mask |= QM_INITFQ_WE_CGID;
1174                 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
1175                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1176         }
1177
1178         flags = QMAN_INITFQ_FLAG_SCHED;
1179
1180         ret = qman_init_fq(rxq, flags, &opts);
1181         if (ret) {
1182                 DPAA_PMD_ERR("Ev-Channel/Q association failed. fqid 0x%x "
1183                                 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
1184                 return ret;
1185         }
1186
1187         /* copy configuration which needs to be filled during dequeue */
1188         memcpy(&rxq->ev, &queue_conf->ev, sizeof(struct rte_event));
1189         dev->data->rx_queues[eth_rx_queue_id] = rxq;
1190
1191         return ret;
1192 }
1193
1194 int
1195 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev,
1196                 int eth_rx_queue_id)
1197 {
1198         struct qm_mcc_initfq opts;
1199         int ret;
1200         u32 flags = 0;
1201         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1202         struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
1203
1204         dpaa_poll_queue_default_config(&opts);
1205
1206         if (dpaa_intf->cgr_rx) {
1207                 opts.we_mask |= QM_INITFQ_WE_CGID;
1208                 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
1209                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1210         }
1211
1212         ret = qman_init_fq(rxq, flags, &opts);
1213         if (ret) {
1214                 DPAA_PMD_ERR("init rx fqid %d failed with ret: %d",
1215                              rxq->fqid, ret);
1216         }
1217
1218         rxq->cb.dqrr_dpdk_cb = NULL;
1219         dev->data->rx_queues[eth_rx_queue_id] = NULL;
1220
1221         return 0;
1222 }
1223
1224 static
1225 void dpaa_eth_rx_queue_release(void *rxq __rte_unused)
1226 {
1227         PMD_INIT_FUNC_TRACE();
1228 }
1229
1230 static
1231 int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1232                             uint16_t nb_desc __rte_unused,
1233                 unsigned int socket_id __rte_unused,
1234                 const struct rte_eth_txconf *tx_conf)
1235 {
1236         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1237         struct qman_fq *txq = &dpaa_intf->tx_queues[queue_idx];
1238
1239         PMD_INIT_FUNC_TRACE();
1240
1241         /* Tx deferred start is not supported */
1242         if (tx_conf->tx_deferred_start) {
1243                 DPAA_PMD_ERR("%p:Tx deferred start not supported", (void *)dev);
1244                 return -EINVAL;
1245         }
1246         txq->nb_desc = UINT16_MAX;
1247         txq->offloads = tx_conf->offloads;
1248
1249         if (queue_idx >= dev->data->nb_tx_queues) {
1250                 rte_errno = EOVERFLOW;
1251                 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
1252                       (void *)dev, queue_idx, dev->data->nb_tx_queues);
1253                 return -rte_errno;
1254         }
1255
1256         DPAA_PMD_INFO("Tx queue setup for queue index: %d fq_id (0x%x)",
1257                         queue_idx, txq->fqid);
1258         dev->data->tx_queues[queue_idx] = txq;
1259
1260         return 0;
1261 }
1262
1263 static void dpaa_eth_tx_queue_release(void *txq __rte_unused)
1264 {
1265         PMD_INIT_FUNC_TRACE();
1266 }
1267
1268 static uint32_t
1269 dpaa_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1270 {
1271         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1272         struct qman_fq *rxq = &dpaa_intf->rx_queues[rx_queue_id];
1273         u32 frm_cnt = 0;
1274
1275         PMD_INIT_FUNC_TRACE();
1276
1277         if (qman_query_fq_frm_cnt(rxq, &frm_cnt) == 0) {
1278                 DPAA_PMD_DEBUG("RX frame count for q(%d) is %u",
1279                                rx_queue_id, frm_cnt);
1280         }
1281         return frm_cnt;
1282 }
1283
1284 static int dpaa_link_down(struct rte_eth_dev *dev)
1285 {
1286         struct fman_if *fif = dev->process_private;
1287         struct __fman_if *__fif;
1288
1289         PMD_INIT_FUNC_TRACE();
1290
1291         __fif = container_of(fif, struct __fman_if, __if);
1292
1293         if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC)
1294                 dpaa_update_link_status(__fif->node_name, ETH_LINK_DOWN);
1295         else
1296                 dpaa_eth_dev_stop(dev);
1297         return 0;
1298 }
1299
1300 static int dpaa_link_up(struct rte_eth_dev *dev)
1301 {
1302         struct fman_if *fif = dev->process_private;
1303         struct __fman_if *__fif;
1304
1305         PMD_INIT_FUNC_TRACE();
1306
1307         __fif = container_of(fif, struct __fman_if, __if);
1308
1309         if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC)
1310                 dpaa_update_link_status(__fif->node_name, ETH_LINK_UP);
1311         else
1312                 dpaa_eth_dev_start(dev);
1313         return 0;
1314 }
1315
1316 static int
1317 dpaa_flow_ctrl_set(struct rte_eth_dev *dev,
1318                    struct rte_eth_fc_conf *fc_conf)
1319 {
1320         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1321         struct rte_eth_fc_conf *net_fc;
1322
1323         PMD_INIT_FUNC_TRACE();
1324
1325         if (!(dpaa_intf->fc_conf)) {
1326                 dpaa_intf->fc_conf = rte_zmalloc(NULL,
1327                         sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
1328                 if (!dpaa_intf->fc_conf) {
1329                         DPAA_PMD_ERR("unable to save flow control info");
1330                         return -ENOMEM;
1331                 }
1332         }
1333         net_fc = dpaa_intf->fc_conf;
1334
1335         if (fc_conf->high_water < fc_conf->low_water) {
1336                 DPAA_PMD_ERR("Incorrect Flow Control Configuration");
1337                 return -EINVAL;
1338         }
1339
1340         if (fc_conf->mode == RTE_FC_NONE) {
1341                 return 0;
1342         } else if (fc_conf->mode == RTE_FC_TX_PAUSE ||
1343                  fc_conf->mode == RTE_FC_FULL) {
1344                 fman_if_set_fc_threshold(dev->process_private,
1345                                          fc_conf->high_water,
1346                                          fc_conf->low_water,
1347                                          dpaa_intf->bp_info->bpid);
1348                 if (fc_conf->pause_time)
1349                         fman_if_set_fc_quanta(dev->process_private,
1350                                               fc_conf->pause_time);
1351         }
1352
1353         /* Save the information in dpaa device */
1354         net_fc->pause_time = fc_conf->pause_time;
1355         net_fc->high_water = fc_conf->high_water;
1356         net_fc->low_water = fc_conf->low_water;
1357         net_fc->send_xon = fc_conf->send_xon;
1358         net_fc->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
1359         net_fc->mode = fc_conf->mode;
1360         net_fc->autoneg = fc_conf->autoneg;
1361
1362         return 0;
1363 }
1364
1365 static int
1366 dpaa_flow_ctrl_get(struct rte_eth_dev *dev,
1367                    struct rte_eth_fc_conf *fc_conf)
1368 {
1369         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1370         struct rte_eth_fc_conf *net_fc = dpaa_intf->fc_conf;
1371         int ret;
1372
1373         PMD_INIT_FUNC_TRACE();
1374
1375         if (net_fc) {
1376                 fc_conf->pause_time = net_fc->pause_time;
1377                 fc_conf->high_water = net_fc->high_water;
1378                 fc_conf->low_water = net_fc->low_water;
1379                 fc_conf->send_xon = net_fc->send_xon;
1380                 fc_conf->mac_ctrl_frame_fwd = net_fc->mac_ctrl_frame_fwd;
1381                 fc_conf->mode = net_fc->mode;
1382                 fc_conf->autoneg = net_fc->autoneg;
1383                 return 0;
1384         }
1385         ret = fman_if_get_fc_threshold(dev->process_private);
1386         if (ret) {
1387                 fc_conf->mode = RTE_FC_TX_PAUSE;
1388                 fc_conf->pause_time =
1389                         fman_if_get_fc_quanta(dev->process_private);
1390         } else {
1391                 fc_conf->mode = RTE_FC_NONE;
1392         }
1393
1394         return 0;
1395 }
1396
1397 static int
1398 dpaa_dev_add_mac_addr(struct rte_eth_dev *dev,
1399                              struct rte_ether_addr *addr,
1400                              uint32_t index,
1401                              __rte_unused uint32_t pool)
1402 {
1403         int ret;
1404
1405         PMD_INIT_FUNC_TRACE();
1406
1407         ret = fman_if_add_mac_addr(dev->process_private,
1408                                    addr->addr_bytes, index);
1409
1410         if (ret)
1411                 DPAA_PMD_ERR("Adding the MAC ADDR failed: err = %d", ret);
1412         return 0;
1413 }
1414
1415 static void
1416 dpaa_dev_remove_mac_addr(struct rte_eth_dev *dev,
1417                           uint32_t index)
1418 {
1419         PMD_INIT_FUNC_TRACE();
1420
1421         fman_if_clear_mac_addr(dev->process_private, index);
1422 }
1423
1424 static int
1425 dpaa_dev_set_mac_addr(struct rte_eth_dev *dev,
1426                        struct rte_ether_addr *addr)
1427 {
1428         int ret;
1429
1430         PMD_INIT_FUNC_TRACE();
1431
1432         ret = fman_if_add_mac_addr(dev->process_private, addr->addr_bytes, 0);
1433         if (ret)
1434                 DPAA_PMD_ERR("Setting the MAC ADDR failed %d", ret);
1435
1436         return ret;
1437 }
1438
1439 static int
1440 dpaa_dev_rss_hash_update(struct rte_eth_dev *dev,
1441                          struct rte_eth_rss_conf *rss_conf)
1442 {
1443         struct rte_eth_dev_data *data = dev->data;
1444         struct rte_eth_conf *eth_conf = &data->dev_conf;
1445
1446         PMD_INIT_FUNC_TRACE();
1447
1448         if (!(default_q || fmc_q)) {
1449                 if (dpaa_fm_config(dev, rss_conf->rss_hf)) {
1450                         DPAA_PMD_ERR("FM port configuration: Failed\n");
1451                         return -1;
1452                 }
1453                 eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf;
1454         } else {
1455                 DPAA_PMD_ERR("Function not supported\n");
1456                 return -ENOTSUP;
1457         }
1458         return 0;
1459 }
1460
1461 static int
1462 dpaa_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
1463                            struct rte_eth_rss_conf *rss_conf)
1464 {
1465         struct rte_eth_dev_data *data = dev->data;
1466         struct rte_eth_conf *eth_conf = &data->dev_conf;
1467
1468         /* dpaa does not support rss_key, so length should be 0*/
1469         rss_conf->rss_key_len = 0;
1470         rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf;
1471         return 0;
1472 }
1473
1474 static int dpaa_dev_queue_intr_enable(struct rte_eth_dev *dev,
1475                                       uint16_t queue_id)
1476 {
1477         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1478         struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id];
1479
1480         if (!rxq->is_static)
1481                 return -EINVAL;
1482
1483         return qman_fq_portal_irqsource_add(rxq->qp, QM_PIRQ_DQRI);
1484 }
1485
1486 static int dpaa_dev_queue_intr_disable(struct rte_eth_dev *dev,
1487                                        uint16_t queue_id)
1488 {
1489         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1490         struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id];
1491         uint32_t temp;
1492         ssize_t temp1;
1493
1494         if (!rxq->is_static)
1495                 return -EINVAL;
1496
1497         qman_fq_portal_irqsource_remove(rxq->qp, ~0);
1498
1499         temp1 = read(rxq->q_fd, &temp, sizeof(temp));
1500         if (temp1 != sizeof(temp))
1501                 DPAA_PMD_ERR("irq read error");
1502
1503         qman_fq_portal_thread_irq(rxq->qp);
1504
1505         return 0;
1506 }
1507
1508 static void
1509 dpaa_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1510         struct rte_eth_rxq_info *qinfo)
1511 {
1512         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1513         struct qman_fq *rxq;
1514
1515         rxq = dev->data->rx_queues[queue_id];
1516
1517         qinfo->mp = dpaa_intf->bp_info->mp;
1518         qinfo->scattered_rx = dev->data->scattered_rx;
1519         qinfo->nb_desc = rxq->nb_desc;
1520         qinfo->conf.rx_free_thresh = 1;
1521         qinfo->conf.rx_drop_en = 1;
1522         qinfo->conf.rx_deferred_start = 0;
1523         qinfo->conf.offloads = rxq->offloads;
1524 }
1525
1526 static void
1527 dpaa_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1528         struct rte_eth_txq_info *qinfo)
1529 {
1530         struct qman_fq *txq;
1531
1532         txq = dev->data->tx_queues[queue_id];
1533
1534         qinfo->nb_desc = txq->nb_desc;
1535         qinfo->conf.tx_thresh.pthresh = 0;
1536         qinfo->conf.tx_thresh.hthresh = 0;
1537         qinfo->conf.tx_thresh.wthresh = 0;
1538
1539         qinfo->conf.tx_free_thresh = 0;
1540         qinfo->conf.tx_rs_thresh = 0;
1541         qinfo->conf.offloads = txq->offloads;
1542         qinfo->conf.tx_deferred_start = 0;
1543 }
1544
1545 static struct eth_dev_ops dpaa_devops = {
1546         .dev_configure            = dpaa_eth_dev_configure,
1547         .dev_start                = dpaa_eth_dev_start,
1548         .dev_stop                 = dpaa_eth_dev_stop,
1549         .dev_close                = dpaa_eth_dev_close,
1550         .dev_infos_get            = dpaa_eth_dev_info,
1551         .dev_supported_ptypes_get = dpaa_supported_ptypes_get,
1552
1553         .rx_queue_setup           = dpaa_eth_rx_queue_setup,
1554         .tx_queue_setup           = dpaa_eth_tx_queue_setup,
1555         .rx_queue_release         = dpaa_eth_rx_queue_release,
1556         .tx_queue_release         = dpaa_eth_tx_queue_release,
1557         .rx_burst_mode_get        = dpaa_dev_rx_burst_mode_get,
1558         .tx_burst_mode_get        = dpaa_dev_tx_burst_mode_get,
1559         .rxq_info_get             = dpaa_rxq_info_get,
1560         .txq_info_get             = dpaa_txq_info_get,
1561
1562         .flow_ctrl_get            = dpaa_flow_ctrl_get,
1563         .flow_ctrl_set            = dpaa_flow_ctrl_set,
1564
1565         .link_update              = dpaa_eth_link_update,
1566         .stats_get                = dpaa_eth_stats_get,
1567         .xstats_get               = dpaa_dev_xstats_get,
1568         .xstats_get_by_id         = dpaa_xstats_get_by_id,
1569         .xstats_get_names_by_id   = dpaa_xstats_get_names_by_id,
1570         .xstats_get_names         = dpaa_xstats_get_names,
1571         .xstats_reset             = dpaa_eth_stats_reset,
1572         .stats_reset              = dpaa_eth_stats_reset,
1573         .promiscuous_enable       = dpaa_eth_promiscuous_enable,
1574         .promiscuous_disable      = dpaa_eth_promiscuous_disable,
1575         .allmulticast_enable      = dpaa_eth_multicast_enable,
1576         .allmulticast_disable     = dpaa_eth_multicast_disable,
1577         .mtu_set                  = dpaa_mtu_set,
1578         .dev_set_link_down        = dpaa_link_down,
1579         .dev_set_link_up          = dpaa_link_up,
1580         .mac_addr_add             = dpaa_dev_add_mac_addr,
1581         .mac_addr_remove          = dpaa_dev_remove_mac_addr,
1582         .mac_addr_set             = dpaa_dev_set_mac_addr,
1583
1584         .fw_version_get           = dpaa_fw_version_get,
1585
1586         .rx_queue_intr_enable     = dpaa_dev_queue_intr_enable,
1587         .rx_queue_intr_disable    = dpaa_dev_queue_intr_disable,
1588         .rss_hash_update          = dpaa_dev_rss_hash_update,
1589         .rss_hash_conf_get        = dpaa_dev_rss_hash_conf_get,
1590 };
1591
1592 static bool
1593 is_device_supported(struct rte_eth_dev *dev, struct rte_dpaa_driver *drv)
1594 {
1595         if (strcmp(dev->device->driver->name,
1596                    drv->driver.name))
1597                 return false;
1598
1599         return true;
1600 }
1601
1602 static bool
1603 is_dpaa_supported(struct rte_eth_dev *dev)
1604 {
1605         return is_device_supported(dev, &rte_dpaa_pmd);
1606 }
1607
1608 int
1609 rte_pmd_dpaa_set_tx_loopback(uint16_t port, uint8_t on)
1610 {
1611         struct rte_eth_dev *dev;
1612
1613         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
1614
1615         dev = &rte_eth_devices[port];
1616
1617         if (!is_dpaa_supported(dev))
1618                 return -ENOTSUP;
1619
1620         if (on)
1621                 fman_if_loopback_enable(dev->process_private);
1622         else
1623                 fman_if_loopback_disable(dev->process_private);
1624
1625         return 0;
1626 }
1627
1628 static int dpaa_fc_set_default(struct dpaa_if *dpaa_intf,
1629                                struct fman_if *fman_intf)
1630 {
1631         struct rte_eth_fc_conf *fc_conf;
1632         int ret;
1633
1634         PMD_INIT_FUNC_TRACE();
1635
1636         if (!(dpaa_intf->fc_conf)) {
1637                 dpaa_intf->fc_conf = rte_zmalloc(NULL,
1638                         sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
1639                 if (!dpaa_intf->fc_conf) {
1640                         DPAA_PMD_ERR("unable to save flow control info");
1641                         return -ENOMEM;
1642                 }
1643         }
1644         fc_conf = dpaa_intf->fc_conf;
1645         ret = fman_if_get_fc_threshold(fman_intf);
1646         if (ret) {
1647                 fc_conf->mode = RTE_FC_TX_PAUSE;
1648                 fc_conf->pause_time = fman_if_get_fc_quanta(fman_intf);
1649         } else {
1650                 fc_conf->mode = RTE_FC_NONE;
1651         }
1652
1653         return 0;
1654 }
1655
1656 /* Initialise an Rx FQ */
1657 static int dpaa_rx_queue_init(struct qman_fq *fq, struct qman_cgr *cgr_rx,
1658                               uint32_t fqid)
1659 {
1660         struct qm_mcc_initfq opts = {0};
1661         int ret;
1662         u32 flags = QMAN_FQ_FLAG_NO_ENQUEUE;
1663         struct qm_mcc_initcgr cgr_opts = {
1664                 .we_mask = QM_CGR_WE_CS_THRES |
1665                                 QM_CGR_WE_CSTD_EN |
1666                                 QM_CGR_WE_MODE,
1667                 .cgr = {
1668                         .cstd_en = QM_CGR_EN,
1669                         .mode = QMAN_CGR_MODE_FRAME
1670                 }
1671         };
1672
1673         if (fmc_q || default_q) {
1674                 ret = qman_reserve_fqid(fqid);
1675                 if (ret) {
1676                         DPAA_PMD_ERR("reserve rx fqid 0x%x failed, ret: %d",
1677                                      fqid, ret);
1678                         return -EINVAL;
1679                 }
1680         }
1681
1682         DPAA_PMD_DEBUG("creating rx fq %p, fqid 0x%x", fq, fqid);
1683         ret = qman_create_fq(fqid, flags, fq);
1684         if (ret) {
1685                 DPAA_PMD_ERR("create rx fqid 0x%x failed with ret: %d",
1686                         fqid, ret);
1687                 return ret;
1688         }
1689         fq->is_static = false;
1690
1691         dpaa_poll_queue_default_config(&opts);
1692
1693         if (cgr_rx) {
1694                 /* Enable tail drop with cgr on this queue */
1695                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, td_threshold, 0);
1696                 cgr_rx->cb = NULL;
1697                 ret = qman_create_cgr(cgr_rx, QMAN_CGR_FLAG_USE_INIT,
1698                                       &cgr_opts);
1699                 if (ret) {
1700                         DPAA_PMD_WARN(
1701                                 "rx taildrop init fail on rx fqid 0x%x(ret=%d)",
1702                                 fq->fqid, ret);
1703                         goto without_cgr;
1704                 }
1705                 opts.we_mask |= QM_INITFQ_WE_CGID;
1706                 opts.fqd.cgid = cgr_rx->cgrid;
1707                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1708         }
1709 without_cgr:
1710         ret = qman_init_fq(fq, 0, &opts);
1711         if (ret)
1712                 DPAA_PMD_ERR("init rx fqid 0x%x failed with ret:%d", fqid, ret);
1713         return ret;
1714 }
1715
1716 /* Initialise a Tx FQ */
1717 static int dpaa_tx_queue_init(struct qman_fq *fq,
1718                               struct fman_if *fman_intf,
1719                               struct qman_cgr *cgr_tx)
1720 {
1721         struct qm_mcc_initfq opts = {0};
1722         struct qm_mcc_initcgr cgr_opts = {
1723                 .we_mask = QM_CGR_WE_CS_THRES |
1724                                 QM_CGR_WE_CSTD_EN |
1725                                 QM_CGR_WE_MODE,
1726                 .cgr = {
1727                         .cstd_en = QM_CGR_EN,
1728                         .mode = QMAN_CGR_MODE_FRAME
1729                 }
1730         };
1731         int ret;
1732
1733         ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID |
1734                              QMAN_FQ_FLAG_TO_DCPORTAL, fq);
1735         if (ret) {
1736                 DPAA_PMD_ERR("create tx fq failed with ret: %d", ret);
1737                 return ret;
1738         }
1739         opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL |
1740                        QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA;
1741         opts.fqd.dest.channel = fman_intf->tx_channel_id;
1742         opts.fqd.dest.wq = DPAA_IF_TX_PRIORITY;
1743         opts.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE;
1744         opts.fqd.context_b = 0;
1745         /* no tx-confirmation */
1746         opts.fqd.context_a.hi = 0x80000000 | fman_dealloc_bufs_mask_hi;
1747         opts.fqd.context_a.lo = 0 | fman_dealloc_bufs_mask_lo;
1748         DPAA_PMD_DEBUG("init tx fq %p, fqid 0x%x", fq, fq->fqid);
1749
1750         if (cgr_tx) {
1751                 /* Enable tail drop with cgr on this queue */
1752                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres,
1753                                       td_tx_threshold, 0);
1754                 cgr_tx->cb = NULL;
1755                 ret = qman_create_cgr(cgr_tx, QMAN_CGR_FLAG_USE_INIT,
1756                                       &cgr_opts);
1757                 if (ret) {
1758                         DPAA_PMD_WARN(
1759                                 "rx taildrop init fail on rx fqid 0x%x(ret=%d)",
1760                                 fq->fqid, ret);
1761                         goto without_cgr;
1762                 }
1763                 opts.we_mask |= QM_INITFQ_WE_CGID;
1764                 opts.fqd.cgid = cgr_tx->cgrid;
1765                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1766                 DPAA_PMD_DEBUG("Tx FQ tail drop enabled, threshold = %d\n",
1767                                 td_tx_threshold);
1768         }
1769 without_cgr:
1770         ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts);
1771         if (ret)
1772                 DPAA_PMD_ERR("init tx fqid 0x%x failed %d", fq->fqid, ret);
1773         return ret;
1774 }
1775
1776 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1777 /* Initialise a DEBUG FQ ([rt]x_error, rx_default). */
1778 static int dpaa_debug_queue_init(struct qman_fq *fq, uint32_t fqid)
1779 {
1780         struct qm_mcc_initfq opts = {0};
1781         int ret;
1782
1783         PMD_INIT_FUNC_TRACE();
1784
1785         ret = qman_reserve_fqid(fqid);
1786         if (ret) {
1787                 DPAA_PMD_ERR("Reserve debug fqid %d failed with ret: %d",
1788                         fqid, ret);
1789                 return -EINVAL;
1790         }
1791         /* "map" this Rx FQ to one of the interfaces Tx FQID */
1792         DPAA_PMD_DEBUG("Creating debug fq %p, fqid %d", fq, fqid);
1793         ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq);
1794         if (ret) {
1795                 DPAA_PMD_ERR("create debug fqid %d failed with ret: %d",
1796                         fqid, ret);
1797                 return ret;
1798         }
1799         opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL;
1800         opts.fqd.dest.wq = DPAA_IF_DEBUG_PRIORITY;
1801         ret = qman_init_fq(fq, 0, &opts);
1802         if (ret)
1803                 DPAA_PMD_ERR("init debug fqid %d failed with ret: %d",
1804                             fqid, ret);
1805         return ret;
1806 }
1807 #endif
1808
1809 /* Initialise a network interface */
1810 static int
1811 dpaa_dev_init_secondary(struct rte_eth_dev *eth_dev)
1812 {
1813         struct rte_dpaa_device *dpaa_device;
1814         struct fm_eth_port_cfg *cfg;
1815         struct dpaa_if *dpaa_intf;
1816         struct fman_if *fman_intf;
1817         int dev_id;
1818
1819         PMD_INIT_FUNC_TRACE();
1820
1821         dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1822         dev_id = dpaa_device->id.dev_id;
1823         cfg = dpaa_get_eth_port_cfg(dev_id);
1824         fman_intf = cfg->fman_if;
1825         eth_dev->process_private = fman_intf;
1826
1827         /* Plugging of UCODE burst API not supported in Secondary */
1828         dpaa_intf = eth_dev->data->dev_private;
1829         eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
1830         if (dpaa_intf->cgr_tx)
1831                 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx_slow;
1832         else
1833                 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx;
1834 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP
1835         qman_set_fq_lookup_table(
1836                 dpaa_intf->rx_queues->qman_fq_lookup_table);
1837 #endif
1838
1839         return 0;
1840 }
1841
1842 /* Initialise a network interface */
1843 static int
1844 dpaa_dev_init(struct rte_eth_dev *eth_dev)
1845 {
1846         int num_rx_fqs, fqid;
1847         int loop, ret = 0;
1848         int dev_id;
1849         struct rte_dpaa_device *dpaa_device;
1850         struct dpaa_if *dpaa_intf;
1851         struct fm_eth_port_cfg *cfg;
1852         struct fman_if *fman_intf;
1853         struct fman_if_bpool *bp, *tmp_bp;
1854         uint32_t cgrid[DPAA_MAX_NUM_PCD_QUEUES];
1855         uint32_t cgrid_tx[MAX_DPAA_CORES];
1856         uint32_t dev_rx_fqids[DPAA_MAX_NUM_PCD_QUEUES];
1857         int8_t dev_vspids[DPAA_MAX_NUM_PCD_QUEUES];
1858         int8_t vsp_id = -1;
1859
1860         PMD_INIT_FUNC_TRACE();
1861
1862         dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1863         dev_id = dpaa_device->id.dev_id;
1864         dpaa_intf = eth_dev->data->dev_private;
1865         cfg = dpaa_get_eth_port_cfg(dev_id);
1866         fman_intf = cfg->fman_if;
1867
1868         dpaa_intf->name = dpaa_device->name;
1869
1870         /* save fman_if & cfg in the interface struture */
1871         eth_dev->process_private = fman_intf;
1872         dpaa_intf->ifid = dev_id;
1873         dpaa_intf->cfg = cfg;
1874
1875         memset((char *)dev_rx_fqids, 0,
1876                 sizeof(uint32_t) * DPAA_MAX_NUM_PCD_QUEUES);
1877
1878         memset(dev_vspids, -1, DPAA_MAX_NUM_PCD_QUEUES);
1879
1880         /* Initialize Rx FQ's */
1881         if (default_q) {
1882                 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES;
1883         } else if (fmc_q) {
1884                 num_rx_fqs = dpaa_port_fmc_init(fman_intf, dev_rx_fqids,
1885                                                 dev_vspids,
1886                                                 DPAA_MAX_NUM_PCD_QUEUES);
1887                 if (num_rx_fqs < 0) {
1888                         DPAA_PMD_ERR("%s FMC initializes failed!",
1889                                 dpaa_intf->name);
1890                         goto free_rx;
1891                 }
1892                 if (!num_rx_fqs) {
1893                         DPAA_PMD_WARN("%s is not configured by FMC.",
1894                                 dpaa_intf->name);
1895                 }
1896         } else {
1897                 /* FMCLESS mode, load balance to multiple cores.*/
1898                 num_rx_fqs = rte_lcore_count();
1899         }
1900
1901         /* Each device can not have more than DPAA_MAX_NUM_PCD_QUEUES RX
1902          * queues.
1903          */
1904         if (num_rx_fqs < 0 || num_rx_fqs > DPAA_MAX_NUM_PCD_QUEUES) {
1905                 DPAA_PMD_ERR("Invalid number of RX queues\n");
1906                 return -EINVAL;
1907         }
1908
1909         if (num_rx_fqs > 0) {
1910                 dpaa_intf->rx_queues = rte_zmalloc(NULL,
1911                         sizeof(struct qman_fq) * num_rx_fqs, MAX_CACHELINE);
1912                 if (!dpaa_intf->rx_queues) {
1913                         DPAA_PMD_ERR("Failed to alloc mem for RX queues\n");
1914                         return -ENOMEM;
1915                 }
1916         } else {
1917                 dpaa_intf->rx_queues = NULL;
1918         }
1919
1920         memset(cgrid, 0, sizeof(cgrid));
1921         memset(cgrid_tx, 0, sizeof(cgrid_tx));
1922
1923         /* if DPAA_TX_TAILDROP_THRESHOLD is set, use that value; if 0, it means
1924          * Tx tail drop is disabled.
1925          */
1926         if (getenv("DPAA_TX_TAILDROP_THRESHOLD")) {
1927                 td_tx_threshold = atoi(getenv("DPAA_TX_TAILDROP_THRESHOLD"));
1928                 DPAA_PMD_DEBUG("Tail drop threshold env configured: %u",
1929                                td_tx_threshold);
1930                 /* if a very large value is being configured */
1931                 if (td_tx_threshold > UINT16_MAX)
1932                         td_tx_threshold = CGR_RX_PERFQ_THRESH;
1933         }
1934
1935         /* If congestion control is enabled globally*/
1936         if (num_rx_fqs > 0 && td_threshold) {
1937                 dpaa_intf->cgr_rx = rte_zmalloc(NULL,
1938                         sizeof(struct qman_cgr) * num_rx_fqs, MAX_CACHELINE);
1939                 if (!dpaa_intf->cgr_rx) {
1940                         DPAA_PMD_ERR("Failed to alloc mem for cgr_rx\n");
1941                         ret = -ENOMEM;
1942                         goto free_rx;
1943                 }
1944
1945                 ret = qman_alloc_cgrid_range(&cgrid[0], num_rx_fqs, 1, 0);
1946                 if (ret != num_rx_fqs) {
1947                         DPAA_PMD_WARN("insufficient CGRIDs available");
1948                         ret = -EINVAL;
1949                         goto free_rx;
1950                 }
1951         } else {
1952                 dpaa_intf->cgr_rx = NULL;
1953         }
1954
1955         if (!fmc_q && !default_q) {
1956                 ret = qman_alloc_fqid_range(dev_rx_fqids, num_rx_fqs,
1957                                             num_rx_fqs, 0);
1958                 if (ret < 0) {
1959                         DPAA_PMD_ERR("Failed to alloc rx fqid's\n");
1960                         goto free_rx;
1961                 }
1962         }
1963
1964         for (loop = 0; loop < num_rx_fqs; loop++) {
1965                 if (default_q)
1966                         fqid = cfg->rx_def;
1967                 else
1968                         fqid = dev_rx_fqids[loop];
1969
1970                 vsp_id = dev_vspids[loop];
1971
1972                 if (dpaa_intf->cgr_rx)
1973                         dpaa_intf->cgr_rx[loop].cgrid = cgrid[loop];
1974
1975                 ret = dpaa_rx_queue_init(&dpaa_intf->rx_queues[loop],
1976                         dpaa_intf->cgr_rx ? &dpaa_intf->cgr_rx[loop] : NULL,
1977                         fqid);
1978                 if (ret)
1979                         goto free_rx;
1980                 dpaa_intf->rx_queues[loop].vsp_id = vsp_id;
1981                 dpaa_intf->rx_queues[loop].dpaa_intf = dpaa_intf;
1982         }
1983         dpaa_intf->nb_rx_queues = num_rx_fqs;
1984
1985         /* Initialise Tx FQs.free_rx Have as many Tx FQ's as number of cores */
1986         dpaa_intf->tx_queues = rte_zmalloc(NULL, sizeof(struct qman_fq) *
1987                 MAX_DPAA_CORES, MAX_CACHELINE);
1988         if (!dpaa_intf->tx_queues) {
1989                 DPAA_PMD_ERR("Failed to alloc mem for TX queues\n");
1990                 ret = -ENOMEM;
1991                 goto free_rx;
1992         }
1993
1994         /* If congestion control is enabled globally*/
1995         if (td_tx_threshold) {
1996                 dpaa_intf->cgr_tx = rte_zmalloc(NULL,
1997                         sizeof(struct qman_cgr) * MAX_DPAA_CORES,
1998                         MAX_CACHELINE);
1999                 if (!dpaa_intf->cgr_tx) {
2000                         DPAA_PMD_ERR("Failed to alloc mem for cgr_tx\n");
2001                         ret = -ENOMEM;
2002                         goto free_rx;
2003                 }
2004
2005                 ret = qman_alloc_cgrid_range(&cgrid_tx[0], MAX_DPAA_CORES,
2006                                              1, 0);
2007                 if (ret != MAX_DPAA_CORES) {
2008                         DPAA_PMD_WARN("insufficient CGRIDs available");
2009                         ret = -EINVAL;
2010                         goto free_rx;
2011                 }
2012         } else {
2013                 dpaa_intf->cgr_tx = NULL;
2014         }
2015
2016
2017         for (loop = 0; loop < MAX_DPAA_CORES; loop++) {
2018                 if (dpaa_intf->cgr_tx)
2019                         dpaa_intf->cgr_tx[loop].cgrid = cgrid_tx[loop];
2020
2021                 ret = dpaa_tx_queue_init(&dpaa_intf->tx_queues[loop],
2022                         fman_intf,
2023                         dpaa_intf->cgr_tx ? &dpaa_intf->cgr_tx[loop] : NULL);
2024                 if (ret)
2025                         goto free_tx;
2026                 dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf;
2027         }
2028         dpaa_intf->nb_tx_queues = MAX_DPAA_CORES;
2029
2030 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
2031         ret = dpaa_debug_queue_init(&dpaa_intf->debug_queues
2032                         [DPAA_DEBUG_FQ_RX_ERROR], fman_intf->fqid_rx_err);
2033         if (ret) {
2034                 DPAA_PMD_ERR("DPAA RX ERROR queue init failed!");
2035                 goto free_tx;
2036         }
2037         dpaa_intf->debug_queues[DPAA_DEBUG_FQ_RX_ERROR].dpaa_intf = dpaa_intf;
2038         ret = dpaa_debug_queue_init(&dpaa_intf->debug_queues
2039                         [DPAA_DEBUG_FQ_TX_ERROR], fman_intf->fqid_tx_err);
2040         if (ret) {
2041                 DPAA_PMD_ERR("DPAA TX ERROR queue init failed!");
2042                 goto free_tx;
2043         }
2044         dpaa_intf->debug_queues[DPAA_DEBUG_FQ_TX_ERROR].dpaa_intf = dpaa_intf;
2045 #endif
2046
2047         DPAA_PMD_DEBUG("All frame queues created");
2048
2049         /* Get the initial configuration for flow control */
2050         dpaa_fc_set_default(dpaa_intf, fman_intf);
2051
2052         /* reset bpool list, initialize bpool dynamically */
2053         list_for_each_entry_safe(bp, tmp_bp, &cfg->fman_if->bpool_list, node) {
2054                 list_del(&bp->node);
2055                 rte_free(bp);
2056         }
2057
2058         /* Populate ethdev structure */
2059         eth_dev->dev_ops = &dpaa_devops;
2060         eth_dev->rx_queue_count = dpaa_dev_rx_queue_count;
2061         eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
2062         eth_dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
2063
2064         /* Allocate memory for storing MAC addresses */
2065         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr",
2066                 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER, 0);
2067         if (eth_dev->data->mac_addrs == NULL) {
2068                 DPAA_PMD_ERR("Failed to allocate %d bytes needed to "
2069                                                 "store MAC addresses",
2070                                 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER);
2071                 ret = -ENOMEM;
2072                 goto free_tx;
2073         }
2074
2075         /* copy the primary mac address */
2076         rte_ether_addr_copy(&fman_intf->mac_addr, &eth_dev->data->mac_addrs[0]);
2077
2078         RTE_LOG(INFO, PMD, "net: dpaa: %s: %02x:%02x:%02x:%02x:%02x:%02x\n",
2079                 dpaa_device->name,
2080                 fman_intf->mac_addr.addr_bytes[0],
2081                 fman_intf->mac_addr.addr_bytes[1],
2082                 fman_intf->mac_addr.addr_bytes[2],
2083                 fman_intf->mac_addr.addr_bytes[3],
2084                 fman_intf->mac_addr.addr_bytes[4],
2085                 fman_intf->mac_addr.addr_bytes[5]);
2086
2087         if (!fman_intf->is_shared_mac) {
2088                 /* Configure error packet handling */
2089                 fman_if_receive_rx_errors(fman_intf,
2090                         FM_FD_RX_STATUS_ERR_MASK);
2091                 /* Disable RX mode */
2092                 fman_if_disable_rx(fman_intf);
2093                 /* Disable promiscuous mode */
2094                 fman_if_promiscuous_disable(fman_intf);
2095                 /* Disable multicast */
2096                 fman_if_reset_mcast_filter_table(fman_intf);
2097                 /* Reset interface statistics */
2098                 fman_if_stats_reset(fman_intf);
2099                 /* Disable SG by default */
2100                 fman_if_set_sg(fman_intf, 0);
2101                 fman_if_set_maxfrm(fman_intf,
2102                                    RTE_ETHER_MAX_LEN + VLAN_TAG_SIZE);
2103         }
2104
2105         return 0;
2106
2107 free_tx:
2108         rte_free(dpaa_intf->tx_queues);
2109         dpaa_intf->tx_queues = NULL;
2110         dpaa_intf->nb_tx_queues = 0;
2111
2112 free_rx:
2113         rte_free(dpaa_intf->cgr_rx);
2114         rte_free(dpaa_intf->cgr_tx);
2115         rte_free(dpaa_intf->rx_queues);
2116         dpaa_intf->rx_queues = NULL;
2117         dpaa_intf->nb_rx_queues = 0;
2118         return ret;
2119 }
2120
2121 static int
2122 rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv,
2123                struct rte_dpaa_device *dpaa_dev)
2124 {
2125         int diag;
2126         int ret;
2127         struct rte_eth_dev *eth_dev;
2128
2129         PMD_INIT_FUNC_TRACE();
2130
2131         if ((DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE) >
2132                 RTE_PKTMBUF_HEADROOM) {
2133                 DPAA_PMD_ERR(
2134                 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA Annotation req(%d)",
2135                 RTE_PKTMBUF_HEADROOM,
2136                 DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE);
2137
2138                 return -1;
2139         }
2140
2141         /* In case of secondary process, the device is already configured
2142          * and no further action is required, except portal initialization
2143          * and verifying secondary attachment to port name.
2144          */
2145         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2146                 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name);
2147                 if (!eth_dev)
2148                         return -ENOMEM;
2149                 eth_dev->device = &dpaa_dev->device;
2150                 eth_dev->dev_ops = &dpaa_devops;
2151
2152                 ret = dpaa_dev_init_secondary(eth_dev);
2153                 if (ret != 0) {
2154                         RTE_LOG(ERR, PMD, "secondary dev init failed\n");
2155                         return ret;
2156                 }
2157
2158                 rte_eth_dev_probing_finish(eth_dev);
2159                 return 0;
2160         }
2161
2162         if (!is_global_init && (rte_eal_process_type() == RTE_PROC_PRIMARY)) {
2163                 if (access("/tmp/fmc.bin", F_OK) == -1) {
2164                         DPAA_PMD_INFO("* FMC not configured.Enabling default mode");
2165                         default_q = 1;
2166                 }
2167
2168                 if (!(default_q || fmc_q)) {
2169                         if (dpaa_fm_init()) {
2170                                 DPAA_PMD_ERR("FM init failed\n");
2171                                 return -1;
2172                         }
2173                 }
2174
2175                 /* disabling the default push mode for LS1043 */
2176                 if (dpaa_svr_family == SVR_LS1043A_FAMILY)
2177                         dpaa_push_mode_max_queue = 0;
2178
2179                 /* if push mode queues to be enabled. Currenly we are allowing
2180                  * only one queue per thread.
2181                  */
2182                 if (getenv("DPAA_PUSH_QUEUES_NUMBER")) {
2183                         dpaa_push_mode_max_queue =
2184                                         atoi(getenv("DPAA_PUSH_QUEUES_NUMBER"));
2185                         if (dpaa_push_mode_max_queue > DPAA_MAX_PUSH_MODE_QUEUE)
2186                             dpaa_push_mode_max_queue = DPAA_MAX_PUSH_MODE_QUEUE;
2187                 }
2188
2189                 is_global_init = 1;
2190         }
2191
2192         if (unlikely(!DPAA_PER_LCORE_PORTAL)) {
2193                 ret = rte_dpaa_portal_init((void *)1);
2194                 if (ret) {
2195                         DPAA_PMD_ERR("Unable to initialize portal");
2196                         return ret;
2197                 }
2198         }
2199
2200         eth_dev = rte_eth_dev_allocate(dpaa_dev->name);
2201         if (!eth_dev)
2202                 return -ENOMEM;
2203
2204         eth_dev->data->dev_private =
2205                         rte_zmalloc("ethdev private structure",
2206                                         sizeof(struct dpaa_if),
2207                                         RTE_CACHE_LINE_SIZE);
2208         if (!eth_dev->data->dev_private) {
2209                 DPAA_PMD_ERR("Cannot allocate memzone for port data");
2210                 rte_eth_dev_release_port(eth_dev);
2211                 return -ENOMEM;
2212         }
2213
2214         eth_dev->device = &dpaa_dev->device;
2215         dpaa_dev->eth_dev = eth_dev;
2216
2217         qman_ern_register_cb(dpaa_free_mbuf);
2218
2219         if (dpaa_drv->drv_flags & RTE_DPAA_DRV_INTR_LSC)
2220                 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;
2221
2222         /* Invoke PMD device initialization function */
2223         diag = dpaa_dev_init(eth_dev);
2224         if (diag == 0) {
2225                 rte_eth_dev_probing_finish(eth_dev);
2226                 return 0;
2227         }
2228
2229         rte_eth_dev_release_port(eth_dev);
2230         return diag;
2231 }
2232
2233 static int
2234 rte_dpaa_remove(struct rte_dpaa_device *dpaa_dev)
2235 {
2236         struct rte_eth_dev *eth_dev;
2237         int ret;
2238
2239         PMD_INIT_FUNC_TRACE();
2240
2241         eth_dev = dpaa_dev->eth_dev;
2242         dpaa_eth_dev_close(eth_dev);
2243         ret = rte_eth_dev_release_port(eth_dev);
2244
2245         return ret;
2246 }
2247
2248 static void __attribute__((destructor(102))) dpaa_finish(void)
2249 {
2250         /* For secondary, primary will do all the cleanup */
2251         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2252                 return;
2253
2254         if (!(default_q || fmc_q)) {
2255                 unsigned int i;
2256
2257                 for (i = 0; i < RTE_MAX_ETHPORTS; i++) {
2258                         if (rte_eth_devices[i].dev_ops == &dpaa_devops) {
2259                                 struct rte_eth_dev *dev = &rte_eth_devices[i];
2260                                 struct dpaa_if *dpaa_intf =
2261                                         dev->data->dev_private;
2262                                 struct fman_if *fif =
2263                                         dev->process_private;
2264                                 if (dpaa_intf->port_handle)
2265                                         if (dpaa_fm_deconfig(dpaa_intf, fif))
2266                                                 DPAA_PMD_WARN("DPAA FM "
2267                                                         "deconfig failed\n");
2268                                 if (fif->num_profiles) {
2269                                         if (dpaa_port_vsp_cleanup(dpaa_intf,
2270                                                                   fif))
2271                                                 DPAA_PMD_WARN("DPAA FM vsp cleanup failed\n");
2272                                 }
2273                         }
2274                 }
2275                 if (is_global_init)
2276                         if (dpaa_fm_term())
2277                                 DPAA_PMD_WARN("DPAA FM term failed\n");
2278
2279                 is_global_init = 0;
2280
2281                 DPAA_PMD_INFO("DPAA fman cleaned up");
2282         }
2283 }
2284
2285 static struct rte_dpaa_driver rte_dpaa_pmd = {
2286         .drv_flags = RTE_DPAA_DRV_INTR_LSC,
2287         .drv_type = FSL_DPAA_ETH,
2288         .probe = rte_dpaa_probe,
2289         .remove = rte_dpaa_remove,
2290 };
2291
2292 RTE_PMD_REGISTER_DPAA(net_dpaa, rte_dpaa_pmd);
2293 RTE_LOG_REGISTER(dpaa_logtype_pmd, pmd.net.dpaa, NOTICE);