drivers/net/dpaa/dpaa_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  *   Copyright 2016 Freescale Semiconductor, Inc. All rights reserved.
   4  *   Copyright 2017-2020 NXP
   5  *
   6  */
   7 /* System headers */
   8 #include <stdio.h>
   9 #include <inttypes.h>
  10 #include <unistd.h>
  11 #include <limits.h>
  12 #include <sched.h>
  13 #include <signal.h>
  14 #include <pthread.h>
  15 #include <sys/types.h>
  16 #include <sys/syscall.h>
  17
  18 #include <rte_string_fns.h>
  19 #include <rte_byteorder.h>
  20 #include <rte_common.h>
  21 #include <rte_interrupts.h>
  22 #include <rte_log.h>
  23 #include <rte_debug.h>
  24 #include <rte_pci.h>
  25 #include <rte_atomic.h>
  26 #include <rte_branch_prediction.h>
  27 #include <rte_memory.h>
  28 #include <rte_tailq.h>
  29 #include <rte_eal.h>
  30 #include <rte_alarm.h>
  31 #include <rte_ether.h>
  32 #include <rte_ethdev_driver.h>
  33 #include <rte_malloc.h>
  34 #include <rte_ring.h>
  35
  36 #include <rte_dpaa_bus.h>
  37 #include <rte_dpaa_logs.h>
  38 #include <dpaa_mempool.h>
  39
  40 #include <dpaa_ethdev.h>
  41 #include <dpaa_rxtx.h>
  42 #include <rte_pmd_dpaa.h>
  43
  44 #include <fsl_usd.h>
  45 #include <fsl_qman.h>
  46 #include <fsl_bman.h>
  47 #include <fsl_fman.h>
  48
  49 /* Supported Rx offloads */
  50 static uint64_t dev_rx_offloads_sup =
  51                 DEV_RX_OFFLOAD_JUMBO_FRAME |
  52                 DEV_RX_OFFLOAD_SCATTER;
  53
  54 /* Rx offloads which cannot be disabled */
  55 static uint64_t dev_rx_offloads_nodis =
  56                 DEV_RX_OFFLOAD_IPV4_CKSUM |
  57                 DEV_RX_OFFLOAD_UDP_CKSUM |
  58                 DEV_RX_OFFLOAD_TCP_CKSUM |
  59                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
  60                 DEV_RX_OFFLOAD_RSS_HASH;
  61
  62 /* Supported Tx offloads */
  63 static uint64_t dev_tx_offloads_sup =
  64                 DEV_TX_OFFLOAD_MT_LOCKFREE |
  65                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
  66
  67 /* Tx offloads which cannot be disabled */
  68 static uint64_t dev_tx_offloads_nodis =
  69                 DEV_TX_OFFLOAD_IPV4_CKSUM |
  70                 DEV_TX_OFFLOAD_UDP_CKSUM |
  71                 DEV_TX_OFFLOAD_TCP_CKSUM |
  72                 DEV_TX_OFFLOAD_SCTP_CKSUM |
  73                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
  74                 DEV_TX_OFFLOAD_MULTI_SEGS;
  75
  76 /* Keep track of whether QMAN and BMAN have been globally initialized */
  77 static int is_global_init;
  78 static int default_q;   /* use default queue - FMC is not executed*/
  79 /* At present we only allow up to 4 push mode queues as default - as each of
  80  * this queue need dedicated portal and we are short of portals.
  81  */
  82 #define DPAA_MAX_PUSH_MODE_QUEUE       8
  83 #define DPAA_DEFAULT_PUSH_MODE_QUEUE   4
  84
  85 static int dpaa_push_mode_max_queue = DPAA_DEFAULT_PUSH_MODE_QUEUE;
  86 static int dpaa_push_queue_idx; /* Queue index which are in push mode*/
  87
  88
  89 /* Per RX FQ Taildrop in frame count */
  90 static unsigned int td_threshold = CGR_RX_PERFQ_THRESH;
  91
  92 /* Per TX FQ Taildrop in frame count, disabled by default */
  93 static unsigned int td_tx_threshold;
  94
  95 struct rte_dpaa_xstats_name_off {
  96         char name[RTE_ETH_XSTATS_NAME_SIZE];
  97         uint32_t offset;
  98 };
  99
 100 static const struct rte_dpaa_xstats_name_off dpaa_xstats_strings[] = {
 101         {"rx_align_err",
 102                 offsetof(struct dpaa_if_stats, raln)},
 103         {"rx_valid_pause",
 104                 offsetof(struct dpaa_if_stats, rxpf)},
 105         {"rx_fcs_err",
 106                 offsetof(struct dpaa_if_stats, rfcs)},
 107         {"rx_vlan_frame",
 108                 offsetof(struct dpaa_if_stats, rvlan)},
 109         {"rx_frame_err",
 110                 offsetof(struct dpaa_if_stats, rerr)},
 111         {"rx_drop_err",
 112                 offsetof(struct dpaa_if_stats, rdrp)},
 113         {"rx_undersized",
 114                 offsetof(struct dpaa_if_stats, rund)},
 115         {"rx_oversize_err",
 116                 offsetof(struct dpaa_if_stats, rovr)},
 117         {"rx_fragment_pkt",
 118                 offsetof(struct dpaa_if_stats, rfrg)},
 119         {"tx_valid_pause",
 120                 offsetof(struct dpaa_if_stats, txpf)},
 121         {"tx_fcs_err",
 122                 offsetof(struct dpaa_if_stats, terr)},
 123         {"tx_vlan_frame",
 124                 offsetof(struct dpaa_if_stats, tvlan)},
 125         {"rx_undersized",
 126                 offsetof(struct dpaa_if_stats, tund)},
 127 };
 128
 129 static struct rte_dpaa_driver rte_dpaa_pmd;
 130
 131 static int
 132 dpaa_eth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info);
 133
 134 static inline void
 135 dpaa_poll_queue_default_config(struct qm_mcc_initfq *opts)
 136 {
 137         memset(opts, 0, sizeof(struct qm_mcc_initfq));
 138         opts->we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
 139         opts->fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | QM_FQCTRL_CTXASTASHING |
 140                            QM_FQCTRL_PREFERINCACHE;
 141         opts->fqd.context_a.stashing.exclusive = 0;
 142         if (dpaa_svr_family != SVR_LS1046A_FAMILY)
 143                 opts->fqd.context_a.stashing.annotation_cl =
 144                                                 DPAA_IF_RX_ANNOTATION_STASH;
 145         opts->fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
 146         opts->fqd.context_a.stashing.context_cl = DPAA_IF_RX_CONTEXT_STASH;
 147 }
 148
 149 static int
 150 dpaa_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 151 {
 152         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 153         uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
 154                                 + VLAN_TAG_SIZE;
 155         uint32_t buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
 156
 157         PMD_INIT_FUNC_TRACE();
 158
 159         if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA_MAX_RX_PKT_LEN)
 160                 return -EINVAL;
 161         /*
 162          * Refuse mtu that requires the support of scattered packets
 163          * when this feature has not been enabled before.
 164          */
 165         if (dev->data->min_rx_buf_size &&
 166                 !dev->data->scattered_rx && frame_size > buffsz) {
 167                 DPAA_PMD_ERR("SG not enabled, will not fit in one buffer");
 168                 return -EINVAL;
 169         }
 170
 171         /* check <seg size> * <max_seg>  >= max_frame */
 172         if (dev->data->min_rx_buf_size && dev->data->scattered_rx &&
 173                 (frame_size > buffsz * DPAA_SGT_MAX_ENTRIES)) {
 174                 DPAA_PMD_ERR("Too big to fit for Max SG list %d",
 175                                 buffsz * DPAA_SGT_MAX_ENTRIES);
 176                 return -EINVAL;
 177         }
 178
 179         if (frame_size > RTE_ETHER_MAX_LEN)
 180                 dev->data->dev_conf.rxmode.offloads |=
 181                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 182         else
 183                 dev->data->dev_conf.rxmode.offloads &=
 184                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 185
 186         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 187
 188         fman_if_set_maxfrm(dpaa_intf->fif, frame_size);
 189
 190         return 0;
 191 }
 192
 193 static int
 194 dpaa_eth_dev_configure(struct rte_eth_dev *dev)
 195 {
 196         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 197         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 198         uint64_t rx_offloads = eth_conf->rxmode.offloads;
 199         uint64_t tx_offloads = eth_conf->txmode.offloads;
 200
 201         PMD_INIT_FUNC_TRACE();
 202
 203         /* Rx offloads which are enabled by default */
 204         if (dev_rx_offloads_nodis & ~rx_offloads) {
 205                 DPAA_PMD_INFO(
 206                 "Some of rx offloads enabled by default - requested 0x%" PRIx64
 207                 " fixed are 0x%" PRIx64,
 208                 rx_offloads, dev_rx_offloads_nodis);
 209         }
 210
 211         /* Tx offloads which are enabled by default */
 212         if (dev_tx_offloads_nodis & ~tx_offloads) {
 213                 DPAA_PMD_INFO(
 214                 "Some of tx offloads enabled by default - requested 0x%" PRIx64
 215                 " fixed are 0x%" PRIx64,
 216                 tx_offloads, dev_tx_offloads_nodis);
 217         }
 218
 219         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 220                 uint32_t max_len;
 221
 222                 DPAA_PMD_DEBUG("enabling jumbo");
 223
 224                 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <=
 225                     DPAA_MAX_RX_PKT_LEN)
 226                         max_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
 227                 else {
 228                         DPAA_PMD_INFO("enabling jumbo override conf max len=%d "
 229                                 "supported is %d",
 230                                 dev->data->dev_conf.rxmode.max_rx_pkt_len,
 231                                 DPAA_MAX_RX_PKT_LEN);
 232                         max_len = DPAA_MAX_RX_PKT_LEN;
 233                 }
 234
 235                 fman_if_set_maxfrm(dpaa_intf->fif, max_len);
 236                 dev->data->mtu = max_len
 237                         - RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE;
 238         }
 239
 240         if (rx_offloads & DEV_RX_OFFLOAD_SCATTER) {
 241                 DPAA_PMD_DEBUG("enabling scatter mode");
 242                 fman_if_set_sg(dpaa_intf->fif, 1);
 243                 dev->data->scattered_rx = 1;
 244         }
 245
 246         return 0;
 247 }
 248
 249 static const uint32_t *
 250 dpaa_supported_ptypes_get(struct rte_eth_dev *dev)
 251 {
 252         static const uint32_t ptypes[] = {
 253                 RTE_PTYPE_L2_ETHER,
 254                 RTE_PTYPE_L2_ETHER_VLAN,
 255                 RTE_PTYPE_L2_ETHER_ARP,
 256                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
 257                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
 258                 RTE_PTYPE_L4_ICMP,
 259                 RTE_PTYPE_L4_TCP,
 260                 RTE_PTYPE_L4_UDP,
 261                 RTE_PTYPE_L4_FRAG,
 262                 RTE_PTYPE_L4_TCP,
 263                 RTE_PTYPE_L4_UDP,
 264                 RTE_PTYPE_L4_SCTP
 265         };
 266
 267         PMD_INIT_FUNC_TRACE();
 268
 269         if (dev->rx_pkt_burst == dpaa_eth_queue_rx)
 270                 return ptypes;
 271         return NULL;
 272 }
 273
 274 static int dpaa_eth_dev_start(struct rte_eth_dev *dev)
 275 {
 276         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 277
 278         PMD_INIT_FUNC_TRACE();
 279
 280         /* Change tx callback to the real one */
 281         if (dpaa_intf->cgr_tx)
 282                 dev->tx_pkt_burst = dpaa_eth_queue_tx_slow;
 283         else
 284                 dev->tx_pkt_burst = dpaa_eth_queue_tx;
 285
 286         fman_if_enable_rx(dpaa_intf->fif);
 287
 288         return 0;
 289 }
 290
 291 static void dpaa_eth_dev_stop(struct rte_eth_dev *dev)
 292 {
 293         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 294
 295         PMD_INIT_FUNC_TRACE();
 296
 297         fman_if_disable_rx(dpaa_intf->fif);
 298         dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
 299 }
 300
 301 static void dpaa_eth_dev_close(struct rte_eth_dev *dev)
 302 {
 303         PMD_INIT_FUNC_TRACE();
 304
 305         dpaa_eth_dev_stop(dev);
 306 }
 307
 308 static int
 309 dpaa_fw_version_get(struct rte_eth_dev *dev __rte_unused,
 310                      char *fw_version,
 311                      size_t fw_size)
 312 {
 313         int ret;
 314         FILE *svr_file = NULL;
 315         unsigned int svr_ver = 0;
 316
 317         PMD_INIT_FUNC_TRACE();
 318
 319         svr_file = fopen(DPAA_SOC_ID_FILE, "r");
 320         if (!svr_file) {
 321                 DPAA_PMD_ERR("Unable to open SoC device");
 322                 return -ENOTSUP; /* Not supported on this infra */
 323         }
 324         if (fscanf(svr_file, "svr:%x", &svr_ver) > 0)
 325                 dpaa_svr_family = svr_ver & SVR_MASK;
 326         else
 327                 DPAA_PMD_ERR("Unable to read SoC device");
 328
 329         fclose(svr_file);
 330
 331         ret = snprintf(fw_version, fw_size, "SVR:%x-fman-v%x",
 332                        svr_ver, fman_ip_rev);
 333         ret += 1; /* add the size of '\0' */
 334
 335         if (fw_size < (uint32_t)ret)
 336                 return ret;
 337         else
 338                 return 0;
 339 }
 340
 341 static int dpaa_eth_dev_info(struct rte_eth_dev *dev,
 342                              struct rte_eth_dev_info *dev_info)
 343 {
 344         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 345
 346         DPAA_PMD_DEBUG(": %s", dpaa_intf->name);
 347
 348         dev_info->max_rx_queues = dpaa_intf->nb_rx_queues;
 349         dev_info->max_tx_queues = dpaa_intf->nb_tx_queues;
 350         dev_info->max_rx_pktlen = DPAA_MAX_RX_PKT_LEN;
 351         dev_info->max_mac_addrs = DPAA_MAX_MAC_FILTER;
 352         dev_info->max_hash_mac_addrs = 0;
 353         dev_info->max_vfs = 0;
 354         dev_info->max_vmdq_pools = ETH_16_POOLS;
 355         dev_info->flow_type_rss_offloads = DPAA_RSS_OFFLOAD_ALL;
 356
 357         if (dpaa_intf->fif->mac_type == fman_mac_1g) {
 358                 dev_info->speed_capa = ETH_LINK_SPEED_1G;
 359         } else if (dpaa_intf->fif->mac_type == fman_mac_2_5g) {
 360                 dev_info->speed_capa = ETH_LINK_SPEED_1G
 361                                         | ETH_LINK_SPEED_2_5G;
 362         } else if (dpaa_intf->fif->mac_type == fman_mac_10g) {
 363                 dev_info->speed_capa = ETH_LINK_SPEED_1G
 364                                         | ETH_LINK_SPEED_2_5G
 365                                         | ETH_LINK_SPEED_10G;
 366         } else {
 367                 DPAA_PMD_ERR("invalid link_speed: %s, %d",
 368                              dpaa_intf->name, dpaa_intf->fif->mac_type);
 369                 return -EINVAL;
 370         }
 371
 372         dev_info->rx_offload_capa = dev_rx_offloads_sup |
 373                                         dev_rx_offloads_nodis;
 374         dev_info->tx_offload_capa = dev_tx_offloads_sup |
 375                                         dev_tx_offloads_nodis;
 376         dev_info->default_rxportconf.burst_size = DPAA_DEF_RX_BURST_SIZE;
 377         dev_info->default_txportconf.burst_size = DPAA_DEF_TX_BURST_SIZE;
 378         dev_info->default_rxportconf.nb_queues = 1;
 379         dev_info->default_txportconf.nb_queues = 1;
 380         dev_info->default_txportconf.ring_size = CGR_TX_CGR_THRESH;
 381         dev_info->default_rxportconf.ring_size = CGR_RX_PERFQ_THRESH;
 382
 383         return 0;
 384 }
 385
 386 static int dpaa_eth_link_update(struct rte_eth_dev *dev,
 387                                 int wait_to_complete __rte_unused)
 388 {
 389         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 390         struct rte_eth_link *link = &dev->data->dev_link;
 391
 392         PMD_INIT_FUNC_TRACE();
 393
 394         if (dpaa_intf->fif->mac_type == fman_mac_1g)
 395                 link->link_speed = ETH_SPEED_NUM_1G;
 396         else if (dpaa_intf->fif->mac_type == fman_mac_2_5g)
 397                 link->link_speed = ETH_SPEED_NUM_2_5G;
 398         else if (dpaa_intf->fif->mac_type == fman_mac_10g)
 399                 link->link_speed = ETH_SPEED_NUM_10G;
 400         else
 401                 DPAA_PMD_ERR("invalid link_speed: %s, %d",
 402                              dpaa_intf->name, dpaa_intf->fif->mac_type);
 403
 404         link->link_status = dpaa_intf->valid;
 405         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 406         link->link_autoneg = ETH_LINK_AUTONEG;
 407         return 0;
 408 }
 409
 410 static int dpaa_eth_stats_get(struct rte_eth_dev *dev,
 411                                struct rte_eth_stats *stats)
 412 {
 413         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 414
 415         PMD_INIT_FUNC_TRACE();
 416
 417         fman_if_stats_get(dpaa_intf->fif, stats);
 418         return 0;
 419 }
 420
 421 static int dpaa_eth_stats_reset(struct rte_eth_dev *dev)
 422 {
 423         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 424
 425         PMD_INIT_FUNC_TRACE();
 426
 427         fman_if_stats_reset(dpaa_intf->fif);
 428
 429         return 0;
 430 }
 431
 432 static int
 433 dpaa_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
 434                     unsigned int n)
 435 {
 436         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 437         unsigned int i = 0, num = RTE_DIM(dpaa_xstats_strings);
 438         uint64_t values[sizeof(struct dpaa_if_stats) / 8];
 439
 440         if (n < num)
 441                 return num;
 442
 443         if (xstats == NULL)
 444                 return 0;
 445
 446         fman_if_stats_get_all(dpaa_intf->fif, values,
 447                               sizeof(struct dpaa_if_stats) / 8);
 448
 449         for (i = 0; i < num; i++) {
 450                 xstats[i].id = i;
 451                 xstats[i].value = values[dpaa_xstats_strings[i].offset / 8];
 452         }
 453         return i;
 454 }
 455
 456 static int
 457 dpaa_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 458                       struct rte_eth_xstat_name *xstats_names,
 459                       unsigned int limit)
 460 {
 461         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 462
 463         if (limit < stat_cnt)
 464                 return stat_cnt;
 465
 466         if (xstats_names != NULL)
 467                 for (i = 0; i < stat_cnt; i++)
 468                         strlcpy(xstats_names[i].name,
 469                                 dpaa_xstats_strings[i].name,
 470                                 sizeof(xstats_names[i].name));
 471
 472         return stat_cnt;
 473 }
 474
 475 static int
 476 dpaa_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 477                       uint64_t *values, unsigned int n)
 478 {
 479         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 480         uint64_t values_copy[sizeof(struct dpaa_if_stats) / 8];
 481
 482         if (!ids) {
 483                 struct dpaa_if *dpaa_intf = dev->data->dev_private;
 484
 485                 if (n < stat_cnt)
 486                         return stat_cnt;
 487
 488                 if (!values)
 489                         return 0;
 490
 491                 fman_if_stats_get_all(dpaa_intf->fif, values_copy,
 492                                       sizeof(struct dpaa_if_stats) / 8);
 493
 494                 for (i = 0; i < stat_cnt; i++)
 495                         values[i] =
 496                                 values_copy[dpaa_xstats_strings[i].offset / 8];
 497
 498                 return stat_cnt;
 499         }
 500
 501         dpaa_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
 502
 503         for (i = 0; i < n; i++) {
 504                 if (ids[i] >= stat_cnt) {
 505                         DPAA_PMD_ERR("id value isn't valid");
 506                         return -1;
 507                 }
 508                 values[i] = values_copy[ids[i]];
 509         }
 510         return n;
 511 }
 512
 513 static int
 514 dpaa_xstats_get_names_by_id(
 515         struct rte_eth_dev *dev,
 516         struct rte_eth_xstat_name *xstats_names,
 517         const uint64_t *ids,
 518         unsigned int limit)
 519 {
 520         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 521         struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
 522
 523         if (!ids)
 524                 return dpaa_xstats_get_names(dev, xstats_names, limit);
 525
 526         dpaa_xstats_get_names(dev, xstats_names_copy, limit);
 527
 528         for (i = 0; i < limit; i++) {
 529                 if (ids[i] >= stat_cnt) {
 530                         DPAA_PMD_ERR("id value isn't valid");
 531                         return -1;
 532                 }
 533                 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
 534         }
 535         return limit;
 536 }
 537
 538 static int dpaa_eth_promiscuous_enable(struct rte_eth_dev *dev)
 539 {
 540         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 541
 542         PMD_INIT_FUNC_TRACE();
 543
 544         fman_if_promiscuous_enable(dpaa_intf->fif);
 545
 546         return 0;
 547 }
 548
 549 static int dpaa_eth_promiscuous_disable(struct rte_eth_dev *dev)
 550 {
 551         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 552
 553         PMD_INIT_FUNC_TRACE();
 554
 555         fman_if_promiscuous_disable(dpaa_intf->fif);
 556
 557         return 0;
 558 }
 559
 560 static int dpaa_eth_multicast_enable(struct rte_eth_dev *dev)
 561 {
 562         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 563
 564         PMD_INIT_FUNC_TRACE();
 565
 566         fman_if_set_mcast_filter_table(dpaa_intf->fif);
 567
 568         return 0;
 569 }
 570
 571 static int dpaa_eth_multicast_disable(struct rte_eth_dev *dev)
 572 {
 573         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 574
 575         PMD_INIT_FUNC_TRACE();
 576
 577         fman_if_reset_mcast_filter_table(dpaa_intf->fif);
 578
 579         return 0;
 580 }
 581
 582 static
 583 int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 584                             uint16_t nb_desc,
 585                             unsigned int socket_id __rte_unused,
 586                             const struct rte_eth_rxconf *rx_conf __rte_unused,
 587                             struct rte_mempool *mp)
 588 {
 589         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 590         struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_idx];
 591         struct qm_mcc_initfq opts = {0};
 592         u32 flags = 0;
 593         int ret;
 594         u32 buffsz = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
 595
 596         PMD_INIT_FUNC_TRACE();
 597
 598         if (queue_idx >= dev->data->nb_rx_queues) {
 599                 rte_errno = EOVERFLOW;
 600                 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
 601                       (void *)dev, queue_idx, dev->data->nb_rx_queues);
 602                 return -rte_errno;
 603         }
 604
 605         DPAA_PMD_INFO("Rx queue setup for queue index: %d fq_id (0x%x)",
 606                         queue_idx, rxq->fqid);
 607
 608         /* Max packet can fit in single buffer */
 609         if (dev->data->dev_conf.rxmode.max_rx_pkt_len <= buffsz) {
 610                 ;
 611         } else if (dev->data->dev_conf.rxmode.offloads &
 612                         DEV_RX_OFFLOAD_SCATTER) {
 613                 if (dev->data->dev_conf.rxmode.max_rx_pkt_len >
 614                         buffsz * DPAA_SGT_MAX_ENTRIES) {
 615                         DPAA_PMD_ERR("max RxPkt size %d too big to fit "
 616                                 "MaxSGlist %d",
 617                                 dev->data->dev_conf.rxmode.max_rx_pkt_len,
 618                                 buffsz * DPAA_SGT_MAX_ENTRIES);
 619                         rte_errno = EOVERFLOW;
 620                         return -rte_errno;
 621                 }
 622         } else {
 623                 DPAA_PMD_WARN("The requested maximum Rx packet size (%u) is"
 624                      " larger than a single mbuf (%u) and scattered"
 625                      " mode has not been requested",
 626                      dev->data->dev_conf.rxmode.max_rx_pkt_len,
 627                      buffsz - RTE_PKTMBUF_HEADROOM);
 628         }
 629
 630         if (!dpaa_intf->bp_info || dpaa_intf->bp_info->mp != mp) {
 631                 struct fman_if_ic_params icp;
 632                 uint32_t fd_offset;
 633                 uint32_t bp_size;
 634
 635                 if (!mp->pool_data) {
 636                         DPAA_PMD_ERR("Not an offloaded buffer pool!");
 637                         return -1;
 638                 }
 639                 dpaa_intf->bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp);
 640
 641                 memset(&icp, 0, sizeof(icp));
 642                 /* set ICEOF for to the default value , which is 0*/
 643                 icp.iciof = DEFAULT_ICIOF;
 644                 icp.iceof = DEFAULT_RX_ICEOF;
 645                 icp.icsz = DEFAULT_ICSZ;
 646                 fman_if_set_ic_params(dpaa_intf->fif, &icp);
 647
 648                 fd_offset = RTE_PKTMBUF_HEADROOM + DPAA_HW_BUF_RESERVE;
 649                 fman_if_set_fdoff(dpaa_intf->fif, fd_offset);
 650
 651                 /* Buffer pool size should be equal to Dataroom Size*/
 652                 bp_size = rte_pktmbuf_data_room_size(mp);
 653                 fman_if_set_bp(dpaa_intf->fif, mp->size,
 654                                dpaa_intf->bp_info->bpid, bp_size);
 655                 dpaa_intf->valid = 1;
 656                 DPAA_PMD_DEBUG("if:%s fd_offset = %d offset = %d",
 657                                 dpaa_intf->name, fd_offset,
 658                                 fman_if_get_fdoff(dpaa_intf->fif));
 659         }
 660         DPAA_PMD_DEBUG("if:%s sg_on = %d, max_frm =%d", dpaa_intf->name,
 661                 fman_if_get_sg_enable(dpaa_intf->fif),
 662                 dev->data->dev_conf.rxmode.max_rx_pkt_len);
 663         /* checking if push mode only, no error check for now */
 664         if (!rxq->is_static &&
 665             dpaa_push_mode_max_queue > dpaa_push_queue_idx) {
 666                 struct qman_portal *qp;
 667                 int q_fd;
 668
 669                 dpaa_push_queue_idx++;
 670                 opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
 671                 opts.fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK |
 672                                    QM_FQCTRL_CTXASTASHING |
 673                                    QM_FQCTRL_PREFERINCACHE;
 674                 opts.fqd.context_a.stashing.exclusive = 0;
 675                 /* In muticore scenario stashing becomes a bottleneck on LS1046.
 676                  * So do not enable stashing in this case
 677                  */
 678                 if (dpaa_svr_family != SVR_LS1046A_FAMILY)
 679                         opts.fqd.context_a.stashing.annotation_cl =
 680                                                 DPAA_IF_RX_ANNOTATION_STASH;
 681                 opts.fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
 682                 opts.fqd.context_a.stashing.context_cl =
 683                                                 DPAA_IF_RX_CONTEXT_STASH;
 684
 685                 /*Create a channel and associate given queue with the channel*/
 686                 qman_alloc_pool_range((u32 *)&rxq->ch_id, 1, 1, 0);
 687                 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
 688                 opts.fqd.dest.channel = rxq->ch_id;
 689                 opts.fqd.dest.wq = DPAA_IF_RX_PRIORITY;
 690                 flags = QMAN_INITFQ_FLAG_SCHED;
 691
 692                 /* Configure tail drop */
 693                 if (dpaa_intf->cgr_rx) {
 694                         opts.we_mask |= QM_INITFQ_WE_CGID;
 695                         opts.fqd.cgid = dpaa_intf->cgr_rx[queue_idx].cgrid;
 696                         opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
 697                 }
 698                 ret = qman_init_fq(rxq, flags, &opts);
 699                 if (ret) {
 700                         DPAA_PMD_ERR("Channel/Q association failed. fqid 0x%x "
 701                                 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
 702                         return ret;
 703                 }
 704                 if (dpaa_svr_family == SVR_LS1043A_FAMILY) {
 705                         rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb_no_prefetch;
 706                 } else {
 707                         rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb;
 708                         rxq->cb.dqrr_prepare = dpaa_rx_cb_prepare;
 709                 }
 710
 711                 rxq->is_static = true;
 712
 713                 /* Allocate qman specific portals */
 714                 qp = fsl_qman_fq_portal_create(&q_fd);
 715                 if (!qp) {
 716                         DPAA_PMD_ERR("Unable to alloc fq portal");
 717                         return -1;
 718                 }
 719                 rxq->qp = qp;
 720
 721                 /* Set up the device interrupt handler */
 722                 if (!dev->intr_handle) {
 723                         struct rte_dpaa_device *dpaa_dev;
 724                         struct rte_device *rdev = dev->device;
 725
 726                         dpaa_dev = container_of(rdev, struct rte_dpaa_device,
 727                                                 device);
 728                         dev->intr_handle = &dpaa_dev->intr_handle;
 729                         dev->intr_handle->intr_vec = rte_zmalloc(NULL,
 730                                         dpaa_push_mode_max_queue, 0);
 731                         if (!dev->intr_handle->intr_vec) {
 732                                 DPAA_PMD_ERR("intr_vec alloc failed");
 733                                 return -ENOMEM;
 734                         }
 735                         dev->intr_handle->nb_efd = dpaa_push_mode_max_queue;
 736                         dev->intr_handle->max_intr = dpaa_push_mode_max_queue;
 737                 }
 738
 739                 dev->intr_handle->type = RTE_INTR_HANDLE_EXT;
 740                 dev->intr_handle->intr_vec[queue_idx] = queue_idx + 1;
 741                 dev->intr_handle->efds[queue_idx] = q_fd;
 742                 rxq->q_fd = q_fd;
 743         }
 744         rxq->bp_array = rte_dpaa_bpid_info;
 745         dev->data->rx_queues[queue_idx] = rxq;
 746
 747         /* configure the CGR size as per the desc size */
 748         if (dpaa_intf->cgr_rx) {
 749                 struct qm_mcc_initcgr cgr_opts = {0};
 750
 751                 /* Enable tail drop with cgr on this queue */
 752                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, nb_desc, 0);
 753                 ret = qman_modify_cgr(dpaa_intf->cgr_rx, 0, &cgr_opts);
 754                 if (ret) {
 755                         DPAA_PMD_WARN(
 756                                 "rx taildrop modify fail on fqid %d (ret=%d)",
 757                                 rxq->fqid, ret);
 758                 }
 759         }
 760
 761         return 0;
 762 }
 763
 764 int
 765 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev,
 766                 int eth_rx_queue_id,
 767                 u16 ch_id,
 768                 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
 769 {
 770         int ret;
 771         u32 flags = 0;
 772         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 773         struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
 774         struct qm_mcc_initfq opts = {0};
 775
 776         if (dpaa_push_mode_max_queue)
 777                 DPAA_PMD_WARN("PUSH mode q and EVENTDEV are not compatible\n"
 778                               "PUSH mode already enabled for first %d queues.\n"
 779                               "To disable set DPAA_PUSH_QUEUES_NUMBER to 0\n",
 780                               dpaa_push_mode_max_queue);
 781
 782         dpaa_poll_queue_default_config(&opts);
 783
 784         switch (queue_conf->ev.sched_type) {
 785         case RTE_SCHED_TYPE_ATOMIC:
 786                 opts.fqd.fq_ctrl |= QM_FQCTRL_HOLDACTIVE;
 787                 /* Reset FQCTRL_AVOIDBLOCK bit as it is unnecessary
 788                  * configuration with HOLD_ACTIVE setting
 789                  */
 790                 opts.fqd.fq_ctrl &= (~QM_FQCTRL_AVOIDBLOCK);
 791                 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_atomic;
 792                 break;
 793         case RTE_SCHED_TYPE_ORDERED:
 794                 DPAA_PMD_ERR("Ordered queue schedule type is not supported\n");
 795                 return -1;
 796         default:
 797                 opts.fqd.fq_ctrl |= QM_FQCTRL_AVOIDBLOCK;
 798                 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_parallel;
 799                 break;
 800         }
 801
 802         opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
 803         opts.fqd.dest.channel = ch_id;
 804         opts.fqd.dest.wq = queue_conf->ev.priority;
 805
 806         if (dpaa_intf->cgr_rx) {
 807                 opts.we_mask |= QM_INITFQ_WE_CGID;
 808                 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
 809                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
 810         }
 811
 812         flags = QMAN_INITFQ_FLAG_SCHED;
 813
 814         ret = qman_init_fq(rxq, flags, &opts);
 815         if (ret) {
 816                 DPAA_PMD_ERR("Ev-Channel/Q association failed. fqid 0x%x "
 817                                 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
 818                 return ret;
 819         }
 820
 821         /* copy configuration which needs to be filled during dequeue */
 822         memcpy(&rxq->ev, &queue_conf->ev, sizeof(struct rte_event));
 823         dev->data->rx_queues[eth_rx_queue_id] = rxq;
 824
 825         return ret;
 826 }
 827
 828 int
 829 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev,
 830                 int eth_rx_queue_id)
 831 {
 832         struct qm_mcc_initfq opts;
 833         int ret;
 834         u32 flags = 0;
 835         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 836         struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
 837
 838         dpaa_poll_queue_default_config(&opts);
 839
 840         if (dpaa_intf->cgr_rx) {
 841                 opts.we_mask |= QM_INITFQ_WE_CGID;
 842                 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
 843                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
 844         }
 845
 846         ret = qman_init_fq(rxq, flags, &opts);
 847         if (ret) {
 848                 DPAA_PMD_ERR("init rx fqid %d failed with ret: %d",
 849                              rxq->fqid, ret);
 850         }
 851
 852         rxq->cb.dqrr_dpdk_cb = NULL;
 853         dev->data->rx_queues[eth_rx_queue_id] = NULL;
 854
 855         return 0;
 856 }
 857
 858 static
 859 void dpaa_eth_rx_queue_release(void *rxq __rte_unused)
 860 {
 861         PMD_INIT_FUNC_TRACE();
 862 }
 863
 864 static
 865 int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 866                             uint16_t nb_desc __rte_unused,
 867                 unsigned int socket_id __rte_unused,
 868                 const struct rte_eth_txconf *tx_conf __rte_unused)
 869 {
 870         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 871
 872         PMD_INIT_FUNC_TRACE();
 873
 874         if (queue_idx >= dev->data->nb_tx_queues) {
 875                 rte_errno = EOVERFLOW;
 876                 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
 877                       (void *)dev, queue_idx, dev->data->nb_tx_queues);
 878                 return -rte_errno;
 879         }
 880
 881         DPAA_PMD_INFO("Tx queue setup for queue index: %d fq_id (0x%x)",
 882                         queue_idx, dpaa_intf->tx_queues[queue_idx].fqid);
 883         dev->data->tx_queues[queue_idx] = &dpaa_intf->tx_queues[queue_idx];
 884
 885         return 0;
 886 }
 887
 888 static void dpaa_eth_tx_queue_release(void *txq __rte_unused)
 889 {
 890         PMD_INIT_FUNC_TRACE();
 891 }
 892
 893 static uint32_t
 894 dpaa_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 895 {
 896         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 897         struct qman_fq *rxq = &dpaa_intf->rx_queues[rx_queue_id];
 898         u32 frm_cnt = 0;
 899
 900         PMD_INIT_FUNC_TRACE();
 901
 902         if (qman_query_fq_frm_cnt(rxq, &frm_cnt) == 0) {
 903                 DPAA_PMD_DEBUG("RX frame count for q(%d) is %u",
 904                                rx_queue_id, frm_cnt);
 905         }
 906         return frm_cnt;
 907 }
 908
 909 static int dpaa_link_down(struct rte_eth_dev *dev)
 910 {
 911         PMD_INIT_FUNC_TRACE();
 912
 913         dpaa_eth_dev_stop(dev);
 914         return 0;
 915 }
 916
 917 static int dpaa_link_up(struct rte_eth_dev *dev)
 918 {
 919         PMD_INIT_FUNC_TRACE();
 920
 921         dpaa_eth_dev_start(dev);
 922         return 0;
 923 }
 924
 925 static int
 926 dpaa_flow_ctrl_set(struct rte_eth_dev *dev,
 927                    struct rte_eth_fc_conf *fc_conf)
 928 {
 929         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 930         struct rte_eth_fc_conf *net_fc;
 931
 932         PMD_INIT_FUNC_TRACE();
 933
 934         if (!(dpaa_intf->fc_conf)) {
 935                 dpaa_intf->fc_conf = rte_zmalloc(NULL,
 936                         sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
 937                 if (!dpaa_intf->fc_conf) {
 938                         DPAA_PMD_ERR("unable to save flow control info");
 939                         return -ENOMEM;
 940                 }
 941         }
 942         net_fc = dpaa_intf->fc_conf;
 943
 944         if (fc_conf->high_water < fc_conf->low_water) {
 945                 DPAA_PMD_ERR("Incorrect Flow Control Configuration");
 946                 return -EINVAL;
 947         }
 948
 949         if (fc_conf->mode == RTE_FC_NONE) {
 950                 return 0;
 951         } else if (fc_conf->mode == RTE_FC_TX_PAUSE ||
 952                  fc_conf->mode == RTE_FC_FULL) {
 953                 fman_if_set_fc_threshold(dpaa_intf->fif, fc_conf->high_water,
 954                                          fc_conf->low_water,
 955                                 dpaa_intf->bp_info->bpid);
 956                 if (fc_conf->pause_time)
 957                         fman_if_set_fc_quanta(dpaa_intf->fif,
 958                                               fc_conf->pause_time);
 959         }
 960
 961         /* Save the information in dpaa device */
 962         net_fc->pause_time = fc_conf->pause_time;
 963         net_fc->high_water = fc_conf->high_water;
 964         net_fc->low_water = fc_conf->low_water;
 965         net_fc->send_xon = fc_conf->send_xon;
 966         net_fc->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
 967         net_fc->mode = fc_conf->mode;
 968         net_fc->autoneg = fc_conf->autoneg;
 969
 970         return 0;
 971 }
 972
 973 static int
 974 dpaa_flow_ctrl_get(struct rte_eth_dev *dev,
 975                    struct rte_eth_fc_conf *fc_conf)
 976 {
 977         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 978         struct rte_eth_fc_conf *net_fc = dpaa_intf->fc_conf;
 979         int ret;
 980
 981         PMD_INIT_FUNC_TRACE();
 982
 983         if (net_fc) {
 984                 fc_conf->pause_time = net_fc->pause_time;
 985                 fc_conf->high_water = net_fc->high_water;
 986                 fc_conf->low_water = net_fc->low_water;
 987                 fc_conf->send_xon = net_fc->send_xon;
 988                 fc_conf->mac_ctrl_frame_fwd = net_fc->mac_ctrl_frame_fwd;
 989                 fc_conf->mode = net_fc->mode;
 990                 fc_conf->autoneg = net_fc->autoneg;
 991                 return 0;
 992         }
 993         ret = fman_if_get_fc_threshold(dpaa_intf->fif);
 994         if (ret) {
 995                 fc_conf->mode = RTE_FC_TX_PAUSE;
 996                 fc_conf->pause_time = fman_if_get_fc_quanta(dpaa_intf->fif);
 997         } else {
 998                 fc_conf->mode = RTE_FC_NONE;
 999         }
1000
1001         return 0;
1002 }
1003
1004 static int
1005 dpaa_dev_add_mac_addr(struct rte_eth_dev *dev,
1006                              struct rte_ether_addr *addr,
1007                              uint32_t index,
1008                              __rte_unused uint32_t pool)
1009 {
1010         int ret;
1011         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1012
1013         PMD_INIT_FUNC_TRACE();
1014
1015         ret = fman_if_add_mac_addr(dpaa_intf->fif, addr->addr_bytes, index);
1016
1017         if (ret)
1018                 DPAA_PMD_ERR("Adding the MAC ADDR failed: err = %d", ret);
1019         return 0;
1020 }
1021
1022 static void
1023 dpaa_dev_remove_mac_addr(struct rte_eth_dev *dev,
1024                           uint32_t index)
1025 {
1026         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1027
1028         PMD_INIT_FUNC_TRACE();
1029
1030         fman_if_clear_mac_addr(dpaa_intf->fif, index);
1031 }
1032
1033 static int
1034 dpaa_dev_set_mac_addr(struct rte_eth_dev *dev,
1035                        struct rte_ether_addr *addr)
1036 {
1037         int ret;
1038         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1039
1040         PMD_INIT_FUNC_TRACE();
1041
1042         ret = fman_if_add_mac_addr(dpaa_intf->fif, addr->addr_bytes, 0);
1043         if (ret)
1044                 DPAA_PMD_ERR("Setting the MAC ADDR failed %d", ret);
1045
1046         return ret;
1047 }
1048
1049 static int dpaa_dev_queue_intr_enable(struct rte_eth_dev *dev,
1050                                       uint16_t queue_id)
1051 {
1052         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1053         struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id];
1054
1055         if (!rxq->is_static)
1056                 return -EINVAL;
1057
1058         return qman_fq_portal_irqsource_add(rxq->qp, QM_PIRQ_DQRI);
1059 }
1060
1061 static int dpaa_dev_queue_intr_disable(struct rte_eth_dev *dev,
1062                                        uint16_t queue_id)
1063 {
1064         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1065         struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id];
1066         uint32_t temp;
1067         ssize_t temp1;
1068
1069         if (!rxq->is_static)
1070                 return -EINVAL;
1071
1072         qman_fq_portal_irqsource_remove(rxq->qp, ~0);
1073
1074         temp1 = read(rxq->q_fd, &temp, sizeof(temp));
1075         if (temp1 != sizeof(temp))
1076                 DPAA_PMD_ERR("irq read error");
1077
1078         qman_fq_portal_thread_irq(rxq->qp);
1079
1080         return 0;
1081 }
1082
1083 static struct eth_dev_ops dpaa_devops = {
1084         .dev_configure            = dpaa_eth_dev_configure,
1085         .dev_start                = dpaa_eth_dev_start,
1086         .dev_stop                 = dpaa_eth_dev_stop,
1087         .dev_close                = dpaa_eth_dev_close,
1088         .dev_infos_get            = dpaa_eth_dev_info,
1089         .dev_supported_ptypes_get = dpaa_supported_ptypes_get,
1090
1091         .rx_queue_setup           = dpaa_eth_rx_queue_setup,
1092         .tx_queue_setup           = dpaa_eth_tx_queue_setup,
1093         .rx_queue_release         = dpaa_eth_rx_queue_release,
1094         .tx_queue_release         = dpaa_eth_tx_queue_release,
1095         .rx_queue_count           = dpaa_dev_rx_queue_count,
1096
1097         .flow_ctrl_get            = dpaa_flow_ctrl_get,
1098         .flow_ctrl_set            = dpaa_flow_ctrl_set,
1099
1100         .link_update              = dpaa_eth_link_update,
1101         .stats_get                = dpaa_eth_stats_get,
1102         .xstats_get               = dpaa_dev_xstats_get,
1103         .xstats_get_by_id         = dpaa_xstats_get_by_id,
1104         .xstats_get_names_by_id   = dpaa_xstats_get_names_by_id,
1105         .xstats_get_names         = dpaa_xstats_get_names,
1106         .xstats_reset             = dpaa_eth_stats_reset,
1107         .stats_reset              = dpaa_eth_stats_reset,
1108         .promiscuous_enable       = dpaa_eth_promiscuous_enable,
1109         .promiscuous_disable      = dpaa_eth_promiscuous_disable,
1110         .allmulticast_enable      = dpaa_eth_multicast_enable,
1111         .allmulticast_disable     = dpaa_eth_multicast_disable,
1112         .mtu_set                  = dpaa_mtu_set,
1113         .dev_set_link_down        = dpaa_link_down,
1114         .dev_set_link_up          = dpaa_link_up,
1115         .mac_addr_add             = dpaa_dev_add_mac_addr,
1116         .mac_addr_remove          = dpaa_dev_remove_mac_addr,
1117         .mac_addr_set             = dpaa_dev_set_mac_addr,
1118
1119         .fw_version_get           = dpaa_fw_version_get,
1120
1121         .rx_queue_intr_enable     = dpaa_dev_queue_intr_enable,
1122         .rx_queue_intr_disable    = dpaa_dev_queue_intr_disable,
1123 };
1124
1125 static bool
1126 is_device_supported(struct rte_eth_dev *dev, struct rte_dpaa_driver *drv)
1127 {
1128         if (strcmp(dev->device->driver->name,
1129                    drv->driver.name))
1130                 return false;
1131
1132         return true;
1133 }
1134
1135 static bool
1136 is_dpaa_supported(struct rte_eth_dev *dev)
1137 {
1138         return is_device_supported(dev, &rte_dpaa_pmd);
1139 }
1140
1141 int
1142 rte_pmd_dpaa_set_tx_loopback(uint8_t port, uint8_t on)
1143 {
1144         struct rte_eth_dev *dev;
1145         struct dpaa_if *dpaa_intf;
1146
1147         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
1148
1149         dev = &rte_eth_devices[port];
1150
1151         if (!is_dpaa_supported(dev))
1152                 return -ENOTSUP;
1153
1154         dpaa_intf = dev->data->dev_private;
1155
1156         if (on)
1157                 fman_if_loopback_enable(dpaa_intf->fif);
1158         else
1159                 fman_if_loopback_disable(dpaa_intf->fif);
1160
1161         return 0;
1162 }
1163
1164 static int dpaa_fc_set_default(struct dpaa_if *dpaa_intf)
1165 {
1166         struct rte_eth_fc_conf *fc_conf;
1167         int ret;
1168
1169         PMD_INIT_FUNC_TRACE();
1170
1171         if (!(dpaa_intf->fc_conf)) {
1172                 dpaa_intf->fc_conf = rte_zmalloc(NULL,
1173                         sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
1174                 if (!dpaa_intf->fc_conf) {
1175                         DPAA_PMD_ERR("unable to save flow control info");
1176                         return -ENOMEM;
1177                 }
1178         }
1179         fc_conf = dpaa_intf->fc_conf;
1180         ret = fman_if_get_fc_threshold(dpaa_intf->fif);
1181         if (ret) {
1182                 fc_conf->mode = RTE_FC_TX_PAUSE;
1183                 fc_conf->pause_time = fman_if_get_fc_quanta(dpaa_intf->fif);
1184         } else {
1185                 fc_conf->mode = RTE_FC_NONE;
1186         }
1187
1188         return 0;
1189 }
1190
1191 /* Initialise an Rx FQ */
1192 static int dpaa_rx_queue_init(struct qman_fq *fq, struct qman_cgr *cgr_rx,
1193                               uint32_t fqid)
1194 {
1195         struct qm_mcc_initfq opts = {0};
1196         int ret;
1197         u32 flags = QMAN_FQ_FLAG_NO_ENQUEUE;
1198         struct qm_mcc_initcgr cgr_opts = {
1199                 .we_mask = QM_CGR_WE_CS_THRES |
1200                                 QM_CGR_WE_CSTD_EN |
1201                                 QM_CGR_WE_MODE,
1202                 .cgr = {
1203                         .cstd_en = QM_CGR_EN,
1204                         .mode = QMAN_CGR_MODE_FRAME
1205                 }
1206         };
1207
1208         if (fqid) {
1209                 ret = qman_reserve_fqid(fqid);
1210                 if (ret) {
1211                         DPAA_PMD_ERR("reserve rx fqid 0x%x failed with ret: %d",
1212                                      fqid, ret);
1213                         return -EINVAL;
1214                 }
1215         } else {
1216                 flags |= QMAN_FQ_FLAG_DYNAMIC_FQID;
1217         }
1218         DPAA_PMD_DEBUG("creating rx fq %p, fqid 0x%x", fq, fqid);
1219         ret = qman_create_fq(fqid, flags, fq);
1220         if (ret) {
1221                 DPAA_PMD_ERR("create rx fqid 0x%x failed with ret: %d",
1222                         fqid, ret);
1223                 return ret;
1224         }
1225         fq->is_static = false;
1226
1227         dpaa_poll_queue_default_config(&opts);
1228
1229         if (cgr_rx) {
1230                 /* Enable tail drop with cgr on this queue */
1231                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, td_threshold, 0);
1232                 cgr_rx->cb = NULL;
1233                 ret = qman_create_cgr(cgr_rx, QMAN_CGR_FLAG_USE_INIT,
1234                                       &cgr_opts);
1235                 if (ret) {
1236                         DPAA_PMD_WARN(
1237                                 "rx taildrop init fail on rx fqid 0x%x(ret=%d)",
1238                                 fq->fqid, ret);
1239                         goto without_cgr;
1240                 }
1241                 opts.we_mask |= QM_INITFQ_WE_CGID;
1242                 opts.fqd.cgid = cgr_rx->cgrid;
1243                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1244         }
1245 without_cgr:
1246         ret = qman_init_fq(fq, 0, &opts);
1247         if (ret)
1248                 DPAA_PMD_ERR("init rx fqid 0x%x failed with ret:%d", fqid, ret);
1249         return ret;
1250 }
1251
1252 /* Initialise a Tx FQ */
1253 static int dpaa_tx_queue_init(struct qman_fq *fq,
1254                               struct fman_if *fman_intf,
1255                               struct qman_cgr *cgr_tx)
1256 {
1257         struct qm_mcc_initfq opts = {0};
1258         struct qm_mcc_initcgr cgr_opts = {
1259                 .we_mask = QM_CGR_WE_CS_THRES |
1260                                 QM_CGR_WE_CSTD_EN |
1261                                 QM_CGR_WE_MODE,
1262                 .cgr = {
1263                         .cstd_en = QM_CGR_EN,
1264                         .mode = QMAN_CGR_MODE_FRAME
1265                 }
1266         };
1267         int ret;
1268
1269         ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID |
1270                              QMAN_FQ_FLAG_TO_DCPORTAL, fq);
1271         if (ret) {
1272                 DPAA_PMD_ERR("create tx fq failed with ret: %d", ret);
1273                 return ret;
1274         }
1275         opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL |
1276                        QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA;
1277         opts.fqd.dest.channel = fman_intf->tx_channel_id;
1278         opts.fqd.dest.wq = DPAA_IF_TX_PRIORITY;
1279         opts.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE;
1280         opts.fqd.context_b = 0;
1281         /* no tx-confirmation */
1282         opts.fqd.context_a.hi = 0x80000000 | fman_dealloc_bufs_mask_hi;
1283         opts.fqd.context_a.lo = 0 | fman_dealloc_bufs_mask_lo;
1284         DPAA_PMD_DEBUG("init tx fq %p, fqid 0x%x", fq, fq->fqid);
1285
1286         if (cgr_tx) {
1287                 /* Enable tail drop with cgr on this queue */
1288                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres,
1289                                       td_tx_threshold, 0);
1290                 cgr_tx->cb = NULL;
1291                 ret = qman_create_cgr(cgr_tx, QMAN_CGR_FLAG_USE_INIT,
1292                                       &cgr_opts);
1293                 if (ret) {
1294                         DPAA_PMD_WARN(
1295                                 "rx taildrop init fail on rx fqid 0x%x(ret=%d)",
1296                                 fq->fqid, ret);
1297                         goto without_cgr;
1298                 }
1299                 opts.we_mask |= QM_INITFQ_WE_CGID;
1300                 opts.fqd.cgid = cgr_tx->cgrid;
1301                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1302                 DPAA_PMD_DEBUG("Tx FQ tail drop enabled, threshold = %d\n",
1303                                 td_tx_threshold);
1304         }
1305 without_cgr:
1306         ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts);
1307         if (ret)
1308                 DPAA_PMD_ERR("init tx fqid 0x%x failed %d", fq->fqid, ret);
1309         return ret;
1310 }
1311
1312 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1313 /* Initialise a DEBUG FQ ([rt]x_error, rx_default). */
1314 static int dpaa_debug_queue_init(struct qman_fq *fq, uint32_t fqid)
1315 {
1316         struct qm_mcc_initfq opts = {0};
1317         int ret;
1318
1319         PMD_INIT_FUNC_TRACE();
1320
1321         ret = qman_reserve_fqid(fqid);
1322         if (ret) {
1323                 DPAA_PMD_ERR("Reserve debug fqid %d failed with ret: %d",
1324                         fqid, ret);
1325                 return -EINVAL;
1326         }
1327         /* "map" this Rx FQ to one of the interfaces Tx FQID */
1328         DPAA_PMD_DEBUG("Creating debug fq %p, fqid %d", fq, fqid);
1329         ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq);
1330         if (ret) {
1331                 DPAA_PMD_ERR("create debug fqid %d failed with ret: %d",
1332                         fqid, ret);
1333                 return ret;
1334         }
1335         opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL;
1336         opts.fqd.dest.wq = DPAA_IF_DEBUG_PRIORITY;
1337         ret = qman_init_fq(fq, 0, &opts);
1338         if (ret)
1339                 DPAA_PMD_ERR("init debug fqid %d failed with ret: %d",
1340                             fqid, ret);
1341         return ret;
1342 }
1343 #endif
1344
1345 /* Initialise a network interface */
1346 static int
1347 dpaa_dev_init(struct rte_eth_dev *eth_dev)
1348 {
1349         int num_rx_fqs, fqid;
1350         int loop, ret = 0;
1351         int dev_id;
1352         struct rte_dpaa_device *dpaa_device;
1353         struct dpaa_if *dpaa_intf;
1354         struct fm_eth_port_cfg *cfg;
1355         struct fman_if *fman_intf;
1356         struct fman_if_bpool *bp, *tmp_bp;
1357         uint32_t cgrid[DPAA_MAX_NUM_PCD_QUEUES];
1358         uint32_t cgrid_tx[MAX_DPAA_CORES];
1359         char eth_buf[RTE_ETHER_ADDR_FMT_SIZE];
1360
1361         PMD_INIT_FUNC_TRACE();
1362
1363         dpaa_intf = eth_dev->data->dev_private;
1364         /* For secondary processes, the primary has done all the work */
1365         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1366                 eth_dev->dev_ops = &dpaa_devops;
1367                 /* Plugging of UCODE burst API not supported in Secondary */
1368                 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
1369                 if (dpaa_intf->cgr_tx)
1370                         eth_dev->tx_pkt_burst = dpaa_eth_queue_tx_slow;
1371                 else
1372                         eth_dev->tx_pkt_burst = dpaa_eth_queue_tx;
1373 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP
1374                 qman_set_fq_lookup_table(
1375                                 dpaa_intf->rx_queues->qman_fq_lookup_table);
1376 #endif
1377                 return 0;
1378         }
1379
1380         dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1381         dev_id = dpaa_device->id.dev_id;
1382         dpaa_intf = eth_dev->data->dev_private;
1383         cfg = dpaa_get_eth_port_cfg(dev_id);
1384         fman_intf = cfg->fman_if;
1385
1386         dpaa_intf->name = dpaa_device->name;
1387
1388         /* save fman_if & cfg in the interface struture */
1389         dpaa_intf->fif = fman_intf;
1390         dpaa_intf->ifid = dev_id;
1391         dpaa_intf->cfg = cfg;
1392
1393         /* Initialize Rx FQ's */
1394         if (default_q) {
1395                 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES;
1396         } else {
1397                 if (getenv("DPAA_NUM_RX_QUEUES"))
1398                         num_rx_fqs = atoi(getenv("DPAA_NUM_RX_QUEUES"));
1399                 else
1400                         num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES;
1401         }
1402
1403
1404         /* Each device can not have more than DPAA_MAX_NUM_PCD_QUEUES RX
1405          * queues.
1406          */
1407         if (num_rx_fqs <= 0 || num_rx_fqs > DPAA_MAX_NUM_PCD_QUEUES) {
1408                 DPAA_PMD_ERR("Invalid number of RX queues\n");
1409                 return -EINVAL;
1410         }
1411
1412         dpaa_intf->rx_queues = rte_zmalloc(NULL,
1413                 sizeof(struct qman_fq) * num_rx_fqs, MAX_CACHELINE);
1414         if (!dpaa_intf->rx_queues) {
1415                 DPAA_PMD_ERR("Failed to alloc mem for RX queues\n");
1416                 return -ENOMEM;
1417         }
1418
1419         memset(cgrid, 0, sizeof(cgrid));
1420         memset(cgrid_tx, 0, sizeof(cgrid_tx));
1421
1422         /* if DPAA_TX_TAILDROP_THRESHOLD is set, use that value; if 0, it means
1423          * Tx tail drop is disabled.
1424          */
1425         if (getenv("DPAA_TX_TAILDROP_THRESHOLD")) {
1426                 td_tx_threshold = atoi(getenv("DPAA_TX_TAILDROP_THRESHOLD"));
1427                 DPAA_PMD_DEBUG("Tail drop threshold env configured: %u",
1428                                td_tx_threshold);
1429                 /* if a very large value is being configured */
1430                 if (td_tx_threshold > UINT16_MAX)
1431                         td_tx_threshold = CGR_RX_PERFQ_THRESH;
1432         }
1433
1434         /* If congestion control is enabled globally*/
1435         if (td_threshold) {
1436                 dpaa_intf->cgr_rx = rte_zmalloc(NULL,
1437                         sizeof(struct qman_cgr) * num_rx_fqs, MAX_CACHELINE);
1438                 if (!dpaa_intf->cgr_rx) {
1439                         DPAA_PMD_ERR("Failed to alloc mem for cgr_rx\n");
1440                         ret = -ENOMEM;
1441                         goto free_rx;
1442                 }
1443
1444                 ret = qman_alloc_cgrid_range(&cgrid[0], num_rx_fqs, 1, 0);
1445                 if (ret != num_rx_fqs) {
1446                         DPAA_PMD_WARN("insufficient CGRIDs available");
1447                         ret = -EINVAL;
1448                         goto free_rx;
1449                 }
1450         } else {
1451                 dpaa_intf->cgr_rx = NULL;
1452         }
1453
1454         for (loop = 0; loop < num_rx_fqs; loop++) {
1455                 if (default_q)
1456                         fqid = cfg->rx_def;
1457                 else
1458                         fqid = DPAA_PCD_FQID_START + dpaa_intf->fif->mac_idx *
1459                                 DPAA_PCD_FQID_MULTIPLIER + loop;
1460
1461                 if (dpaa_intf->cgr_rx)
1462                         dpaa_intf->cgr_rx[loop].cgrid = cgrid[loop];
1463
1464                 ret = dpaa_rx_queue_init(&dpaa_intf->rx_queues[loop],
1465                         dpaa_intf->cgr_rx ? &dpaa_intf->cgr_rx[loop] : NULL,
1466                         fqid);
1467                 if (ret)
1468                         goto free_rx;
1469                 dpaa_intf->rx_queues[loop].dpaa_intf = dpaa_intf;
1470         }
1471         dpaa_intf->nb_rx_queues = num_rx_fqs;
1472
1473         /* Initialise Tx FQs.free_rx Have as many Tx FQ's as number of cores */
1474         dpaa_intf->tx_queues = rte_zmalloc(NULL, sizeof(struct qman_fq) *
1475                 MAX_DPAA_CORES, MAX_CACHELINE);
1476         if (!dpaa_intf->tx_queues) {
1477                 DPAA_PMD_ERR("Failed to alloc mem for TX queues\n");
1478                 ret = -ENOMEM;
1479                 goto free_rx;
1480         }
1481
1482         /* If congestion control is enabled globally*/
1483         if (td_tx_threshold) {
1484                 dpaa_intf->cgr_tx = rte_zmalloc(NULL,
1485                         sizeof(struct qman_cgr) * MAX_DPAA_CORES,
1486                         MAX_CACHELINE);
1487                 if (!dpaa_intf->cgr_tx) {
1488                         DPAA_PMD_ERR("Failed to alloc mem for cgr_tx\n");
1489                         ret = -ENOMEM;
1490                         goto free_rx;
1491                 }
1492
1493                 ret = qman_alloc_cgrid_range(&cgrid_tx[0], MAX_DPAA_CORES,
1494                                              1, 0);
1495                 if (ret != MAX_DPAA_CORES) {
1496                         DPAA_PMD_WARN("insufficient CGRIDs available");
1497                         ret = -EINVAL;
1498                         goto free_rx;
1499                 }
1500         } else {
1501                 dpaa_intf->cgr_tx = NULL;
1502         }
1503
1504
1505         for (loop = 0; loop < MAX_DPAA_CORES; loop++) {
1506                 if (dpaa_intf->cgr_tx)
1507                         dpaa_intf->cgr_tx[loop].cgrid = cgrid_tx[loop];
1508
1509                 ret = dpaa_tx_queue_init(&dpaa_intf->tx_queues[loop],
1510                         fman_intf,
1511                         dpaa_intf->cgr_tx ? &dpaa_intf->cgr_tx[loop] : NULL);
1512                 if (ret)
1513                         goto free_tx;
1514                 dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf;
1515         }
1516         dpaa_intf->nb_tx_queues = MAX_DPAA_CORES;
1517
1518 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1519         dpaa_debug_queue_init(&dpaa_intf->debug_queues[
1520                 DPAA_DEBUG_FQ_RX_ERROR], fman_intf->fqid_rx_err);
1521         dpaa_intf->debug_queues[DPAA_DEBUG_FQ_RX_ERROR].dpaa_intf = dpaa_intf;
1522         dpaa_debug_queue_init(&dpaa_intf->debug_queues[
1523                 DPAA_DEBUG_FQ_TX_ERROR], fman_intf->fqid_tx_err);
1524         dpaa_intf->debug_queues[DPAA_DEBUG_FQ_TX_ERROR].dpaa_intf = dpaa_intf;
1525 #endif
1526
1527         DPAA_PMD_DEBUG("All frame queues created");
1528
1529         /* Get the initial configuration for flow control */
1530         dpaa_fc_set_default(dpaa_intf);
1531
1532         /* reset bpool list, initialize bpool dynamically */
1533         list_for_each_entry_safe(bp, tmp_bp, &cfg->fman_if->bpool_list, node) {
1534                 list_del(&bp->node);
1535                 rte_free(bp);
1536         }
1537
1538         /* Populate ethdev structure */
1539         eth_dev->dev_ops = &dpaa_devops;
1540         eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
1541         eth_dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
1542
1543         /* Allocate memory for storing MAC addresses */
1544         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr",
1545                 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER, 0);
1546         if (eth_dev->data->mac_addrs == NULL) {
1547                 DPAA_PMD_ERR("Failed to allocate %d bytes needed to "
1548                                                 "store MAC addresses",
1549                                 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER);
1550                 ret = -ENOMEM;
1551                 goto free_tx;
1552         }
1553
1554         /* copy the primary mac address */
1555         rte_ether_addr_copy(&fman_intf->mac_addr, &eth_dev->data->mac_addrs[0]);
1556         rte_ether_format_addr(eth_buf, sizeof(eth_buf), &fman_intf->mac_addr);
1557
1558         DPAA_PMD_INFO("net: dpaa: %s: %s", dpaa_device->name, eth_buf);
1559
1560         /* Disable RX mode */
1561         fman_if_discard_rx_errors(fman_intf);
1562         fman_if_disable_rx(fman_intf);
1563         /* Disable promiscuous mode */
1564         fman_if_promiscuous_disable(fman_intf);
1565         /* Disable multicast */
1566         fman_if_reset_mcast_filter_table(fman_intf);
1567         /* Reset interface statistics */
1568         fman_if_stats_reset(fman_intf);
1569         /* Disable SG by default */
1570         fman_if_set_sg(fman_intf, 0);
1571         fman_if_set_maxfrm(fman_intf, RTE_ETHER_MAX_LEN + VLAN_TAG_SIZE);
1572
1573         return 0;
1574
1575 free_tx:
1576         rte_free(dpaa_intf->tx_queues);
1577         dpaa_intf->tx_queues = NULL;
1578         dpaa_intf->nb_tx_queues = 0;
1579
1580 free_rx:
1581         rte_free(dpaa_intf->cgr_rx);
1582         rte_free(dpaa_intf->cgr_tx);
1583         rte_free(dpaa_intf->rx_queues);
1584         dpaa_intf->rx_queues = NULL;
1585         dpaa_intf->nb_rx_queues = 0;
1586         return ret;
1587 }
1588
1589 static int
1590 dpaa_dev_uninit(struct rte_eth_dev *dev)
1591 {
1592         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1593         int loop;
1594
1595         PMD_INIT_FUNC_TRACE();
1596
1597         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1598                 return -EPERM;
1599
1600         if (!dpaa_intf) {
1601                 DPAA_PMD_WARN("Already closed or not started");
1602                 return -1;
1603         }
1604
1605         dpaa_eth_dev_close(dev);
1606
1607         /* release configuration memory */
1608         if (dpaa_intf->fc_conf)
1609                 rte_free(dpaa_intf->fc_conf);
1610
1611         /* Release RX congestion Groups */
1612         if (dpaa_intf->cgr_rx) {
1613                 for (loop = 0; loop < dpaa_intf->nb_rx_queues; loop++)
1614                         qman_delete_cgr(&dpaa_intf->cgr_rx[loop]);
1615
1616                 qman_release_cgrid_range(dpaa_intf->cgr_rx[loop].cgrid,
1617                                          dpaa_intf->nb_rx_queues);
1618         }
1619
1620         rte_free(dpaa_intf->cgr_rx);
1621         dpaa_intf->cgr_rx = NULL;
1622
1623         /* Release TX congestion Groups */
1624         if (dpaa_intf->cgr_tx) {
1625                 for (loop = 0; loop < MAX_DPAA_CORES; loop++)
1626                         qman_delete_cgr(&dpaa_intf->cgr_tx[loop]);
1627
1628                 qman_release_cgrid_range(dpaa_intf->cgr_tx[loop].cgrid,
1629                                          MAX_DPAA_CORES);
1630                 rte_free(dpaa_intf->cgr_tx);
1631                 dpaa_intf->cgr_tx = NULL;
1632         }
1633
1634         rte_free(dpaa_intf->rx_queues);
1635         dpaa_intf->rx_queues = NULL;
1636
1637         rte_free(dpaa_intf->tx_queues);
1638         dpaa_intf->tx_queues = NULL;
1639
1640         dev->dev_ops = NULL;
1641         dev->rx_pkt_burst = NULL;
1642         dev->tx_pkt_burst = NULL;
1643
1644         return 0;
1645 }
1646
1647 static int
1648 rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv __rte_unused,
1649                struct rte_dpaa_device *dpaa_dev)
1650 {
1651         int diag;
1652         int ret;
1653         struct rte_eth_dev *eth_dev;
1654
1655         PMD_INIT_FUNC_TRACE();
1656
1657         if ((DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE) >
1658                 RTE_PKTMBUF_HEADROOM) {
1659                 DPAA_PMD_ERR(
1660                 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA Annotation req(%d)",
1661                 RTE_PKTMBUF_HEADROOM,
1662                 DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE);
1663
1664                 return -1;
1665         }
1666
1667         /* In case of secondary process, the device is already configured
1668          * and no further action is required, except portal initialization
1669          * and verifying secondary attachment to port name.
1670          */
1671         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1672                 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name);
1673                 if (!eth_dev)
1674                         return -ENOMEM;
1675                 eth_dev->device = &dpaa_dev->device;
1676                 eth_dev->dev_ops = &dpaa_devops;
1677                 rte_eth_dev_probing_finish(eth_dev);
1678                 return 0;
1679         }
1680
1681         if (!is_global_init && (rte_eal_process_type() == RTE_PROC_PRIMARY)) {
1682                 if (access("/tmp/fmc.bin", F_OK) == -1) {
1683                         DPAA_PMD_INFO("* FMC not configured.Enabling default mode");
1684                         default_q = 1;
1685                 }
1686
1687                 /* disabling the default push mode for LS1043 */
1688                 if (dpaa_svr_family == SVR_LS1043A_FAMILY)
1689                         dpaa_push_mode_max_queue = 0;
1690
1691                 /* if push mode queues to be enabled. Currenly we are allowing
1692                  * only one queue per thread.
1693                  */
1694                 if (getenv("DPAA_PUSH_QUEUES_NUMBER")) {
1695                         dpaa_push_mode_max_queue =
1696                                         atoi(getenv("DPAA_PUSH_QUEUES_NUMBER"));
1697                         if (dpaa_push_mode_max_queue > DPAA_MAX_PUSH_MODE_QUEUE)
1698                             dpaa_push_mode_max_queue = DPAA_MAX_PUSH_MODE_QUEUE;
1699                 }
1700
1701                 is_global_init = 1;
1702         }
1703
1704         if (unlikely(!RTE_PER_LCORE(dpaa_io))) {
1705                 ret = rte_dpaa_portal_init((void *)1);
1706                 if (ret) {
1707                         DPAA_PMD_ERR("Unable to initialize portal");
1708                         return ret;
1709                 }
1710         }
1711
1712         /* In case of secondary process, the device is already configured
1713          * and no further action is required, except portal initialization
1714          * and verifying secondary attachment to port name.
1715          */
1716         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1717                 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name);
1718                 if (!eth_dev)
1719                         return -ENOMEM;
1720         } else {
1721                 eth_dev = rte_eth_dev_allocate(dpaa_dev->name);
1722                 if (eth_dev == NULL)
1723                         return -ENOMEM;
1724
1725                 eth_dev->data->dev_private = rte_zmalloc(
1726                                                 "ethdev private structure",
1727                                                 sizeof(struct dpaa_if),
1728                                                 RTE_CACHE_LINE_SIZE);
1729                 if (!eth_dev->data->dev_private) {
1730                         DPAA_PMD_ERR("Cannot allocate memzone for port data");
1731                         rte_eth_dev_release_port(eth_dev);
1732                         return -ENOMEM;
1733                 }
1734         }
1735         eth_dev->device = &dpaa_dev->device;
1736         dpaa_dev->eth_dev = eth_dev;
1737
1738         qman_ern_register_cb(dpaa_free_mbuf);
1739
1740         /* Invoke PMD device initialization function */
1741         diag = dpaa_dev_init(eth_dev);
1742         if (diag == 0) {
1743                 rte_eth_dev_probing_finish(eth_dev);
1744                 return 0;
1745         }
1746
1747         rte_eth_dev_release_port(eth_dev);
1748         return diag;
1749 }
1750
1751 static int
1752 rte_dpaa_remove(struct rte_dpaa_device *dpaa_dev)
1753 {
1754         struct rte_eth_dev *eth_dev;
1755
1756         PMD_INIT_FUNC_TRACE();
1757
1758         eth_dev = dpaa_dev->eth_dev;
1759         dpaa_dev_uninit(eth_dev);
1760
1761         rte_eth_dev_release_port(eth_dev);
1762
1763         return 0;
1764 }
1765
1766 static struct rte_dpaa_driver rte_dpaa_pmd = {
1767         .drv_type = FSL_DPAA_ETH,
1768         .probe = rte_dpaa_probe,
1769         .remove = rte_dpaa_remove,
1770 };
1771
1772 RTE_PMD_REGISTER_DPAA(net_dpaa, rte_dpaa_pmd);
1773 RTE_LOG_REGISTER(dpaa_logtype_pmd, pmd.net.dpaa, NOTICE);