drivers/net/dpaa/dpaa_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  *   Copyright 2016 Freescale Semiconductor, Inc. All rights reserved.
   4  *   Copyright 2017-2020 NXP
   5  *
   6  */
   7 /* System headers */
   8 #include <stdio.h>
   9 #include <inttypes.h>
  10 #include <unistd.h>
  11 #include <limits.h>
  12 #include <sched.h>
  13 #include <signal.h>
  14 #include <pthread.h>
  15 #include <sys/types.h>
  16 #include <sys/syscall.h>
  17
  18 #include <rte_string_fns.h>
  19 #include <rte_byteorder.h>
  20 #include <rte_common.h>
  21 #include <rte_interrupts.h>
  22 #include <rte_log.h>
  23 #include <rte_debug.h>
  24 #include <rte_pci.h>
  25 #include <rte_atomic.h>
  26 #include <rte_branch_prediction.h>
  27 #include <rte_memory.h>
  28 #include <rte_tailq.h>
  29 #include <rte_eal.h>
  30 #include <rte_alarm.h>
  31 #include <rte_ether.h>
  32 #include <rte_ethdev_driver.h>
  33 #include <rte_malloc.h>
  34 #include <rte_ring.h>
  35
  36 #include <rte_dpaa_bus.h>
  37 #include <rte_dpaa_logs.h>
  38 #include <dpaa_mempool.h>
  39
  40 #include <dpaa_ethdev.h>
  41 #include <dpaa_rxtx.h>
  42 #include <dpaa_flow.h>
  43 #include <rte_pmd_dpaa.h>
  44
  45 #include <fsl_usd.h>
  46 #include <fsl_qman.h>
  47 #include <fsl_bman.h>
  48 #include <fsl_fman.h>
  49 #include <process.h>
  50
  51 /* Supported Rx offloads */
  52 static uint64_t dev_rx_offloads_sup =
  53                 DEV_RX_OFFLOAD_JUMBO_FRAME |
  54                 DEV_RX_OFFLOAD_SCATTER;
  55
  56 /* Rx offloads which cannot be disabled */
  57 static uint64_t dev_rx_offloads_nodis =
  58                 DEV_RX_OFFLOAD_IPV4_CKSUM |
  59                 DEV_RX_OFFLOAD_UDP_CKSUM |
  60                 DEV_RX_OFFLOAD_TCP_CKSUM |
  61                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
  62                 DEV_RX_OFFLOAD_RSS_HASH;
  63
  64 /* Supported Tx offloads */
  65 static uint64_t dev_tx_offloads_sup =
  66                 DEV_TX_OFFLOAD_MT_LOCKFREE |
  67                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
  68
  69 /* Tx offloads which cannot be disabled */
  70 static uint64_t dev_tx_offloads_nodis =
  71                 DEV_TX_OFFLOAD_IPV4_CKSUM |
  72                 DEV_TX_OFFLOAD_UDP_CKSUM |
  73                 DEV_TX_OFFLOAD_TCP_CKSUM |
  74                 DEV_TX_OFFLOAD_SCTP_CKSUM |
  75                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
  76                 DEV_TX_OFFLOAD_MULTI_SEGS;
  77
  78 /* Keep track of whether QMAN and BMAN have been globally initialized */
  79 static int is_global_init;
  80 static int fmc_q = 1;   /* Indicates the use of static fmc for distribution */
  81 static int default_q;   /* use default queue - FMC is not executed*/
  82 /* At present we only allow up to 4 push mode queues as default - as each of
  83  * this queue need dedicated portal and we are short of portals.
  84  */
  85 #define DPAA_MAX_PUSH_MODE_QUEUE       8
  86 #define DPAA_DEFAULT_PUSH_MODE_QUEUE   4
  87
  88 static int dpaa_push_mode_max_queue = DPAA_DEFAULT_PUSH_MODE_QUEUE;
  89 static int dpaa_push_queue_idx; /* Queue index which are in push mode*/
  90
  91
  92 /* Per RX FQ Taildrop in frame count */
  93 static unsigned int td_threshold = CGR_RX_PERFQ_THRESH;
  94
  95 /* Per TX FQ Taildrop in frame count, disabled by default */
  96 static unsigned int td_tx_threshold;
  97
  98 struct rte_dpaa_xstats_name_off {
  99         char name[RTE_ETH_XSTATS_NAME_SIZE];
 100         uint32_t offset;
 101 };
 102
 103 static const struct rte_dpaa_xstats_name_off dpaa_xstats_strings[] = {
 104         {"rx_align_err",
 105                 offsetof(struct dpaa_if_stats, raln)},
 106         {"rx_valid_pause",
 107                 offsetof(struct dpaa_if_stats, rxpf)},
 108         {"rx_fcs_err",
 109                 offsetof(struct dpaa_if_stats, rfcs)},
 110         {"rx_vlan_frame",
 111                 offsetof(struct dpaa_if_stats, rvlan)},
 112         {"rx_frame_err",
 113                 offsetof(struct dpaa_if_stats, rerr)},
 114         {"rx_drop_err",
 115                 offsetof(struct dpaa_if_stats, rdrp)},
 116         {"rx_undersized",
 117                 offsetof(struct dpaa_if_stats, rund)},
 118         {"rx_oversize_err",
 119                 offsetof(struct dpaa_if_stats, rovr)},
 120         {"rx_fragment_pkt",
 121                 offsetof(struct dpaa_if_stats, rfrg)},
 122         {"tx_valid_pause",
 123                 offsetof(struct dpaa_if_stats, txpf)},
 124         {"tx_fcs_err",
 125                 offsetof(struct dpaa_if_stats, terr)},
 126         {"tx_vlan_frame",
 127                 offsetof(struct dpaa_if_stats, tvlan)},
 128         {"rx_undersized",
 129                 offsetof(struct dpaa_if_stats, tund)},
 130 };
 131
 132 static struct rte_dpaa_driver rte_dpaa_pmd;
 133
 134 static int
 135 dpaa_eth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info);
 136
 137 static int dpaa_eth_link_update(struct rte_eth_dev *dev,
 138                                 int wait_to_complete __rte_unused);
 139
 140 static void dpaa_interrupt_handler(void *param);
 141
 142 static inline void
 143 dpaa_poll_queue_default_config(struct qm_mcc_initfq *opts)
 144 {
 145         memset(opts, 0, sizeof(struct qm_mcc_initfq));
 146         opts->we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
 147         opts->fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | QM_FQCTRL_CTXASTASHING |
 148                            QM_FQCTRL_PREFERINCACHE;
 149         opts->fqd.context_a.stashing.exclusive = 0;
 150         if (dpaa_svr_family != SVR_LS1046A_FAMILY)
 151                 opts->fqd.context_a.stashing.annotation_cl =
 152                                                 DPAA_IF_RX_ANNOTATION_STASH;
 153         opts->fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
 154         opts->fqd.context_a.stashing.context_cl = DPAA_IF_RX_CONTEXT_STASH;
 155 }
 156
 157 static int
 158 dpaa_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 159 {
 160         uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
 161                                 + VLAN_TAG_SIZE;
 162         uint32_t buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
 163
 164         PMD_INIT_FUNC_TRACE();
 165
 166         if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA_MAX_RX_PKT_LEN)
 167                 return -EINVAL;
 168         /*
 169          * Refuse mtu that requires the support of scattered packets
 170          * when this feature has not been enabled before.
 171          */
 172         if (dev->data->min_rx_buf_size &&
 173                 !dev->data->scattered_rx && frame_size > buffsz) {
 174                 DPAA_PMD_ERR("SG not enabled, will not fit in one buffer");
 175                 return -EINVAL;
 176         }
 177
 178         /* check <seg size> * <max_seg>  >= max_frame */
 179         if (dev->data->min_rx_buf_size && dev->data->scattered_rx &&
 180                 (frame_size > buffsz * DPAA_SGT_MAX_ENTRIES)) {
 181                 DPAA_PMD_ERR("Too big to fit for Max SG list %d",
 182                                 buffsz * DPAA_SGT_MAX_ENTRIES);
 183                 return -EINVAL;
 184         }
 185
 186         if (frame_size > RTE_ETHER_MAX_LEN)
 187                 dev->data->dev_conf.rxmode.offloads |=
 188                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 189         else
 190                 dev->data->dev_conf.rxmode.offloads &=
 191                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 192
 193         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 194
 195         fman_if_set_maxfrm(dev->process_private, frame_size);
 196
 197         return 0;
 198 }
 199
 200 static int
 201 dpaa_eth_dev_configure(struct rte_eth_dev *dev)
 202 {
 203         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 204         uint64_t rx_offloads = eth_conf->rxmode.offloads;
 205         uint64_t tx_offloads = eth_conf->txmode.offloads;
 206         struct rte_device *rdev = dev->device;
 207         struct rte_dpaa_device *dpaa_dev;
 208         struct fman_if *fif = dev->process_private;
 209         struct __fman_if *__fif;
 210         struct rte_intr_handle *intr_handle;
 211         int ret;
 212
 213         PMD_INIT_FUNC_TRACE();
 214
 215         dpaa_dev = container_of(rdev, struct rte_dpaa_device, device);
 216         intr_handle = &dpaa_dev->intr_handle;
 217         __fif = container_of(fif, struct __fman_if, __if);
 218
 219         /* Rx offloads which are enabled by default */
 220         if (dev_rx_offloads_nodis & ~rx_offloads) {
 221                 DPAA_PMD_INFO(
 222                 "Some of rx offloads enabled by default - requested 0x%" PRIx64
 223                 " fixed are 0x%" PRIx64,
 224                 rx_offloads, dev_rx_offloads_nodis);
 225         }
 226
 227         /* Tx offloads which are enabled by default */
 228         if (dev_tx_offloads_nodis & ~tx_offloads) {
 229                 DPAA_PMD_INFO(
 230                 "Some of tx offloads enabled by default - requested 0x%" PRIx64
 231                 " fixed are 0x%" PRIx64,
 232                 tx_offloads, dev_tx_offloads_nodis);
 233         }
 234
 235         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 236                 uint32_t max_len;
 237
 238                 DPAA_PMD_DEBUG("enabling jumbo");
 239
 240                 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <=
 241                     DPAA_MAX_RX_PKT_LEN)
 242                         max_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
 243                 else {
 244                         DPAA_PMD_INFO("enabling jumbo override conf max len=%d "
 245                                 "supported is %d",
 246                                 dev->data->dev_conf.rxmode.max_rx_pkt_len,
 247                                 DPAA_MAX_RX_PKT_LEN);
 248                         max_len = DPAA_MAX_RX_PKT_LEN;
 249                 }
 250
 251                 fman_if_set_maxfrm(dev->process_private, max_len);
 252                 dev->data->mtu = max_len
 253                         - RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE;
 254         }
 255
 256         if (rx_offloads & DEV_RX_OFFLOAD_SCATTER) {
 257                 DPAA_PMD_DEBUG("enabling scatter mode");
 258                 fman_if_set_sg(dev->process_private, 1);
 259                 dev->data->scattered_rx = 1;
 260         }
 261
 262         /* if the interrupts were configured on this devices*/
 263         if (intr_handle && intr_handle->fd) {
 264                 if (dev->data->dev_conf.intr_conf.lsc != 0)
 265                         rte_intr_callback_register(intr_handle,
 266                                            dpaa_interrupt_handler,
 267                                            (void *)dev);
 268
 269                 ret = dpaa_intr_enable(__fif->node_name, intr_handle->fd);
 270                 if (ret) {
 271                         if (dev->data->dev_conf.intr_conf.lsc != 0) {
 272                                 rte_intr_callback_unregister(intr_handle,
 273                                         dpaa_interrupt_handler,
 274                                         (void *)dev);
 275                                 if (ret == EINVAL)
 276                                         printf("Failed to enable interrupt: Not Supported\n");
 277                                 else
 278                                         printf("Failed to enable interrupt\n");
 279                         }
 280                         dev->data->dev_conf.intr_conf.lsc = 0;
 281                         dev->data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC;
 282                 }
 283         }
 284         return 0;
 285 }
 286
 287 static const uint32_t *
 288 dpaa_supported_ptypes_get(struct rte_eth_dev *dev)
 289 {
 290         static const uint32_t ptypes[] = {
 291                 RTE_PTYPE_L2_ETHER,
 292                 RTE_PTYPE_L2_ETHER_VLAN,
 293                 RTE_PTYPE_L2_ETHER_ARP,
 294                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
 295                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
 296                 RTE_PTYPE_L4_ICMP,
 297                 RTE_PTYPE_L4_TCP,
 298                 RTE_PTYPE_L4_UDP,
 299                 RTE_PTYPE_L4_FRAG,
 300                 RTE_PTYPE_L4_TCP,
 301                 RTE_PTYPE_L4_UDP,
 302                 RTE_PTYPE_L4_SCTP
 303         };
 304
 305         PMD_INIT_FUNC_TRACE();
 306
 307         if (dev->rx_pkt_burst == dpaa_eth_queue_rx)
 308                 return ptypes;
 309         return NULL;
 310 }
 311
 312 static void dpaa_interrupt_handler(void *param)
 313 {
 314         struct rte_eth_dev *dev = param;
 315         struct rte_device *rdev = dev->device;
 316         struct rte_dpaa_device *dpaa_dev;
 317         struct rte_intr_handle *intr_handle;
 318         uint64_t buf;
 319         int bytes_read;
 320
 321         dpaa_dev = container_of(rdev, struct rte_dpaa_device, device);
 322         intr_handle = &dpaa_dev->intr_handle;
 323
 324         bytes_read = read(intr_handle->fd, &buf, sizeof(uint64_t));
 325         if (bytes_read < 0)
 326                 DPAA_PMD_ERR("Error reading eventfd\n");
 327         dpaa_eth_link_update(dev, 0);
 328         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
 329 }
 330
 331 static int dpaa_eth_dev_start(struct rte_eth_dev *dev)
 332 {
 333         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 334
 335         PMD_INIT_FUNC_TRACE();
 336
 337         /* Change tx callback to the real one */
 338         if (dpaa_intf->cgr_tx)
 339                 dev->tx_pkt_burst = dpaa_eth_queue_tx_slow;
 340         else
 341                 dev->tx_pkt_burst = dpaa_eth_queue_tx;
 342
 343         fman_if_enable_rx(dev->process_private);
 344
 345         return 0;
 346 }
 347
 348 static void dpaa_eth_dev_stop(struct rte_eth_dev *dev)
 349 {
 350         struct fman_if *fif = dev->process_private;
 351
 352         PMD_INIT_FUNC_TRACE();
 353
 354         if (!fif->is_shared_mac)
 355                 fman_if_disable_rx(fif);
 356         dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
 357 }
 358
 359 static void dpaa_eth_dev_close(struct rte_eth_dev *dev)
 360 {
 361         struct fman_if *fif = dev->process_private;
 362         struct __fman_if *__fif;
 363         struct rte_device *rdev = dev->device;
 364         struct rte_dpaa_device *dpaa_dev;
 365         struct rte_intr_handle *intr_handle;
 366
 367         PMD_INIT_FUNC_TRACE();
 368
 369         dpaa_dev = container_of(rdev, struct rte_dpaa_device, device);
 370         intr_handle = &dpaa_dev->intr_handle;
 371         __fif = container_of(fif, struct __fman_if, __if);
 372
 373         dpaa_eth_dev_stop(dev);
 374
 375         if (intr_handle && intr_handle->fd &&
 376             dev->data->dev_conf.intr_conf.lsc != 0) {
 377                 dpaa_intr_disable(__fif->node_name);
 378                 rte_intr_callback_unregister(intr_handle,
 379                                              dpaa_interrupt_handler,
 380                                              (void *)dev);
 381         }
 382 }
 383
 384 static int
 385 dpaa_fw_version_get(struct rte_eth_dev *dev __rte_unused,
 386                      char *fw_version,
 387                      size_t fw_size)
 388 {
 389         int ret;
 390         FILE *svr_file = NULL;
 391         unsigned int svr_ver = 0;
 392
 393         PMD_INIT_FUNC_TRACE();
 394
 395         svr_file = fopen(DPAA_SOC_ID_FILE, "r");
 396         if (!svr_file) {
 397                 DPAA_PMD_ERR("Unable to open SoC device");
 398                 return -ENOTSUP; /* Not supported on this infra */
 399         }
 400         if (fscanf(svr_file, "svr:%x", &svr_ver) > 0)
 401                 dpaa_svr_family = svr_ver & SVR_MASK;
 402         else
 403                 DPAA_PMD_ERR("Unable to read SoC device");
 404
 405         fclose(svr_file);
 406
 407         ret = snprintf(fw_version, fw_size, "SVR:%x-fman-v%x",
 408                        svr_ver, fman_ip_rev);
 409         ret += 1; /* add the size of '\0' */
 410
 411         if (fw_size < (uint32_t)ret)
 412                 return ret;
 413         else
 414                 return 0;
 415 }
 416
 417 static int dpaa_eth_dev_info(struct rte_eth_dev *dev,
 418                              struct rte_eth_dev_info *dev_info)
 419 {
 420         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 421         struct fman_if *fif = dev->process_private;
 422
 423         DPAA_PMD_DEBUG(": %s", dpaa_intf->name);
 424
 425         dev_info->max_rx_queues = dpaa_intf->nb_rx_queues;
 426         dev_info->max_tx_queues = dpaa_intf->nb_tx_queues;
 427         dev_info->max_rx_pktlen = DPAA_MAX_RX_PKT_LEN;
 428         dev_info->max_mac_addrs = DPAA_MAX_MAC_FILTER;
 429         dev_info->max_hash_mac_addrs = 0;
 430         dev_info->max_vfs = 0;
 431         dev_info->max_vmdq_pools = ETH_16_POOLS;
 432         dev_info->flow_type_rss_offloads = DPAA_RSS_OFFLOAD_ALL;
 433
 434         if (fif->mac_type == fman_mac_1g) {
 435                 dev_info->speed_capa = ETH_LINK_SPEED_1G;
 436         } else if (fif->mac_type == fman_mac_2_5g) {
 437                 dev_info->speed_capa = ETH_LINK_SPEED_1G
 438                                         | ETH_LINK_SPEED_2_5G;
 439         } else if (fif->mac_type == fman_mac_10g) {
 440                 dev_info->speed_capa = ETH_LINK_SPEED_1G
 441                                         | ETH_LINK_SPEED_2_5G
 442                                         | ETH_LINK_SPEED_10G;
 443         } else {
 444                 DPAA_PMD_ERR("invalid link_speed: %s, %d",
 445                              dpaa_intf->name, fif->mac_type);
 446                 return -EINVAL;
 447         }
 448
 449         dev_info->rx_offload_capa = dev_rx_offloads_sup |
 450                                         dev_rx_offloads_nodis;
 451         dev_info->tx_offload_capa = dev_tx_offloads_sup |
 452                                         dev_tx_offloads_nodis;
 453         dev_info->default_rxportconf.burst_size = DPAA_DEF_RX_BURST_SIZE;
 454         dev_info->default_txportconf.burst_size = DPAA_DEF_TX_BURST_SIZE;
 455         dev_info->default_rxportconf.nb_queues = 1;
 456         dev_info->default_txportconf.nb_queues = 1;
 457         dev_info->default_txportconf.ring_size = CGR_TX_CGR_THRESH;
 458         dev_info->default_rxportconf.ring_size = CGR_RX_PERFQ_THRESH;
 459
 460         return 0;
 461 }
 462
 463 static int
 464 dpaa_dev_rx_burst_mode_get(struct rte_eth_dev *dev,
 465                         __rte_unused uint16_t queue_id,
 466                         struct rte_eth_burst_mode *mode)
 467 {
 468         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 469         int ret = -EINVAL;
 470         unsigned int i;
 471         const struct burst_info {
 472                 uint64_t flags;
 473                 const char *output;
 474         } rx_offload_map[] = {
 475                         {DEV_RX_OFFLOAD_JUMBO_FRAME, " Jumbo frame,"},
 476                         {DEV_RX_OFFLOAD_SCATTER, " Scattered,"},
 477                         {DEV_RX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"},
 478                         {DEV_RX_OFFLOAD_UDP_CKSUM, " UDP csum,"},
 479                         {DEV_RX_OFFLOAD_TCP_CKSUM, " TCP csum,"},
 480                         {DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
 481                         {DEV_RX_OFFLOAD_RSS_HASH, " RSS,"}
 482         };
 483
 484         /* Update Rx offload info */
 485         for (i = 0; i < RTE_DIM(rx_offload_map); i++) {
 486                 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) {
 487                         snprintf(mode->info, sizeof(mode->info), "%s",
 488                                 rx_offload_map[i].output);
 489                         ret = 0;
 490                         break;
 491                 }
 492         }
 493         return ret;
 494 }
 495
 496 static int
 497 dpaa_dev_tx_burst_mode_get(struct rte_eth_dev *dev,
 498                         __rte_unused uint16_t queue_id,
 499                         struct rte_eth_burst_mode *mode)
 500 {
 501         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 502         int ret = -EINVAL;
 503         unsigned int i;
 504         const struct burst_info {
 505                 uint64_t flags;
 506                 const char *output;
 507         } tx_offload_map[] = {
 508                         {DEV_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"},
 509                         {DEV_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"},
 510                         {DEV_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"},
 511                         {DEV_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"},
 512                         {DEV_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"},
 513                         {DEV_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
 514                         {DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
 515                         {DEV_TX_OFFLOAD_MULTI_SEGS, " Scattered,"}
 516         };
 517
 518         /* Update Tx offload info */
 519         for (i = 0; i < RTE_DIM(tx_offload_map); i++) {
 520                 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) {
 521                         snprintf(mode->info, sizeof(mode->info), "%s",
 522                                 tx_offload_map[i].output);
 523                         ret = 0;
 524                         break;
 525                 }
 526         }
 527         return ret;
 528 }
 529
 530 static int dpaa_eth_link_update(struct rte_eth_dev *dev,
 531                                 int wait_to_complete __rte_unused)
 532 {
 533         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 534         struct rte_eth_link *link = &dev->data->dev_link;
 535         struct fman_if *fif = dev->process_private;
 536         struct __fman_if *__fif = container_of(fif, struct __fman_if, __if);
 537         int ret;
 538
 539         PMD_INIT_FUNC_TRACE();
 540
 541         if (fif->mac_type == fman_mac_1g)
 542                 link->link_speed = ETH_SPEED_NUM_1G;
 543         else if (fif->mac_type == fman_mac_2_5g)
 544                 link->link_speed = ETH_SPEED_NUM_2_5G;
 545         else if (fif->mac_type == fman_mac_10g)
 546                 link->link_speed = ETH_SPEED_NUM_10G;
 547         else
 548                 DPAA_PMD_ERR("invalid link_speed: %s, %d",
 549                              dpaa_intf->name, fif->mac_type);
 550
 551         if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC) {
 552                 ret = dpaa_get_link_status(__fif->node_name);
 553                 if (ret < 0)
 554                         return ret;
 555                 link->link_status = ret;
 556         } else {
 557                 link->link_status = dpaa_intf->valid;
 558         }
 559
 560         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 561         link->link_autoneg = ETH_LINK_AUTONEG;
 562
 563         DPAA_PMD_INFO("Port %d Link is %s\n", dev->data->port_id,
 564                       link->link_status ? "Up" : "Down");
 565         return 0;
 566 }
 567
 568 static int dpaa_eth_stats_get(struct rte_eth_dev *dev,
 569                                struct rte_eth_stats *stats)
 570 {
 571         PMD_INIT_FUNC_TRACE();
 572
 573         fman_if_stats_get(dev->process_private, stats);
 574         return 0;
 575 }
 576
 577 static int dpaa_eth_stats_reset(struct rte_eth_dev *dev)
 578 {
 579         PMD_INIT_FUNC_TRACE();
 580
 581         fman_if_stats_reset(dev->process_private);
 582
 583         return 0;
 584 }
 585
 586 static int
 587 dpaa_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
 588                     unsigned int n)
 589 {
 590         unsigned int i = 0, num = RTE_DIM(dpaa_xstats_strings);
 591         uint64_t values[sizeof(struct dpaa_if_stats) / 8];
 592
 593         if (n < num)
 594                 return num;
 595
 596         if (xstats == NULL)
 597                 return 0;
 598
 599         fman_if_stats_get_all(dev->process_private, values,
 600                               sizeof(struct dpaa_if_stats) / 8);
 601
 602         for (i = 0; i < num; i++) {
 603                 xstats[i].id = i;
 604                 xstats[i].value = values[dpaa_xstats_strings[i].offset / 8];
 605         }
 606         return i;
 607 }
 608
 609 static int
 610 dpaa_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 611                       struct rte_eth_xstat_name *xstats_names,
 612                       unsigned int limit)
 613 {
 614         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 615
 616         if (limit < stat_cnt)
 617                 return stat_cnt;
 618
 619         if (xstats_names != NULL)
 620                 for (i = 0; i < stat_cnt; i++)
 621                         strlcpy(xstats_names[i].name,
 622                                 dpaa_xstats_strings[i].name,
 623                                 sizeof(xstats_names[i].name));
 624
 625         return stat_cnt;
 626 }
 627
 628 static int
 629 dpaa_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 630                       uint64_t *values, unsigned int n)
 631 {
 632         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 633         uint64_t values_copy[sizeof(struct dpaa_if_stats) / 8];
 634
 635         if (!ids) {
 636                 if (n < stat_cnt)
 637                         return stat_cnt;
 638
 639                 if (!values)
 640                         return 0;
 641
 642                 fman_if_stats_get_all(dev->process_private, values_copy,
 643                                       sizeof(struct dpaa_if_stats) / 8);
 644
 645                 for (i = 0; i < stat_cnt; i++)
 646                         values[i] =
 647                                 values_copy[dpaa_xstats_strings[i].offset / 8];
 648
 649                 return stat_cnt;
 650         }
 651
 652         dpaa_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
 653
 654         for (i = 0; i < n; i++) {
 655                 if (ids[i] >= stat_cnt) {
 656                         DPAA_PMD_ERR("id value isn't valid");
 657                         return -1;
 658                 }
 659                 values[i] = values_copy[ids[i]];
 660         }
 661         return n;
 662 }
 663
 664 static int
 665 dpaa_xstats_get_names_by_id(
 666         struct rte_eth_dev *dev,
 667         struct rte_eth_xstat_name *xstats_names,
 668         const uint64_t *ids,
 669         unsigned int limit)
 670 {
 671         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 672         struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
 673
 674         if (!ids)
 675                 return dpaa_xstats_get_names(dev, xstats_names, limit);
 676
 677         dpaa_xstats_get_names(dev, xstats_names_copy, limit);
 678
 679         for (i = 0; i < limit; i++) {
 680                 if (ids[i] >= stat_cnt) {
 681                         DPAA_PMD_ERR("id value isn't valid");
 682                         return -1;
 683                 }
 684                 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
 685         }
 686         return limit;
 687 }
 688
 689 static int dpaa_eth_promiscuous_enable(struct rte_eth_dev *dev)
 690 {
 691         PMD_INIT_FUNC_TRACE();
 692
 693         fman_if_promiscuous_enable(dev->process_private);
 694
 695         return 0;
 696 }
 697
 698 static int dpaa_eth_promiscuous_disable(struct rte_eth_dev *dev)
 699 {
 700         PMD_INIT_FUNC_TRACE();
 701
 702         fman_if_promiscuous_disable(dev->process_private);
 703
 704         return 0;
 705 }
 706
 707 static int dpaa_eth_multicast_enable(struct rte_eth_dev *dev)
 708 {
 709         PMD_INIT_FUNC_TRACE();
 710
 711         fman_if_set_mcast_filter_table(dev->process_private);
 712
 713         return 0;
 714 }
 715
 716 static int dpaa_eth_multicast_disable(struct rte_eth_dev *dev)
 717 {
 718         PMD_INIT_FUNC_TRACE();
 719
 720         fman_if_reset_mcast_filter_table(dev->process_private);
 721
 722         return 0;
 723 }
 724
 725 static
 726 int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 727                             uint16_t nb_desc,
 728                             unsigned int socket_id __rte_unused,
 729                             const struct rte_eth_rxconf *rx_conf,
 730                             struct rte_mempool *mp)
 731 {
 732         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 733         struct fman_if *fif = dev->process_private;
 734         struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_idx];
 735         struct qm_mcc_initfq opts = {0};
 736         u32 flags = 0;
 737         int ret;
 738         u32 buffsz = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
 739
 740         PMD_INIT_FUNC_TRACE();
 741
 742         if (queue_idx >= dev->data->nb_rx_queues) {
 743                 rte_errno = EOVERFLOW;
 744                 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
 745                       (void *)dev, queue_idx, dev->data->nb_rx_queues);
 746                 return -rte_errno;
 747         }
 748
 749         /* Rx deferred start is not supported */
 750         if (rx_conf->rx_deferred_start) {
 751                 DPAA_PMD_ERR("%p:Rx deferred start not supported", (void *)dev);
 752                 return -EINVAL;
 753         }
 754         rxq->nb_desc = UINT16_MAX;
 755         rxq->offloads = rx_conf->offloads;
 756
 757         DPAA_PMD_INFO("Rx queue setup for queue index: %d fq_id (0x%x)",
 758                         queue_idx, rxq->fqid);
 759
 760         /* Max packet can fit in single buffer */
 761         if (dev->data->dev_conf.rxmode.max_rx_pkt_len <= buffsz) {
 762                 ;
 763         } else if (dev->data->dev_conf.rxmode.offloads &
 764                         DEV_RX_OFFLOAD_SCATTER) {
 765                 if (dev->data->dev_conf.rxmode.max_rx_pkt_len >
 766                         buffsz * DPAA_SGT_MAX_ENTRIES) {
 767                         DPAA_PMD_ERR("max RxPkt size %d too big to fit "
 768                                 "MaxSGlist %d",
 769                                 dev->data->dev_conf.rxmode.max_rx_pkt_len,
 770                                 buffsz * DPAA_SGT_MAX_ENTRIES);
 771                         rte_errno = EOVERFLOW;
 772                         return -rte_errno;
 773                 }
 774         } else {
 775                 DPAA_PMD_WARN("The requested maximum Rx packet size (%u) is"
 776                      " larger than a single mbuf (%u) and scattered"
 777                      " mode has not been requested",
 778                      dev->data->dev_conf.rxmode.max_rx_pkt_len,
 779                      buffsz - RTE_PKTMBUF_HEADROOM);
 780         }
 781
 782         if (!dpaa_intf->bp_info || dpaa_intf->bp_info->mp != mp) {
 783                 struct fman_if_ic_params icp;
 784                 uint32_t fd_offset;
 785                 uint32_t bp_size;
 786
 787                 if (!mp->pool_data) {
 788                         DPAA_PMD_ERR("Not an offloaded buffer pool!");
 789                         return -1;
 790                 }
 791                 dpaa_intf->bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp);
 792
 793                 memset(&icp, 0, sizeof(icp));
 794                 /* set ICEOF for to the default value , which is 0*/
 795                 icp.iciof = DEFAULT_ICIOF;
 796                 icp.iceof = DEFAULT_RX_ICEOF;
 797                 icp.icsz = DEFAULT_ICSZ;
 798                 fman_if_set_ic_params(fif, &icp);
 799
 800                 fd_offset = RTE_PKTMBUF_HEADROOM + DPAA_HW_BUF_RESERVE;
 801                 fman_if_set_fdoff(fif, fd_offset);
 802
 803                 /* Buffer pool size should be equal to Dataroom Size*/
 804                 bp_size = rte_pktmbuf_data_room_size(mp);
 805                 fman_if_set_bp(fif, mp->size,
 806                                dpaa_intf->bp_info->bpid, bp_size);
 807                 dpaa_intf->valid = 1;
 808                 DPAA_PMD_DEBUG("if:%s fd_offset = %d offset = %d",
 809                                 dpaa_intf->name, fd_offset,
 810                                 fman_if_get_fdoff(fif));
 811         }
 812         DPAA_PMD_DEBUG("if:%s sg_on = %d, max_frm =%d", dpaa_intf->name,
 813                 fman_if_get_sg_enable(fif),
 814                 dev->data->dev_conf.rxmode.max_rx_pkt_len);
 815         /* checking if push mode only, no error check for now */
 816         if (!rxq->is_static &&
 817             dpaa_push_mode_max_queue > dpaa_push_queue_idx) {
 818                 struct qman_portal *qp;
 819                 int q_fd;
 820
 821                 dpaa_push_queue_idx++;
 822                 opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
 823                 opts.fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK |
 824                                    QM_FQCTRL_CTXASTASHING |
 825                                    QM_FQCTRL_PREFERINCACHE;
 826                 opts.fqd.context_a.stashing.exclusive = 0;
 827                 /* In muticore scenario stashing becomes a bottleneck on LS1046.
 828                  * So do not enable stashing in this case
 829                  */
 830                 if (dpaa_svr_family != SVR_LS1046A_FAMILY)
 831                         opts.fqd.context_a.stashing.annotation_cl =
 832                                                 DPAA_IF_RX_ANNOTATION_STASH;
 833                 opts.fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
 834                 opts.fqd.context_a.stashing.context_cl =
 835                                                 DPAA_IF_RX_CONTEXT_STASH;
 836
 837                 /*Create a channel and associate given queue with the channel*/
 838                 qman_alloc_pool_range((u32 *)&rxq->ch_id, 1, 1, 0);
 839                 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
 840                 opts.fqd.dest.channel = rxq->ch_id;
 841                 opts.fqd.dest.wq = DPAA_IF_RX_PRIORITY;
 842                 flags = QMAN_INITFQ_FLAG_SCHED;
 843
 844                 /* Configure tail drop */
 845                 if (dpaa_intf->cgr_rx) {
 846                         opts.we_mask |= QM_INITFQ_WE_CGID;
 847                         opts.fqd.cgid = dpaa_intf->cgr_rx[queue_idx].cgrid;
 848                         opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
 849                 }
 850                 ret = qman_init_fq(rxq, flags, &opts);
 851                 if (ret) {
 852                         DPAA_PMD_ERR("Channel/Q association failed. fqid 0x%x "
 853                                 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
 854                         return ret;
 855                 }
 856                 if (dpaa_svr_family == SVR_LS1043A_FAMILY) {
 857                         rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb_no_prefetch;
 858                 } else {
 859                         rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb;
 860                         rxq->cb.dqrr_prepare = dpaa_rx_cb_prepare;
 861                 }
 862
 863                 rxq->is_static = true;
 864
 865                 /* Allocate qman specific portals */
 866                 qp = fsl_qman_fq_portal_create(&q_fd);
 867                 if (!qp) {
 868                         DPAA_PMD_ERR("Unable to alloc fq portal");
 869                         return -1;
 870                 }
 871                 rxq->qp = qp;
 872
 873                 /* Set up the device interrupt handler */
 874                 if (!dev->intr_handle) {
 875                         struct rte_dpaa_device *dpaa_dev;
 876                         struct rte_device *rdev = dev->device;
 877
 878                         dpaa_dev = container_of(rdev, struct rte_dpaa_device,
 879                                                 device);
 880                         dev->intr_handle = &dpaa_dev->intr_handle;
 881                         dev->intr_handle->intr_vec = rte_zmalloc(NULL,
 882                                         dpaa_push_mode_max_queue, 0);
 883                         if (!dev->intr_handle->intr_vec) {
 884                                 DPAA_PMD_ERR("intr_vec alloc failed");
 885                                 return -ENOMEM;
 886                         }
 887                         dev->intr_handle->nb_efd = dpaa_push_mode_max_queue;
 888                         dev->intr_handle->max_intr = dpaa_push_mode_max_queue;
 889                 }
 890
 891                 dev->intr_handle->type = RTE_INTR_HANDLE_EXT;
 892                 dev->intr_handle->intr_vec[queue_idx] = queue_idx + 1;
 893                 dev->intr_handle->efds[queue_idx] = q_fd;
 894                 rxq->q_fd = q_fd;
 895         }
 896         rxq->bp_array = rte_dpaa_bpid_info;
 897         dev->data->rx_queues[queue_idx] = rxq;
 898
 899         /* configure the CGR size as per the desc size */
 900         if (dpaa_intf->cgr_rx) {
 901                 struct qm_mcc_initcgr cgr_opts = {0};
 902
 903                 rxq->nb_desc = nb_desc;
 904                 /* Enable tail drop with cgr on this queue */
 905                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, nb_desc, 0);
 906                 ret = qman_modify_cgr(dpaa_intf->cgr_rx, 0, &cgr_opts);
 907                 if (ret) {
 908                         DPAA_PMD_WARN(
 909                                 "rx taildrop modify fail on fqid %d (ret=%d)",
 910                                 rxq->fqid, ret);
 911                 }
 912         }
 913
 914         return 0;
 915 }
 916
 917 int
 918 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev,
 919                 int eth_rx_queue_id,
 920                 u16 ch_id,
 921                 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
 922 {
 923         int ret;
 924         u32 flags = 0;
 925         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 926         struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
 927         struct qm_mcc_initfq opts = {0};
 928
 929         if (dpaa_push_mode_max_queue)
 930                 DPAA_PMD_WARN("PUSH mode q and EVENTDEV are not compatible\n"
 931                               "PUSH mode already enabled for first %d queues.\n"
 932                               "To disable set DPAA_PUSH_QUEUES_NUMBER to 0\n",
 933                               dpaa_push_mode_max_queue);
 934
 935         dpaa_poll_queue_default_config(&opts);
 936
 937         switch (queue_conf->ev.sched_type) {
 938         case RTE_SCHED_TYPE_ATOMIC:
 939                 opts.fqd.fq_ctrl |= QM_FQCTRL_HOLDACTIVE;
 940                 /* Reset FQCTRL_AVOIDBLOCK bit as it is unnecessary
 941                  * configuration with HOLD_ACTIVE setting
 942                  */
 943                 opts.fqd.fq_ctrl &= (~QM_FQCTRL_AVOIDBLOCK);
 944                 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_atomic;
 945                 break;
 946         case RTE_SCHED_TYPE_ORDERED:
 947                 DPAA_PMD_ERR("Ordered queue schedule type is not supported\n");
 948                 return -1;
 949         default:
 950                 opts.fqd.fq_ctrl |= QM_FQCTRL_AVOIDBLOCK;
 951                 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_parallel;
 952                 break;
 953         }
 954
 955         opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
 956         opts.fqd.dest.channel = ch_id;
 957         opts.fqd.dest.wq = queue_conf->ev.priority;
 958
 959         if (dpaa_intf->cgr_rx) {
 960                 opts.we_mask |= QM_INITFQ_WE_CGID;
 961                 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
 962                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
 963         }
 964
 965         flags = QMAN_INITFQ_FLAG_SCHED;
 966
 967         ret = qman_init_fq(rxq, flags, &opts);
 968         if (ret) {
 969                 DPAA_PMD_ERR("Ev-Channel/Q association failed. fqid 0x%x "
 970                                 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
 971                 return ret;
 972         }
 973
 974         /* copy configuration which needs to be filled during dequeue */
 975         memcpy(&rxq->ev, &queue_conf->ev, sizeof(struct rte_event));
 976         dev->data->rx_queues[eth_rx_queue_id] = rxq;
 977
 978         return ret;
 979 }
 980
 981 int
 982 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev,
 983                 int eth_rx_queue_id)
 984 {
 985         struct qm_mcc_initfq opts;
 986         int ret;
 987         u32 flags = 0;
 988         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 989         struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
 990
 991         dpaa_poll_queue_default_config(&opts);
 992
 993         if (dpaa_intf->cgr_rx) {
 994                 opts.we_mask |= QM_INITFQ_WE_CGID;
 995                 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
 996                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
 997         }
 998
 999         ret = qman_init_fq(rxq, flags, &opts);
1000         if (ret) {
1001                 DPAA_PMD_ERR("init rx fqid %d failed with ret: %d",
1002                              rxq->fqid, ret);
1003         }
1004
1005         rxq->cb.dqrr_dpdk_cb = NULL;
1006         dev->data->rx_queues[eth_rx_queue_id] = NULL;
1007
1008         return 0;
1009 }
1010
1011 static
1012 void dpaa_eth_rx_queue_release(void *rxq __rte_unused)
1013 {
1014         PMD_INIT_FUNC_TRACE();
1015 }
1016
1017 static
1018 int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1019                             uint16_t nb_desc __rte_unused,
1020                 unsigned int socket_id __rte_unused,
1021                 const struct rte_eth_txconf *tx_conf)
1022 {
1023         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1024         struct qman_fq *txq = &dpaa_intf->tx_queues[queue_idx];
1025
1026         PMD_INIT_FUNC_TRACE();
1027
1028         /* Tx deferred start is not supported */
1029         if (tx_conf->tx_deferred_start) {
1030                 DPAA_PMD_ERR("%p:Tx deferred start not supported", (void *)dev);
1031                 return -EINVAL;
1032         }
1033         txq->nb_desc = UINT16_MAX;
1034         txq->offloads = tx_conf->offloads;
1035
1036         if (queue_idx >= dev->data->nb_tx_queues) {
1037                 rte_errno = EOVERFLOW;
1038                 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
1039                       (void *)dev, queue_idx, dev->data->nb_tx_queues);
1040                 return -rte_errno;
1041         }
1042
1043         DPAA_PMD_INFO("Tx queue setup for queue index: %d fq_id (0x%x)",
1044                         queue_idx, txq->fqid);
1045         dev->data->tx_queues[queue_idx] = txq;
1046
1047         return 0;
1048 }
1049
1050 static void dpaa_eth_tx_queue_release(void *txq __rte_unused)
1051 {
1052         PMD_INIT_FUNC_TRACE();
1053 }
1054
1055 static uint32_t
1056 dpaa_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1057 {
1058         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1059         struct qman_fq *rxq = &dpaa_intf->rx_queues[rx_queue_id];
1060         u32 frm_cnt = 0;
1061
1062         PMD_INIT_FUNC_TRACE();
1063
1064         if (qman_query_fq_frm_cnt(rxq, &frm_cnt) == 0) {
1065                 DPAA_PMD_DEBUG("RX frame count for q(%d) is %u",
1066                                rx_queue_id, frm_cnt);
1067         }
1068         return frm_cnt;
1069 }
1070
1071 static int dpaa_link_down(struct rte_eth_dev *dev)
1072 {
1073         struct fman_if *fif = dev->process_private;
1074         struct __fman_if *__fif;
1075
1076         PMD_INIT_FUNC_TRACE();
1077
1078         __fif = container_of(fif, struct __fman_if, __if);
1079
1080         if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC)
1081                 dpaa_update_link_status(__fif->node_name, ETH_LINK_DOWN);
1082         else
1083                 dpaa_eth_dev_stop(dev);
1084         return 0;
1085 }
1086
1087 static int dpaa_link_up(struct rte_eth_dev *dev)
1088 {
1089         struct fman_if *fif = dev->process_private;
1090         struct __fman_if *__fif;
1091
1092         PMD_INIT_FUNC_TRACE();
1093
1094         __fif = container_of(fif, struct __fman_if, __if);
1095
1096         if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC)
1097                 dpaa_update_link_status(__fif->node_name, ETH_LINK_UP);
1098         else
1099                 dpaa_eth_dev_start(dev);
1100         return 0;
1101 }
1102
1103 static int
1104 dpaa_flow_ctrl_set(struct rte_eth_dev *dev,
1105                    struct rte_eth_fc_conf *fc_conf)
1106 {
1107         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1108         struct rte_eth_fc_conf *net_fc;
1109
1110         PMD_INIT_FUNC_TRACE();
1111
1112         if (!(dpaa_intf->fc_conf)) {
1113                 dpaa_intf->fc_conf = rte_zmalloc(NULL,
1114                         sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
1115                 if (!dpaa_intf->fc_conf) {
1116                         DPAA_PMD_ERR("unable to save flow control info");
1117                         return -ENOMEM;
1118                 }
1119         }
1120         net_fc = dpaa_intf->fc_conf;
1121
1122         if (fc_conf->high_water < fc_conf->low_water) {
1123                 DPAA_PMD_ERR("Incorrect Flow Control Configuration");
1124                 return -EINVAL;
1125         }
1126
1127         if (fc_conf->mode == RTE_FC_NONE) {
1128                 return 0;
1129         } else if (fc_conf->mode == RTE_FC_TX_PAUSE ||
1130                  fc_conf->mode == RTE_FC_FULL) {
1131                 fman_if_set_fc_threshold(dev->process_private,
1132                                          fc_conf->high_water,
1133                                          fc_conf->low_water,
1134                                          dpaa_intf->bp_info->bpid);
1135                 if (fc_conf->pause_time)
1136                         fman_if_set_fc_quanta(dev->process_private,
1137                                               fc_conf->pause_time);
1138         }
1139
1140         /* Save the information in dpaa device */
1141         net_fc->pause_time = fc_conf->pause_time;
1142         net_fc->high_water = fc_conf->high_water;
1143         net_fc->low_water = fc_conf->low_water;
1144         net_fc->send_xon = fc_conf->send_xon;
1145         net_fc->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
1146         net_fc->mode = fc_conf->mode;
1147         net_fc->autoneg = fc_conf->autoneg;
1148
1149         return 0;
1150 }
1151
1152 static int
1153 dpaa_flow_ctrl_get(struct rte_eth_dev *dev,
1154                    struct rte_eth_fc_conf *fc_conf)
1155 {
1156         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1157         struct rte_eth_fc_conf *net_fc = dpaa_intf->fc_conf;
1158         int ret;
1159
1160         PMD_INIT_FUNC_TRACE();
1161
1162         if (net_fc) {
1163                 fc_conf->pause_time = net_fc->pause_time;
1164                 fc_conf->high_water = net_fc->high_water;
1165                 fc_conf->low_water = net_fc->low_water;
1166                 fc_conf->send_xon = net_fc->send_xon;
1167                 fc_conf->mac_ctrl_frame_fwd = net_fc->mac_ctrl_frame_fwd;
1168                 fc_conf->mode = net_fc->mode;
1169                 fc_conf->autoneg = net_fc->autoneg;
1170                 return 0;
1171         }
1172         ret = fman_if_get_fc_threshold(dev->process_private);
1173         if (ret) {
1174                 fc_conf->mode = RTE_FC_TX_PAUSE;
1175                 fc_conf->pause_time =
1176                         fman_if_get_fc_quanta(dev->process_private);
1177         } else {
1178                 fc_conf->mode = RTE_FC_NONE;
1179         }
1180
1181         return 0;
1182 }
1183
1184 static int
1185 dpaa_dev_add_mac_addr(struct rte_eth_dev *dev,
1186                              struct rte_ether_addr *addr,
1187                              uint32_t index,
1188                              __rte_unused uint32_t pool)
1189 {
1190         int ret;
1191
1192         PMD_INIT_FUNC_TRACE();
1193
1194         ret = fman_if_add_mac_addr(dev->process_private,
1195                                    addr->addr_bytes, index);
1196
1197         if (ret)
1198                 DPAA_PMD_ERR("Adding the MAC ADDR failed: err = %d", ret);
1199         return 0;
1200 }
1201
1202 static void
1203 dpaa_dev_remove_mac_addr(struct rte_eth_dev *dev,
1204                           uint32_t index)
1205 {
1206         PMD_INIT_FUNC_TRACE();
1207
1208         fman_if_clear_mac_addr(dev->process_private, index);
1209 }
1210
1211 static int
1212 dpaa_dev_set_mac_addr(struct rte_eth_dev *dev,
1213                        struct rte_ether_addr *addr)
1214 {
1215         int ret;
1216
1217         PMD_INIT_FUNC_TRACE();
1218
1219         ret = fman_if_add_mac_addr(dev->process_private, addr->addr_bytes, 0);
1220         if (ret)
1221                 DPAA_PMD_ERR("Setting the MAC ADDR failed %d", ret);
1222
1223         return ret;
1224 }
1225
1226 static int dpaa_dev_queue_intr_enable(struct rte_eth_dev *dev,
1227                                       uint16_t queue_id)
1228 {
1229         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1230         struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id];
1231
1232         if (!rxq->is_static)
1233                 return -EINVAL;
1234
1235         return qman_fq_portal_irqsource_add(rxq->qp, QM_PIRQ_DQRI);
1236 }
1237
1238 static int dpaa_dev_queue_intr_disable(struct rte_eth_dev *dev,
1239                                        uint16_t queue_id)
1240 {
1241         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1242         struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id];
1243         uint32_t temp;
1244         ssize_t temp1;
1245
1246         if (!rxq->is_static)
1247                 return -EINVAL;
1248
1249         qman_fq_portal_irqsource_remove(rxq->qp, ~0);
1250
1251         temp1 = read(rxq->q_fd, &temp, sizeof(temp));
1252         if (temp1 != sizeof(temp))
1253                 DPAA_PMD_ERR("irq read error");
1254
1255         qman_fq_portal_thread_irq(rxq->qp);
1256
1257         return 0;
1258 }
1259
1260 static void
1261 dpaa_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1262         struct rte_eth_rxq_info *qinfo)
1263 {
1264         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1265         struct qman_fq *rxq;
1266
1267         rxq = dev->data->rx_queues[queue_id];
1268
1269         qinfo->mp = dpaa_intf->bp_info->mp;
1270         qinfo->scattered_rx = dev->data->scattered_rx;
1271         qinfo->nb_desc = rxq->nb_desc;
1272         qinfo->conf.rx_free_thresh = 1;
1273         qinfo->conf.rx_drop_en = 1;
1274         qinfo->conf.rx_deferred_start = 0;
1275         qinfo->conf.offloads = rxq->offloads;
1276 }
1277
1278 static void
1279 dpaa_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1280         struct rte_eth_txq_info *qinfo)
1281 {
1282         struct qman_fq *txq;
1283
1284         txq = dev->data->tx_queues[queue_id];
1285
1286         qinfo->nb_desc = txq->nb_desc;
1287         qinfo->conf.tx_thresh.pthresh = 0;
1288         qinfo->conf.tx_thresh.hthresh = 0;
1289         qinfo->conf.tx_thresh.wthresh = 0;
1290
1291         qinfo->conf.tx_free_thresh = 0;
1292         qinfo->conf.tx_rs_thresh = 0;
1293         qinfo->conf.offloads = txq->offloads;
1294         qinfo->conf.tx_deferred_start = 0;
1295 }
1296
1297 static struct eth_dev_ops dpaa_devops = {
1298         .dev_configure            = dpaa_eth_dev_configure,
1299         .dev_start                = dpaa_eth_dev_start,
1300         .dev_stop                 = dpaa_eth_dev_stop,
1301         .dev_close                = dpaa_eth_dev_close,
1302         .dev_infos_get            = dpaa_eth_dev_info,
1303         .dev_supported_ptypes_get = dpaa_supported_ptypes_get,
1304
1305         .rx_queue_setup           = dpaa_eth_rx_queue_setup,
1306         .tx_queue_setup           = dpaa_eth_tx_queue_setup,
1307         .rx_queue_release         = dpaa_eth_rx_queue_release,
1308         .tx_queue_release         = dpaa_eth_tx_queue_release,
1309         .rx_queue_count           = dpaa_dev_rx_queue_count,
1310         .rx_burst_mode_get        = dpaa_dev_rx_burst_mode_get,
1311         .tx_burst_mode_get        = dpaa_dev_tx_burst_mode_get,
1312         .rxq_info_get             = dpaa_rxq_info_get,
1313         .txq_info_get             = dpaa_txq_info_get,
1314
1315         .flow_ctrl_get            = dpaa_flow_ctrl_get,
1316         .flow_ctrl_set            = dpaa_flow_ctrl_set,
1317
1318         .link_update              = dpaa_eth_link_update,
1319         .stats_get                = dpaa_eth_stats_get,
1320         .xstats_get               = dpaa_dev_xstats_get,
1321         .xstats_get_by_id         = dpaa_xstats_get_by_id,
1322         .xstats_get_names_by_id   = dpaa_xstats_get_names_by_id,
1323         .xstats_get_names         = dpaa_xstats_get_names,
1324         .xstats_reset             = dpaa_eth_stats_reset,
1325         .stats_reset              = dpaa_eth_stats_reset,
1326         .promiscuous_enable       = dpaa_eth_promiscuous_enable,
1327         .promiscuous_disable      = dpaa_eth_promiscuous_disable,
1328         .allmulticast_enable      = dpaa_eth_multicast_enable,
1329         .allmulticast_disable     = dpaa_eth_multicast_disable,
1330         .mtu_set                  = dpaa_mtu_set,
1331         .dev_set_link_down        = dpaa_link_down,
1332         .dev_set_link_up          = dpaa_link_up,
1333         .mac_addr_add             = dpaa_dev_add_mac_addr,
1334         .mac_addr_remove          = dpaa_dev_remove_mac_addr,
1335         .mac_addr_set             = dpaa_dev_set_mac_addr,
1336
1337         .fw_version_get           = dpaa_fw_version_get,
1338
1339         .rx_queue_intr_enable     = dpaa_dev_queue_intr_enable,
1340         .rx_queue_intr_disable    = dpaa_dev_queue_intr_disable,
1341 };
1342
1343 static bool
1344 is_device_supported(struct rte_eth_dev *dev, struct rte_dpaa_driver *drv)
1345 {
1346         if (strcmp(dev->device->driver->name,
1347                    drv->driver.name))
1348                 return false;
1349
1350         return true;
1351 }
1352
1353 static bool
1354 is_dpaa_supported(struct rte_eth_dev *dev)
1355 {
1356         return is_device_supported(dev, &rte_dpaa_pmd);
1357 }
1358
1359 int
1360 rte_pmd_dpaa_set_tx_loopback(uint8_t port, uint8_t on)
1361 {
1362         struct rte_eth_dev *dev;
1363
1364         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
1365
1366         dev = &rte_eth_devices[port];
1367
1368         if (!is_dpaa_supported(dev))
1369                 return -ENOTSUP;
1370
1371         if (on)
1372                 fman_if_loopback_enable(dev->process_private);
1373         else
1374                 fman_if_loopback_disable(dev->process_private);
1375
1376         return 0;
1377 }
1378
1379 static int dpaa_fc_set_default(struct dpaa_if *dpaa_intf,
1380                                struct fman_if *fman_intf)
1381 {
1382         struct rte_eth_fc_conf *fc_conf;
1383         int ret;
1384
1385         PMD_INIT_FUNC_TRACE();
1386
1387         if (!(dpaa_intf->fc_conf)) {
1388                 dpaa_intf->fc_conf = rte_zmalloc(NULL,
1389                         sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
1390                 if (!dpaa_intf->fc_conf) {
1391                         DPAA_PMD_ERR("unable to save flow control info");
1392                         return -ENOMEM;
1393                 }
1394         }
1395         fc_conf = dpaa_intf->fc_conf;
1396         ret = fman_if_get_fc_threshold(fman_intf);
1397         if (ret) {
1398                 fc_conf->mode = RTE_FC_TX_PAUSE;
1399                 fc_conf->pause_time = fman_if_get_fc_quanta(fman_intf);
1400         } else {
1401                 fc_conf->mode = RTE_FC_NONE;
1402         }
1403
1404         return 0;
1405 }
1406
1407 /* Initialise an Rx FQ */
1408 static int dpaa_rx_queue_init(struct qman_fq *fq, struct qman_cgr *cgr_rx,
1409                               uint32_t fqid)
1410 {
1411         struct qm_mcc_initfq opts = {0};
1412         int ret;
1413         u32 flags = QMAN_FQ_FLAG_NO_ENQUEUE;
1414         struct qm_mcc_initcgr cgr_opts = {
1415                 .we_mask = QM_CGR_WE_CS_THRES |
1416                                 QM_CGR_WE_CSTD_EN |
1417                                 QM_CGR_WE_MODE,
1418                 .cgr = {
1419                         .cstd_en = QM_CGR_EN,
1420                         .mode = QMAN_CGR_MODE_FRAME
1421                 }
1422         };
1423
1424         if (fmc_q || default_q) {
1425                 ret = qman_reserve_fqid(fqid);
1426                 if (ret) {
1427                         DPAA_PMD_ERR("reserve rx fqid 0x%x failed, ret: %d",
1428                                      fqid, ret);
1429                         return -EINVAL;
1430                 }
1431         }
1432
1433         DPAA_PMD_DEBUG("creating rx fq %p, fqid 0x%x", fq, fqid);
1434         ret = qman_create_fq(fqid, flags, fq);
1435         if (ret) {
1436                 DPAA_PMD_ERR("create rx fqid 0x%x failed with ret: %d",
1437                         fqid, ret);
1438                 return ret;
1439         }
1440         fq->is_static = false;
1441
1442         dpaa_poll_queue_default_config(&opts);
1443
1444         if (cgr_rx) {
1445                 /* Enable tail drop with cgr on this queue */
1446                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, td_threshold, 0);
1447                 cgr_rx->cb = NULL;
1448                 ret = qman_create_cgr(cgr_rx, QMAN_CGR_FLAG_USE_INIT,
1449                                       &cgr_opts);
1450                 if (ret) {
1451                         DPAA_PMD_WARN(
1452                                 "rx taildrop init fail on rx fqid 0x%x(ret=%d)",
1453                                 fq->fqid, ret);
1454                         goto without_cgr;
1455                 }
1456                 opts.we_mask |= QM_INITFQ_WE_CGID;
1457                 opts.fqd.cgid = cgr_rx->cgrid;
1458                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1459         }
1460 without_cgr:
1461         ret = qman_init_fq(fq, 0, &opts);
1462         if (ret)
1463                 DPAA_PMD_ERR("init rx fqid 0x%x failed with ret:%d", fqid, ret);
1464         return ret;
1465 }
1466
1467 /* Initialise a Tx FQ */
1468 static int dpaa_tx_queue_init(struct qman_fq *fq,
1469                               struct fman_if *fman_intf,
1470                               struct qman_cgr *cgr_tx)
1471 {
1472         struct qm_mcc_initfq opts = {0};
1473         struct qm_mcc_initcgr cgr_opts = {
1474                 .we_mask = QM_CGR_WE_CS_THRES |
1475                                 QM_CGR_WE_CSTD_EN |
1476                                 QM_CGR_WE_MODE,
1477                 .cgr = {
1478                         .cstd_en = QM_CGR_EN,
1479                         .mode = QMAN_CGR_MODE_FRAME
1480                 }
1481         };
1482         int ret;
1483
1484         ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID |
1485                              QMAN_FQ_FLAG_TO_DCPORTAL, fq);
1486         if (ret) {
1487                 DPAA_PMD_ERR("create tx fq failed with ret: %d", ret);
1488                 return ret;
1489         }
1490         opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL |
1491                        QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA;
1492         opts.fqd.dest.channel = fman_intf->tx_channel_id;
1493         opts.fqd.dest.wq = DPAA_IF_TX_PRIORITY;
1494         opts.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE;
1495         opts.fqd.context_b = 0;
1496         /* no tx-confirmation */
1497         opts.fqd.context_a.hi = 0x80000000 | fman_dealloc_bufs_mask_hi;
1498         opts.fqd.context_a.lo = 0 | fman_dealloc_bufs_mask_lo;
1499         DPAA_PMD_DEBUG("init tx fq %p, fqid 0x%x", fq, fq->fqid);
1500
1501         if (cgr_tx) {
1502                 /* Enable tail drop with cgr on this queue */
1503                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres,
1504                                       td_tx_threshold, 0);
1505                 cgr_tx->cb = NULL;
1506                 ret = qman_create_cgr(cgr_tx, QMAN_CGR_FLAG_USE_INIT,
1507                                       &cgr_opts);
1508                 if (ret) {
1509                         DPAA_PMD_WARN(
1510                                 "rx taildrop init fail on rx fqid 0x%x(ret=%d)",
1511                                 fq->fqid, ret);
1512                         goto without_cgr;
1513                 }
1514                 opts.we_mask |= QM_INITFQ_WE_CGID;
1515                 opts.fqd.cgid = cgr_tx->cgrid;
1516                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1517                 DPAA_PMD_DEBUG("Tx FQ tail drop enabled, threshold = %d\n",
1518                                 td_tx_threshold);
1519         }
1520 without_cgr:
1521         ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts);
1522         if (ret)
1523                 DPAA_PMD_ERR("init tx fqid 0x%x failed %d", fq->fqid, ret);
1524         return ret;
1525 }
1526
1527 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1528 /* Initialise a DEBUG FQ ([rt]x_error, rx_default). */
1529 static int dpaa_debug_queue_init(struct qman_fq *fq, uint32_t fqid)
1530 {
1531         struct qm_mcc_initfq opts = {0};
1532         int ret;
1533
1534         PMD_INIT_FUNC_TRACE();
1535
1536         ret = qman_reserve_fqid(fqid);
1537         if (ret) {
1538                 DPAA_PMD_ERR("Reserve debug fqid %d failed with ret: %d",
1539                         fqid, ret);
1540                 return -EINVAL;
1541         }
1542         /* "map" this Rx FQ to one of the interfaces Tx FQID */
1543         DPAA_PMD_DEBUG("Creating debug fq %p, fqid %d", fq, fqid);
1544         ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq);
1545         if (ret) {
1546                 DPAA_PMD_ERR("create debug fqid %d failed with ret: %d",
1547                         fqid, ret);
1548                 return ret;
1549         }
1550         opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL;
1551         opts.fqd.dest.wq = DPAA_IF_DEBUG_PRIORITY;
1552         ret = qman_init_fq(fq, 0, &opts);
1553         if (ret)
1554                 DPAA_PMD_ERR("init debug fqid %d failed with ret: %d",
1555                             fqid, ret);
1556         return ret;
1557 }
1558 #endif
1559
1560 /* Initialise a network interface */
1561 static int
1562 dpaa_dev_init_secondary(struct rte_eth_dev *eth_dev)
1563 {
1564         struct rte_dpaa_device *dpaa_device;
1565         struct fm_eth_port_cfg *cfg;
1566         struct dpaa_if *dpaa_intf;
1567         struct fman_if *fman_intf;
1568         int dev_id;
1569
1570         PMD_INIT_FUNC_TRACE();
1571
1572         dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1573         dev_id = dpaa_device->id.dev_id;
1574         cfg = dpaa_get_eth_port_cfg(dev_id);
1575         fman_intf = cfg->fman_if;
1576         eth_dev->process_private = fman_intf;
1577
1578         /* Plugging of UCODE burst API not supported in Secondary */
1579         dpaa_intf = eth_dev->data->dev_private;
1580         eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
1581         if (dpaa_intf->cgr_tx)
1582                 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx_slow;
1583         else
1584                 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx;
1585 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP
1586         qman_set_fq_lookup_table(
1587                 dpaa_intf->rx_queues->qman_fq_lookup_table);
1588 #endif
1589
1590         return 0;
1591 }
1592
1593 /* Initialise a network interface */
1594 static int
1595 dpaa_dev_init(struct rte_eth_dev *eth_dev)
1596 {
1597         int num_rx_fqs, fqid;
1598         int loop, ret = 0;
1599         int dev_id;
1600         struct rte_dpaa_device *dpaa_device;
1601         struct dpaa_if *dpaa_intf;
1602         struct fm_eth_port_cfg *cfg;
1603         struct fman_if *fman_intf;
1604         struct fman_if_bpool *bp, *tmp_bp;
1605         uint32_t cgrid[DPAA_MAX_NUM_PCD_QUEUES];
1606         uint32_t cgrid_tx[MAX_DPAA_CORES];
1607         uint32_t dev_rx_fqids[DPAA_MAX_NUM_PCD_QUEUES];
1608
1609         PMD_INIT_FUNC_TRACE();
1610
1611         dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1612         dev_id = dpaa_device->id.dev_id;
1613         dpaa_intf = eth_dev->data->dev_private;
1614         cfg = dpaa_get_eth_port_cfg(dev_id);
1615         fman_intf = cfg->fman_if;
1616
1617         dpaa_intf->name = dpaa_device->name;
1618
1619         /* save fman_if & cfg in the interface struture */
1620         eth_dev->process_private = fman_intf;
1621         dpaa_intf->ifid = dev_id;
1622         dpaa_intf->cfg = cfg;
1623
1624         memset((char *)dev_rx_fqids, 0,
1625                 sizeof(uint32_t) * DPAA_MAX_NUM_PCD_QUEUES);
1626
1627         /* Initialize Rx FQ's */
1628         if (default_q) {
1629                 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES;
1630         } else if (fmc_q) {
1631                 num_rx_fqs = 1;
1632         } else {
1633                 /* FMCLESS mode, load balance to multiple cores.*/
1634                 num_rx_fqs = rte_lcore_count();
1635         }
1636
1637         /* Each device can not have more than DPAA_MAX_NUM_PCD_QUEUES RX
1638          * queues.
1639          */
1640         if (num_rx_fqs < 0 || num_rx_fqs > DPAA_MAX_NUM_PCD_QUEUES) {
1641                 DPAA_PMD_ERR("Invalid number of RX queues\n");
1642                 return -EINVAL;
1643         }
1644
1645         if (num_rx_fqs > 0) {
1646                 dpaa_intf->rx_queues = rte_zmalloc(NULL,
1647                         sizeof(struct qman_fq) * num_rx_fqs, MAX_CACHELINE);
1648                 if (!dpaa_intf->rx_queues) {
1649                         DPAA_PMD_ERR("Failed to alloc mem for RX queues\n");
1650                         return -ENOMEM;
1651                 }
1652         } else {
1653                 dpaa_intf->rx_queues = NULL;
1654         }
1655
1656         memset(cgrid, 0, sizeof(cgrid));
1657         memset(cgrid_tx, 0, sizeof(cgrid_tx));
1658
1659         /* if DPAA_TX_TAILDROP_THRESHOLD is set, use that value; if 0, it means
1660          * Tx tail drop is disabled.
1661          */
1662         if (getenv("DPAA_TX_TAILDROP_THRESHOLD")) {
1663                 td_tx_threshold = atoi(getenv("DPAA_TX_TAILDROP_THRESHOLD"));
1664                 DPAA_PMD_DEBUG("Tail drop threshold env configured: %u",
1665                                td_tx_threshold);
1666                 /* if a very large value is being configured */
1667                 if (td_tx_threshold > UINT16_MAX)
1668                         td_tx_threshold = CGR_RX_PERFQ_THRESH;
1669         }
1670
1671         /* If congestion control is enabled globally*/
1672         if (num_rx_fqs > 0 && td_threshold) {
1673                 dpaa_intf->cgr_rx = rte_zmalloc(NULL,
1674                         sizeof(struct qman_cgr) * num_rx_fqs, MAX_CACHELINE);
1675                 if (!dpaa_intf->cgr_rx) {
1676                         DPAA_PMD_ERR("Failed to alloc mem for cgr_rx\n");
1677                         ret = -ENOMEM;
1678                         goto free_rx;
1679                 }
1680
1681                 ret = qman_alloc_cgrid_range(&cgrid[0], num_rx_fqs, 1, 0);
1682                 if (ret != num_rx_fqs) {
1683                         DPAA_PMD_WARN("insufficient CGRIDs available");
1684                         ret = -EINVAL;
1685                         goto free_rx;
1686                 }
1687         } else {
1688                 dpaa_intf->cgr_rx = NULL;
1689         }
1690
1691         if (!fmc_q && !default_q) {
1692                 ret = qman_alloc_fqid_range(dev_rx_fqids, num_rx_fqs,
1693                                             num_rx_fqs, 0);
1694                 if (ret < 0) {
1695                         DPAA_PMD_ERR("Failed to alloc rx fqid's\n");
1696                         goto free_rx;
1697                 }
1698         }
1699
1700         for (loop = 0; loop < num_rx_fqs; loop++) {
1701                 if (default_q)
1702                         fqid = cfg->rx_def;
1703                 else
1704                         fqid = dev_rx_fqids[loop];
1705
1706                 if (dpaa_intf->cgr_rx)
1707                         dpaa_intf->cgr_rx[loop].cgrid = cgrid[loop];
1708
1709                 ret = dpaa_rx_queue_init(&dpaa_intf->rx_queues[loop],
1710                         dpaa_intf->cgr_rx ? &dpaa_intf->cgr_rx[loop] : NULL,
1711                         fqid);
1712                 if (ret)
1713                         goto free_rx;
1714                 dpaa_intf->rx_queues[loop].dpaa_intf = dpaa_intf;
1715         }
1716         dpaa_intf->nb_rx_queues = num_rx_fqs;
1717
1718         /* Initialise Tx FQs.free_rx Have as many Tx FQ's as number of cores */
1719         dpaa_intf->tx_queues = rte_zmalloc(NULL, sizeof(struct qman_fq) *
1720                 MAX_DPAA_CORES, MAX_CACHELINE);
1721         if (!dpaa_intf->tx_queues) {
1722                 DPAA_PMD_ERR("Failed to alloc mem for TX queues\n");
1723                 ret = -ENOMEM;
1724                 goto free_rx;
1725         }
1726
1727         /* If congestion control is enabled globally*/
1728         if (td_tx_threshold) {
1729                 dpaa_intf->cgr_tx = rte_zmalloc(NULL,
1730                         sizeof(struct qman_cgr) * MAX_DPAA_CORES,
1731                         MAX_CACHELINE);
1732                 if (!dpaa_intf->cgr_tx) {
1733                         DPAA_PMD_ERR("Failed to alloc mem for cgr_tx\n");
1734                         ret = -ENOMEM;
1735                         goto free_rx;
1736                 }
1737
1738                 ret = qman_alloc_cgrid_range(&cgrid_tx[0], MAX_DPAA_CORES,
1739                                              1, 0);
1740                 if (ret != MAX_DPAA_CORES) {
1741                         DPAA_PMD_WARN("insufficient CGRIDs available");
1742                         ret = -EINVAL;
1743                         goto free_rx;
1744                 }
1745         } else {
1746                 dpaa_intf->cgr_tx = NULL;
1747         }
1748
1749
1750         for (loop = 0; loop < MAX_DPAA_CORES; loop++) {
1751                 if (dpaa_intf->cgr_tx)
1752                         dpaa_intf->cgr_tx[loop].cgrid = cgrid_tx[loop];
1753
1754                 ret = dpaa_tx_queue_init(&dpaa_intf->tx_queues[loop],
1755                         fman_intf,
1756                         dpaa_intf->cgr_tx ? &dpaa_intf->cgr_tx[loop] : NULL);
1757                 if (ret)
1758                         goto free_tx;
1759                 dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf;
1760         }
1761         dpaa_intf->nb_tx_queues = MAX_DPAA_CORES;
1762
1763 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1764         dpaa_debug_queue_init(&dpaa_intf->debug_queues[
1765                 DPAA_DEBUG_FQ_RX_ERROR], fman_intf->fqid_rx_err);
1766         dpaa_intf->debug_queues[DPAA_DEBUG_FQ_RX_ERROR].dpaa_intf = dpaa_intf;
1767         dpaa_debug_queue_init(&dpaa_intf->debug_queues[
1768                 DPAA_DEBUG_FQ_TX_ERROR], fman_intf->fqid_tx_err);
1769         dpaa_intf->debug_queues[DPAA_DEBUG_FQ_TX_ERROR].dpaa_intf = dpaa_intf;
1770 #endif
1771
1772         DPAA_PMD_DEBUG("All frame queues created");
1773
1774         /* Get the initial configuration for flow control */
1775         dpaa_fc_set_default(dpaa_intf, fman_intf);
1776
1777         /* reset bpool list, initialize bpool dynamically */
1778         list_for_each_entry_safe(bp, tmp_bp, &cfg->fman_if->bpool_list, node) {
1779                 list_del(&bp->node);
1780                 rte_free(bp);
1781         }
1782
1783         /* Populate ethdev structure */
1784         eth_dev->dev_ops = &dpaa_devops;
1785         eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
1786         eth_dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
1787
1788         /* Allocate memory for storing MAC addresses */
1789         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr",
1790                 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER, 0);
1791         if (eth_dev->data->mac_addrs == NULL) {
1792                 DPAA_PMD_ERR("Failed to allocate %d bytes needed to "
1793                                                 "store MAC addresses",
1794                                 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER);
1795                 ret = -ENOMEM;
1796                 goto free_tx;
1797         }
1798
1799         /* copy the primary mac address */
1800         rte_ether_addr_copy(&fman_intf->mac_addr, &eth_dev->data->mac_addrs[0]);
1801
1802         RTE_LOG(INFO, PMD, "net: dpaa: %s: %02x:%02x:%02x:%02x:%02x:%02x\n",
1803                 dpaa_device->name,
1804                 fman_intf->mac_addr.addr_bytes[0],
1805                 fman_intf->mac_addr.addr_bytes[1],
1806                 fman_intf->mac_addr.addr_bytes[2],
1807                 fman_intf->mac_addr.addr_bytes[3],
1808                 fman_intf->mac_addr.addr_bytes[4],
1809                 fman_intf->mac_addr.addr_bytes[5]);
1810
1811         if (!fman_intf->is_shared_mac) {
1812                 /* Disable RX mode */
1813                 fman_if_discard_rx_errors(fman_intf);
1814                 fman_if_disable_rx(fman_intf);
1815                 /* Disable promiscuous mode */
1816                 fman_if_promiscuous_disable(fman_intf);
1817                 /* Disable multicast */
1818                 fman_if_reset_mcast_filter_table(fman_intf);
1819                 /* Reset interface statistics */
1820                 fman_if_stats_reset(fman_intf);
1821                 /* Disable SG by default */
1822                 fman_if_set_sg(fman_intf, 0);
1823                 fman_if_set_maxfrm(fman_intf,
1824                                    RTE_ETHER_MAX_LEN + VLAN_TAG_SIZE);
1825         }
1826
1827         return 0;
1828
1829 free_tx:
1830         rte_free(dpaa_intf->tx_queues);
1831         dpaa_intf->tx_queues = NULL;
1832         dpaa_intf->nb_tx_queues = 0;
1833
1834 free_rx:
1835         rte_free(dpaa_intf->cgr_rx);
1836         rte_free(dpaa_intf->cgr_tx);
1837         rte_free(dpaa_intf->rx_queues);
1838         dpaa_intf->rx_queues = NULL;
1839         dpaa_intf->nb_rx_queues = 0;
1840         return ret;
1841 }
1842
1843 static int
1844 dpaa_dev_uninit(struct rte_eth_dev *dev)
1845 {
1846         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1847         int loop;
1848
1849         PMD_INIT_FUNC_TRACE();
1850
1851         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1852                 return -EPERM;
1853
1854         if (!dpaa_intf) {
1855                 DPAA_PMD_WARN("Already closed or not started");
1856                 return -1;
1857         }
1858
1859         /* DPAA FM deconfig */
1860         if (!(default_q || fmc_q)) {
1861                 if (dpaa_fm_deconfig(dpaa_intf, dev->process_private))
1862                         DPAA_PMD_WARN("DPAA FM deconfig failed\n");
1863         }
1864
1865         dpaa_eth_dev_close(dev);
1866
1867         /* release configuration memory */
1868         if (dpaa_intf->fc_conf)
1869                 rte_free(dpaa_intf->fc_conf);
1870
1871         /* Release RX congestion Groups */
1872         if (dpaa_intf->cgr_rx) {
1873                 for (loop = 0; loop < dpaa_intf->nb_rx_queues; loop++)
1874                         qman_delete_cgr(&dpaa_intf->cgr_rx[loop]);
1875
1876                 qman_release_cgrid_range(dpaa_intf->cgr_rx[loop].cgrid,
1877                                          dpaa_intf->nb_rx_queues);
1878         }
1879
1880         rte_free(dpaa_intf->cgr_rx);
1881         dpaa_intf->cgr_rx = NULL;
1882
1883         /* Release TX congestion Groups */
1884         if (dpaa_intf->cgr_tx) {
1885                 for (loop = 0; loop < MAX_DPAA_CORES; loop++)
1886                         qman_delete_cgr(&dpaa_intf->cgr_tx[loop]);
1887
1888                 qman_release_cgrid_range(dpaa_intf->cgr_tx[loop].cgrid,
1889                                          MAX_DPAA_CORES);
1890                 rte_free(dpaa_intf->cgr_tx);
1891                 dpaa_intf->cgr_tx = NULL;
1892         }
1893
1894         rte_free(dpaa_intf->rx_queues);
1895         dpaa_intf->rx_queues = NULL;
1896
1897         rte_free(dpaa_intf->tx_queues);
1898         dpaa_intf->tx_queues = NULL;
1899
1900         dev->dev_ops = NULL;
1901         dev->rx_pkt_burst = NULL;
1902         dev->tx_pkt_burst = NULL;
1903
1904         return 0;
1905 }
1906
1907 static int
1908 rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv,
1909                struct rte_dpaa_device *dpaa_dev)
1910 {
1911         int diag;
1912         int ret;
1913         struct rte_eth_dev *eth_dev;
1914
1915         PMD_INIT_FUNC_TRACE();
1916
1917         if ((DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE) >
1918                 RTE_PKTMBUF_HEADROOM) {
1919                 DPAA_PMD_ERR(
1920                 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA Annotation req(%d)",
1921                 RTE_PKTMBUF_HEADROOM,
1922                 DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE);
1923
1924                 return -1;
1925         }
1926
1927         /* In case of secondary process, the device is already configured
1928          * and no further action is required, except portal initialization
1929          * and verifying secondary attachment to port name.
1930          */
1931         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1932                 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name);
1933                 if (!eth_dev)
1934                         return -ENOMEM;
1935                 eth_dev->device = &dpaa_dev->device;
1936                 eth_dev->dev_ops = &dpaa_devops;
1937
1938                 ret = dpaa_dev_init_secondary(eth_dev);
1939                 if (ret != 0) {
1940                         RTE_LOG(ERR, PMD, "secondary dev init failed\n");
1941                         return ret;
1942                 }
1943
1944                 rte_eth_dev_probing_finish(eth_dev);
1945                 return 0;
1946         }
1947
1948         if (!is_global_init && (rte_eal_process_type() == RTE_PROC_PRIMARY)) {
1949                 if (access("/tmp/fmc.bin", F_OK) == -1) {
1950                         DPAA_PMD_INFO("* FMC not configured.Enabling default mode");
1951                         default_q = 1;
1952                 }
1953
1954                 if (!(default_q || fmc_q)) {
1955                         if (dpaa_fm_init()) {
1956                                 DPAA_PMD_ERR("FM init failed\n");
1957                                 return -1;
1958                         }
1959                 }
1960
1961                 /* disabling the default push mode for LS1043 */
1962                 if (dpaa_svr_family == SVR_LS1043A_FAMILY)
1963                         dpaa_push_mode_max_queue = 0;
1964
1965                 /* if push mode queues to be enabled. Currenly we are allowing
1966                  * only one queue per thread.
1967                  */
1968                 if (getenv("DPAA_PUSH_QUEUES_NUMBER")) {
1969                         dpaa_push_mode_max_queue =
1970                                         atoi(getenv("DPAA_PUSH_QUEUES_NUMBER"));
1971                         if (dpaa_push_mode_max_queue > DPAA_MAX_PUSH_MODE_QUEUE)
1972                             dpaa_push_mode_max_queue = DPAA_MAX_PUSH_MODE_QUEUE;
1973                 }
1974
1975                 is_global_init = 1;
1976         }
1977
1978         if (unlikely(!DPAA_PER_LCORE_PORTAL)) {
1979                 ret = rte_dpaa_portal_init((void *)1);
1980                 if (ret) {
1981                         DPAA_PMD_ERR("Unable to initialize portal");
1982                         return ret;
1983                 }
1984         }
1985
1986         eth_dev = rte_eth_dev_allocate(dpaa_dev->name);
1987         if (!eth_dev)
1988                 return -ENOMEM;
1989
1990         eth_dev->data->dev_private =
1991                         rte_zmalloc("ethdev private structure",
1992                                         sizeof(struct dpaa_if),
1993                                         RTE_CACHE_LINE_SIZE);
1994         if (!eth_dev->data->dev_private) {
1995                 DPAA_PMD_ERR("Cannot allocate memzone for port data");
1996                 rte_eth_dev_release_port(eth_dev);
1997                 return -ENOMEM;
1998         }
1999
2000         eth_dev->device = &dpaa_dev->device;
2001         dpaa_dev->eth_dev = eth_dev;
2002
2003         qman_ern_register_cb(dpaa_free_mbuf);
2004
2005         if (dpaa_drv->drv_flags & RTE_DPAA_DRV_INTR_LSC)
2006                 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;
2007
2008         /* Invoke PMD device initialization function */
2009         diag = dpaa_dev_init(eth_dev);
2010         if (diag == 0) {
2011                 rte_eth_dev_probing_finish(eth_dev);
2012                 return 0;
2013         }
2014
2015         rte_eth_dev_release_port(eth_dev);
2016         return diag;
2017 }
2018
2019 static int
2020 rte_dpaa_remove(struct rte_dpaa_device *dpaa_dev)
2021 {
2022         struct rte_eth_dev *eth_dev;
2023
2024         PMD_INIT_FUNC_TRACE();
2025
2026         eth_dev = dpaa_dev->eth_dev;
2027         dpaa_dev_uninit(eth_dev);
2028
2029         rte_eth_dev_release_port(eth_dev);
2030
2031         return 0;
2032 }
2033
2034 static void __attribute__((destructor(102))) dpaa_finish(void)
2035 {
2036         /* For secondary, primary will do all the cleanup */
2037         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2038                 return;
2039
2040         if (!(default_q || fmc_q)) {
2041                 unsigned int i;
2042
2043                 for (i = 0; i < RTE_MAX_ETHPORTS; i++) {
2044                         if (rte_eth_devices[i].dev_ops == &dpaa_devops) {
2045                                 struct rte_eth_dev *dev = &rte_eth_devices[i];
2046                                 struct dpaa_if *dpaa_intf =
2047                                         dev->data->dev_private;
2048                                 struct fman_if *fif =
2049                                         dev->process_private;
2050                                 if (dpaa_intf->port_handle)
2051                                         if (dpaa_fm_deconfig(dpaa_intf, fif))
2052                                                 DPAA_PMD_WARN("DPAA FM "
2053                                                         "deconfig failed\n");
2054                         }
2055                 }
2056                 if (is_global_init)
2057                         if (dpaa_fm_term())
2058                                 DPAA_PMD_WARN("DPAA FM term failed\n");
2059
2060                 is_global_init = 0;
2061
2062                 DPAA_PMD_INFO("DPAA fman cleaned up");
2063         }
2064 }
2065
2066 static struct rte_dpaa_driver rte_dpaa_pmd = {
2067         .drv_flags = RTE_DPAA_DRV_INTR_LSC,
2068         .drv_type = FSL_DPAA_ETH,
2069         .probe = rte_dpaa_probe,
2070         .remove = rte_dpaa_remove,
2071 };
2072
2073 RTE_PMD_REGISTER_DPAA(net_dpaa, rte_dpaa_pmd);
2074 RTE_LOG_REGISTER(dpaa_logtype_pmd, pmd.net.dpaa, NOTICE);