drivers/net/dpaa/dpaa_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  *   Copyright 2016 Freescale Semiconductor, Inc. All rights reserved.
   4  *   Copyright 2017 NXP
   5  *
   6  */
   7 /* System headers */
   8 #include <stdio.h>
   9 #include <inttypes.h>
  10 #include <unistd.h>
  11 #include <limits.h>
  12 #include <sched.h>
  13 #include <signal.h>
  14 #include <pthread.h>
  15 #include <sys/types.h>
  16 #include <sys/syscall.h>
  17
  18 #include <rte_byteorder.h>
  19 #include <rte_common.h>
  20 #include <rte_interrupts.h>
  21 #include <rte_log.h>
  22 #include <rte_debug.h>
  23 #include <rte_pci.h>
  24 #include <rte_atomic.h>
  25 #include <rte_branch_prediction.h>
  26 #include <rte_memory.h>
  27 #include <rte_tailq.h>
  28 #include <rte_eal.h>
  29 #include <rte_alarm.h>
  30 #include <rte_ether.h>
  31 #include <rte_ethdev_driver.h>
  32 #include <rte_malloc.h>
  33 #include <rte_ring.h>
  34
  35 #include <rte_dpaa_bus.h>
  36 #include <rte_dpaa_logs.h>
  37 #include <dpaa_mempool.h>
  38
  39 #include <dpaa_ethdev.h>
  40 #include <dpaa_rxtx.h>
  41 #include <rte_pmd_dpaa.h>
  42
  43 #include <fsl_usd.h>
  44 #include <fsl_qman.h>
  45 #include <fsl_bman.h>
  46 #include <fsl_fman.h>
  47
  48 /* Supported Rx offloads */
  49 static uint64_t dev_rx_offloads_sup =
  50                 DEV_RX_OFFLOAD_JUMBO_FRAME |
  51                 DEV_RX_OFFLOAD_SCATTER;
  52
  53 /* Rx offloads which cannot be disabled */
  54 static uint64_t dev_rx_offloads_nodis =
  55                 DEV_RX_OFFLOAD_IPV4_CKSUM |
  56                 DEV_RX_OFFLOAD_UDP_CKSUM |
  57                 DEV_RX_OFFLOAD_TCP_CKSUM |
  58                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
  59
  60 /* Supported Tx offloads */
  61 static uint64_t dev_tx_offloads_sup;
  62
  63 /* Tx offloads which cannot be disabled */
  64 static uint64_t dev_tx_offloads_nodis =
  65                 DEV_TX_OFFLOAD_IPV4_CKSUM |
  66                 DEV_TX_OFFLOAD_UDP_CKSUM |
  67                 DEV_TX_OFFLOAD_TCP_CKSUM |
  68                 DEV_TX_OFFLOAD_SCTP_CKSUM |
  69                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
  70                 DEV_TX_OFFLOAD_MULTI_SEGS |
  71                 DEV_TX_OFFLOAD_MT_LOCKFREE |
  72                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
  73
  74 /* Keep track of whether QMAN and BMAN have been globally initialized */
  75 static int is_global_init;
  76 static int default_q;   /* use default queue - FMC is not executed*/
  77 /* At present we only allow up to 4 push mode queues as default - as each of
  78  * this queue need dedicated portal and we are short of portals.
  79  */
  80 #define DPAA_MAX_PUSH_MODE_QUEUE       8
  81 #define DPAA_DEFAULT_PUSH_MODE_QUEUE   4
  82
  83 static int dpaa_push_mode_max_queue = DPAA_DEFAULT_PUSH_MODE_QUEUE;
  84 static int dpaa_push_queue_idx; /* Queue index which are in push mode*/
  85
  86
  87 /* Per FQ Taildrop in frame count */
  88 static unsigned int td_threshold = CGR_RX_PERFQ_THRESH;
  89
  90 struct rte_dpaa_xstats_name_off {
  91         char name[RTE_ETH_XSTATS_NAME_SIZE];
  92         uint32_t offset;
  93 };
  94
  95 static const struct rte_dpaa_xstats_name_off dpaa_xstats_strings[] = {
  96         {"rx_align_err",
  97                 offsetof(struct dpaa_if_stats, raln)},
  98         {"rx_valid_pause",
  99                 offsetof(struct dpaa_if_stats, rxpf)},
 100         {"rx_fcs_err",
 101                 offsetof(struct dpaa_if_stats, rfcs)},
 102         {"rx_vlan_frame",
 103                 offsetof(struct dpaa_if_stats, rvlan)},
 104         {"rx_frame_err",
 105                 offsetof(struct dpaa_if_stats, rerr)},
 106         {"rx_drop_err",
 107                 offsetof(struct dpaa_if_stats, rdrp)},
 108         {"rx_undersized",
 109                 offsetof(struct dpaa_if_stats, rund)},
 110         {"rx_oversize_err",
 111                 offsetof(struct dpaa_if_stats, rovr)},
 112         {"rx_fragment_pkt",
 113                 offsetof(struct dpaa_if_stats, rfrg)},
 114         {"tx_valid_pause",
 115                 offsetof(struct dpaa_if_stats, txpf)},
 116         {"tx_fcs_err",
 117                 offsetof(struct dpaa_if_stats, terr)},
 118         {"tx_vlan_frame",
 119                 offsetof(struct dpaa_if_stats, tvlan)},
 120         {"rx_undersized",
 121                 offsetof(struct dpaa_if_stats, tund)},
 122 };
 123
 124 static struct rte_dpaa_driver rte_dpaa_pmd;
 125
 126 static void
 127 dpaa_eth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info);
 128
 129 static inline void
 130 dpaa_poll_queue_default_config(struct qm_mcc_initfq *opts)
 131 {
 132         memset(opts, 0, sizeof(struct qm_mcc_initfq));
 133         opts->we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
 134         opts->fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | QM_FQCTRL_CTXASTASHING |
 135                            QM_FQCTRL_PREFERINCACHE;
 136         opts->fqd.context_a.stashing.exclusive = 0;
 137         if (dpaa_svr_family != SVR_LS1046A_FAMILY)
 138                 opts->fqd.context_a.stashing.annotation_cl =
 139                                                 DPAA_IF_RX_ANNOTATION_STASH;
 140         opts->fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
 141         opts->fqd.context_a.stashing.context_cl = DPAA_IF_RX_CONTEXT_STASH;
 142 }
 143
 144 static int
 145 dpaa_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 146 {
 147         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 148         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN
 149                                 + VLAN_TAG_SIZE;
 150         uint32_t buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
 151
 152         PMD_INIT_FUNC_TRACE();
 153
 154         if (mtu < ETHER_MIN_MTU || frame_size > DPAA_MAX_RX_PKT_LEN)
 155                 return -EINVAL;
 156         /*
 157          * Refuse mtu that requires the support of scattered packets
 158          * when this feature has not been enabled before.
 159          */
 160         if (dev->data->min_rx_buf_size &&
 161                 !dev->data->scattered_rx && frame_size > buffsz) {
 162                 DPAA_PMD_ERR("SG not enabled, will not fit in one buffer");
 163                 return -EINVAL;
 164         }
 165
 166         /* check <seg size> * <max_seg>  >= max_frame */
 167         if (dev->data->min_rx_buf_size && dev->data->scattered_rx &&
 168                 (frame_size > buffsz * DPAA_SGT_MAX_ENTRIES)) {
 169                 DPAA_PMD_ERR("Too big to fit for Max SG list %d",
 170                                 buffsz * DPAA_SGT_MAX_ENTRIES);
 171                 return -EINVAL;
 172         }
 173
 174         if (frame_size > ETHER_MAX_LEN)
 175                 dev->data->dev_conf.rxmode.offloads &=
 176                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 177         else
 178                 dev->data->dev_conf.rxmode.offloads &=
 179                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 180
 181         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 182
 183         fman_if_set_maxfrm(dpaa_intf->fif, frame_size);
 184
 185         return 0;
 186 }
 187
 188 static int
 189 dpaa_eth_dev_configure(struct rte_eth_dev *dev)
 190 {
 191         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 192         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 193         uint64_t rx_offloads = eth_conf->rxmode.offloads;
 194         uint64_t tx_offloads = eth_conf->txmode.offloads;
 195
 196         PMD_INIT_FUNC_TRACE();
 197
 198         /* Rx offloads validation */
 199         if (dev_rx_offloads_nodis & ~rx_offloads) {
 200                 DPAA_PMD_WARN(
 201                 "Rx offloads non configurable - requested 0x%" PRIx64
 202                 " ignored 0x%" PRIx64,
 203                         rx_offloads, dev_rx_offloads_nodis);
 204         }
 205
 206         /* Tx offloads validation */
 207         if (dev_tx_offloads_nodis & ~tx_offloads) {
 208                 DPAA_PMD_WARN(
 209                 "Tx offloads non configurable - requested 0x%" PRIx64
 210                 " ignored 0x%" PRIx64,
 211                         tx_offloads, dev_tx_offloads_nodis);
 212         }
 213
 214         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 215                 uint32_t max_len;
 216
 217                 DPAA_PMD_DEBUG("enabling jumbo");
 218
 219                 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <=
 220                     DPAA_MAX_RX_PKT_LEN)
 221                         max_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
 222                 else {
 223                         DPAA_PMD_INFO("enabling jumbo override conf max len=%d "
 224                                 "supported is %d",
 225                                 dev->data->dev_conf.rxmode.max_rx_pkt_len,
 226                                 DPAA_MAX_RX_PKT_LEN);
 227                         max_len = DPAA_MAX_RX_PKT_LEN;
 228                 }
 229
 230                 fman_if_set_maxfrm(dpaa_intf->fif, max_len);
 231                 dev->data->mtu = max_len
 232                                 - ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE;
 233         }
 234
 235         if (rx_offloads & DEV_RX_OFFLOAD_SCATTER) {
 236                 DPAA_PMD_DEBUG("enabling scatter mode");
 237                 fman_if_set_sg(dpaa_intf->fif, 1);
 238                 dev->data->scattered_rx = 1;
 239         }
 240
 241         return 0;
 242 }
 243
 244 static const uint32_t *
 245 dpaa_supported_ptypes_get(struct rte_eth_dev *dev)
 246 {
 247         static const uint32_t ptypes[] = {
 248                 /*todo -= add more types */
 249                 RTE_PTYPE_L2_ETHER,
 250                 RTE_PTYPE_L3_IPV4,
 251                 RTE_PTYPE_L3_IPV4_EXT,
 252                 RTE_PTYPE_L3_IPV6,
 253                 RTE_PTYPE_L3_IPV6_EXT,
 254                 RTE_PTYPE_L4_TCP,
 255                 RTE_PTYPE_L4_UDP,
 256                 RTE_PTYPE_L4_SCTP
 257         };
 258
 259         PMD_INIT_FUNC_TRACE();
 260
 261         if (dev->rx_pkt_burst == dpaa_eth_queue_rx)
 262                 return ptypes;
 263         return NULL;
 264 }
 265
 266 static int dpaa_eth_dev_start(struct rte_eth_dev *dev)
 267 {
 268         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 269
 270         PMD_INIT_FUNC_TRACE();
 271
 272         /* Change tx callback to the real one */
 273         dev->tx_pkt_burst = dpaa_eth_queue_tx;
 274         fman_if_enable_rx(dpaa_intf->fif);
 275
 276         return 0;
 277 }
 278
 279 static void dpaa_eth_dev_stop(struct rte_eth_dev *dev)
 280 {
 281         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 282
 283         PMD_INIT_FUNC_TRACE();
 284
 285         fman_if_disable_rx(dpaa_intf->fif);
 286         dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
 287 }
 288
 289 static void dpaa_eth_dev_close(struct rte_eth_dev *dev)
 290 {
 291         PMD_INIT_FUNC_TRACE();
 292
 293         dpaa_eth_dev_stop(dev);
 294 }
 295
 296 static int
 297 dpaa_fw_version_get(struct rte_eth_dev *dev __rte_unused,
 298                      char *fw_version,
 299                      size_t fw_size)
 300 {
 301         int ret;
 302         FILE *svr_file = NULL;
 303         unsigned int svr_ver = 0;
 304
 305         PMD_INIT_FUNC_TRACE();
 306
 307         svr_file = fopen(DPAA_SOC_ID_FILE, "r");
 308         if (!svr_file) {
 309                 DPAA_PMD_ERR("Unable to open SoC device");
 310                 return -ENOTSUP; /* Not supported on this infra */
 311         }
 312         if (fscanf(svr_file, "svr:%x", &svr_ver) > 0)
 313                 dpaa_svr_family = svr_ver & SVR_MASK;
 314         else
 315                 DPAA_PMD_ERR("Unable to read SoC device");
 316
 317         fclose(svr_file);
 318
 319         ret = snprintf(fw_version, fw_size, "SVR:%x-fman-v%x",
 320                        svr_ver, fman_ip_rev);
 321         ret += 1; /* add the size of '\0' */
 322
 323         if (fw_size < (uint32_t)ret)
 324                 return ret;
 325         else
 326                 return 0;
 327 }
 328
 329 static void dpaa_eth_dev_info(struct rte_eth_dev *dev,
 330                               struct rte_eth_dev_info *dev_info)
 331 {
 332         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 333
 334         PMD_INIT_FUNC_TRACE();
 335
 336         dev_info->max_rx_queues = dpaa_intf->nb_rx_queues;
 337         dev_info->max_tx_queues = dpaa_intf->nb_tx_queues;
 338         dev_info->max_rx_pktlen = DPAA_MAX_RX_PKT_LEN;
 339         dev_info->max_mac_addrs = DPAA_MAX_MAC_FILTER;
 340         dev_info->max_hash_mac_addrs = 0;
 341         dev_info->max_vfs = 0;
 342         dev_info->max_vmdq_pools = ETH_16_POOLS;
 343         dev_info->flow_type_rss_offloads = DPAA_RSS_OFFLOAD_ALL;
 344
 345         if (dpaa_intf->fif->mac_type == fman_mac_1g)
 346                 dev_info->speed_capa = ETH_LINK_SPEED_1G;
 347         else if (dpaa_intf->fif->mac_type == fman_mac_10g)
 348                 dev_info->speed_capa = (ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G);
 349         else
 350                 DPAA_PMD_ERR("invalid link_speed: %s, %d",
 351                              dpaa_intf->name, dpaa_intf->fif->mac_type);
 352
 353         dev_info->rx_offload_capa = dev_rx_offloads_sup |
 354                                         dev_rx_offloads_nodis;
 355         dev_info->tx_offload_capa = dev_tx_offloads_sup |
 356                                         dev_tx_offloads_nodis;
 357         dev_info->default_rxportconf.burst_size = DPAA_DEF_RX_BURST_SIZE;
 358         dev_info->default_txportconf.burst_size = DPAA_DEF_TX_BURST_SIZE;
 359 }
 360
 361 static int dpaa_eth_link_update(struct rte_eth_dev *dev,
 362                                 int wait_to_complete __rte_unused)
 363 {
 364         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 365         struct rte_eth_link *link = &dev->data->dev_link;
 366
 367         PMD_INIT_FUNC_TRACE();
 368
 369         if (dpaa_intf->fif->mac_type == fman_mac_1g)
 370                 link->link_speed = ETH_SPEED_NUM_1G;
 371         else if (dpaa_intf->fif->mac_type == fman_mac_10g)
 372                 link->link_speed = ETH_SPEED_NUM_10G;
 373         else
 374                 DPAA_PMD_ERR("invalid link_speed: %s, %d",
 375                              dpaa_intf->name, dpaa_intf->fif->mac_type);
 376
 377         link->link_status = dpaa_intf->valid;
 378         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 379         link->link_autoneg = ETH_LINK_AUTONEG;
 380         return 0;
 381 }
 382
 383 static int dpaa_eth_stats_get(struct rte_eth_dev *dev,
 384                                struct rte_eth_stats *stats)
 385 {
 386         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 387
 388         PMD_INIT_FUNC_TRACE();
 389
 390         fman_if_stats_get(dpaa_intf->fif, stats);
 391         return 0;
 392 }
 393
 394 static void dpaa_eth_stats_reset(struct rte_eth_dev *dev)
 395 {
 396         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 397
 398         PMD_INIT_FUNC_TRACE();
 399
 400         fman_if_stats_reset(dpaa_intf->fif);
 401 }
 402
 403 static int
 404 dpaa_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
 405                     unsigned int n)
 406 {
 407         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 408         unsigned int i = 0, num = RTE_DIM(dpaa_xstats_strings);
 409         uint64_t values[sizeof(struct dpaa_if_stats) / 8];
 410
 411         if (n < num)
 412                 return num;
 413
 414         if (xstats == NULL)
 415                 return 0;
 416
 417         fman_if_stats_get_all(dpaa_intf->fif, values,
 418                               sizeof(struct dpaa_if_stats) / 8);
 419
 420         for (i = 0; i < num; i++) {
 421                 xstats[i].id = i;
 422                 xstats[i].value = values[dpaa_xstats_strings[i].offset / 8];
 423         }
 424         return i;
 425 }
 426
 427 static int
 428 dpaa_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 429                       struct rte_eth_xstat_name *xstats_names,
 430                       unsigned int limit)
 431 {
 432         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 433
 434         if (limit < stat_cnt)
 435                 return stat_cnt;
 436
 437         if (xstats_names != NULL)
 438                 for (i = 0; i < stat_cnt; i++)
 439                         snprintf(xstats_names[i].name,
 440                                  sizeof(xstats_names[i].name),
 441                                  "%s",
 442                                  dpaa_xstats_strings[i].name);
 443
 444         return stat_cnt;
 445 }
 446
 447 static int
 448 dpaa_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 449                       uint64_t *values, unsigned int n)
 450 {
 451         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 452         uint64_t values_copy[sizeof(struct dpaa_if_stats) / 8];
 453
 454         if (!ids) {
 455                 struct dpaa_if *dpaa_intf = dev->data->dev_private;
 456
 457                 if (n < stat_cnt)
 458                         return stat_cnt;
 459
 460                 if (!values)
 461                         return 0;
 462
 463                 fman_if_stats_get_all(dpaa_intf->fif, values_copy,
 464                                       sizeof(struct dpaa_if_stats) / 8);
 465
 466                 for (i = 0; i < stat_cnt; i++)
 467                         values[i] =
 468                                 values_copy[dpaa_xstats_strings[i].offset / 8];
 469
 470                 return stat_cnt;
 471         }
 472
 473         dpaa_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
 474
 475         for (i = 0; i < n; i++) {
 476                 if (ids[i] >= stat_cnt) {
 477                         DPAA_PMD_ERR("id value isn't valid");
 478                         return -1;
 479                 }
 480                 values[i] = values_copy[ids[i]];
 481         }
 482         return n;
 483 }
 484
 485 static int
 486 dpaa_xstats_get_names_by_id(
 487         struct rte_eth_dev *dev,
 488         struct rte_eth_xstat_name *xstats_names,
 489         const uint64_t *ids,
 490         unsigned int limit)
 491 {
 492         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 493         struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
 494
 495         if (!ids)
 496                 return dpaa_xstats_get_names(dev, xstats_names, limit);
 497
 498         dpaa_xstats_get_names(dev, xstats_names_copy, limit);
 499
 500         for (i = 0; i < limit; i++) {
 501                 if (ids[i] >= stat_cnt) {
 502                         DPAA_PMD_ERR("id value isn't valid");
 503                         return -1;
 504                 }
 505                 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
 506         }
 507         return limit;
 508 }
 509
 510 static void dpaa_eth_promiscuous_enable(struct rte_eth_dev *dev)
 511 {
 512         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 513
 514         PMD_INIT_FUNC_TRACE();
 515
 516         fman_if_promiscuous_enable(dpaa_intf->fif);
 517 }
 518
 519 static void dpaa_eth_promiscuous_disable(struct rte_eth_dev *dev)
 520 {
 521         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 522
 523         PMD_INIT_FUNC_TRACE();
 524
 525         fman_if_promiscuous_disable(dpaa_intf->fif);
 526 }
 527
 528 static void dpaa_eth_multicast_enable(struct rte_eth_dev *dev)
 529 {
 530         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 531
 532         PMD_INIT_FUNC_TRACE();
 533
 534         fman_if_set_mcast_filter_table(dpaa_intf->fif);
 535 }
 536
 537 static void dpaa_eth_multicast_disable(struct rte_eth_dev *dev)
 538 {
 539         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 540
 541         PMD_INIT_FUNC_TRACE();
 542
 543         fman_if_reset_mcast_filter_table(dpaa_intf->fif);
 544 }
 545
 546 static
 547 int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 548                             uint16_t nb_desc,
 549                             unsigned int socket_id __rte_unused,
 550                             const struct rte_eth_rxconf *rx_conf __rte_unused,
 551                             struct rte_mempool *mp)
 552 {
 553         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 554         struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_idx];
 555         struct qm_mcc_initfq opts = {0};
 556         u32 flags = 0;
 557         int ret;
 558         u32 buffsz = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
 559
 560         PMD_INIT_FUNC_TRACE();
 561
 562         if (queue_idx >= dev->data->nb_rx_queues) {
 563                 rte_errno = EOVERFLOW;
 564                 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
 565                       (void *)dev, queue_idx, dev->data->nb_rx_queues);
 566                 return -rte_errno;
 567         }
 568
 569         DPAA_PMD_INFO("Rx queue setup for queue index: %d fq_id (0x%x)",
 570                         queue_idx, rxq->fqid);
 571
 572         /* Max packet can fit in single buffer */
 573         if (dev->data->dev_conf.rxmode.max_rx_pkt_len <= buffsz) {
 574                 ;
 575         } else if (dev->data->dev_conf.rxmode.offloads &
 576                         DEV_RX_OFFLOAD_SCATTER) {
 577                 if (dev->data->dev_conf.rxmode.max_rx_pkt_len >
 578                         buffsz * DPAA_SGT_MAX_ENTRIES) {
 579                         DPAA_PMD_ERR("max RxPkt size %d too big to fit "
 580                                 "MaxSGlist %d",
 581                                 dev->data->dev_conf.rxmode.max_rx_pkt_len,
 582                                 buffsz * DPAA_SGT_MAX_ENTRIES);
 583                         rte_errno = EOVERFLOW;
 584                         return -rte_errno;
 585                 }
 586         } else {
 587                 DPAA_PMD_WARN("The requested maximum Rx packet size (%u) is"
 588                      " larger than a single mbuf (%u) and scattered"
 589                      " mode has not been requested",
 590                      dev->data->dev_conf.rxmode.max_rx_pkt_len,
 591                      buffsz - RTE_PKTMBUF_HEADROOM);
 592         }
 593
 594         if (!dpaa_intf->bp_info || dpaa_intf->bp_info->mp != mp) {
 595                 struct fman_if_ic_params icp;
 596                 uint32_t fd_offset;
 597                 uint32_t bp_size;
 598
 599                 if (!mp->pool_data) {
 600                         DPAA_PMD_ERR("Not an offloaded buffer pool!");
 601                         return -1;
 602                 }
 603                 dpaa_intf->bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp);
 604
 605                 memset(&icp, 0, sizeof(icp));
 606                 /* set ICEOF for to the default value , which is 0*/
 607                 icp.iciof = DEFAULT_ICIOF;
 608                 icp.iceof = DEFAULT_RX_ICEOF;
 609                 icp.icsz = DEFAULT_ICSZ;
 610                 fman_if_set_ic_params(dpaa_intf->fif, &icp);
 611
 612                 fd_offset = RTE_PKTMBUF_HEADROOM + DPAA_HW_BUF_RESERVE;
 613                 fman_if_set_fdoff(dpaa_intf->fif, fd_offset);
 614
 615                 /* Buffer pool size should be equal to Dataroom Size*/
 616                 bp_size = rte_pktmbuf_data_room_size(mp);
 617                 fman_if_set_bp(dpaa_intf->fif, mp->size,
 618                                dpaa_intf->bp_info->bpid, bp_size);
 619                 dpaa_intf->valid = 1;
 620                 DPAA_PMD_DEBUG("if:%s fd_offset = %d offset = %d",
 621                                 dpaa_intf->name, fd_offset,
 622                                 fman_if_get_fdoff(dpaa_intf->fif));
 623         }
 624         DPAA_PMD_DEBUG("if:%s sg_on = %d, max_frm =%d", dpaa_intf->name,
 625                 fman_if_get_sg_enable(dpaa_intf->fif),
 626                 dev->data->dev_conf.rxmode.max_rx_pkt_len);
 627         /* checking if push mode only, no error check for now */
 628         if (dpaa_push_mode_max_queue > dpaa_push_queue_idx) {
 629                 dpaa_push_queue_idx++;
 630                 opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
 631                 opts.fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK |
 632                                    QM_FQCTRL_CTXASTASHING |
 633                                    QM_FQCTRL_PREFERINCACHE;
 634                 opts.fqd.context_a.stashing.exclusive = 0;
 635                 /* In muticore scenario stashing becomes a bottleneck on LS1046.
 636                  * So do not enable stashing in this case
 637                  */
 638                 if (dpaa_svr_family != SVR_LS1046A_FAMILY)
 639                         opts.fqd.context_a.stashing.annotation_cl =
 640                                                 DPAA_IF_RX_ANNOTATION_STASH;
 641                 opts.fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
 642                 opts.fqd.context_a.stashing.context_cl =
 643                                                 DPAA_IF_RX_CONTEXT_STASH;
 644
 645                 /*Create a channel and associate given queue with the channel*/
 646                 qman_alloc_pool_range((u32 *)&rxq->ch_id, 1, 1, 0);
 647                 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
 648                 opts.fqd.dest.channel = rxq->ch_id;
 649                 opts.fqd.dest.wq = DPAA_IF_RX_PRIORITY;
 650                 flags = QMAN_INITFQ_FLAG_SCHED;
 651
 652                 /* Configure tail drop */
 653                 if (dpaa_intf->cgr_rx) {
 654                         opts.we_mask |= QM_INITFQ_WE_CGID;
 655                         opts.fqd.cgid = dpaa_intf->cgr_rx[queue_idx].cgrid;
 656                         opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
 657                 }
 658                 ret = qman_init_fq(rxq, flags, &opts);
 659                 if (ret) {
 660                         DPAA_PMD_ERR("Channel/Q association failed. fqid 0x%x "
 661                                 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
 662                         return ret;
 663                 }
 664                 rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb;
 665                 rxq->cb.dqrr_prepare = dpaa_rx_cb_prepare;
 666                 rxq->is_static = true;
 667         }
 668         dev->data->rx_queues[queue_idx] = rxq;
 669
 670         /* configure the CGR size as per the desc size */
 671         if (dpaa_intf->cgr_rx) {
 672                 struct qm_mcc_initcgr cgr_opts = {0};
 673
 674                 /* Enable tail drop with cgr on this queue */
 675                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, nb_desc, 0);
 676                 ret = qman_modify_cgr(dpaa_intf->cgr_rx, 0, &cgr_opts);
 677                 if (ret) {
 678                         DPAA_PMD_WARN(
 679                                 "rx taildrop modify fail on fqid %d (ret=%d)",
 680                                 rxq->fqid, ret);
 681                 }
 682         }
 683
 684         return 0;
 685 }
 686
 687 int
 688 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev,
 689                 int eth_rx_queue_id,
 690                 u16 ch_id,
 691                 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
 692 {
 693         int ret;
 694         u32 flags = 0;
 695         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 696         struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
 697         struct qm_mcc_initfq opts = {0};
 698
 699         if (dpaa_push_mode_max_queue)
 700                 DPAA_PMD_WARN("PUSH mode q and EVENTDEV are not compatible\n"
 701                               "PUSH mode already enabled for first %d queues.\n"
 702                               "To disable set DPAA_PUSH_QUEUES_NUMBER to 0\n",
 703                               dpaa_push_mode_max_queue);
 704
 705         dpaa_poll_queue_default_config(&opts);
 706
 707         switch (queue_conf->ev.sched_type) {
 708         case RTE_SCHED_TYPE_ATOMIC:
 709                 opts.fqd.fq_ctrl |= QM_FQCTRL_HOLDACTIVE;
 710                 /* Reset FQCTRL_AVOIDBLOCK bit as it is unnecessary
 711                  * configuration with HOLD_ACTIVE setting
 712                  */
 713                 opts.fqd.fq_ctrl &= (~QM_FQCTRL_AVOIDBLOCK);
 714                 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_atomic;
 715                 break;
 716         case RTE_SCHED_TYPE_ORDERED:
 717                 DPAA_PMD_ERR("Ordered queue schedule type is not supported\n");
 718                 return -1;
 719         default:
 720                 opts.fqd.fq_ctrl |= QM_FQCTRL_AVOIDBLOCK;
 721                 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_parallel;
 722                 break;
 723         }
 724
 725         opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
 726         opts.fqd.dest.channel = ch_id;
 727         opts.fqd.dest.wq = queue_conf->ev.priority;
 728
 729         if (dpaa_intf->cgr_rx) {
 730                 opts.we_mask |= QM_INITFQ_WE_CGID;
 731                 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
 732                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
 733         }
 734
 735         flags = QMAN_INITFQ_FLAG_SCHED;
 736
 737         ret = qman_init_fq(rxq, flags, &opts);
 738         if (ret) {
 739                 DPAA_PMD_ERR("Ev-Channel/Q association failed. fqid 0x%x "
 740                                 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
 741                 return ret;
 742         }
 743
 744         /* copy configuration which needs to be filled during dequeue */
 745         memcpy(&rxq->ev, &queue_conf->ev, sizeof(struct rte_event));
 746         dev->data->rx_queues[eth_rx_queue_id] = rxq;
 747
 748         return ret;
 749 }
 750
 751 int
 752 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev,
 753                 int eth_rx_queue_id)
 754 {
 755         struct qm_mcc_initfq opts;
 756         int ret;
 757         u32 flags = 0;
 758         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 759         struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
 760
 761         dpaa_poll_queue_default_config(&opts);
 762
 763         if (dpaa_intf->cgr_rx) {
 764                 opts.we_mask |= QM_INITFQ_WE_CGID;
 765                 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
 766                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
 767         }
 768
 769         ret = qman_init_fq(rxq, flags, &opts);
 770         if (ret) {
 771                 DPAA_PMD_ERR("init rx fqid %d failed with ret: %d",
 772                              rxq->fqid, ret);
 773         }
 774
 775         rxq->cb.dqrr_dpdk_cb = NULL;
 776         dev->data->rx_queues[eth_rx_queue_id] = NULL;
 777
 778         return 0;
 779 }
 780
 781 static
 782 void dpaa_eth_rx_queue_release(void *rxq __rte_unused)
 783 {
 784         PMD_INIT_FUNC_TRACE();
 785 }
 786
 787 static
 788 int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 789                             uint16_t nb_desc __rte_unused,
 790                 unsigned int socket_id __rte_unused,
 791                 const struct rte_eth_txconf *tx_conf __rte_unused)
 792 {
 793         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 794
 795         PMD_INIT_FUNC_TRACE();
 796
 797         if (queue_idx >= dev->data->nb_tx_queues) {
 798                 rte_errno = EOVERFLOW;
 799                 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
 800                       (void *)dev, queue_idx, dev->data->nb_tx_queues);
 801                 return -rte_errno;
 802         }
 803
 804         DPAA_PMD_INFO("Tx queue setup for queue index: %d fq_id (0x%x)",
 805                         queue_idx, dpaa_intf->tx_queues[queue_idx].fqid);
 806         dev->data->tx_queues[queue_idx] = &dpaa_intf->tx_queues[queue_idx];
 807         return 0;
 808 }
 809
 810 static void dpaa_eth_tx_queue_release(void *txq __rte_unused)
 811 {
 812         PMD_INIT_FUNC_TRACE();
 813 }
 814
 815 static uint32_t
 816 dpaa_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 817 {
 818         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 819         struct qman_fq *rxq = &dpaa_intf->rx_queues[rx_queue_id];
 820         u32 frm_cnt = 0;
 821
 822         PMD_INIT_FUNC_TRACE();
 823
 824         if (qman_query_fq_frm_cnt(rxq, &frm_cnt) == 0) {
 825                 RTE_LOG(DEBUG, PMD, "RX frame count for q(%d) is %u\n",
 826                         rx_queue_id, frm_cnt);
 827         }
 828         return frm_cnt;
 829 }
 830
 831 static int dpaa_link_down(struct rte_eth_dev *dev)
 832 {
 833         PMD_INIT_FUNC_TRACE();
 834
 835         dpaa_eth_dev_stop(dev);
 836         return 0;
 837 }
 838
 839 static int dpaa_link_up(struct rte_eth_dev *dev)
 840 {
 841         PMD_INIT_FUNC_TRACE();
 842
 843         dpaa_eth_dev_start(dev);
 844         return 0;
 845 }
 846
 847 static int
 848 dpaa_flow_ctrl_set(struct rte_eth_dev *dev,
 849                    struct rte_eth_fc_conf *fc_conf)
 850 {
 851         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 852         struct rte_eth_fc_conf *net_fc;
 853
 854         PMD_INIT_FUNC_TRACE();
 855
 856         if (!(dpaa_intf->fc_conf)) {
 857                 dpaa_intf->fc_conf = rte_zmalloc(NULL,
 858                         sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
 859                 if (!dpaa_intf->fc_conf) {
 860                         DPAA_PMD_ERR("unable to save flow control info");
 861                         return -ENOMEM;
 862                 }
 863         }
 864         net_fc = dpaa_intf->fc_conf;
 865
 866         if (fc_conf->high_water < fc_conf->low_water) {
 867                 DPAA_PMD_ERR("Incorrect Flow Control Configuration");
 868                 return -EINVAL;
 869         }
 870
 871         if (fc_conf->mode == RTE_FC_NONE) {
 872                 return 0;
 873         } else if (fc_conf->mode == RTE_FC_TX_PAUSE ||
 874                  fc_conf->mode == RTE_FC_FULL) {
 875                 fman_if_set_fc_threshold(dpaa_intf->fif, fc_conf->high_water,
 876                                          fc_conf->low_water,
 877                                 dpaa_intf->bp_info->bpid);
 878                 if (fc_conf->pause_time)
 879                         fman_if_set_fc_quanta(dpaa_intf->fif,
 880                                               fc_conf->pause_time);
 881         }
 882
 883         /* Save the information in dpaa device */
 884         net_fc->pause_time = fc_conf->pause_time;
 885         net_fc->high_water = fc_conf->high_water;
 886         net_fc->low_water = fc_conf->low_water;
 887         net_fc->send_xon = fc_conf->send_xon;
 888         net_fc->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
 889         net_fc->mode = fc_conf->mode;
 890         net_fc->autoneg = fc_conf->autoneg;
 891
 892         return 0;
 893 }
 894
 895 static int
 896 dpaa_flow_ctrl_get(struct rte_eth_dev *dev,
 897                    struct rte_eth_fc_conf *fc_conf)
 898 {
 899         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 900         struct rte_eth_fc_conf *net_fc = dpaa_intf->fc_conf;
 901         int ret;
 902
 903         PMD_INIT_FUNC_TRACE();
 904
 905         if (net_fc) {
 906                 fc_conf->pause_time = net_fc->pause_time;
 907                 fc_conf->high_water = net_fc->high_water;
 908                 fc_conf->low_water = net_fc->low_water;
 909                 fc_conf->send_xon = net_fc->send_xon;
 910                 fc_conf->mac_ctrl_frame_fwd = net_fc->mac_ctrl_frame_fwd;
 911                 fc_conf->mode = net_fc->mode;
 912                 fc_conf->autoneg = net_fc->autoneg;
 913                 return 0;
 914         }
 915         ret = fman_if_get_fc_threshold(dpaa_intf->fif);
 916         if (ret) {
 917                 fc_conf->mode = RTE_FC_TX_PAUSE;
 918                 fc_conf->pause_time = fman_if_get_fc_quanta(dpaa_intf->fif);
 919         } else {
 920                 fc_conf->mode = RTE_FC_NONE;
 921         }
 922
 923         return 0;
 924 }
 925
 926 static int
 927 dpaa_dev_add_mac_addr(struct rte_eth_dev *dev,
 928                              struct ether_addr *addr,
 929                              uint32_t index,
 930                              __rte_unused uint32_t pool)
 931 {
 932         int ret;
 933         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 934
 935         PMD_INIT_FUNC_TRACE();
 936
 937         ret = fman_if_add_mac_addr(dpaa_intf->fif, addr->addr_bytes, index);
 938
 939         if (ret)
 940                 RTE_LOG(ERR, PMD, "error: Adding the MAC ADDR failed:"
 941                         " err = %d", ret);
 942         return 0;
 943 }
 944
 945 static void
 946 dpaa_dev_remove_mac_addr(struct rte_eth_dev *dev,
 947                           uint32_t index)
 948 {
 949         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 950
 951         PMD_INIT_FUNC_TRACE();
 952
 953         fman_if_clear_mac_addr(dpaa_intf->fif, index);
 954 }
 955
 956 static int
 957 dpaa_dev_set_mac_addr(struct rte_eth_dev *dev,
 958                        struct ether_addr *addr)
 959 {
 960         int ret;
 961         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 962
 963         PMD_INIT_FUNC_TRACE();
 964
 965         ret = fman_if_add_mac_addr(dpaa_intf->fif, addr->addr_bytes, 0);
 966         if (ret)
 967                 RTE_LOG(ERR, PMD, "error: Setting the MAC ADDR failed %d", ret);
 968
 969         return ret;
 970 }
 971
 972 static struct eth_dev_ops dpaa_devops = {
 973         .dev_configure            = dpaa_eth_dev_configure,
 974         .dev_start                = dpaa_eth_dev_start,
 975         .dev_stop                 = dpaa_eth_dev_stop,
 976         .dev_close                = dpaa_eth_dev_close,
 977         .dev_infos_get            = dpaa_eth_dev_info,
 978         .dev_supported_ptypes_get = dpaa_supported_ptypes_get,
 979
 980         .rx_queue_setup           = dpaa_eth_rx_queue_setup,
 981         .tx_queue_setup           = dpaa_eth_tx_queue_setup,
 982         .rx_queue_release         = dpaa_eth_rx_queue_release,
 983         .tx_queue_release         = dpaa_eth_tx_queue_release,
 984         .rx_queue_count           = dpaa_dev_rx_queue_count,
 985
 986         .flow_ctrl_get            = dpaa_flow_ctrl_get,
 987         .flow_ctrl_set            = dpaa_flow_ctrl_set,
 988
 989         .link_update              = dpaa_eth_link_update,
 990         .stats_get                = dpaa_eth_stats_get,
 991         .xstats_get               = dpaa_dev_xstats_get,
 992         .xstats_get_by_id         = dpaa_xstats_get_by_id,
 993         .xstats_get_names_by_id   = dpaa_xstats_get_names_by_id,
 994         .xstats_get_names         = dpaa_xstats_get_names,
 995         .xstats_reset             = dpaa_eth_stats_reset,
 996         .stats_reset              = dpaa_eth_stats_reset,
 997         .promiscuous_enable       = dpaa_eth_promiscuous_enable,
 998         .promiscuous_disable      = dpaa_eth_promiscuous_disable,
 999         .allmulticast_enable      = dpaa_eth_multicast_enable,
1000         .allmulticast_disable     = dpaa_eth_multicast_disable,
1001         .mtu_set                  = dpaa_mtu_set,
1002         .dev_set_link_down        = dpaa_link_down,
1003         .dev_set_link_up          = dpaa_link_up,
1004         .mac_addr_add             = dpaa_dev_add_mac_addr,
1005         .mac_addr_remove          = dpaa_dev_remove_mac_addr,
1006         .mac_addr_set             = dpaa_dev_set_mac_addr,
1007
1008         .fw_version_get           = dpaa_fw_version_get,
1009 };
1010
1011 static bool
1012 is_device_supported(struct rte_eth_dev *dev, struct rte_dpaa_driver *drv)
1013 {
1014         if (strcmp(dev->device->driver->name,
1015                    drv->driver.name))
1016                 return false;
1017
1018         return true;
1019 }
1020
1021 static bool
1022 is_dpaa_supported(struct rte_eth_dev *dev)
1023 {
1024         return is_device_supported(dev, &rte_dpaa_pmd);
1025 }
1026
1027 int
1028 rte_pmd_dpaa_set_tx_loopback(uint8_t port, uint8_t on)
1029 {
1030         struct rte_eth_dev *dev;
1031         struct dpaa_if *dpaa_intf;
1032
1033         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
1034
1035         dev = &rte_eth_devices[port];
1036
1037         if (!is_dpaa_supported(dev))
1038                 return -ENOTSUP;
1039
1040         dpaa_intf = dev->data->dev_private;
1041
1042         if (on)
1043                 fman_if_loopback_enable(dpaa_intf->fif);
1044         else
1045                 fman_if_loopback_disable(dpaa_intf->fif);
1046
1047         return 0;
1048 }
1049
1050 static int dpaa_fc_set_default(struct dpaa_if *dpaa_intf)
1051 {
1052         struct rte_eth_fc_conf *fc_conf;
1053         int ret;
1054
1055         PMD_INIT_FUNC_TRACE();
1056
1057         if (!(dpaa_intf->fc_conf)) {
1058                 dpaa_intf->fc_conf = rte_zmalloc(NULL,
1059                         sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
1060                 if (!dpaa_intf->fc_conf) {
1061                         DPAA_PMD_ERR("unable to save flow control info");
1062                         return -ENOMEM;
1063                 }
1064         }
1065         fc_conf = dpaa_intf->fc_conf;
1066         ret = fman_if_get_fc_threshold(dpaa_intf->fif);
1067         if (ret) {
1068                 fc_conf->mode = RTE_FC_TX_PAUSE;
1069                 fc_conf->pause_time = fman_if_get_fc_quanta(dpaa_intf->fif);
1070         } else {
1071                 fc_conf->mode = RTE_FC_NONE;
1072         }
1073
1074         return 0;
1075 }
1076
1077 /* Initialise an Rx FQ */
1078 static int dpaa_rx_queue_init(struct qman_fq *fq, struct qman_cgr *cgr_rx,
1079                               uint32_t fqid)
1080 {
1081         struct qm_mcc_initfq opts = {0};
1082         int ret;
1083         u32 flags = QMAN_FQ_FLAG_NO_ENQUEUE;
1084         struct qm_mcc_initcgr cgr_opts = {
1085                 .we_mask = QM_CGR_WE_CS_THRES |
1086                                 QM_CGR_WE_CSTD_EN |
1087                                 QM_CGR_WE_MODE,
1088                 .cgr = {
1089                         .cstd_en = QM_CGR_EN,
1090                         .mode = QMAN_CGR_MODE_FRAME
1091                 }
1092         };
1093
1094         PMD_INIT_FUNC_TRACE();
1095
1096         if (fqid) {
1097                 ret = qman_reserve_fqid(fqid);
1098                 if (ret) {
1099                         DPAA_PMD_ERR("reserve rx fqid 0x%x failed with ret: %d",
1100                                      fqid, ret);
1101                         return -EINVAL;
1102                 }
1103         } else {
1104                 flags |= QMAN_FQ_FLAG_DYNAMIC_FQID;
1105         }
1106         DPAA_PMD_DEBUG("creating rx fq %p, fqid 0x%x", fq, fqid);
1107         ret = qman_create_fq(fqid, flags, fq);
1108         if (ret) {
1109                 DPAA_PMD_ERR("create rx fqid 0x%x failed with ret: %d",
1110                         fqid, ret);
1111                 return ret;
1112         }
1113         fq->is_static = false;
1114
1115         dpaa_poll_queue_default_config(&opts);
1116
1117         if (cgr_rx) {
1118                 /* Enable tail drop with cgr on this queue */
1119                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, td_threshold, 0);
1120                 cgr_rx->cb = NULL;
1121                 ret = qman_create_cgr(cgr_rx, QMAN_CGR_FLAG_USE_INIT,
1122                                       &cgr_opts);
1123                 if (ret) {
1124                         DPAA_PMD_WARN(
1125                                 "rx taildrop init fail on rx fqid 0x%x(ret=%d)",
1126                                 fq->fqid, ret);
1127                         goto without_cgr;
1128                 }
1129                 opts.we_mask |= QM_INITFQ_WE_CGID;
1130                 opts.fqd.cgid = cgr_rx->cgrid;
1131                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1132         }
1133 without_cgr:
1134         ret = qman_init_fq(fq, 0, &opts);
1135         if (ret)
1136                 DPAA_PMD_ERR("init rx fqid 0x%x failed with ret:%d", fqid, ret);
1137         return ret;
1138 }
1139
1140 /* Initialise a Tx FQ */
1141 static int dpaa_tx_queue_init(struct qman_fq *fq,
1142                               struct fman_if *fman_intf)
1143 {
1144         struct qm_mcc_initfq opts = {0};
1145         int ret;
1146
1147         PMD_INIT_FUNC_TRACE();
1148
1149         ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID |
1150                              QMAN_FQ_FLAG_TO_DCPORTAL, fq);
1151         if (ret) {
1152                 DPAA_PMD_ERR("create tx fq failed with ret: %d", ret);
1153                 return ret;
1154         }
1155         opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL |
1156                        QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA;
1157         opts.fqd.dest.channel = fman_intf->tx_channel_id;
1158         opts.fqd.dest.wq = DPAA_IF_TX_PRIORITY;
1159         opts.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE;
1160         opts.fqd.context_b = 0;
1161         /* no tx-confirmation */
1162         opts.fqd.context_a.hi = 0x80000000 | fman_dealloc_bufs_mask_hi;
1163         opts.fqd.context_a.lo = 0 | fman_dealloc_bufs_mask_lo;
1164         DPAA_PMD_DEBUG("init tx fq %p, fqid 0x%x", fq, fq->fqid);
1165         ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts);
1166         if (ret)
1167                 DPAA_PMD_ERR("init tx fqid 0x%x failed %d", fq->fqid, ret);
1168         return ret;
1169 }
1170
1171 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1172 /* Initialise a DEBUG FQ ([rt]x_error, rx_default). */
1173 static int dpaa_debug_queue_init(struct qman_fq *fq, uint32_t fqid)
1174 {
1175         struct qm_mcc_initfq opts = {0};
1176         int ret;
1177
1178         PMD_INIT_FUNC_TRACE();
1179
1180         ret = qman_reserve_fqid(fqid);
1181         if (ret) {
1182                 DPAA_PMD_ERR("Reserve debug fqid %d failed with ret: %d",
1183                         fqid, ret);
1184                 return -EINVAL;
1185         }
1186         /* "map" this Rx FQ to one of the interfaces Tx FQID */
1187         DPAA_PMD_DEBUG("Creating debug fq %p, fqid %d", fq, fqid);
1188         ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq);
1189         if (ret) {
1190                 DPAA_PMD_ERR("create debug fqid %d failed with ret: %d",
1191                         fqid, ret);
1192                 return ret;
1193         }
1194         opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL;
1195         opts.fqd.dest.wq = DPAA_IF_DEBUG_PRIORITY;
1196         ret = qman_init_fq(fq, 0, &opts);
1197         if (ret)
1198                 DPAA_PMD_ERR("init debug fqid %d failed with ret: %d",
1199                             fqid, ret);
1200         return ret;
1201 }
1202 #endif
1203
1204 /* Initialise a network interface */
1205 static int
1206 dpaa_dev_init(struct rte_eth_dev *eth_dev)
1207 {
1208         int num_cores, num_rx_fqs, fqid;
1209         int loop, ret = 0;
1210         int dev_id;
1211         struct rte_dpaa_device *dpaa_device;
1212         struct dpaa_if *dpaa_intf;
1213         struct fm_eth_port_cfg *cfg;
1214         struct fman_if *fman_intf;
1215         struct fman_if_bpool *bp, *tmp_bp;
1216         uint32_t cgrid[DPAA_MAX_NUM_PCD_QUEUES];
1217
1218         PMD_INIT_FUNC_TRACE();
1219
1220         /* For secondary processes, the primary has done all the work */
1221         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1222                 return 0;
1223
1224         dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1225         dev_id = dpaa_device->id.dev_id;
1226         dpaa_intf = eth_dev->data->dev_private;
1227         cfg = &dpaa_netcfg->port_cfg[dev_id];
1228         fman_intf = cfg->fman_if;
1229
1230         dpaa_intf->name = dpaa_device->name;
1231
1232         /* save fman_if & cfg in the interface struture */
1233         dpaa_intf->fif = fman_intf;
1234         dpaa_intf->ifid = dev_id;
1235         dpaa_intf->cfg = cfg;
1236
1237         /* Initialize Rx FQ's */
1238         if (default_q) {
1239                 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES;
1240         } else {
1241                 if (getenv("DPAA_NUM_RX_QUEUES"))
1242                         num_rx_fqs = atoi(getenv("DPAA_NUM_RX_QUEUES"));
1243                 else
1244                         num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES;
1245         }
1246
1247
1248         /* Each device can not have more than DPAA_MAX_NUM_PCD_QUEUES RX
1249          * queues.
1250          */
1251         if (num_rx_fqs <= 0 || num_rx_fqs > DPAA_MAX_NUM_PCD_QUEUES) {
1252                 DPAA_PMD_ERR("Invalid number of RX queues\n");
1253                 return -EINVAL;
1254         }
1255
1256         dpaa_intf->rx_queues = rte_zmalloc(NULL,
1257                 sizeof(struct qman_fq) * num_rx_fqs, MAX_CACHELINE);
1258         if (!dpaa_intf->rx_queues) {
1259                 DPAA_PMD_ERR("Failed to alloc mem for RX queues\n");
1260                 return -ENOMEM;
1261         }
1262
1263         /* If congestion control is enabled globally*/
1264         if (td_threshold) {
1265                 dpaa_intf->cgr_rx = rte_zmalloc(NULL,
1266                         sizeof(struct qman_cgr) * num_rx_fqs, MAX_CACHELINE);
1267                 if (!dpaa_intf->cgr_rx) {
1268                         DPAA_PMD_ERR("Failed to alloc mem for cgr_rx\n");
1269                         ret = -ENOMEM;
1270                         goto free_rx;
1271                 }
1272
1273                 ret = qman_alloc_cgrid_range(&cgrid[0], num_rx_fqs, 1, 0);
1274                 if (ret != num_rx_fqs) {
1275                         DPAA_PMD_WARN("insufficient CGRIDs available");
1276                         ret = -EINVAL;
1277                         goto free_rx;
1278                 }
1279         } else {
1280                 dpaa_intf->cgr_rx = NULL;
1281         }
1282
1283         for (loop = 0; loop < num_rx_fqs; loop++) {
1284                 if (default_q)
1285                         fqid = cfg->rx_def;
1286                 else
1287                         fqid = DPAA_PCD_FQID_START + dpaa_intf->fif->mac_idx *
1288                                 DPAA_PCD_FQID_MULTIPLIER + loop;
1289
1290                 if (dpaa_intf->cgr_rx)
1291                         dpaa_intf->cgr_rx[loop].cgrid = cgrid[loop];
1292
1293                 ret = dpaa_rx_queue_init(&dpaa_intf->rx_queues[loop],
1294                         dpaa_intf->cgr_rx ? &dpaa_intf->cgr_rx[loop] : NULL,
1295                         fqid);
1296                 if (ret)
1297                         goto free_rx;
1298                 dpaa_intf->rx_queues[loop].dpaa_intf = dpaa_intf;
1299         }
1300         dpaa_intf->nb_rx_queues = num_rx_fqs;
1301
1302         /* Initialise Tx FQs.free_rx Have as many Tx FQ's as number of cores */
1303         num_cores = rte_lcore_count();
1304         dpaa_intf->tx_queues = rte_zmalloc(NULL, sizeof(struct qman_fq) *
1305                 num_cores, MAX_CACHELINE);
1306         if (!dpaa_intf->tx_queues) {
1307                 DPAA_PMD_ERR("Failed to alloc mem for TX queues\n");
1308                 ret = -ENOMEM;
1309                 goto free_rx;
1310         }
1311
1312         for (loop = 0; loop < num_cores; loop++) {
1313                 ret = dpaa_tx_queue_init(&dpaa_intf->tx_queues[loop],
1314                                          fman_intf);
1315                 if (ret)
1316                         goto free_tx;
1317                 dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf;
1318         }
1319         dpaa_intf->nb_tx_queues = num_cores;
1320
1321 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1322         dpaa_debug_queue_init(&dpaa_intf->debug_queues[
1323                 DPAA_DEBUG_FQ_RX_ERROR], fman_intf->fqid_rx_err);
1324         dpaa_intf->debug_queues[DPAA_DEBUG_FQ_RX_ERROR].dpaa_intf = dpaa_intf;
1325         dpaa_debug_queue_init(&dpaa_intf->debug_queues[
1326                 DPAA_DEBUG_FQ_TX_ERROR], fman_intf->fqid_tx_err);
1327         dpaa_intf->debug_queues[DPAA_DEBUG_FQ_TX_ERROR].dpaa_intf = dpaa_intf;
1328 #endif
1329
1330         DPAA_PMD_DEBUG("All frame queues created");
1331
1332         /* Get the initial configuration for flow control */
1333         dpaa_fc_set_default(dpaa_intf);
1334
1335         /* reset bpool list, initialize bpool dynamically */
1336         list_for_each_entry_safe(bp, tmp_bp, &cfg->fman_if->bpool_list, node) {
1337                 list_del(&bp->node);
1338                 free(bp);
1339         }
1340
1341         /* Populate ethdev structure */
1342         eth_dev->dev_ops = &dpaa_devops;
1343         eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
1344         eth_dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
1345
1346         /* Allocate memory for storing MAC addresses */
1347         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr",
1348                 ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER, 0);
1349         if (eth_dev->data->mac_addrs == NULL) {
1350                 DPAA_PMD_ERR("Failed to allocate %d bytes needed to "
1351                                                 "store MAC addresses",
1352                                 ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER);
1353                 ret = -ENOMEM;
1354                 goto free_tx;
1355         }
1356
1357         /* copy the primary mac address */
1358         ether_addr_copy(&fman_intf->mac_addr, &eth_dev->data->mac_addrs[0]);
1359
1360         RTE_LOG(INFO, PMD, "net: dpaa: %s: %02x:%02x:%02x:%02x:%02x:%02x\n",
1361                 dpaa_device->name,
1362                 fman_intf->mac_addr.addr_bytes[0],
1363                 fman_intf->mac_addr.addr_bytes[1],
1364                 fman_intf->mac_addr.addr_bytes[2],
1365                 fman_intf->mac_addr.addr_bytes[3],
1366                 fman_intf->mac_addr.addr_bytes[4],
1367                 fman_intf->mac_addr.addr_bytes[5]);
1368
1369         /* Disable RX mode */
1370         fman_if_discard_rx_errors(fman_intf);
1371         fman_if_disable_rx(fman_intf);
1372         /* Disable promiscuous mode */
1373         fman_if_promiscuous_disable(fman_intf);
1374         /* Disable multicast */
1375         fman_if_reset_mcast_filter_table(fman_intf);
1376         /* Reset interface statistics */
1377         fman_if_stats_reset(fman_intf);
1378         /* Disable SG by default */
1379         fman_if_set_sg(fman_intf, 0);
1380         fman_if_set_maxfrm(fman_intf, ETHER_MAX_LEN + VLAN_TAG_SIZE);
1381
1382         return 0;
1383
1384 free_tx:
1385         rte_free(dpaa_intf->tx_queues);
1386         dpaa_intf->tx_queues = NULL;
1387         dpaa_intf->nb_tx_queues = 0;
1388
1389 free_rx:
1390         rte_free(dpaa_intf->cgr_rx);
1391         rte_free(dpaa_intf->rx_queues);
1392         dpaa_intf->rx_queues = NULL;
1393         dpaa_intf->nb_rx_queues = 0;
1394         return ret;
1395 }
1396
1397 static int
1398 dpaa_dev_uninit(struct rte_eth_dev *dev)
1399 {
1400         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1401         int loop;
1402
1403         PMD_INIT_FUNC_TRACE();
1404
1405         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1406                 return -EPERM;
1407
1408         if (!dpaa_intf) {
1409                 DPAA_PMD_WARN("Already closed or not started");
1410                 return -1;
1411         }
1412
1413         dpaa_eth_dev_close(dev);
1414
1415         /* release configuration memory */
1416         if (dpaa_intf->fc_conf)
1417                 rte_free(dpaa_intf->fc_conf);
1418
1419         /* Release RX congestion Groups */
1420         if (dpaa_intf->cgr_rx) {
1421                 for (loop = 0; loop < dpaa_intf->nb_rx_queues; loop++)
1422                         qman_delete_cgr(&dpaa_intf->cgr_rx[loop]);
1423
1424                 qman_release_cgrid_range(dpaa_intf->cgr_rx[loop].cgrid,
1425                                          dpaa_intf->nb_rx_queues);
1426         }
1427
1428         rte_free(dpaa_intf->cgr_rx);
1429         dpaa_intf->cgr_rx = NULL;
1430
1431         rte_free(dpaa_intf->rx_queues);
1432         dpaa_intf->rx_queues = NULL;
1433
1434         rte_free(dpaa_intf->tx_queues);
1435         dpaa_intf->tx_queues = NULL;
1436
1437         /* free memory for storing MAC addresses */
1438         rte_free(dev->data->mac_addrs);
1439         dev->data->mac_addrs = NULL;
1440
1441         dev->dev_ops = NULL;
1442         dev->rx_pkt_burst = NULL;
1443         dev->tx_pkt_burst = NULL;
1444
1445         return 0;
1446 }
1447
1448 static int
1449 rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv __rte_unused,
1450                struct rte_dpaa_device *dpaa_dev)
1451 {
1452         int diag;
1453         int ret;
1454         struct rte_eth_dev *eth_dev;
1455
1456         PMD_INIT_FUNC_TRACE();
1457
1458         /* In case of secondary process, the device is already configured
1459          * and no further action is required, except portal initialization
1460          * and verifying secondary attachment to port name.
1461          */
1462         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1463                 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name);
1464                 if (!eth_dev)
1465                         return -ENOMEM;
1466                 eth_dev->device = &dpaa_dev->device;
1467                 eth_dev->dev_ops = &dpaa_devops;
1468                 rte_eth_dev_probing_finish(eth_dev);
1469                 return 0;
1470         }
1471
1472         if (!is_global_init) {
1473                 /* One time load of Qman/Bman drivers */
1474                 ret = qman_global_init();
1475                 if (ret) {
1476                         DPAA_PMD_ERR("QMAN initialization failed: %d",
1477                                      ret);
1478                         return ret;
1479                 }
1480                 ret = bman_global_init();
1481                 if (ret) {
1482                         DPAA_PMD_ERR("BMAN initialization failed: %d",
1483                                      ret);
1484                         return ret;
1485                 }
1486
1487                 if (access("/tmp/fmc.bin", F_OK) == -1) {
1488                         RTE_LOG(INFO, PMD,
1489                                 "* FMC not configured.Enabling default mode\n");
1490                         default_q = 1;
1491                 }
1492
1493                 /* disabling the default push mode for LS1043 */
1494                 if (dpaa_svr_family == SVR_LS1043A_FAMILY)
1495                         dpaa_push_mode_max_queue = 0;
1496
1497                 /* if push mode queues to be enabled. Currenly we are allowing
1498                  * only one queue per thread.
1499                  */
1500                 if (getenv("DPAA_PUSH_QUEUES_NUMBER")) {
1501                         dpaa_push_mode_max_queue =
1502                                         atoi(getenv("DPAA_PUSH_QUEUES_NUMBER"));
1503                         if (dpaa_push_mode_max_queue > DPAA_MAX_PUSH_MODE_QUEUE)
1504                             dpaa_push_mode_max_queue = DPAA_MAX_PUSH_MODE_QUEUE;
1505                 }
1506
1507                 is_global_init = 1;
1508         }
1509
1510         if (unlikely(!RTE_PER_LCORE(dpaa_io))) {
1511                 ret = rte_dpaa_portal_init((void *)1);
1512                 if (ret) {
1513                         DPAA_PMD_ERR("Unable to initialize portal");
1514                         return ret;
1515                 }
1516         }
1517
1518         eth_dev = rte_eth_dev_allocate(dpaa_dev->name);
1519         if (eth_dev == NULL)
1520                 return -ENOMEM;
1521
1522         eth_dev->data->dev_private = rte_zmalloc(
1523                                         "ethdev private structure",
1524                                         sizeof(struct dpaa_if),
1525                                         RTE_CACHE_LINE_SIZE);
1526         if (!eth_dev->data->dev_private) {
1527                 DPAA_PMD_ERR("Cannot allocate memzone for port data");
1528                 rte_eth_dev_release_port(eth_dev);
1529                 return -ENOMEM;
1530         }
1531
1532         eth_dev->device = &dpaa_dev->device;
1533         dpaa_dev->eth_dev = eth_dev;
1534
1535         /* Invoke PMD device initialization function */
1536         diag = dpaa_dev_init(eth_dev);
1537         if (diag == 0) {
1538                 rte_eth_dev_probing_finish(eth_dev);
1539                 return 0;
1540         }
1541
1542         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
1543                 rte_free(eth_dev->data->dev_private);
1544
1545         rte_eth_dev_release_port(eth_dev);
1546         return diag;
1547 }
1548
1549 static int
1550 rte_dpaa_remove(struct rte_dpaa_device *dpaa_dev)
1551 {
1552         struct rte_eth_dev *eth_dev;
1553
1554         PMD_INIT_FUNC_TRACE();
1555
1556         eth_dev = dpaa_dev->eth_dev;
1557         dpaa_dev_uninit(eth_dev);
1558
1559         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
1560                 rte_free(eth_dev->data->dev_private);
1561
1562         rte_eth_dev_release_port(eth_dev);
1563
1564         return 0;
1565 }
1566
1567 static struct rte_dpaa_driver rte_dpaa_pmd = {
1568         .drv_type = FSL_DPAA_ETH,
1569         .probe = rte_dpaa_probe,
1570         .remove = rte_dpaa_remove,
1571 };
1572
1573 RTE_PMD_REGISTER_DPAA(net_dpaa, rte_dpaa_pmd);