drivers/net/dpaa/dpaa_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  *   Copyright 2016 Freescale Semiconductor, Inc. All rights reserved.
   4  *   Copyright 2017-2019 NXP
   5  *
   6  */
   7 /* System headers */
   8 #include <stdio.h>
   9 #include <inttypes.h>
  10 #include <unistd.h>
  11 #include <limits.h>
  12 #include <sched.h>
  13 #include <signal.h>
  14 #include <pthread.h>
  15 #include <sys/types.h>
  16 #include <sys/syscall.h>
  17
  18 #include <rte_string_fns.h>
  19 #include <rte_byteorder.h>
  20 #include <rte_common.h>
  21 #include <rte_interrupts.h>
  22 #include <rte_log.h>
  23 #include <rte_debug.h>
  24 #include <rte_pci.h>
  25 #include <rte_atomic.h>
  26 #include <rte_branch_prediction.h>
  27 #include <rte_memory.h>
  28 #include <rte_tailq.h>
  29 #include <rte_eal.h>
  30 #include <rte_alarm.h>
  31 #include <rte_ether.h>
  32 #include <rte_ethdev_driver.h>
  33 #include <rte_malloc.h>
  34 #include <rte_ring.h>
  35
  36 #include <rte_dpaa_bus.h>
  37 #include <rte_dpaa_logs.h>
  38 #include <dpaa_mempool.h>
  39
  40 #include <dpaa_ethdev.h>
  41 #include <dpaa_rxtx.h>
  42 #include <rte_pmd_dpaa.h>
  43
  44 #include <fsl_usd.h>
  45 #include <fsl_qman.h>
  46 #include <fsl_bman.h>
  47 #include <fsl_fman.h>
  48
  49 /* Supported Rx offloads */
  50 static uint64_t dev_rx_offloads_sup =
  51                 DEV_RX_OFFLOAD_JUMBO_FRAME |
  52                 DEV_RX_OFFLOAD_SCATTER;
  53
  54 /* Rx offloads which cannot be disabled */
  55 static uint64_t dev_rx_offloads_nodis =
  56                 DEV_RX_OFFLOAD_IPV4_CKSUM |
  57                 DEV_RX_OFFLOAD_UDP_CKSUM |
  58                 DEV_RX_OFFLOAD_TCP_CKSUM |
  59                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
  60                 DEV_RX_OFFLOAD_RSS_HASH;
  61
  62 /* Supported Tx offloads */
  63 static uint64_t dev_tx_offloads_sup =
  64                 DEV_TX_OFFLOAD_MT_LOCKFREE |
  65                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
  66
  67 /* Tx offloads which cannot be disabled */
  68 static uint64_t dev_tx_offloads_nodis =
  69                 DEV_TX_OFFLOAD_IPV4_CKSUM |
  70                 DEV_TX_OFFLOAD_UDP_CKSUM |
  71                 DEV_TX_OFFLOAD_TCP_CKSUM |
  72                 DEV_TX_OFFLOAD_SCTP_CKSUM |
  73                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
  74                 DEV_TX_OFFLOAD_MULTI_SEGS;
  75
  76 /* Keep track of whether QMAN and BMAN have been globally initialized */
  77 static int is_global_init;
  78 static int default_q;   /* use default queue - FMC is not executed*/
  79 /* At present we only allow up to 4 push mode queues as default - as each of
  80  * this queue need dedicated portal and we are short of portals.
  81  */
  82 #define DPAA_MAX_PUSH_MODE_QUEUE       8
  83 #define DPAA_DEFAULT_PUSH_MODE_QUEUE   4
  84
  85 static int dpaa_push_mode_max_queue = DPAA_DEFAULT_PUSH_MODE_QUEUE;
  86 static int dpaa_push_queue_idx; /* Queue index which are in push mode*/
  87
  88
  89 /* Per FQ Taildrop in frame count */
  90 static unsigned int td_threshold = CGR_RX_PERFQ_THRESH;
  91
  92 struct rte_dpaa_xstats_name_off {
  93         char name[RTE_ETH_XSTATS_NAME_SIZE];
  94         uint32_t offset;
  95 };
  96
  97 static const struct rte_dpaa_xstats_name_off dpaa_xstats_strings[] = {
  98         {"rx_align_err",
  99                 offsetof(struct dpaa_if_stats, raln)},
 100         {"rx_valid_pause",
 101                 offsetof(struct dpaa_if_stats, rxpf)},
 102         {"rx_fcs_err",
 103                 offsetof(struct dpaa_if_stats, rfcs)},
 104         {"rx_vlan_frame",
 105                 offsetof(struct dpaa_if_stats, rvlan)},
 106         {"rx_frame_err",
 107                 offsetof(struct dpaa_if_stats, rerr)},
 108         {"rx_drop_err",
 109                 offsetof(struct dpaa_if_stats, rdrp)},
 110         {"rx_undersized",
 111                 offsetof(struct dpaa_if_stats, rund)},
 112         {"rx_oversize_err",
 113                 offsetof(struct dpaa_if_stats, rovr)},
 114         {"rx_fragment_pkt",
 115                 offsetof(struct dpaa_if_stats, rfrg)},
 116         {"tx_valid_pause",
 117                 offsetof(struct dpaa_if_stats, txpf)},
 118         {"tx_fcs_err",
 119                 offsetof(struct dpaa_if_stats, terr)},
 120         {"tx_vlan_frame",
 121                 offsetof(struct dpaa_if_stats, tvlan)},
 122         {"rx_undersized",
 123                 offsetof(struct dpaa_if_stats, tund)},
 124 };
 125
 126 static struct rte_dpaa_driver rte_dpaa_pmd;
 127
 128 static int
 129 dpaa_eth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info);
 130
 131 static inline void
 132 dpaa_poll_queue_default_config(struct qm_mcc_initfq *opts)
 133 {
 134         memset(opts, 0, sizeof(struct qm_mcc_initfq));
 135         opts->we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
 136         opts->fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | QM_FQCTRL_CTXASTASHING |
 137                            QM_FQCTRL_PREFERINCACHE;
 138         opts->fqd.context_a.stashing.exclusive = 0;
 139         if (dpaa_svr_family != SVR_LS1046A_FAMILY)
 140                 opts->fqd.context_a.stashing.annotation_cl =
 141                                                 DPAA_IF_RX_ANNOTATION_STASH;
 142         opts->fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
 143         opts->fqd.context_a.stashing.context_cl = DPAA_IF_RX_CONTEXT_STASH;
 144 }
 145
 146 static int
 147 dpaa_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 148 {
 149         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 150         uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
 151                                 + VLAN_TAG_SIZE;
 152         uint32_t buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
 153
 154         PMD_INIT_FUNC_TRACE();
 155
 156         if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA_MAX_RX_PKT_LEN)
 157                 return -EINVAL;
 158         /*
 159          * Refuse mtu that requires the support of scattered packets
 160          * when this feature has not been enabled before.
 161          */
 162         if (dev->data->min_rx_buf_size &&
 163                 !dev->data->scattered_rx && frame_size > buffsz) {
 164                 DPAA_PMD_ERR("SG not enabled, will not fit in one buffer");
 165                 return -EINVAL;
 166         }
 167
 168         /* check <seg size> * <max_seg>  >= max_frame */
 169         if (dev->data->min_rx_buf_size && dev->data->scattered_rx &&
 170                 (frame_size > buffsz * DPAA_SGT_MAX_ENTRIES)) {
 171                 DPAA_PMD_ERR("Too big to fit for Max SG list %d",
 172                                 buffsz * DPAA_SGT_MAX_ENTRIES);
 173                 return -EINVAL;
 174         }
 175
 176         if (frame_size > RTE_ETHER_MAX_LEN)
 177                 dev->data->dev_conf.rxmode.offloads |=
 178                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 179         else
 180                 dev->data->dev_conf.rxmode.offloads &=
 181                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 182
 183         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 184
 185         fman_if_set_maxfrm(dpaa_intf->fif, frame_size);
 186
 187         return 0;
 188 }
 189
 190 static int
 191 dpaa_eth_dev_configure(struct rte_eth_dev *dev)
 192 {
 193         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 194         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 195         uint64_t rx_offloads = eth_conf->rxmode.offloads;
 196         uint64_t tx_offloads = eth_conf->txmode.offloads;
 197
 198         PMD_INIT_FUNC_TRACE();
 199
 200         /* Rx offloads which are enabled by default */
 201         if (dev_rx_offloads_nodis & ~rx_offloads) {
 202                 DPAA_PMD_INFO(
 203                 "Some of rx offloads enabled by default - requested 0x%" PRIx64
 204                 " fixed are 0x%" PRIx64,
 205                 rx_offloads, dev_rx_offloads_nodis);
 206         }
 207
 208         /* Tx offloads which are enabled by default */
 209         if (dev_tx_offloads_nodis & ~tx_offloads) {
 210                 DPAA_PMD_INFO(
 211                 "Some of tx offloads enabled by default - requested 0x%" PRIx64
 212                 " fixed are 0x%" PRIx64,
 213                 tx_offloads, dev_tx_offloads_nodis);
 214         }
 215
 216         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 217                 uint32_t max_len;
 218
 219                 DPAA_PMD_DEBUG("enabling jumbo");
 220
 221                 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <=
 222                     DPAA_MAX_RX_PKT_LEN)
 223                         max_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
 224                 else {
 225                         DPAA_PMD_INFO("enabling jumbo override conf max len=%d "
 226                                 "supported is %d",
 227                                 dev->data->dev_conf.rxmode.max_rx_pkt_len,
 228                                 DPAA_MAX_RX_PKT_LEN);
 229                         max_len = DPAA_MAX_RX_PKT_LEN;
 230                 }
 231
 232                 fman_if_set_maxfrm(dpaa_intf->fif, max_len);
 233                 dev->data->mtu = max_len
 234                         - RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE;
 235         }
 236
 237         if (rx_offloads & DEV_RX_OFFLOAD_SCATTER) {
 238                 DPAA_PMD_DEBUG("enabling scatter mode");
 239                 fman_if_set_sg(dpaa_intf->fif, 1);
 240                 dev->data->scattered_rx = 1;
 241         }
 242
 243         return 0;
 244 }
 245
 246 static const uint32_t *
 247 dpaa_supported_ptypes_get(struct rte_eth_dev *dev)
 248 {
 249         static const uint32_t ptypes[] = {
 250                 RTE_PTYPE_L2_ETHER,
 251                 RTE_PTYPE_L2_ETHER_VLAN,
 252                 RTE_PTYPE_L2_ETHER_ARP,
 253                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
 254                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
 255                 RTE_PTYPE_L4_ICMP,
 256                 RTE_PTYPE_L4_TCP,
 257                 RTE_PTYPE_L4_UDP,
 258                 RTE_PTYPE_L4_FRAG,
 259                 RTE_PTYPE_L4_TCP,
 260                 RTE_PTYPE_L4_UDP,
 261                 RTE_PTYPE_L4_SCTP
 262         };
 263
 264         PMD_INIT_FUNC_TRACE();
 265
 266         if (dev->rx_pkt_burst == dpaa_eth_queue_rx)
 267                 return ptypes;
 268         return NULL;
 269 }
 270
 271 static int dpaa_eth_dev_start(struct rte_eth_dev *dev)
 272 {
 273         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 274
 275         PMD_INIT_FUNC_TRACE();
 276
 277         /* Change tx callback to the real one */
 278         dev->tx_pkt_burst = dpaa_eth_queue_tx;
 279         fman_if_enable_rx(dpaa_intf->fif);
 280
 281         return 0;
 282 }
 283
 284 static void dpaa_eth_dev_stop(struct rte_eth_dev *dev)
 285 {
 286         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 287
 288         PMD_INIT_FUNC_TRACE();
 289
 290         fman_if_disable_rx(dpaa_intf->fif);
 291         dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
 292 }
 293
 294 static void dpaa_eth_dev_close(struct rte_eth_dev *dev)
 295 {
 296         PMD_INIT_FUNC_TRACE();
 297
 298         dpaa_eth_dev_stop(dev);
 299 }
 300
 301 static int
 302 dpaa_fw_version_get(struct rte_eth_dev *dev __rte_unused,
 303                      char *fw_version,
 304                      size_t fw_size)
 305 {
 306         int ret;
 307         FILE *svr_file = NULL;
 308         unsigned int svr_ver = 0;
 309
 310         PMD_INIT_FUNC_TRACE();
 311
 312         svr_file = fopen(DPAA_SOC_ID_FILE, "r");
 313         if (!svr_file) {
 314                 DPAA_PMD_ERR("Unable to open SoC device");
 315                 return -ENOTSUP; /* Not supported on this infra */
 316         }
 317         if (fscanf(svr_file, "svr:%x", &svr_ver) > 0)
 318                 dpaa_svr_family = svr_ver & SVR_MASK;
 319         else
 320                 DPAA_PMD_ERR("Unable to read SoC device");
 321
 322         fclose(svr_file);
 323
 324         ret = snprintf(fw_version, fw_size, "SVR:%x-fman-v%x",
 325                        svr_ver, fman_ip_rev);
 326         ret += 1; /* add the size of '\0' */
 327
 328         if (fw_size < (uint32_t)ret)
 329                 return ret;
 330         else
 331                 return 0;
 332 }
 333
 334 static int dpaa_eth_dev_info(struct rte_eth_dev *dev,
 335                              struct rte_eth_dev_info *dev_info)
 336 {
 337         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 338
 339         DPAA_PMD_DEBUG(": %s", dpaa_intf->name);
 340
 341         dev_info->max_rx_queues = dpaa_intf->nb_rx_queues;
 342         dev_info->max_tx_queues = dpaa_intf->nb_tx_queues;
 343         dev_info->max_rx_pktlen = DPAA_MAX_RX_PKT_LEN;
 344         dev_info->max_mac_addrs = DPAA_MAX_MAC_FILTER;
 345         dev_info->max_hash_mac_addrs = 0;
 346         dev_info->max_vfs = 0;
 347         dev_info->max_vmdq_pools = ETH_16_POOLS;
 348         dev_info->flow_type_rss_offloads = DPAA_RSS_OFFLOAD_ALL;
 349
 350         if (dpaa_intf->fif->mac_type == fman_mac_1g) {
 351                 dev_info->speed_capa = ETH_LINK_SPEED_1G;
 352         } else if (dpaa_intf->fif->mac_type == fman_mac_10g) {
 353                 dev_info->speed_capa = (ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G);
 354         } else {
 355                 DPAA_PMD_ERR("invalid link_speed: %s, %d",
 356                              dpaa_intf->name, dpaa_intf->fif->mac_type);
 357                 return -EINVAL;
 358         }
 359
 360         dev_info->rx_offload_capa = dev_rx_offloads_sup |
 361                                         dev_rx_offloads_nodis;
 362         dev_info->tx_offload_capa = dev_tx_offloads_sup |
 363                                         dev_tx_offloads_nodis;
 364         dev_info->default_rxportconf.burst_size = DPAA_DEF_RX_BURST_SIZE;
 365         dev_info->default_txportconf.burst_size = DPAA_DEF_TX_BURST_SIZE;
 366
 367         return 0;
 368 }
 369
 370 static int dpaa_eth_link_update(struct rte_eth_dev *dev,
 371                                 int wait_to_complete __rte_unused)
 372 {
 373         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 374         struct rte_eth_link *link = &dev->data->dev_link;
 375
 376         PMD_INIT_FUNC_TRACE();
 377
 378         if (dpaa_intf->fif->mac_type == fman_mac_1g)
 379                 link->link_speed = ETH_SPEED_NUM_1G;
 380         else if (dpaa_intf->fif->mac_type == fman_mac_10g)
 381                 link->link_speed = ETH_SPEED_NUM_10G;
 382         else
 383                 DPAA_PMD_ERR("invalid link_speed: %s, %d",
 384                              dpaa_intf->name, dpaa_intf->fif->mac_type);
 385
 386         link->link_status = dpaa_intf->valid;
 387         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 388         link->link_autoneg = ETH_LINK_AUTONEG;
 389         return 0;
 390 }
 391
 392 static int dpaa_eth_stats_get(struct rte_eth_dev *dev,
 393                                struct rte_eth_stats *stats)
 394 {
 395         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 396
 397         PMD_INIT_FUNC_TRACE();
 398
 399         fman_if_stats_get(dpaa_intf->fif, stats);
 400         return 0;
 401 }
 402
 403 static int dpaa_eth_stats_reset(struct rte_eth_dev *dev)
 404 {
 405         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 406
 407         PMD_INIT_FUNC_TRACE();
 408
 409         fman_if_stats_reset(dpaa_intf->fif);
 410
 411         return 0;
 412 }
 413
 414 static int
 415 dpaa_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
 416                     unsigned int n)
 417 {
 418         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 419         unsigned int i = 0, num = RTE_DIM(dpaa_xstats_strings);
 420         uint64_t values[sizeof(struct dpaa_if_stats) / 8];
 421
 422         if (n < num)
 423                 return num;
 424
 425         if (xstats == NULL)
 426                 return 0;
 427
 428         fman_if_stats_get_all(dpaa_intf->fif, values,
 429                               sizeof(struct dpaa_if_stats) / 8);
 430
 431         for (i = 0; i < num; i++) {
 432                 xstats[i].id = i;
 433                 xstats[i].value = values[dpaa_xstats_strings[i].offset / 8];
 434         }
 435         return i;
 436 }
 437
 438 static int
 439 dpaa_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 440                       struct rte_eth_xstat_name *xstats_names,
 441                       unsigned int limit)
 442 {
 443         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 444
 445         if (limit < stat_cnt)
 446                 return stat_cnt;
 447
 448         if (xstats_names != NULL)
 449                 for (i = 0; i < stat_cnt; i++)
 450                         strlcpy(xstats_names[i].name,
 451                                 dpaa_xstats_strings[i].name,
 452                                 sizeof(xstats_names[i].name));
 453
 454         return stat_cnt;
 455 }
 456
 457 static int
 458 dpaa_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 459                       uint64_t *values, unsigned int n)
 460 {
 461         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 462         uint64_t values_copy[sizeof(struct dpaa_if_stats) / 8];
 463
 464         if (!ids) {
 465                 struct dpaa_if *dpaa_intf = dev->data->dev_private;
 466
 467                 if (n < stat_cnt)
 468                         return stat_cnt;
 469
 470                 if (!values)
 471                         return 0;
 472
 473                 fman_if_stats_get_all(dpaa_intf->fif, values_copy,
 474                                       sizeof(struct dpaa_if_stats) / 8);
 475
 476                 for (i = 0; i < stat_cnt; i++)
 477                         values[i] =
 478                                 values_copy[dpaa_xstats_strings[i].offset / 8];
 479
 480                 return stat_cnt;
 481         }
 482
 483         dpaa_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
 484
 485         for (i = 0; i < n; i++) {
 486                 if (ids[i] >= stat_cnt) {
 487                         DPAA_PMD_ERR("id value isn't valid");
 488                         return -1;
 489                 }
 490                 values[i] = values_copy[ids[i]];
 491         }
 492         return n;
 493 }
 494
 495 static int
 496 dpaa_xstats_get_names_by_id(
 497         struct rte_eth_dev *dev,
 498         struct rte_eth_xstat_name *xstats_names,
 499         const uint64_t *ids,
 500         unsigned int limit)
 501 {
 502         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 503         struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
 504
 505         if (!ids)
 506                 return dpaa_xstats_get_names(dev, xstats_names, limit);
 507
 508         dpaa_xstats_get_names(dev, xstats_names_copy, limit);
 509
 510         for (i = 0; i < limit; i++) {
 511                 if (ids[i] >= stat_cnt) {
 512                         DPAA_PMD_ERR("id value isn't valid");
 513                         return -1;
 514                 }
 515                 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
 516         }
 517         return limit;
 518 }
 519
 520 static int dpaa_eth_promiscuous_enable(struct rte_eth_dev *dev)
 521 {
 522         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 523
 524         PMD_INIT_FUNC_TRACE();
 525
 526         fman_if_promiscuous_enable(dpaa_intf->fif);
 527
 528         return 0;
 529 }
 530
 531 static int dpaa_eth_promiscuous_disable(struct rte_eth_dev *dev)
 532 {
 533         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 534
 535         PMD_INIT_FUNC_TRACE();
 536
 537         fman_if_promiscuous_disable(dpaa_intf->fif);
 538
 539         return 0;
 540 }
 541
 542 static int dpaa_eth_multicast_enable(struct rte_eth_dev *dev)
 543 {
 544         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 545
 546         PMD_INIT_FUNC_TRACE();
 547
 548         fman_if_set_mcast_filter_table(dpaa_intf->fif);
 549
 550         return 0;
 551 }
 552
 553 static int dpaa_eth_multicast_disable(struct rte_eth_dev *dev)
 554 {
 555         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 556
 557         PMD_INIT_FUNC_TRACE();
 558
 559         fman_if_reset_mcast_filter_table(dpaa_intf->fif);
 560
 561         return 0;
 562 }
 563
 564 static
 565 int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 566                             uint16_t nb_desc,
 567                             unsigned int socket_id __rte_unused,
 568                             const struct rte_eth_rxconf *rx_conf __rte_unused,
 569                             struct rte_mempool *mp)
 570 {
 571         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 572         struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_idx];
 573         struct qm_mcc_initfq opts = {0};
 574         u32 flags = 0;
 575         int ret;
 576         u32 buffsz = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
 577
 578         PMD_INIT_FUNC_TRACE();
 579
 580         if (queue_idx >= dev->data->nb_rx_queues) {
 581                 rte_errno = EOVERFLOW;
 582                 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
 583                       (void *)dev, queue_idx, dev->data->nb_rx_queues);
 584                 return -rte_errno;
 585         }
 586
 587         DPAA_PMD_INFO("Rx queue setup for queue index: %d fq_id (0x%x)",
 588                         queue_idx, rxq->fqid);
 589
 590         /* Max packet can fit in single buffer */
 591         if (dev->data->dev_conf.rxmode.max_rx_pkt_len <= buffsz) {
 592                 ;
 593         } else if (dev->data->dev_conf.rxmode.offloads &
 594                         DEV_RX_OFFLOAD_SCATTER) {
 595                 if (dev->data->dev_conf.rxmode.max_rx_pkt_len >
 596                         buffsz * DPAA_SGT_MAX_ENTRIES) {
 597                         DPAA_PMD_ERR("max RxPkt size %d too big to fit "
 598                                 "MaxSGlist %d",
 599                                 dev->data->dev_conf.rxmode.max_rx_pkt_len,
 600                                 buffsz * DPAA_SGT_MAX_ENTRIES);
 601                         rte_errno = EOVERFLOW;
 602                         return -rte_errno;
 603                 }
 604         } else {
 605                 DPAA_PMD_WARN("The requested maximum Rx packet size (%u) is"
 606                      " larger than a single mbuf (%u) and scattered"
 607                      " mode has not been requested",
 608                      dev->data->dev_conf.rxmode.max_rx_pkt_len,
 609                      buffsz - RTE_PKTMBUF_HEADROOM);
 610         }
 611
 612         if (!dpaa_intf->bp_info || dpaa_intf->bp_info->mp != mp) {
 613                 struct fman_if_ic_params icp;
 614                 uint32_t fd_offset;
 615                 uint32_t bp_size;
 616
 617                 if (!mp->pool_data) {
 618                         DPAA_PMD_ERR("Not an offloaded buffer pool!");
 619                         return -1;
 620                 }
 621                 dpaa_intf->bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp);
 622
 623                 memset(&icp, 0, sizeof(icp));
 624                 /* set ICEOF for to the default value , which is 0*/
 625                 icp.iciof = DEFAULT_ICIOF;
 626                 icp.iceof = DEFAULT_RX_ICEOF;
 627                 icp.icsz = DEFAULT_ICSZ;
 628                 fman_if_set_ic_params(dpaa_intf->fif, &icp);
 629
 630                 fd_offset = RTE_PKTMBUF_HEADROOM + DPAA_HW_BUF_RESERVE;
 631                 fman_if_set_fdoff(dpaa_intf->fif, fd_offset);
 632
 633                 /* Buffer pool size should be equal to Dataroom Size*/
 634                 bp_size = rte_pktmbuf_data_room_size(mp);
 635                 fman_if_set_bp(dpaa_intf->fif, mp->size,
 636                                dpaa_intf->bp_info->bpid, bp_size);
 637                 dpaa_intf->valid = 1;
 638                 DPAA_PMD_DEBUG("if:%s fd_offset = %d offset = %d",
 639                                 dpaa_intf->name, fd_offset,
 640                                 fman_if_get_fdoff(dpaa_intf->fif));
 641         }
 642         DPAA_PMD_DEBUG("if:%s sg_on = %d, max_frm =%d", dpaa_intf->name,
 643                 fman_if_get_sg_enable(dpaa_intf->fif),
 644                 dev->data->dev_conf.rxmode.max_rx_pkt_len);
 645         /* checking if push mode only, no error check for now */
 646         if (!rxq->is_static &&
 647             dpaa_push_mode_max_queue > dpaa_push_queue_idx) {
 648                 struct qman_portal *qp;
 649                 int q_fd;
 650
 651                 dpaa_push_queue_idx++;
 652                 opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
 653                 opts.fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK |
 654                                    QM_FQCTRL_CTXASTASHING |
 655                                    QM_FQCTRL_PREFERINCACHE;
 656                 opts.fqd.context_a.stashing.exclusive = 0;
 657                 /* In muticore scenario stashing becomes a bottleneck on LS1046.
 658                  * So do not enable stashing in this case
 659                  */
 660                 if (dpaa_svr_family != SVR_LS1046A_FAMILY)
 661                         opts.fqd.context_a.stashing.annotation_cl =
 662                                                 DPAA_IF_RX_ANNOTATION_STASH;
 663                 opts.fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
 664                 opts.fqd.context_a.stashing.context_cl =
 665                                                 DPAA_IF_RX_CONTEXT_STASH;
 666
 667                 /*Create a channel and associate given queue with the channel*/
 668                 qman_alloc_pool_range((u32 *)&rxq->ch_id, 1, 1, 0);
 669                 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
 670                 opts.fqd.dest.channel = rxq->ch_id;
 671                 opts.fqd.dest.wq = DPAA_IF_RX_PRIORITY;
 672                 flags = QMAN_INITFQ_FLAG_SCHED;
 673
 674                 /* Configure tail drop */
 675                 if (dpaa_intf->cgr_rx) {
 676                         opts.we_mask |= QM_INITFQ_WE_CGID;
 677                         opts.fqd.cgid = dpaa_intf->cgr_rx[queue_idx].cgrid;
 678                         opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
 679                 }
 680                 ret = qman_init_fq(rxq, flags, &opts);
 681                 if (ret) {
 682                         DPAA_PMD_ERR("Channel/Q association failed. fqid 0x%x "
 683                                 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
 684                         return ret;
 685                 }
 686                 if (dpaa_svr_family == SVR_LS1043A_FAMILY) {
 687                         rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb_no_prefetch;
 688                 } else {
 689                         rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb;
 690                         rxq->cb.dqrr_prepare = dpaa_rx_cb_prepare;
 691                 }
 692
 693                 rxq->is_static = true;
 694
 695                 /* Allocate qman specific portals */
 696                 qp = fsl_qman_fq_portal_create(&q_fd);
 697                 if (!qp) {
 698                         DPAA_PMD_ERR("Unable to alloc fq portal");
 699                         return -1;
 700                 }
 701                 rxq->qp = qp;
 702
 703                 /* Set up the device interrupt handler */
 704                 if (!dev->intr_handle) {
 705                         struct rte_dpaa_device *dpaa_dev;
 706                         struct rte_device *rdev = dev->device;
 707
 708                         dpaa_dev = container_of(rdev, struct rte_dpaa_device,
 709                                                 device);
 710                         dev->intr_handle = &dpaa_dev->intr_handle;
 711                         dev->intr_handle->intr_vec = rte_zmalloc(NULL,
 712                                         dpaa_push_mode_max_queue, 0);
 713                         if (!dev->intr_handle->intr_vec) {
 714                                 DPAA_PMD_ERR("intr_vec alloc failed");
 715                                 return -ENOMEM;
 716                         }
 717                         dev->intr_handle->nb_efd = dpaa_push_mode_max_queue;
 718                         dev->intr_handle->max_intr = dpaa_push_mode_max_queue;
 719                 }
 720
 721                 dev->intr_handle->type = RTE_INTR_HANDLE_EXT;
 722                 dev->intr_handle->intr_vec[queue_idx] = queue_idx + 1;
 723                 dev->intr_handle->efds[queue_idx] = q_fd;
 724                 rxq->q_fd = q_fd;
 725         }
 726         rxq->bp_array = rte_dpaa_bpid_info;
 727         dev->data->rx_queues[queue_idx] = rxq;
 728
 729         /* configure the CGR size as per the desc size */
 730         if (dpaa_intf->cgr_rx) {
 731                 struct qm_mcc_initcgr cgr_opts = {0};
 732
 733                 /* Enable tail drop with cgr on this queue */
 734                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, nb_desc, 0);
 735                 ret = qman_modify_cgr(dpaa_intf->cgr_rx, 0, &cgr_opts);
 736                 if (ret) {
 737                         DPAA_PMD_WARN(
 738                                 "rx taildrop modify fail on fqid %d (ret=%d)",
 739                                 rxq->fqid, ret);
 740                 }
 741         }
 742
 743         return 0;
 744 }
 745
 746 int
 747 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev,
 748                 int eth_rx_queue_id,
 749                 u16 ch_id,
 750                 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
 751 {
 752         int ret;
 753         u32 flags = 0;
 754         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 755         struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
 756         struct qm_mcc_initfq opts = {0};
 757
 758         if (dpaa_push_mode_max_queue)
 759                 DPAA_PMD_WARN("PUSH mode q and EVENTDEV are not compatible\n"
 760                               "PUSH mode already enabled for first %d queues.\n"
 761                               "To disable set DPAA_PUSH_QUEUES_NUMBER to 0\n",
 762                               dpaa_push_mode_max_queue);
 763
 764         dpaa_poll_queue_default_config(&opts);
 765
 766         switch (queue_conf->ev.sched_type) {
 767         case RTE_SCHED_TYPE_ATOMIC:
 768                 opts.fqd.fq_ctrl |= QM_FQCTRL_HOLDACTIVE;
 769                 /* Reset FQCTRL_AVOIDBLOCK bit as it is unnecessary
 770                  * configuration with HOLD_ACTIVE setting
 771                  */
 772                 opts.fqd.fq_ctrl &= (~QM_FQCTRL_AVOIDBLOCK);
 773                 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_atomic;
 774                 break;
 775         case RTE_SCHED_TYPE_ORDERED:
 776                 DPAA_PMD_ERR("Ordered queue schedule type is not supported\n");
 777                 return -1;
 778         default:
 779                 opts.fqd.fq_ctrl |= QM_FQCTRL_AVOIDBLOCK;
 780                 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_parallel;
 781                 break;
 782         }
 783
 784         opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
 785         opts.fqd.dest.channel = ch_id;
 786         opts.fqd.dest.wq = queue_conf->ev.priority;
 787
 788         if (dpaa_intf->cgr_rx) {
 789                 opts.we_mask |= QM_INITFQ_WE_CGID;
 790                 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
 791                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
 792         }
 793
 794         flags = QMAN_INITFQ_FLAG_SCHED;
 795
 796         ret = qman_init_fq(rxq, flags, &opts);
 797         if (ret) {
 798                 DPAA_PMD_ERR("Ev-Channel/Q association failed. fqid 0x%x "
 799                                 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
 800                 return ret;
 801         }
 802
 803         /* copy configuration which needs to be filled during dequeue */
 804         memcpy(&rxq->ev, &queue_conf->ev, sizeof(struct rte_event));
 805         dev->data->rx_queues[eth_rx_queue_id] = rxq;
 806
 807         return ret;
 808 }
 809
 810 int
 811 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev,
 812                 int eth_rx_queue_id)
 813 {
 814         struct qm_mcc_initfq opts;
 815         int ret;
 816         u32 flags = 0;
 817         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 818         struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
 819
 820         dpaa_poll_queue_default_config(&opts);
 821
 822         if (dpaa_intf->cgr_rx) {
 823                 opts.we_mask |= QM_INITFQ_WE_CGID;
 824                 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
 825                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
 826         }
 827
 828         ret = qman_init_fq(rxq, flags, &opts);
 829         if (ret) {
 830                 DPAA_PMD_ERR("init rx fqid %d failed with ret: %d",
 831                              rxq->fqid, ret);
 832         }
 833
 834         rxq->cb.dqrr_dpdk_cb = NULL;
 835         dev->data->rx_queues[eth_rx_queue_id] = NULL;
 836
 837         return 0;
 838 }
 839
 840 static
 841 void dpaa_eth_rx_queue_release(void *rxq __rte_unused)
 842 {
 843         PMD_INIT_FUNC_TRACE();
 844 }
 845
 846 static
 847 int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 848                             uint16_t nb_desc __rte_unused,
 849                 unsigned int socket_id __rte_unused,
 850                 const struct rte_eth_txconf *tx_conf __rte_unused)
 851 {
 852         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 853
 854         PMD_INIT_FUNC_TRACE();
 855
 856         if (queue_idx >= dev->data->nb_tx_queues) {
 857                 rte_errno = EOVERFLOW;
 858                 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
 859                       (void *)dev, queue_idx, dev->data->nb_tx_queues);
 860                 return -rte_errno;
 861         }
 862
 863         DPAA_PMD_INFO("Tx queue setup for queue index: %d fq_id (0x%x)",
 864                         queue_idx, dpaa_intf->tx_queues[queue_idx].fqid);
 865         dev->data->tx_queues[queue_idx] = &dpaa_intf->tx_queues[queue_idx];
 866         return 0;
 867 }
 868
 869 static void dpaa_eth_tx_queue_release(void *txq __rte_unused)
 870 {
 871         PMD_INIT_FUNC_TRACE();
 872 }
 873
 874 static uint32_t
 875 dpaa_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 876 {
 877         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 878         struct qman_fq *rxq = &dpaa_intf->rx_queues[rx_queue_id];
 879         u32 frm_cnt = 0;
 880
 881         PMD_INIT_FUNC_TRACE();
 882
 883         if (qman_query_fq_frm_cnt(rxq, &frm_cnt) == 0) {
 884                 RTE_LOG(DEBUG, PMD, "RX frame count for q(%d) is %u\n",
 885                         rx_queue_id, frm_cnt);
 886         }
 887         return frm_cnt;
 888 }
 889
 890 static int dpaa_link_down(struct rte_eth_dev *dev)
 891 {
 892         PMD_INIT_FUNC_TRACE();
 893
 894         dpaa_eth_dev_stop(dev);
 895         return 0;
 896 }
 897
 898 static int dpaa_link_up(struct rte_eth_dev *dev)
 899 {
 900         PMD_INIT_FUNC_TRACE();
 901
 902         dpaa_eth_dev_start(dev);
 903         return 0;
 904 }
 905
 906 static int
 907 dpaa_flow_ctrl_set(struct rte_eth_dev *dev,
 908                    struct rte_eth_fc_conf *fc_conf)
 909 {
 910         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 911         struct rte_eth_fc_conf *net_fc;
 912
 913         PMD_INIT_FUNC_TRACE();
 914
 915         if (!(dpaa_intf->fc_conf)) {
 916                 dpaa_intf->fc_conf = rte_zmalloc(NULL,
 917                         sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
 918                 if (!dpaa_intf->fc_conf) {
 919                         DPAA_PMD_ERR("unable to save flow control info");
 920                         return -ENOMEM;
 921                 }
 922         }
 923         net_fc = dpaa_intf->fc_conf;
 924
 925         if (fc_conf->high_water < fc_conf->low_water) {
 926                 DPAA_PMD_ERR("Incorrect Flow Control Configuration");
 927                 return -EINVAL;
 928         }
 929
 930         if (fc_conf->mode == RTE_FC_NONE) {
 931                 return 0;
 932         } else if (fc_conf->mode == RTE_FC_TX_PAUSE ||
 933                  fc_conf->mode == RTE_FC_FULL) {
 934                 fman_if_set_fc_threshold(dpaa_intf->fif, fc_conf->high_water,
 935                                          fc_conf->low_water,
 936                                 dpaa_intf->bp_info->bpid);
 937                 if (fc_conf->pause_time)
 938                         fman_if_set_fc_quanta(dpaa_intf->fif,
 939                                               fc_conf->pause_time);
 940         }
 941
 942         /* Save the information in dpaa device */
 943         net_fc->pause_time = fc_conf->pause_time;
 944         net_fc->high_water = fc_conf->high_water;
 945         net_fc->low_water = fc_conf->low_water;
 946         net_fc->send_xon = fc_conf->send_xon;
 947         net_fc->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
 948         net_fc->mode = fc_conf->mode;
 949         net_fc->autoneg = fc_conf->autoneg;
 950
 951         return 0;
 952 }
 953
 954 static int
 955 dpaa_flow_ctrl_get(struct rte_eth_dev *dev,
 956                    struct rte_eth_fc_conf *fc_conf)
 957 {
 958         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 959         struct rte_eth_fc_conf *net_fc = dpaa_intf->fc_conf;
 960         int ret;
 961
 962         PMD_INIT_FUNC_TRACE();
 963
 964         if (net_fc) {
 965                 fc_conf->pause_time = net_fc->pause_time;
 966                 fc_conf->high_water = net_fc->high_water;
 967                 fc_conf->low_water = net_fc->low_water;
 968                 fc_conf->send_xon = net_fc->send_xon;
 969                 fc_conf->mac_ctrl_frame_fwd = net_fc->mac_ctrl_frame_fwd;
 970                 fc_conf->mode = net_fc->mode;
 971                 fc_conf->autoneg = net_fc->autoneg;
 972                 return 0;
 973         }
 974         ret = fman_if_get_fc_threshold(dpaa_intf->fif);
 975         if (ret) {
 976                 fc_conf->mode = RTE_FC_TX_PAUSE;
 977                 fc_conf->pause_time = fman_if_get_fc_quanta(dpaa_intf->fif);
 978         } else {
 979                 fc_conf->mode = RTE_FC_NONE;
 980         }
 981
 982         return 0;
 983 }
 984
 985 static int
 986 dpaa_dev_add_mac_addr(struct rte_eth_dev *dev,
 987                              struct rte_ether_addr *addr,
 988                              uint32_t index,
 989                              __rte_unused uint32_t pool)
 990 {
 991         int ret;
 992         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 993
 994         PMD_INIT_FUNC_TRACE();
 995
 996         ret = fman_if_add_mac_addr(dpaa_intf->fif, addr->addr_bytes, index);
 997
 998         if (ret)
 999                 RTE_LOG(ERR, PMD, "error: Adding the MAC ADDR failed:"
1000                         " err = %d", ret);
1001         return 0;
1002 }
1003
1004 static void
1005 dpaa_dev_remove_mac_addr(struct rte_eth_dev *dev,
1006                           uint32_t index)
1007 {
1008         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1009
1010         PMD_INIT_FUNC_TRACE();
1011
1012         fman_if_clear_mac_addr(dpaa_intf->fif, index);
1013 }
1014
1015 static int
1016 dpaa_dev_set_mac_addr(struct rte_eth_dev *dev,
1017                        struct rte_ether_addr *addr)
1018 {
1019         int ret;
1020         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1021
1022         PMD_INIT_FUNC_TRACE();
1023
1024         ret = fman_if_add_mac_addr(dpaa_intf->fif, addr->addr_bytes, 0);
1025         if (ret)
1026                 RTE_LOG(ERR, PMD, "error: Setting the MAC ADDR failed %d", ret);
1027
1028         return ret;
1029 }
1030
1031 static int dpaa_dev_queue_intr_enable(struct rte_eth_dev *dev,
1032                                       uint16_t queue_id)
1033 {
1034         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1035         struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id];
1036
1037         if (!rxq->is_static)
1038                 return -EINVAL;
1039
1040         return qman_fq_portal_irqsource_add(rxq->qp, QM_PIRQ_DQRI);
1041 }
1042
1043 static int dpaa_dev_queue_intr_disable(struct rte_eth_dev *dev,
1044                                        uint16_t queue_id)
1045 {
1046         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1047         struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id];
1048         uint32_t temp;
1049         ssize_t temp1;
1050
1051         if (!rxq->is_static)
1052                 return -EINVAL;
1053
1054         qman_fq_portal_irqsource_remove(rxq->qp, ~0);
1055
1056         temp1 = read(rxq->q_fd, &temp, sizeof(temp));
1057         if (temp1 != sizeof(temp))
1058                 DPAA_EVENTDEV_ERR("irq read error");
1059
1060         qman_fq_portal_thread_irq(rxq->qp);
1061
1062         return 0;
1063 }
1064
1065 static struct eth_dev_ops dpaa_devops = {
1066         .dev_configure            = dpaa_eth_dev_configure,
1067         .dev_start                = dpaa_eth_dev_start,
1068         .dev_stop                 = dpaa_eth_dev_stop,
1069         .dev_close                = dpaa_eth_dev_close,
1070         .dev_infos_get            = dpaa_eth_dev_info,
1071         .dev_supported_ptypes_get = dpaa_supported_ptypes_get,
1072
1073         .rx_queue_setup           = dpaa_eth_rx_queue_setup,
1074         .tx_queue_setup           = dpaa_eth_tx_queue_setup,
1075         .rx_queue_release         = dpaa_eth_rx_queue_release,
1076         .tx_queue_release         = dpaa_eth_tx_queue_release,
1077         .rx_queue_count           = dpaa_dev_rx_queue_count,
1078
1079         .flow_ctrl_get            = dpaa_flow_ctrl_get,
1080         .flow_ctrl_set            = dpaa_flow_ctrl_set,
1081
1082         .link_update              = dpaa_eth_link_update,
1083         .stats_get                = dpaa_eth_stats_get,
1084         .xstats_get               = dpaa_dev_xstats_get,
1085         .xstats_get_by_id         = dpaa_xstats_get_by_id,
1086         .xstats_get_names_by_id   = dpaa_xstats_get_names_by_id,
1087         .xstats_get_names         = dpaa_xstats_get_names,
1088         .xstats_reset             = dpaa_eth_stats_reset,
1089         .stats_reset              = dpaa_eth_stats_reset,
1090         .promiscuous_enable       = dpaa_eth_promiscuous_enable,
1091         .promiscuous_disable      = dpaa_eth_promiscuous_disable,
1092         .allmulticast_enable      = dpaa_eth_multicast_enable,
1093         .allmulticast_disable     = dpaa_eth_multicast_disable,
1094         .mtu_set                  = dpaa_mtu_set,
1095         .dev_set_link_down        = dpaa_link_down,
1096         .dev_set_link_up          = dpaa_link_up,
1097         .mac_addr_add             = dpaa_dev_add_mac_addr,
1098         .mac_addr_remove          = dpaa_dev_remove_mac_addr,
1099         .mac_addr_set             = dpaa_dev_set_mac_addr,
1100
1101         .fw_version_get           = dpaa_fw_version_get,
1102
1103         .rx_queue_intr_enable     = dpaa_dev_queue_intr_enable,
1104         .rx_queue_intr_disable    = dpaa_dev_queue_intr_disable,
1105 };
1106
1107 static bool
1108 is_device_supported(struct rte_eth_dev *dev, struct rte_dpaa_driver *drv)
1109 {
1110         if (strcmp(dev->device->driver->name,
1111                    drv->driver.name))
1112                 return false;
1113
1114         return true;
1115 }
1116
1117 static bool
1118 is_dpaa_supported(struct rte_eth_dev *dev)
1119 {
1120         return is_device_supported(dev, &rte_dpaa_pmd);
1121 }
1122
1123 int
1124 rte_pmd_dpaa_set_tx_loopback(uint8_t port, uint8_t on)
1125 {
1126         struct rte_eth_dev *dev;
1127         struct dpaa_if *dpaa_intf;
1128
1129         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
1130
1131         dev = &rte_eth_devices[port];
1132
1133         if (!is_dpaa_supported(dev))
1134                 return -ENOTSUP;
1135
1136         dpaa_intf = dev->data->dev_private;
1137
1138         if (on)
1139                 fman_if_loopback_enable(dpaa_intf->fif);
1140         else
1141                 fman_if_loopback_disable(dpaa_intf->fif);
1142
1143         return 0;
1144 }
1145
1146 static int dpaa_fc_set_default(struct dpaa_if *dpaa_intf)
1147 {
1148         struct rte_eth_fc_conf *fc_conf;
1149         int ret;
1150
1151         PMD_INIT_FUNC_TRACE();
1152
1153         if (!(dpaa_intf->fc_conf)) {
1154                 dpaa_intf->fc_conf = rte_zmalloc(NULL,
1155                         sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
1156                 if (!dpaa_intf->fc_conf) {
1157                         DPAA_PMD_ERR("unable to save flow control info");
1158                         return -ENOMEM;
1159                 }
1160         }
1161         fc_conf = dpaa_intf->fc_conf;
1162         ret = fman_if_get_fc_threshold(dpaa_intf->fif);
1163         if (ret) {
1164                 fc_conf->mode = RTE_FC_TX_PAUSE;
1165                 fc_conf->pause_time = fman_if_get_fc_quanta(dpaa_intf->fif);
1166         } else {
1167                 fc_conf->mode = RTE_FC_NONE;
1168         }
1169
1170         return 0;
1171 }
1172
1173 /* Initialise an Rx FQ */
1174 static int dpaa_rx_queue_init(struct qman_fq *fq, struct qman_cgr *cgr_rx,
1175                               uint32_t fqid)
1176 {
1177         struct qm_mcc_initfq opts = {0};
1178         int ret;
1179         u32 flags = QMAN_FQ_FLAG_NO_ENQUEUE;
1180         struct qm_mcc_initcgr cgr_opts = {
1181                 .we_mask = QM_CGR_WE_CS_THRES |
1182                                 QM_CGR_WE_CSTD_EN |
1183                                 QM_CGR_WE_MODE,
1184                 .cgr = {
1185                         .cstd_en = QM_CGR_EN,
1186                         .mode = QMAN_CGR_MODE_FRAME
1187                 }
1188         };
1189
1190         if (fqid) {
1191                 ret = qman_reserve_fqid(fqid);
1192                 if (ret) {
1193                         DPAA_PMD_ERR("reserve rx fqid 0x%x failed with ret: %d",
1194                                      fqid, ret);
1195                         return -EINVAL;
1196                 }
1197         } else {
1198                 flags |= QMAN_FQ_FLAG_DYNAMIC_FQID;
1199         }
1200         DPAA_PMD_DEBUG("creating rx fq %p, fqid 0x%x", fq, fqid);
1201         ret = qman_create_fq(fqid, flags, fq);
1202         if (ret) {
1203                 DPAA_PMD_ERR("create rx fqid 0x%x failed with ret: %d",
1204                         fqid, ret);
1205                 return ret;
1206         }
1207         fq->is_static = false;
1208
1209         dpaa_poll_queue_default_config(&opts);
1210
1211         if (cgr_rx) {
1212                 /* Enable tail drop with cgr on this queue */
1213                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, td_threshold, 0);
1214                 cgr_rx->cb = NULL;
1215                 ret = qman_create_cgr(cgr_rx, QMAN_CGR_FLAG_USE_INIT,
1216                                       &cgr_opts);
1217                 if (ret) {
1218                         DPAA_PMD_WARN(
1219                                 "rx taildrop init fail on rx fqid 0x%x(ret=%d)",
1220                                 fq->fqid, ret);
1221                         goto without_cgr;
1222                 }
1223                 opts.we_mask |= QM_INITFQ_WE_CGID;
1224                 opts.fqd.cgid = cgr_rx->cgrid;
1225                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1226         }
1227 without_cgr:
1228         ret = qman_init_fq(fq, 0, &opts);
1229         if (ret)
1230                 DPAA_PMD_ERR("init rx fqid 0x%x failed with ret:%d", fqid, ret);
1231         return ret;
1232 }
1233
1234 /* Initialise a Tx FQ */
1235 static int dpaa_tx_queue_init(struct qman_fq *fq,
1236                               struct fman_if *fman_intf)
1237 {
1238         struct qm_mcc_initfq opts = {0};
1239         int ret;
1240
1241         ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID |
1242                              QMAN_FQ_FLAG_TO_DCPORTAL, fq);
1243         if (ret) {
1244                 DPAA_PMD_ERR("create tx fq failed with ret: %d", ret);
1245                 return ret;
1246         }
1247         opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL |
1248                        QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA;
1249         opts.fqd.dest.channel = fman_intf->tx_channel_id;
1250         opts.fqd.dest.wq = DPAA_IF_TX_PRIORITY;
1251         opts.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE;
1252         opts.fqd.context_b = 0;
1253         /* no tx-confirmation */
1254         opts.fqd.context_a.hi = 0x80000000 | fman_dealloc_bufs_mask_hi;
1255         opts.fqd.context_a.lo = 0 | fman_dealloc_bufs_mask_lo;
1256         DPAA_PMD_DEBUG("init tx fq %p, fqid 0x%x", fq, fq->fqid);
1257         ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts);
1258         if (ret)
1259                 DPAA_PMD_ERR("init tx fqid 0x%x failed %d", fq->fqid, ret);
1260         return ret;
1261 }
1262
1263 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1264 /* Initialise a DEBUG FQ ([rt]x_error, rx_default). */
1265 static int dpaa_debug_queue_init(struct qman_fq *fq, uint32_t fqid)
1266 {
1267         struct qm_mcc_initfq opts = {0};
1268         int ret;
1269
1270         PMD_INIT_FUNC_TRACE();
1271
1272         ret = qman_reserve_fqid(fqid);
1273         if (ret) {
1274                 DPAA_PMD_ERR("Reserve debug fqid %d failed with ret: %d",
1275                         fqid, ret);
1276                 return -EINVAL;
1277         }
1278         /* "map" this Rx FQ to one of the interfaces Tx FQID */
1279         DPAA_PMD_DEBUG("Creating debug fq %p, fqid %d", fq, fqid);
1280         ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq);
1281         if (ret) {
1282                 DPAA_PMD_ERR("create debug fqid %d failed with ret: %d",
1283                         fqid, ret);
1284                 return ret;
1285         }
1286         opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL;
1287         opts.fqd.dest.wq = DPAA_IF_DEBUG_PRIORITY;
1288         ret = qman_init_fq(fq, 0, &opts);
1289         if (ret)
1290                 DPAA_PMD_ERR("init debug fqid %d failed with ret: %d",
1291                             fqid, ret);
1292         return ret;
1293 }
1294 #endif
1295
1296 /* Initialise a network interface */
1297 static int
1298 dpaa_dev_init(struct rte_eth_dev *eth_dev)
1299 {
1300         int num_rx_fqs, fqid;
1301         int loop, ret = 0;
1302         int dev_id;
1303         struct rte_dpaa_device *dpaa_device;
1304         struct dpaa_if *dpaa_intf;
1305         struct fm_eth_port_cfg *cfg;
1306         struct fman_if *fman_intf;
1307         struct fman_if_bpool *bp, *tmp_bp;
1308         uint32_t cgrid[DPAA_MAX_NUM_PCD_QUEUES];
1309
1310         PMD_INIT_FUNC_TRACE();
1311
1312         dpaa_intf = eth_dev->data->dev_private;
1313         /* For secondary processes, the primary has done all the work */
1314         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1315                 eth_dev->dev_ops = &dpaa_devops;
1316                 /* Plugging of UCODE burst API not supported in Secondary */
1317                 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
1318                 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx;
1319 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP
1320                 qman_set_fq_lookup_table(
1321                                 dpaa_intf->rx_queues->qman_fq_lookup_table);
1322 #endif
1323                 return 0;
1324         }
1325
1326         dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1327         dev_id = dpaa_device->id.dev_id;
1328         dpaa_intf = eth_dev->data->dev_private;
1329         cfg = &dpaa_netcfg->port_cfg[dev_id];
1330         fman_intf = cfg->fman_if;
1331
1332         dpaa_intf->name = dpaa_device->name;
1333
1334         /* save fman_if & cfg in the interface struture */
1335         dpaa_intf->fif = fman_intf;
1336         dpaa_intf->ifid = dev_id;
1337         dpaa_intf->cfg = cfg;
1338
1339         /* Initialize Rx FQ's */
1340         if (default_q) {
1341                 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES;
1342         } else {
1343                 if (getenv("DPAA_NUM_RX_QUEUES"))
1344                         num_rx_fqs = atoi(getenv("DPAA_NUM_RX_QUEUES"));
1345                 else
1346                         num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES;
1347         }
1348
1349
1350         /* Each device can not have more than DPAA_MAX_NUM_PCD_QUEUES RX
1351          * queues.
1352          */
1353         if (num_rx_fqs <= 0 || num_rx_fqs > DPAA_MAX_NUM_PCD_QUEUES) {
1354                 DPAA_PMD_ERR("Invalid number of RX queues\n");
1355                 return -EINVAL;
1356         }
1357
1358         dpaa_intf->rx_queues = rte_zmalloc(NULL,
1359                 sizeof(struct qman_fq) * num_rx_fqs, MAX_CACHELINE);
1360         if (!dpaa_intf->rx_queues) {
1361                 DPAA_PMD_ERR("Failed to alloc mem for RX queues\n");
1362                 return -ENOMEM;
1363         }
1364
1365         /* If congestion control is enabled globally*/
1366         if (td_threshold) {
1367                 dpaa_intf->cgr_rx = rte_zmalloc(NULL,
1368                         sizeof(struct qman_cgr) * num_rx_fqs, MAX_CACHELINE);
1369                 if (!dpaa_intf->cgr_rx) {
1370                         DPAA_PMD_ERR("Failed to alloc mem for cgr_rx\n");
1371                         ret = -ENOMEM;
1372                         goto free_rx;
1373                 }
1374
1375                 ret = qman_alloc_cgrid_range(&cgrid[0], num_rx_fqs, 1, 0);
1376                 if (ret != num_rx_fqs) {
1377                         DPAA_PMD_WARN("insufficient CGRIDs available");
1378                         ret = -EINVAL;
1379                         goto free_rx;
1380                 }
1381         } else {
1382                 dpaa_intf->cgr_rx = NULL;
1383         }
1384
1385         for (loop = 0; loop < num_rx_fqs; loop++) {
1386                 if (default_q)
1387                         fqid = cfg->rx_def;
1388                 else
1389                         fqid = DPAA_PCD_FQID_START + dpaa_intf->fif->mac_idx *
1390                                 DPAA_PCD_FQID_MULTIPLIER + loop;
1391
1392                 if (dpaa_intf->cgr_rx)
1393                         dpaa_intf->cgr_rx[loop].cgrid = cgrid[loop];
1394
1395                 ret = dpaa_rx_queue_init(&dpaa_intf->rx_queues[loop],
1396                         dpaa_intf->cgr_rx ? &dpaa_intf->cgr_rx[loop] : NULL,
1397                         fqid);
1398                 if (ret)
1399                         goto free_rx;
1400                 dpaa_intf->rx_queues[loop].dpaa_intf = dpaa_intf;
1401         }
1402         dpaa_intf->nb_rx_queues = num_rx_fqs;
1403
1404         /* Initialise Tx FQs.free_rx Have as many Tx FQ's as number of cores */
1405         dpaa_intf->tx_queues = rte_zmalloc(NULL, sizeof(struct qman_fq) *
1406                 MAX_DPAA_CORES, MAX_CACHELINE);
1407         if (!dpaa_intf->tx_queues) {
1408                 DPAA_PMD_ERR("Failed to alloc mem for TX queues\n");
1409                 ret = -ENOMEM;
1410                 goto free_rx;
1411         }
1412
1413         for (loop = 0; loop < MAX_DPAA_CORES; loop++) {
1414                 ret = dpaa_tx_queue_init(&dpaa_intf->tx_queues[loop],
1415                                          fman_intf);
1416                 if (ret)
1417                         goto free_tx;
1418                 dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf;
1419         }
1420         dpaa_intf->nb_tx_queues = MAX_DPAA_CORES;
1421
1422 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1423         dpaa_debug_queue_init(&dpaa_intf->debug_queues[
1424                 DPAA_DEBUG_FQ_RX_ERROR], fman_intf->fqid_rx_err);
1425         dpaa_intf->debug_queues[DPAA_DEBUG_FQ_RX_ERROR].dpaa_intf = dpaa_intf;
1426         dpaa_debug_queue_init(&dpaa_intf->debug_queues[
1427                 DPAA_DEBUG_FQ_TX_ERROR], fman_intf->fqid_tx_err);
1428         dpaa_intf->debug_queues[DPAA_DEBUG_FQ_TX_ERROR].dpaa_intf = dpaa_intf;
1429 #endif
1430
1431         DPAA_PMD_DEBUG("All frame queues created");
1432
1433         /* Get the initial configuration for flow control */
1434         dpaa_fc_set_default(dpaa_intf);
1435
1436         /* reset bpool list, initialize bpool dynamically */
1437         list_for_each_entry_safe(bp, tmp_bp, &cfg->fman_if->bpool_list, node) {
1438                 list_del(&bp->node);
1439                 rte_free(bp);
1440         }
1441
1442         /* Populate ethdev structure */
1443         eth_dev->dev_ops = &dpaa_devops;
1444         eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
1445         eth_dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
1446
1447         /* Allocate memory for storing MAC addresses */
1448         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr",
1449                 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER, 0);
1450         if (eth_dev->data->mac_addrs == NULL) {
1451                 DPAA_PMD_ERR("Failed to allocate %d bytes needed to "
1452                                                 "store MAC addresses",
1453                                 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER);
1454                 ret = -ENOMEM;
1455                 goto free_tx;
1456         }
1457
1458         /* copy the primary mac address */
1459         rte_ether_addr_copy(&fman_intf->mac_addr, &eth_dev->data->mac_addrs[0]);
1460
1461         RTE_LOG(INFO, PMD, "net: dpaa: %s: %02x:%02x:%02x:%02x:%02x:%02x\n",
1462                 dpaa_device->name,
1463                 fman_intf->mac_addr.addr_bytes[0],
1464                 fman_intf->mac_addr.addr_bytes[1],
1465                 fman_intf->mac_addr.addr_bytes[2],
1466                 fman_intf->mac_addr.addr_bytes[3],
1467                 fman_intf->mac_addr.addr_bytes[4],
1468                 fman_intf->mac_addr.addr_bytes[5]);
1469
1470         /* Disable RX mode */
1471         fman_if_discard_rx_errors(fman_intf);
1472         fman_if_disable_rx(fman_intf);
1473         /* Disable promiscuous mode */
1474         fman_if_promiscuous_disable(fman_intf);
1475         /* Disable multicast */
1476         fman_if_reset_mcast_filter_table(fman_intf);
1477         /* Reset interface statistics */
1478         fman_if_stats_reset(fman_intf);
1479         /* Disable SG by default */
1480         fman_if_set_sg(fman_intf, 0);
1481         fman_if_set_maxfrm(fman_intf, RTE_ETHER_MAX_LEN + VLAN_TAG_SIZE);
1482
1483         return 0;
1484
1485 free_tx:
1486         rte_free(dpaa_intf->tx_queues);
1487         dpaa_intf->tx_queues = NULL;
1488         dpaa_intf->nb_tx_queues = 0;
1489
1490 free_rx:
1491         rte_free(dpaa_intf->cgr_rx);
1492         rte_free(dpaa_intf->rx_queues);
1493         dpaa_intf->rx_queues = NULL;
1494         dpaa_intf->nb_rx_queues = 0;
1495         return ret;
1496 }
1497
1498 static int
1499 dpaa_dev_uninit(struct rte_eth_dev *dev)
1500 {
1501         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1502         int loop;
1503
1504         PMD_INIT_FUNC_TRACE();
1505
1506         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1507                 return -EPERM;
1508
1509         if (!dpaa_intf) {
1510                 DPAA_PMD_WARN("Already closed or not started");
1511                 return -1;
1512         }
1513
1514         dpaa_eth_dev_close(dev);
1515
1516         /* release configuration memory */
1517         if (dpaa_intf->fc_conf)
1518                 rte_free(dpaa_intf->fc_conf);
1519
1520         /* Release RX congestion Groups */
1521         if (dpaa_intf->cgr_rx) {
1522                 for (loop = 0; loop < dpaa_intf->nb_rx_queues; loop++)
1523                         qman_delete_cgr(&dpaa_intf->cgr_rx[loop]);
1524
1525                 qman_release_cgrid_range(dpaa_intf->cgr_rx[loop].cgrid,
1526                                          dpaa_intf->nb_rx_queues);
1527         }
1528
1529         rte_free(dpaa_intf->cgr_rx);
1530         dpaa_intf->cgr_rx = NULL;
1531
1532         rte_free(dpaa_intf->rx_queues);
1533         dpaa_intf->rx_queues = NULL;
1534
1535         rte_free(dpaa_intf->tx_queues);
1536         dpaa_intf->tx_queues = NULL;
1537
1538         dev->dev_ops = NULL;
1539         dev->rx_pkt_burst = NULL;
1540         dev->tx_pkt_burst = NULL;
1541
1542         return 0;
1543 }
1544
1545 static int
1546 rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv __rte_unused,
1547                struct rte_dpaa_device *dpaa_dev)
1548 {
1549         int diag;
1550         int ret;
1551         struct rte_eth_dev *eth_dev;
1552
1553         PMD_INIT_FUNC_TRACE();
1554
1555         if ((DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE) >
1556                 RTE_PKTMBUF_HEADROOM) {
1557                 DPAA_PMD_ERR(
1558                 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA Annotation req(%d)",
1559                 RTE_PKTMBUF_HEADROOM,
1560                 DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE);
1561
1562                 return -1;
1563         }
1564
1565         /* In case of secondary process, the device is already configured
1566          * and no further action is required, except portal initialization
1567          * and verifying secondary attachment to port name.
1568          */
1569         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1570                 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name);
1571                 if (!eth_dev)
1572                         return -ENOMEM;
1573                 eth_dev->device = &dpaa_dev->device;
1574                 eth_dev->dev_ops = &dpaa_devops;
1575                 rte_eth_dev_probing_finish(eth_dev);
1576                 return 0;
1577         }
1578
1579         if (!is_global_init && (rte_eal_process_type() == RTE_PROC_PRIMARY)) {
1580                 if (access("/tmp/fmc.bin", F_OK) == -1) {
1581                         RTE_LOG(INFO, PMD,
1582                                 "* FMC not configured.Enabling default mode\n");
1583                         default_q = 1;
1584                 }
1585
1586                 /* disabling the default push mode for LS1043 */
1587                 if (dpaa_svr_family == SVR_LS1043A_FAMILY)
1588                         dpaa_push_mode_max_queue = 0;
1589
1590                 /* if push mode queues to be enabled. Currenly we are allowing
1591                  * only one queue per thread.
1592                  */
1593                 if (getenv("DPAA_PUSH_QUEUES_NUMBER")) {
1594                         dpaa_push_mode_max_queue =
1595                                         atoi(getenv("DPAA_PUSH_QUEUES_NUMBER"));
1596                         if (dpaa_push_mode_max_queue > DPAA_MAX_PUSH_MODE_QUEUE)
1597                             dpaa_push_mode_max_queue = DPAA_MAX_PUSH_MODE_QUEUE;
1598                 }
1599
1600                 is_global_init = 1;
1601         }
1602
1603         if (unlikely(!RTE_PER_LCORE(dpaa_io))) {
1604                 ret = rte_dpaa_portal_init((void *)1);
1605                 if (ret) {
1606                         DPAA_PMD_ERR("Unable to initialize portal");
1607                         return ret;
1608                 }
1609         }
1610
1611         /* In case of secondary process, the device is already configured
1612          * and no further action is required, except portal initialization
1613          * and verifying secondary attachment to port name.
1614          */
1615         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1616                 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name);
1617                 if (!eth_dev)
1618                         return -ENOMEM;
1619         } else {
1620                 eth_dev = rte_eth_dev_allocate(dpaa_dev->name);
1621                 if (eth_dev == NULL)
1622                         return -ENOMEM;
1623
1624                 eth_dev->data->dev_private = rte_zmalloc(
1625                                                 "ethdev private structure",
1626                                                 sizeof(struct dpaa_if),
1627                                                 RTE_CACHE_LINE_SIZE);
1628                 if (!eth_dev->data->dev_private) {
1629                         DPAA_PMD_ERR("Cannot allocate memzone for port data");
1630                         rte_eth_dev_release_port(eth_dev);
1631                         return -ENOMEM;
1632                 }
1633         }
1634         eth_dev->device = &dpaa_dev->device;
1635         dpaa_dev->eth_dev = eth_dev;
1636
1637         /* Invoke PMD device initialization function */
1638         diag = dpaa_dev_init(eth_dev);
1639         if (diag == 0) {
1640                 rte_eth_dev_probing_finish(eth_dev);
1641                 return 0;
1642         }
1643
1644         rte_eth_dev_release_port(eth_dev);
1645         return diag;
1646 }
1647
1648 static int
1649 rte_dpaa_remove(struct rte_dpaa_device *dpaa_dev)
1650 {
1651         struct rte_eth_dev *eth_dev;
1652
1653         PMD_INIT_FUNC_TRACE();
1654
1655         eth_dev = dpaa_dev->eth_dev;
1656         dpaa_dev_uninit(eth_dev);
1657
1658         rte_eth_dev_release_port(eth_dev);
1659
1660         return 0;
1661 }
1662
1663 static struct rte_dpaa_driver rte_dpaa_pmd = {
1664         .drv_type = FSL_DPAA_ETH,
1665         .probe = rte_dpaa_probe,
1666         .remove = rte_dpaa_remove,
1667 };
1668
1669 RTE_PMD_REGISTER_DPAA(net_dpaa, rte_dpaa_pmd);