drivers/net/dpaa/dpaa_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  *   Copyright 2016 Freescale Semiconductor, Inc. All rights reserved.
   4  *   Copyright 2017-2020 NXP
   5  *
   6  */
   7 /* System headers */
   8 #include <stdio.h>
   9 #include <inttypes.h>
  10 #include <unistd.h>
  11 #include <limits.h>
  12 #include <sched.h>
  13 #include <signal.h>
  14 #include <pthread.h>
  15 #include <sys/types.h>
  16 #include <sys/syscall.h>
  17
  18 #include <rte_string_fns.h>
  19 #include <rte_byteorder.h>
  20 #include <rte_common.h>
  21 #include <rte_interrupts.h>
  22 #include <rte_log.h>
  23 #include <rte_debug.h>
  24 #include <rte_pci.h>
  25 #include <rte_atomic.h>
  26 #include <rte_branch_prediction.h>
  27 #include <rte_memory.h>
  28 #include <rte_tailq.h>
  29 #include <rte_eal.h>
  30 #include <rte_alarm.h>
  31 #include <rte_ether.h>
  32 #include <rte_ethdev_driver.h>
  33 #include <rte_malloc.h>
  34 #include <rte_ring.h>
  35
  36 #include <rte_dpaa_bus.h>
  37 #include <rte_dpaa_logs.h>
  38 #include <dpaa_mempool.h>
  39
  40 #include <dpaa_ethdev.h>
  41 #include <dpaa_rxtx.h>
  42 #include <rte_pmd_dpaa.h>
  43
  44 #include <fsl_usd.h>
  45 #include <fsl_qman.h>
  46 #include <fsl_bman.h>
  47 #include <fsl_fman.h>
  48 #include <process.h>
  49
  50 /* Supported Rx offloads */
  51 static uint64_t dev_rx_offloads_sup =
  52                 DEV_RX_OFFLOAD_JUMBO_FRAME |
  53                 DEV_RX_OFFLOAD_SCATTER;
  54
  55 /* Rx offloads which cannot be disabled */
  56 static uint64_t dev_rx_offloads_nodis =
  57                 DEV_RX_OFFLOAD_IPV4_CKSUM |
  58                 DEV_RX_OFFLOAD_UDP_CKSUM |
  59                 DEV_RX_OFFLOAD_TCP_CKSUM |
  60                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
  61                 DEV_RX_OFFLOAD_RSS_HASH;
  62
  63 /* Supported Tx offloads */
  64 static uint64_t dev_tx_offloads_sup =
  65                 DEV_TX_OFFLOAD_MT_LOCKFREE |
  66                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
  67
  68 /* Tx offloads which cannot be disabled */
  69 static uint64_t dev_tx_offloads_nodis =
  70                 DEV_TX_OFFLOAD_IPV4_CKSUM |
  71                 DEV_TX_OFFLOAD_UDP_CKSUM |
  72                 DEV_TX_OFFLOAD_TCP_CKSUM |
  73                 DEV_TX_OFFLOAD_SCTP_CKSUM |
  74                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
  75                 DEV_TX_OFFLOAD_MULTI_SEGS;
  76
  77 /* Keep track of whether QMAN and BMAN have been globally initialized */
  78 static int is_global_init;
  79 static int default_q;   /* use default queue - FMC is not executed*/
  80 /* At present we only allow up to 4 push mode queues as default - as each of
  81  * this queue need dedicated portal and we are short of portals.
  82  */
  83 #define DPAA_MAX_PUSH_MODE_QUEUE       8
  84 #define DPAA_DEFAULT_PUSH_MODE_QUEUE   4
  85
  86 static int dpaa_push_mode_max_queue = DPAA_DEFAULT_PUSH_MODE_QUEUE;
  87 static int dpaa_push_queue_idx; /* Queue index which are in push mode*/
  88
  89
  90 /* Per RX FQ Taildrop in frame count */
  91 static unsigned int td_threshold = CGR_RX_PERFQ_THRESH;
  92
  93 /* Per TX FQ Taildrop in frame count, disabled by default */
  94 static unsigned int td_tx_threshold;
  95
  96 struct rte_dpaa_xstats_name_off {
  97         char name[RTE_ETH_XSTATS_NAME_SIZE];
  98         uint32_t offset;
  99 };
 100
 101 static const struct rte_dpaa_xstats_name_off dpaa_xstats_strings[] = {
 102         {"rx_align_err",
 103                 offsetof(struct dpaa_if_stats, raln)},
 104         {"rx_valid_pause",
 105                 offsetof(struct dpaa_if_stats, rxpf)},
 106         {"rx_fcs_err",
 107                 offsetof(struct dpaa_if_stats, rfcs)},
 108         {"rx_vlan_frame",
 109                 offsetof(struct dpaa_if_stats, rvlan)},
 110         {"rx_frame_err",
 111                 offsetof(struct dpaa_if_stats, rerr)},
 112         {"rx_drop_err",
 113                 offsetof(struct dpaa_if_stats, rdrp)},
 114         {"rx_undersized",
 115                 offsetof(struct dpaa_if_stats, rund)},
 116         {"rx_oversize_err",
 117                 offsetof(struct dpaa_if_stats, rovr)},
 118         {"rx_fragment_pkt",
 119                 offsetof(struct dpaa_if_stats, rfrg)},
 120         {"tx_valid_pause",
 121                 offsetof(struct dpaa_if_stats, txpf)},
 122         {"tx_fcs_err",
 123                 offsetof(struct dpaa_if_stats, terr)},
 124         {"tx_vlan_frame",
 125                 offsetof(struct dpaa_if_stats, tvlan)},
 126         {"rx_undersized",
 127                 offsetof(struct dpaa_if_stats, tund)},
 128 };
 129
 130 static struct rte_dpaa_driver rte_dpaa_pmd;
 131
 132 static int
 133 dpaa_eth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info);
 134
 135 static int dpaa_eth_link_update(struct rte_eth_dev *dev,
 136                                 int wait_to_complete __rte_unused);
 137
 138 static void dpaa_interrupt_handler(void *param);
 139
 140 static inline void
 141 dpaa_poll_queue_default_config(struct qm_mcc_initfq *opts)
 142 {
 143         memset(opts, 0, sizeof(struct qm_mcc_initfq));
 144         opts->we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
 145         opts->fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | QM_FQCTRL_CTXASTASHING |
 146                            QM_FQCTRL_PREFERINCACHE;
 147         opts->fqd.context_a.stashing.exclusive = 0;
 148         if (dpaa_svr_family != SVR_LS1046A_FAMILY)
 149                 opts->fqd.context_a.stashing.annotation_cl =
 150                                                 DPAA_IF_RX_ANNOTATION_STASH;
 151         opts->fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
 152         opts->fqd.context_a.stashing.context_cl = DPAA_IF_RX_CONTEXT_STASH;
 153 }
 154
 155 static int
 156 dpaa_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 157 {
 158         uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
 159                                 + VLAN_TAG_SIZE;
 160         uint32_t buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
 161
 162         PMD_INIT_FUNC_TRACE();
 163
 164         if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA_MAX_RX_PKT_LEN)
 165                 return -EINVAL;
 166         /*
 167          * Refuse mtu that requires the support of scattered packets
 168          * when this feature has not been enabled before.
 169          */
 170         if (dev->data->min_rx_buf_size &&
 171                 !dev->data->scattered_rx && frame_size > buffsz) {
 172                 DPAA_PMD_ERR("SG not enabled, will not fit in one buffer");
 173                 return -EINVAL;
 174         }
 175
 176         /* check <seg size> * <max_seg>  >= max_frame */
 177         if (dev->data->min_rx_buf_size && dev->data->scattered_rx &&
 178                 (frame_size > buffsz * DPAA_SGT_MAX_ENTRIES)) {
 179                 DPAA_PMD_ERR("Too big to fit for Max SG list %d",
 180                                 buffsz * DPAA_SGT_MAX_ENTRIES);
 181                 return -EINVAL;
 182         }
 183
 184         if (frame_size > RTE_ETHER_MAX_LEN)
 185                 dev->data->dev_conf.rxmode.offloads |=
 186                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 187         else
 188                 dev->data->dev_conf.rxmode.offloads &=
 189                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 190
 191         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 192
 193         fman_if_set_maxfrm(dev->process_private, frame_size);
 194
 195         return 0;
 196 }
 197
 198 static int
 199 dpaa_eth_dev_configure(struct rte_eth_dev *dev)
 200 {
 201         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 202         uint64_t rx_offloads = eth_conf->rxmode.offloads;
 203         uint64_t tx_offloads = eth_conf->txmode.offloads;
 204         struct rte_device *rdev = dev->device;
 205         struct rte_dpaa_device *dpaa_dev;
 206         struct fman_if *fif = dev->process_private;
 207         struct __fman_if *__fif;
 208         struct rte_intr_handle *intr_handle;
 209         int ret;
 210
 211         PMD_INIT_FUNC_TRACE();
 212
 213         dpaa_dev = container_of(rdev, struct rte_dpaa_device, device);
 214         intr_handle = &dpaa_dev->intr_handle;
 215         __fif = container_of(fif, struct __fman_if, __if);
 216
 217         /* Rx offloads which are enabled by default */
 218         if (dev_rx_offloads_nodis & ~rx_offloads) {
 219                 DPAA_PMD_INFO(
 220                 "Some of rx offloads enabled by default - requested 0x%" PRIx64
 221                 " fixed are 0x%" PRIx64,
 222                 rx_offloads, dev_rx_offloads_nodis);
 223         }
 224
 225         /* Tx offloads which are enabled by default */
 226         if (dev_tx_offloads_nodis & ~tx_offloads) {
 227                 DPAA_PMD_INFO(
 228                 "Some of tx offloads enabled by default - requested 0x%" PRIx64
 229                 " fixed are 0x%" PRIx64,
 230                 tx_offloads, dev_tx_offloads_nodis);
 231         }
 232
 233         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 234                 uint32_t max_len;
 235
 236                 DPAA_PMD_DEBUG("enabling jumbo");
 237
 238                 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <=
 239                     DPAA_MAX_RX_PKT_LEN)
 240                         max_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
 241                 else {
 242                         DPAA_PMD_INFO("enabling jumbo override conf max len=%d "
 243                                 "supported is %d",
 244                                 dev->data->dev_conf.rxmode.max_rx_pkt_len,
 245                                 DPAA_MAX_RX_PKT_LEN);
 246                         max_len = DPAA_MAX_RX_PKT_LEN;
 247                 }
 248
 249                 fman_if_set_maxfrm(dev->process_private, max_len);
 250                 dev->data->mtu = max_len
 251                         - RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE;
 252         }
 253
 254         if (rx_offloads & DEV_RX_OFFLOAD_SCATTER) {
 255                 DPAA_PMD_DEBUG("enabling scatter mode");
 256                 fman_if_set_sg(dev->process_private, 1);
 257                 dev->data->scattered_rx = 1;
 258         }
 259
 260         /* if the interrupts were configured on this devices*/
 261         if (intr_handle && intr_handle->fd) {
 262                 if (dev->data->dev_conf.intr_conf.lsc != 0)
 263                         rte_intr_callback_register(intr_handle,
 264                                            dpaa_interrupt_handler,
 265                                            (void *)dev);
 266
 267                 ret = dpaa_intr_enable(__fif->node_name, intr_handle->fd);
 268                 if (ret) {
 269                         if (dev->data->dev_conf.intr_conf.lsc != 0) {
 270                                 rte_intr_callback_unregister(intr_handle,
 271                                         dpaa_interrupt_handler,
 272                                         (void *)dev);
 273                                 if (ret == EINVAL)
 274                                         printf("Failed to enable interrupt: Not Supported\n");
 275                                 else
 276                                         printf("Failed to enable interrupt\n");
 277                         }
 278                         dev->data->dev_conf.intr_conf.lsc = 0;
 279                         dev->data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC;
 280                 }
 281         }
 282         return 0;
 283 }
 284
 285 static const uint32_t *
 286 dpaa_supported_ptypes_get(struct rte_eth_dev *dev)
 287 {
 288         static const uint32_t ptypes[] = {
 289                 RTE_PTYPE_L2_ETHER,
 290                 RTE_PTYPE_L2_ETHER_VLAN,
 291                 RTE_PTYPE_L2_ETHER_ARP,
 292                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
 293                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
 294                 RTE_PTYPE_L4_ICMP,
 295                 RTE_PTYPE_L4_TCP,
 296                 RTE_PTYPE_L4_UDP,
 297                 RTE_PTYPE_L4_FRAG,
 298                 RTE_PTYPE_L4_TCP,
 299                 RTE_PTYPE_L4_UDP,
 300                 RTE_PTYPE_L4_SCTP
 301         };
 302
 303         PMD_INIT_FUNC_TRACE();
 304
 305         if (dev->rx_pkt_burst == dpaa_eth_queue_rx)
 306                 return ptypes;
 307         return NULL;
 308 }
 309
 310 static void dpaa_interrupt_handler(void *param)
 311 {
 312         struct rte_eth_dev *dev = param;
 313         struct rte_device *rdev = dev->device;
 314         struct rte_dpaa_device *dpaa_dev;
 315         struct rte_intr_handle *intr_handle;
 316         uint64_t buf;
 317         int bytes_read;
 318
 319         dpaa_dev = container_of(rdev, struct rte_dpaa_device, device);
 320         intr_handle = &dpaa_dev->intr_handle;
 321
 322         bytes_read = read(intr_handle->fd, &buf, sizeof(uint64_t));
 323         if (bytes_read < 0)
 324                 DPAA_PMD_ERR("Error reading eventfd\n");
 325         dpaa_eth_link_update(dev, 0);
 326         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
 327 }
 328
 329 static int dpaa_eth_dev_start(struct rte_eth_dev *dev)
 330 {
 331         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 332
 333         PMD_INIT_FUNC_TRACE();
 334
 335         /* Change tx callback to the real one */
 336         if (dpaa_intf->cgr_tx)
 337                 dev->tx_pkt_burst = dpaa_eth_queue_tx_slow;
 338         else
 339                 dev->tx_pkt_burst = dpaa_eth_queue_tx;
 340
 341         fman_if_enable_rx(dev->process_private);
 342
 343         return 0;
 344 }
 345
 346 static void dpaa_eth_dev_stop(struct rte_eth_dev *dev)
 347 {
 348         struct fman_if *fif = dev->process_private;
 349
 350         PMD_INIT_FUNC_TRACE();
 351
 352         fman_if_disable_rx(fif);
 353         dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
 354 }
 355
 356 static void dpaa_eth_dev_close(struct rte_eth_dev *dev)
 357 {
 358         struct fman_if *fif = dev->process_private;
 359         struct __fman_if *__fif;
 360         struct rte_device *rdev = dev->device;
 361         struct rte_dpaa_device *dpaa_dev;
 362         struct rte_intr_handle *intr_handle;
 363
 364         PMD_INIT_FUNC_TRACE();
 365
 366         dpaa_dev = container_of(rdev, struct rte_dpaa_device, device);
 367         intr_handle = &dpaa_dev->intr_handle;
 368         __fif = container_of(fif, struct __fman_if, __if);
 369
 370         dpaa_eth_dev_stop(dev);
 371
 372         if (intr_handle && intr_handle->fd &&
 373             dev->data->dev_conf.intr_conf.lsc != 0) {
 374                 dpaa_intr_disable(__fif->node_name);
 375                 rte_intr_callback_unregister(intr_handle,
 376                                              dpaa_interrupt_handler,
 377                                              (void *)dev);
 378         }
 379 }
 380
 381 static int
 382 dpaa_fw_version_get(struct rte_eth_dev *dev __rte_unused,
 383                      char *fw_version,
 384                      size_t fw_size)
 385 {
 386         int ret;
 387         FILE *svr_file = NULL;
 388         unsigned int svr_ver = 0;
 389
 390         PMD_INIT_FUNC_TRACE();
 391
 392         svr_file = fopen(DPAA_SOC_ID_FILE, "r");
 393         if (!svr_file) {
 394                 DPAA_PMD_ERR("Unable to open SoC device");
 395                 return -ENOTSUP; /* Not supported on this infra */
 396         }
 397         if (fscanf(svr_file, "svr:%x", &svr_ver) > 0)
 398                 dpaa_svr_family = svr_ver & SVR_MASK;
 399         else
 400                 DPAA_PMD_ERR("Unable to read SoC device");
 401
 402         fclose(svr_file);
 403
 404         ret = snprintf(fw_version, fw_size, "SVR:%x-fman-v%x",
 405                        svr_ver, fman_ip_rev);
 406         ret += 1; /* add the size of '\0' */
 407
 408         if (fw_size < (uint32_t)ret)
 409                 return ret;
 410         else
 411                 return 0;
 412 }
 413
 414 static int dpaa_eth_dev_info(struct rte_eth_dev *dev,
 415                              struct rte_eth_dev_info *dev_info)
 416 {
 417         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 418         struct fman_if *fif = dev->process_private;
 419
 420         DPAA_PMD_DEBUG(": %s", dpaa_intf->name);
 421
 422         dev_info->max_rx_queues = dpaa_intf->nb_rx_queues;
 423         dev_info->max_tx_queues = dpaa_intf->nb_tx_queues;
 424         dev_info->max_rx_pktlen = DPAA_MAX_RX_PKT_LEN;
 425         dev_info->max_mac_addrs = DPAA_MAX_MAC_FILTER;
 426         dev_info->max_hash_mac_addrs = 0;
 427         dev_info->max_vfs = 0;
 428         dev_info->max_vmdq_pools = ETH_16_POOLS;
 429         dev_info->flow_type_rss_offloads = DPAA_RSS_OFFLOAD_ALL;
 430
 431         if (fif->mac_type == fman_mac_1g) {
 432                 dev_info->speed_capa = ETH_LINK_SPEED_1G;
 433         } else if (fif->mac_type == fman_mac_2_5g) {
 434                 dev_info->speed_capa = ETH_LINK_SPEED_1G
 435                                         | ETH_LINK_SPEED_2_5G;
 436         } else if (fif->mac_type == fman_mac_10g) {
 437                 dev_info->speed_capa = ETH_LINK_SPEED_1G
 438                                         | ETH_LINK_SPEED_2_5G
 439                                         | ETH_LINK_SPEED_10G;
 440         } else {
 441                 DPAA_PMD_ERR("invalid link_speed: %s, %d",
 442                              dpaa_intf->name, fif->mac_type);
 443                 return -EINVAL;
 444         }
 445
 446         dev_info->rx_offload_capa = dev_rx_offloads_sup |
 447                                         dev_rx_offloads_nodis;
 448         dev_info->tx_offload_capa = dev_tx_offloads_sup |
 449                                         dev_tx_offloads_nodis;
 450         dev_info->default_rxportconf.burst_size = DPAA_DEF_RX_BURST_SIZE;
 451         dev_info->default_txportconf.burst_size = DPAA_DEF_TX_BURST_SIZE;
 452         dev_info->default_rxportconf.nb_queues = 1;
 453         dev_info->default_txportconf.nb_queues = 1;
 454         dev_info->default_txportconf.ring_size = CGR_TX_CGR_THRESH;
 455         dev_info->default_rxportconf.ring_size = CGR_RX_PERFQ_THRESH;
 456
 457         return 0;
 458 }
 459
 460 static int dpaa_eth_link_update(struct rte_eth_dev *dev,
 461                                 int wait_to_complete __rte_unused)
 462 {
 463         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 464         struct rte_eth_link *link = &dev->data->dev_link;
 465         struct fman_if *fif = dev->process_private;
 466         struct __fman_if *__fif = container_of(fif, struct __fman_if, __if);
 467         int ret;
 468
 469         PMD_INIT_FUNC_TRACE();
 470
 471         if (fif->mac_type == fman_mac_1g)
 472                 link->link_speed = ETH_SPEED_NUM_1G;
 473         else if (fif->mac_type == fman_mac_2_5g)
 474                 link->link_speed = ETH_SPEED_NUM_2_5G;
 475         else if (fif->mac_type == fman_mac_10g)
 476                 link->link_speed = ETH_SPEED_NUM_10G;
 477         else
 478                 DPAA_PMD_ERR("invalid link_speed: %s, %d",
 479                              dpaa_intf->name, fif->mac_type);
 480
 481         ret = dpaa_get_link_status(__fif->node_name);
 482         if (ret < 0) {
 483                 if (ret == -EINVAL) {
 484                         DPAA_PMD_DEBUG("Using default link status-No Support");
 485                         ret = 1;
 486                 } else {
 487                         DPAA_PMD_ERR("rte_dpaa_get_link_status %d", ret);
 488                         return ret;
 489                 }
 490         }
 491
 492         link->link_status = ret;
 493         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 494         link->link_autoneg = ETH_LINK_AUTONEG;
 495
 496         DPAA_PMD_INFO("Port %d Link is %s\n", dev->data->port_id,
 497                       link->link_status ? "Up" : "Down");
 498         return 0;
 499 }
 500
 501 static int dpaa_eth_stats_get(struct rte_eth_dev *dev,
 502                                struct rte_eth_stats *stats)
 503 {
 504         PMD_INIT_FUNC_TRACE();
 505
 506         fman_if_stats_get(dev->process_private, stats);
 507         return 0;
 508 }
 509
 510 static int dpaa_eth_stats_reset(struct rte_eth_dev *dev)
 511 {
 512         PMD_INIT_FUNC_TRACE();
 513
 514         fman_if_stats_reset(dev->process_private);
 515
 516         return 0;
 517 }
 518
 519 static int
 520 dpaa_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
 521                     unsigned int n)
 522 {
 523         unsigned int i = 0, num = RTE_DIM(dpaa_xstats_strings);
 524         uint64_t values[sizeof(struct dpaa_if_stats) / 8];
 525
 526         if (n < num)
 527                 return num;
 528
 529         if (xstats == NULL)
 530                 return 0;
 531
 532         fman_if_stats_get_all(dev->process_private, values,
 533                               sizeof(struct dpaa_if_stats) / 8);
 534
 535         for (i = 0; i < num; i++) {
 536                 xstats[i].id = i;
 537                 xstats[i].value = values[dpaa_xstats_strings[i].offset / 8];
 538         }
 539         return i;
 540 }
 541
 542 static int
 543 dpaa_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 544                       struct rte_eth_xstat_name *xstats_names,
 545                       unsigned int limit)
 546 {
 547         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 548
 549         if (limit < stat_cnt)
 550                 return stat_cnt;
 551
 552         if (xstats_names != NULL)
 553                 for (i = 0; i < stat_cnt; i++)
 554                         strlcpy(xstats_names[i].name,
 555                                 dpaa_xstats_strings[i].name,
 556                                 sizeof(xstats_names[i].name));
 557
 558         return stat_cnt;
 559 }
 560
 561 static int
 562 dpaa_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 563                       uint64_t *values, unsigned int n)
 564 {
 565         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 566         uint64_t values_copy[sizeof(struct dpaa_if_stats) / 8];
 567
 568         if (!ids) {
 569                 if (n < stat_cnt)
 570                         return stat_cnt;
 571
 572                 if (!values)
 573                         return 0;
 574
 575                 fman_if_stats_get_all(dev->process_private, values_copy,
 576                                       sizeof(struct dpaa_if_stats) / 8);
 577
 578                 for (i = 0; i < stat_cnt; i++)
 579                         values[i] =
 580                                 values_copy[dpaa_xstats_strings[i].offset / 8];
 581
 582                 return stat_cnt;
 583         }
 584
 585         dpaa_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
 586
 587         for (i = 0; i < n; i++) {
 588                 if (ids[i] >= stat_cnt) {
 589                         DPAA_PMD_ERR("id value isn't valid");
 590                         return -1;
 591                 }
 592                 values[i] = values_copy[ids[i]];
 593         }
 594         return n;
 595 }
 596
 597 static int
 598 dpaa_xstats_get_names_by_id(
 599         struct rte_eth_dev *dev,
 600         struct rte_eth_xstat_name *xstats_names,
 601         const uint64_t *ids,
 602         unsigned int limit)
 603 {
 604         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 605         struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
 606
 607         if (!ids)
 608                 return dpaa_xstats_get_names(dev, xstats_names, limit);
 609
 610         dpaa_xstats_get_names(dev, xstats_names_copy, limit);
 611
 612         for (i = 0; i < limit; i++) {
 613                 if (ids[i] >= stat_cnt) {
 614                         DPAA_PMD_ERR("id value isn't valid");
 615                         return -1;
 616                 }
 617                 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
 618         }
 619         return limit;
 620 }
 621
 622 static int dpaa_eth_promiscuous_enable(struct rte_eth_dev *dev)
 623 {
 624         PMD_INIT_FUNC_TRACE();
 625
 626         fman_if_promiscuous_enable(dev->process_private);
 627
 628         return 0;
 629 }
 630
 631 static int dpaa_eth_promiscuous_disable(struct rte_eth_dev *dev)
 632 {
 633         PMD_INIT_FUNC_TRACE();
 634
 635         fman_if_promiscuous_disable(dev->process_private);
 636
 637         return 0;
 638 }
 639
 640 static int dpaa_eth_multicast_enable(struct rte_eth_dev *dev)
 641 {
 642         PMD_INIT_FUNC_TRACE();
 643
 644         fman_if_set_mcast_filter_table(dev->process_private);
 645
 646         return 0;
 647 }
 648
 649 static int dpaa_eth_multicast_disable(struct rte_eth_dev *dev)
 650 {
 651         PMD_INIT_FUNC_TRACE();
 652
 653         fman_if_reset_mcast_filter_table(dev->process_private);
 654
 655         return 0;
 656 }
 657
 658 static
 659 int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 660                             uint16_t nb_desc,
 661                             unsigned int socket_id __rte_unused,
 662                             const struct rte_eth_rxconf *rx_conf __rte_unused,
 663                             struct rte_mempool *mp)
 664 {
 665         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 666         struct fman_if *fif = dev->process_private;
 667         struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_idx];
 668         struct qm_mcc_initfq opts = {0};
 669         u32 flags = 0;
 670         int ret;
 671         u32 buffsz = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
 672
 673         PMD_INIT_FUNC_TRACE();
 674
 675         if (queue_idx >= dev->data->nb_rx_queues) {
 676                 rte_errno = EOVERFLOW;
 677                 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
 678                       (void *)dev, queue_idx, dev->data->nb_rx_queues);
 679                 return -rte_errno;
 680         }
 681
 682         DPAA_PMD_INFO("Rx queue setup for queue index: %d fq_id (0x%x)",
 683                         queue_idx, rxq->fqid);
 684
 685         /* Max packet can fit in single buffer */
 686         if (dev->data->dev_conf.rxmode.max_rx_pkt_len <= buffsz) {
 687                 ;
 688         } else if (dev->data->dev_conf.rxmode.offloads &
 689                         DEV_RX_OFFLOAD_SCATTER) {
 690                 if (dev->data->dev_conf.rxmode.max_rx_pkt_len >
 691                         buffsz * DPAA_SGT_MAX_ENTRIES) {
 692                         DPAA_PMD_ERR("max RxPkt size %d too big to fit "
 693                                 "MaxSGlist %d",
 694                                 dev->data->dev_conf.rxmode.max_rx_pkt_len,
 695                                 buffsz * DPAA_SGT_MAX_ENTRIES);
 696                         rte_errno = EOVERFLOW;
 697                         return -rte_errno;
 698                 }
 699         } else {
 700                 DPAA_PMD_WARN("The requested maximum Rx packet size (%u) is"
 701                      " larger than a single mbuf (%u) and scattered"
 702                      " mode has not been requested",
 703                      dev->data->dev_conf.rxmode.max_rx_pkt_len,
 704                      buffsz - RTE_PKTMBUF_HEADROOM);
 705         }
 706
 707         if (!dpaa_intf->bp_info || dpaa_intf->bp_info->mp != mp) {
 708                 struct fman_if_ic_params icp;
 709                 uint32_t fd_offset;
 710                 uint32_t bp_size;
 711
 712                 if (!mp->pool_data) {
 713                         DPAA_PMD_ERR("Not an offloaded buffer pool!");
 714                         return -1;
 715                 }
 716                 dpaa_intf->bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp);
 717
 718                 memset(&icp, 0, sizeof(icp));
 719                 /* set ICEOF for to the default value , which is 0*/
 720                 icp.iciof = DEFAULT_ICIOF;
 721                 icp.iceof = DEFAULT_RX_ICEOF;
 722                 icp.icsz = DEFAULT_ICSZ;
 723                 fman_if_set_ic_params(fif, &icp);
 724
 725                 fd_offset = RTE_PKTMBUF_HEADROOM + DPAA_HW_BUF_RESERVE;
 726                 fman_if_set_fdoff(fif, fd_offset);
 727
 728                 /* Buffer pool size should be equal to Dataroom Size*/
 729                 bp_size = rte_pktmbuf_data_room_size(mp);
 730                 fman_if_set_bp(fif, mp->size,
 731                                dpaa_intf->bp_info->bpid, bp_size);
 732                 dpaa_intf->valid = 1;
 733                 DPAA_PMD_DEBUG("if:%s fd_offset = %d offset = %d",
 734                                 dpaa_intf->name, fd_offset,
 735                                 fman_if_get_fdoff(fif));
 736         }
 737         DPAA_PMD_DEBUG("if:%s sg_on = %d, max_frm =%d", dpaa_intf->name,
 738                 fman_if_get_sg_enable(fif),
 739                 dev->data->dev_conf.rxmode.max_rx_pkt_len);
 740         /* checking if push mode only, no error check for now */
 741         if (!rxq->is_static &&
 742             dpaa_push_mode_max_queue > dpaa_push_queue_idx) {
 743                 struct qman_portal *qp;
 744                 int q_fd;
 745
 746                 dpaa_push_queue_idx++;
 747                 opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
 748                 opts.fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK |
 749                                    QM_FQCTRL_CTXASTASHING |
 750                                    QM_FQCTRL_PREFERINCACHE;
 751                 opts.fqd.context_a.stashing.exclusive = 0;
 752                 /* In muticore scenario stashing becomes a bottleneck on LS1046.
 753                  * So do not enable stashing in this case
 754                  */
 755                 if (dpaa_svr_family != SVR_LS1046A_FAMILY)
 756                         opts.fqd.context_a.stashing.annotation_cl =
 757                                                 DPAA_IF_RX_ANNOTATION_STASH;
 758                 opts.fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
 759                 opts.fqd.context_a.stashing.context_cl =
 760                                                 DPAA_IF_RX_CONTEXT_STASH;
 761
 762                 /*Create a channel and associate given queue with the channel*/
 763                 qman_alloc_pool_range((u32 *)&rxq->ch_id, 1, 1, 0);
 764                 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
 765                 opts.fqd.dest.channel = rxq->ch_id;
 766                 opts.fqd.dest.wq = DPAA_IF_RX_PRIORITY;
 767                 flags = QMAN_INITFQ_FLAG_SCHED;
 768
 769                 /* Configure tail drop */
 770                 if (dpaa_intf->cgr_rx) {
 771                         opts.we_mask |= QM_INITFQ_WE_CGID;
 772                         opts.fqd.cgid = dpaa_intf->cgr_rx[queue_idx].cgrid;
 773                         opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
 774                 }
 775                 ret = qman_init_fq(rxq, flags, &opts);
 776                 if (ret) {
 777                         DPAA_PMD_ERR("Channel/Q association failed. fqid 0x%x "
 778                                 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
 779                         return ret;
 780                 }
 781                 if (dpaa_svr_family == SVR_LS1043A_FAMILY) {
 782                         rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb_no_prefetch;
 783                 } else {
 784                         rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb;
 785                         rxq->cb.dqrr_prepare = dpaa_rx_cb_prepare;
 786                 }
 787
 788                 rxq->is_static = true;
 789
 790                 /* Allocate qman specific portals */
 791                 qp = fsl_qman_fq_portal_create(&q_fd);
 792                 if (!qp) {
 793                         DPAA_PMD_ERR("Unable to alloc fq portal");
 794                         return -1;
 795                 }
 796                 rxq->qp = qp;
 797
 798                 /* Set up the device interrupt handler */
 799                 if (!dev->intr_handle) {
 800                         struct rte_dpaa_device *dpaa_dev;
 801                         struct rte_device *rdev = dev->device;
 802
 803                         dpaa_dev = container_of(rdev, struct rte_dpaa_device,
 804                                                 device);
 805                         dev->intr_handle = &dpaa_dev->intr_handle;
 806                         dev->intr_handle->intr_vec = rte_zmalloc(NULL,
 807                                         dpaa_push_mode_max_queue, 0);
 808                         if (!dev->intr_handle->intr_vec) {
 809                                 DPAA_PMD_ERR("intr_vec alloc failed");
 810                                 return -ENOMEM;
 811                         }
 812                         dev->intr_handle->nb_efd = dpaa_push_mode_max_queue;
 813                         dev->intr_handle->max_intr = dpaa_push_mode_max_queue;
 814                 }
 815
 816                 dev->intr_handle->type = RTE_INTR_HANDLE_EXT;
 817                 dev->intr_handle->intr_vec[queue_idx] = queue_idx + 1;
 818                 dev->intr_handle->efds[queue_idx] = q_fd;
 819                 rxq->q_fd = q_fd;
 820         }
 821         rxq->bp_array = rte_dpaa_bpid_info;
 822         dev->data->rx_queues[queue_idx] = rxq;
 823
 824         /* configure the CGR size as per the desc size */
 825         if (dpaa_intf->cgr_rx) {
 826                 struct qm_mcc_initcgr cgr_opts = {0};
 827
 828                 /* Enable tail drop with cgr on this queue */
 829                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, nb_desc, 0);
 830                 ret = qman_modify_cgr(dpaa_intf->cgr_rx, 0, &cgr_opts);
 831                 if (ret) {
 832                         DPAA_PMD_WARN(
 833                                 "rx taildrop modify fail on fqid %d (ret=%d)",
 834                                 rxq->fqid, ret);
 835                 }
 836         }
 837
 838         return 0;
 839 }
 840
 841 int
 842 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev,
 843                 int eth_rx_queue_id,
 844                 u16 ch_id,
 845                 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
 846 {
 847         int ret;
 848         u32 flags = 0;
 849         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 850         struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
 851         struct qm_mcc_initfq opts = {0};
 852
 853         if (dpaa_push_mode_max_queue)
 854                 DPAA_PMD_WARN("PUSH mode q and EVENTDEV are not compatible\n"
 855                               "PUSH mode already enabled for first %d queues.\n"
 856                               "To disable set DPAA_PUSH_QUEUES_NUMBER to 0\n",
 857                               dpaa_push_mode_max_queue);
 858
 859         dpaa_poll_queue_default_config(&opts);
 860
 861         switch (queue_conf->ev.sched_type) {
 862         case RTE_SCHED_TYPE_ATOMIC:
 863                 opts.fqd.fq_ctrl |= QM_FQCTRL_HOLDACTIVE;
 864                 /* Reset FQCTRL_AVOIDBLOCK bit as it is unnecessary
 865                  * configuration with HOLD_ACTIVE setting
 866                  */
 867                 opts.fqd.fq_ctrl &= (~QM_FQCTRL_AVOIDBLOCK);
 868                 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_atomic;
 869                 break;
 870         case RTE_SCHED_TYPE_ORDERED:
 871                 DPAA_PMD_ERR("Ordered queue schedule type is not supported\n");
 872                 return -1;
 873         default:
 874                 opts.fqd.fq_ctrl |= QM_FQCTRL_AVOIDBLOCK;
 875                 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_parallel;
 876                 break;
 877         }
 878
 879         opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
 880         opts.fqd.dest.channel = ch_id;
 881         opts.fqd.dest.wq = queue_conf->ev.priority;
 882
 883         if (dpaa_intf->cgr_rx) {
 884                 opts.we_mask |= QM_INITFQ_WE_CGID;
 885                 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
 886                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
 887         }
 888
 889         flags = QMAN_INITFQ_FLAG_SCHED;
 890
 891         ret = qman_init_fq(rxq, flags, &opts);
 892         if (ret) {
 893                 DPAA_PMD_ERR("Ev-Channel/Q association failed. fqid 0x%x "
 894                                 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
 895                 return ret;
 896         }
 897
 898         /* copy configuration which needs to be filled during dequeue */
 899         memcpy(&rxq->ev, &queue_conf->ev, sizeof(struct rte_event));
 900         dev->data->rx_queues[eth_rx_queue_id] = rxq;
 901
 902         return ret;
 903 }
 904
 905 int
 906 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev,
 907                 int eth_rx_queue_id)
 908 {
 909         struct qm_mcc_initfq opts;
 910         int ret;
 911         u32 flags = 0;
 912         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 913         struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
 914
 915         dpaa_poll_queue_default_config(&opts);
 916
 917         if (dpaa_intf->cgr_rx) {
 918                 opts.we_mask |= QM_INITFQ_WE_CGID;
 919                 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
 920                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
 921         }
 922
 923         ret = qman_init_fq(rxq, flags, &opts);
 924         if (ret) {
 925                 DPAA_PMD_ERR("init rx fqid %d failed with ret: %d",
 926                              rxq->fqid, ret);
 927         }
 928
 929         rxq->cb.dqrr_dpdk_cb = NULL;
 930         dev->data->rx_queues[eth_rx_queue_id] = NULL;
 931
 932         return 0;
 933 }
 934
 935 static
 936 void dpaa_eth_rx_queue_release(void *rxq __rte_unused)
 937 {
 938         PMD_INIT_FUNC_TRACE();
 939 }
 940
 941 static
 942 int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 943                             uint16_t nb_desc __rte_unused,
 944                 unsigned int socket_id __rte_unused,
 945                 const struct rte_eth_txconf *tx_conf __rte_unused)
 946 {
 947         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 948
 949         PMD_INIT_FUNC_TRACE();
 950
 951         if (queue_idx >= dev->data->nb_tx_queues) {
 952                 rte_errno = EOVERFLOW;
 953                 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
 954                       (void *)dev, queue_idx, dev->data->nb_tx_queues);
 955                 return -rte_errno;
 956         }
 957
 958         DPAA_PMD_INFO("Tx queue setup for queue index: %d fq_id (0x%x)",
 959                         queue_idx, dpaa_intf->tx_queues[queue_idx].fqid);
 960         dev->data->tx_queues[queue_idx] = &dpaa_intf->tx_queues[queue_idx];
 961
 962         return 0;
 963 }
 964
 965 static void dpaa_eth_tx_queue_release(void *txq __rte_unused)
 966 {
 967         PMD_INIT_FUNC_TRACE();
 968 }
 969
 970 static uint32_t
 971 dpaa_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 972 {
 973         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 974         struct qman_fq *rxq = &dpaa_intf->rx_queues[rx_queue_id];
 975         u32 frm_cnt = 0;
 976
 977         PMD_INIT_FUNC_TRACE();
 978
 979         if (qman_query_fq_frm_cnt(rxq, &frm_cnt) == 0) {
 980                 DPAA_PMD_DEBUG("RX frame count for q(%d) is %u",
 981                                rx_queue_id, frm_cnt);
 982         }
 983         return frm_cnt;
 984 }
 985
 986 static int dpaa_link_down(struct rte_eth_dev *dev)
 987 {
 988         PMD_INIT_FUNC_TRACE();
 989
 990         dpaa_eth_dev_stop(dev);
 991         return 0;
 992 }
 993
 994 static int dpaa_link_up(struct rte_eth_dev *dev)
 995 {
 996         PMD_INIT_FUNC_TRACE();
 997
 998         dpaa_eth_dev_start(dev);
 999         return 0;
1000 }
1001
1002 static int
1003 dpaa_flow_ctrl_set(struct rte_eth_dev *dev,
1004                    struct rte_eth_fc_conf *fc_conf)
1005 {
1006         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1007         struct rte_eth_fc_conf *net_fc;
1008
1009         PMD_INIT_FUNC_TRACE();
1010
1011         if (!(dpaa_intf->fc_conf)) {
1012                 dpaa_intf->fc_conf = rte_zmalloc(NULL,
1013                         sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
1014                 if (!dpaa_intf->fc_conf) {
1015                         DPAA_PMD_ERR("unable to save flow control info");
1016                         return -ENOMEM;
1017                 }
1018         }
1019         net_fc = dpaa_intf->fc_conf;
1020
1021         if (fc_conf->high_water < fc_conf->low_water) {
1022                 DPAA_PMD_ERR("Incorrect Flow Control Configuration");
1023                 return -EINVAL;
1024         }
1025
1026         if (fc_conf->mode == RTE_FC_NONE) {
1027                 return 0;
1028         } else if (fc_conf->mode == RTE_FC_TX_PAUSE ||
1029                  fc_conf->mode == RTE_FC_FULL) {
1030                 fman_if_set_fc_threshold(dev->process_private,
1031                                          fc_conf->high_water,
1032                                          fc_conf->low_water,
1033                                          dpaa_intf->bp_info->bpid);
1034                 if (fc_conf->pause_time)
1035                         fman_if_set_fc_quanta(dev->process_private,
1036                                               fc_conf->pause_time);
1037         }
1038
1039         /* Save the information in dpaa device */
1040         net_fc->pause_time = fc_conf->pause_time;
1041         net_fc->high_water = fc_conf->high_water;
1042         net_fc->low_water = fc_conf->low_water;
1043         net_fc->send_xon = fc_conf->send_xon;
1044         net_fc->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
1045         net_fc->mode = fc_conf->mode;
1046         net_fc->autoneg = fc_conf->autoneg;
1047
1048         return 0;
1049 }
1050
1051 static int
1052 dpaa_flow_ctrl_get(struct rte_eth_dev *dev,
1053                    struct rte_eth_fc_conf *fc_conf)
1054 {
1055         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1056         struct rte_eth_fc_conf *net_fc = dpaa_intf->fc_conf;
1057         int ret;
1058
1059         PMD_INIT_FUNC_TRACE();
1060
1061         if (net_fc) {
1062                 fc_conf->pause_time = net_fc->pause_time;
1063                 fc_conf->high_water = net_fc->high_water;
1064                 fc_conf->low_water = net_fc->low_water;
1065                 fc_conf->send_xon = net_fc->send_xon;
1066                 fc_conf->mac_ctrl_frame_fwd = net_fc->mac_ctrl_frame_fwd;
1067                 fc_conf->mode = net_fc->mode;
1068                 fc_conf->autoneg = net_fc->autoneg;
1069                 return 0;
1070         }
1071         ret = fman_if_get_fc_threshold(dev->process_private);
1072         if (ret) {
1073                 fc_conf->mode = RTE_FC_TX_PAUSE;
1074                 fc_conf->pause_time =
1075                         fman_if_get_fc_quanta(dev->process_private);
1076         } else {
1077                 fc_conf->mode = RTE_FC_NONE;
1078         }
1079
1080         return 0;
1081 }
1082
1083 static int
1084 dpaa_dev_add_mac_addr(struct rte_eth_dev *dev,
1085                              struct rte_ether_addr *addr,
1086                              uint32_t index,
1087                              __rte_unused uint32_t pool)
1088 {
1089         int ret;
1090
1091         PMD_INIT_FUNC_TRACE();
1092
1093         ret = fman_if_add_mac_addr(dev->process_private,
1094                                    addr->addr_bytes, index);
1095
1096         if (ret)
1097                 DPAA_PMD_ERR("Adding the MAC ADDR failed: err = %d", ret);
1098         return 0;
1099 }
1100
1101 static void
1102 dpaa_dev_remove_mac_addr(struct rte_eth_dev *dev,
1103                           uint32_t index)
1104 {
1105         PMD_INIT_FUNC_TRACE();
1106
1107         fman_if_clear_mac_addr(dev->process_private, index);
1108 }
1109
1110 static int
1111 dpaa_dev_set_mac_addr(struct rte_eth_dev *dev,
1112                        struct rte_ether_addr *addr)
1113 {
1114         int ret;
1115
1116         PMD_INIT_FUNC_TRACE();
1117
1118         ret = fman_if_add_mac_addr(dev->process_private, addr->addr_bytes, 0);
1119         if (ret)
1120                 DPAA_PMD_ERR("Setting the MAC ADDR failed %d", ret);
1121
1122         return ret;
1123 }
1124
1125 static int dpaa_dev_queue_intr_enable(struct rte_eth_dev *dev,
1126                                       uint16_t queue_id)
1127 {
1128         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1129         struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id];
1130
1131         if (!rxq->is_static)
1132                 return -EINVAL;
1133
1134         return qman_fq_portal_irqsource_add(rxq->qp, QM_PIRQ_DQRI);
1135 }
1136
1137 static int dpaa_dev_queue_intr_disable(struct rte_eth_dev *dev,
1138                                        uint16_t queue_id)
1139 {
1140         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1141         struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id];
1142         uint32_t temp;
1143         ssize_t temp1;
1144
1145         if (!rxq->is_static)
1146                 return -EINVAL;
1147
1148         qman_fq_portal_irqsource_remove(rxq->qp, ~0);
1149
1150         temp1 = read(rxq->q_fd, &temp, sizeof(temp));
1151         if (temp1 != sizeof(temp))
1152                 DPAA_PMD_ERR("irq read error");
1153
1154         qman_fq_portal_thread_irq(rxq->qp);
1155
1156         return 0;
1157 }
1158
1159 static struct eth_dev_ops dpaa_devops = {
1160         .dev_configure            = dpaa_eth_dev_configure,
1161         .dev_start                = dpaa_eth_dev_start,
1162         .dev_stop                 = dpaa_eth_dev_stop,
1163         .dev_close                = dpaa_eth_dev_close,
1164         .dev_infos_get            = dpaa_eth_dev_info,
1165         .dev_supported_ptypes_get = dpaa_supported_ptypes_get,
1166
1167         .rx_queue_setup           = dpaa_eth_rx_queue_setup,
1168         .tx_queue_setup           = dpaa_eth_tx_queue_setup,
1169         .rx_queue_release         = dpaa_eth_rx_queue_release,
1170         .tx_queue_release         = dpaa_eth_tx_queue_release,
1171         .rx_queue_count           = dpaa_dev_rx_queue_count,
1172
1173         .flow_ctrl_get            = dpaa_flow_ctrl_get,
1174         .flow_ctrl_set            = dpaa_flow_ctrl_set,
1175
1176         .link_update              = dpaa_eth_link_update,
1177         .stats_get                = dpaa_eth_stats_get,
1178         .xstats_get               = dpaa_dev_xstats_get,
1179         .xstats_get_by_id         = dpaa_xstats_get_by_id,
1180         .xstats_get_names_by_id   = dpaa_xstats_get_names_by_id,
1181         .xstats_get_names         = dpaa_xstats_get_names,
1182         .xstats_reset             = dpaa_eth_stats_reset,
1183         .stats_reset              = dpaa_eth_stats_reset,
1184         .promiscuous_enable       = dpaa_eth_promiscuous_enable,
1185         .promiscuous_disable      = dpaa_eth_promiscuous_disable,
1186         .allmulticast_enable      = dpaa_eth_multicast_enable,
1187         .allmulticast_disable     = dpaa_eth_multicast_disable,
1188         .mtu_set                  = dpaa_mtu_set,
1189         .dev_set_link_down        = dpaa_link_down,
1190         .dev_set_link_up          = dpaa_link_up,
1191         .mac_addr_add             = dpaa_dev_add_mac_addr,
1192         .mac_addr_remove          = dpaa_dev_remove_mac_addr,
1193         .mac_addr_set             = dpaa_dev_set_mac_addr,
1194
1195         .fw_version_get           = dpaa_fw_version_get,
1196
1197         .rx_queue_intr_enable     = dpaa_dev_queue_intr_enable,
1198         .rx_queue_intr_disable    = dpaa_dev_queue_intr_disable,
1199 };
1200
1201 static bool
1202 is_device_supported(struct rte_eth_dev *dev, struct rte_dpaa_driver *drv)
1203 {
1204         if (strcmp(dev->device->driver->name,
1205                    drv->driver.name))
1206                 return false;
1207
1208         return true;
1209 }
1210
1211 static bool
1212 is_dpaa_supported(struct rte_eth_dev *dev)
1213 {
1214         return is_device_supported(dev, &rte_dpaa_pmd);
1215 }
1216
1217 int
1218 rte_pmd_dpaa_set_tx_loopback(uint8_t port, uint8_t on)
1219 {
1220         struct rte_eth_dev *dev;
1221
1222         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
1223
1224         dev = &rte_eth_devices[port];
1225
1226         if (!is_dpaa_supported(dev))
1227                 return -ENOTSUP;
1228
1229         if (on)
1230                 fman_if_loopback_enable(dev->process_private);
1231         else
1232                 fman_if_loopback_disable(dev->process_private);
1233
1234         return 0;
1235 }
1236
1237 static int dpaa_fc_set_default(struct dpaa_if *dpaa_intf,
1238                                struct fman_if *fman_intf)
1239 {
1240         struct rte_eth_fc_conf *fc_conf;
1241         int ret;
1242
1243         PMD_INIT_FUNC_TRACE();
1244
1245         if (!(dpaa_intf->fc_conf)) {
1246                 dpaa_intf->fc_conf = rte_zmalloc(NULL,
1247                         sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
1248                 if (!dpaa_intf->fc_conf) {
1249                         DPAA_PMD_ERR("unable to save flow control info");
1250                         return -ENOMEM;
1251                 }
1252         }
1253         fc_conf = dpaa_intf->fc_conf;
1254         ret = fman_if_get_fc_threshold(fman_intf);
1255         if (ret) {
1256                 fc_conf->mode = RTE_FC_TX_PAUSE;
1257                 fc_conf->pause_time = fman_if_get_fc_quanta(fman_intf);
1258         } else {
1259                 fc_conf->mode = RTE_FC_NONE;
1260         }
1261
1262         return 0;
1263 }
1264
1265 /* Initialise an Rx FQ */
1266 static int dpaa_rx_queue_init(struct qman_fq *fq, struct qman_cgr *cgr_rx,
1267                               uint32_t fqid)
1268 {
1269         struct qm_mcc_initfq opts = {0};
1270         int ret;
1271         u32 flags = QMAN_FQ_FLAG_NO_ENQUEUE;
1272         struct qm_mcc_initcgr cgr_opts = {
1273                 .we_mask = QM_CGR_WE_CS_THRES |
1274                                 QM_CGR_WE_CSTD_EN |
1275                                 QM_CGR_WE_MODE,
1276                 .cgr = {
1277                         .cstd_en = QM_CGR_EN,
1278                         .mode = QMAN_CGR_MODE_FRAME
1279                 }
1280         };
1281
1282         if (fqid) {
1283                 ret = qman_reserve_fqid(fqid);
1284                 if (ret) {
1285                         DPAA_PMD_ERR("reserve rx fqid 0x%x failed with ret: %d",
1286                                      fqid, ret);
1287                         return -EINVAL;
1288                 }
1289         } else {
1290                 flags |= QMAN_FQ_FLAG_DYNAMIC_FQID;
1291         }
1292         DPAA_PMD_DEBUG("creating rx fq %p, fqid 0x%x", fq, fqid);
1293         ret = qman_create_fq(fqid, flags, fq);
1294         if (ret) {
1295                 DPAA_PMD_ERR("create rx fqid 0x%x failed with ret: %d",
1296                         fqid, ret);
1297                 return ret;
1298         }
1299         fq->is_static = false;
1300
1301         dpaa_poll_queue_default_config(&opts);
1302
1303         if (cgr_rx) {
1304                 /* Enable tail drop with cgr on this queue */
1305                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, td_threshold, 0);
1306                 cgr_rx->cb = NULL;
1307                 ret = qman_create_cgr(cgr_rx, QMAN_CGR_FLAG_USE_INIT,
1308                                       &cgr_opts);
1309                 if (ret) {
1310                         DPAA_PMD_WARN(
1311                                 "rx taildrop init fail on rx fqid 0x%x(ret=%d)",
1312                                 fq->fqid, ret);
1313                         goto without_cgr;
1314                 }
1315                 opts.we_mask |= QM_INITFQ_WE_CGID;
1316                 opts.fqd.cgid = cgr_rx->cgrid;
1317                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1318         }
1319 without_cgr:
1320         ret = qman_init_fq(fq, 0, &opts);
1321         if (ret)
1322                 DPAA_PMD_ERR("init rx fqid 0x%x failed with ret:%d", fqid, ret);
1323         return ret;
1324 }
1325
1326 /* Initialise a Tx FQ */
1327 static int dpaa_tx_queue_init(struct qman_fq *fq,
1328                               struct fman_if *fman_intf,
1329                               struct qman_cgr *cgr_tx)
1330 {
1331         struct qm_mcc_initfq opts = {0};
1332         struct qm_mcc_initcgr cgr_opts = {
1333                 .we_mask = QM_CGR_WE_CS_THRES |
1334                                 QM_CGR_WE_CSTD_EN |
1335                                 QM_CGR_WE_MODE,
1336                 .cgr = {
1337                         .cstd_en = QM_CGR_EN,
1338                         .mode = QMAN_CGR_MODE_FRAME
1339                 }
1340         };
1341         int ret;
1342
1343         ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID |
1344                              QMAN_FQ_FLAG_TO_DCPORTAL, fq);
1345         if (ret) {
1346                 DPAA_PMD_ERR("create tx fq failed with ret: %d", ret);
1347                 return ret;
1348         }
1349         opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL |
1350                        QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA;
1351         opts.fqd.dest.channel = fman_intf->tx_channel_id;
1352         opts.fqd.dest.wq = DPAA_IF_TX_PRIORITY;
1353         opts.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE;
1354         opts.fqd.context_b = 0;
1355         /* no tx-confirmation */
1356         opts.fqd.context_a.hi = 0x80000000 | fman_dealloc_bufs_mask_hi;
1357         opts.fqd.context_a.lo = 0 | fman_dealloc_bufs_mask_lo;
1358         DPAA_PMD_DEBUG("init tx fq %p, fqid 0x%x", fq, fq->fqid);
1359
1360         if (cgr_tx) {
1361                 /* Enable tail drop with cgr on this queue */
1362                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres,
1363                                       td_tx_threshold, 0);
1364                 cgr_tx->cb = NULL;
1365                 ret = qman_create_cgr(cgr_tx, QMAN_CGR_FLAG_USE_INIT,
1366                                       &cgr_opts);
1367                 if (ret) {
1368                         DPAA_PMD_WARN(
1369                                 "rx taildrop init fail on rx fqid 0x%x(ret=%d)",
1370                                 fq->fqid, ret);
1371                         goto without_cgr;
1372                 }
1373                 opts.we_mask |= QM_INITFQ_WE_CGID;
1374                 opts.fqd.cgid = cgr_tx->cgrid;
1375                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1376                 DPAA_PMD_DEBUG("Tx FQ tail drop enabled, threshold = %d\n",
1377                                 td_tx_threshold);
1378         }
1379 without_cgr:
1380         ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts);
1381         if (ret)
1382                 DPAA_PMD_ERR("init tx fqid 0x%x failed %d", fq->fqid, ret);
1383         return ret;
1384 }
1385
1386 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1387 /* Initialise a DEBUG FQ ([rt]x_error, rx_default). */
1388 static int dpaa_debug_queue_init(struct qman_fq *fq, uint32_t fqid)
1389 {
1390         struct qm_mcc_initfq opts = {0};
1391         int ret;
1392
1393         PMD_INIT_FUNC_TRACE();
1394
1395         ret = qman_reserve_fqid(fqid);
1396         if (ret) {
1397                 DPAA_PMD_ERR("Reserve debug fqid %d failed with ret: %d",
1398                         fqid, ret);
1399                 return -EINVAL;
1400         }
1401         /* "map" this Rx FQ to one of the interfaces Tx FQID */
1402         DPAA_PMD_DEBUG("Creating debug fq %p, fqid %d", fq, fqid);
1403         ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq);
1404         if (ret) {
1405                 DPAA_PMD_ERR("create debug fqid %d failed with ret: %d",
1406                         fqid, ret);
1407                 return ret;
1408         }
1409         opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL;
1410         opts.fqd.dest.wq = DPAA_IF_DEBUG_PRIORITY;
1411         ret = qman_init_fq(fq, 0, &opts);
1412         if (ret)
1413                 DPAA_PMD_ERR("init debug fqid %d failed with ret: %d",
1414                             fqid, ret);
1415         return ret;
1416 }
1417 #endif
1418
1419 /* Initialise a network interface */
1420 static int
1421 dpaa_dev_init_secondary(struct rte_eth_dev *eth_dev)
1422 {
1423         struct rte_dpaa_device *dpaa_device;
1424         struct fm_eth_port_cfg *cfg;
1425         struct dpaa_if *dpaa_intf;
1426         struct fman_if *fman_intf;
1427         int dev_id;
1428
1429         PMD_INIT_FUNC_TRACE();
1430
1431         dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1432         dev_id = dpaa_device->id.dev_id;
1433         cfg = dpaa_get_eth_port_cfg(dev_id);
1434         fman_intf = cfg->fman_if;
1435         eth_dev->process_private = fman_intf;
1436
1437         /* Plugging of UCODE burst API not supported in Secondary */
1438         dpaa_intf = eth_dev->data->dev_private;
1439         eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
1440         if (dpaa_intf->cgr_tx)
1441                 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx_slow;
1442         else
1443                 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx;
1444 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP
1445         qman_set_fq_lookup_table(
1446                 dpaa_intf->rx_queues->qman_fq_lookup_table);
1447 #endif
1448
1449         return 0;
1450 }
1451
1452 /* Initialise a network interface */
1453 static int
1454 dpaa_dev_init(struct rte_eth_dev *eth_dev)
1455 {
1456         int num_rx_fqs, fqid;
1457         int loop, ret = 0;
1458         int dev_id;
1459         struct rte_dpaa_device *dpaa_device;
1460         struct dpaa_if *dpaa_intf;
1461         struct fm_eth_port_cfg *cfg;
1462         struct fman_if *fman_intf;
1463         struct fman_if_bpool *bp, *tmp_bp;
1464         uint32_t cgrid[DPAA_MAX_NUM_PCD_QUEUES];
1465         uint32_t cgrid_tx[MAX_DPAA_CORES];
1466         char eth_buf[RTE_ETHER_ADDR_FMT_SIZE];
1467
1468         PMD_INIT_FUNC_TRACE();
1469
1470         dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1471         dev_id = dpaa_device->id.dev_id;
1472         dpaa_intf = eth_dev->data->dev_private;
1473         cfg = dpaa_get_eth_port_cfg(dev_id);
1474         fman_intf = cfg->fman_if;
1475
1476         dpaa_intf->name = dpaa_device->name;
1477
1478         /* save fman_if & cfg in the interface struture */
1479         eth_dev->process_private = fman_intf;
1480         dpaa_intf->ifid = dev_id;
1481         dpaa_intf->cfg = cfg;
1482
1483         /* Initialize Rx FQ's */
1484         if (default_q) {
1485                 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES;
1486         } else {
1487                 if (getenv("DPAA_NUM_RX_QUEUES"))
1488                         num_rx_fqs = atoi(getenv("DPAA_NUM_RX_QUEUES"));
1489                 else
1490                         num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES;
1491         }
1492
1493
1494         /* Each device can not have more than DPAA_MAX_NUM_PCD_QUEUES RX
1495          * queues.
1496          */
1497         if (num_rx_fqs <= 0 || num_rx_fqs > DPAA_MAX_NUM_PCD_QUEUES) {
1498                 DPAA_PMD_ERR("Invalid number of RX queues\n");
1499                 return -EINVAL;
1500         }
1501
1502         dpaa_intf->rx_queues = rte_zmalloc(NULL,
1503                 sizeof(struct qman_fq) * num_rx_fqs, MAX_CACHELINE);
1504         if (!dpaa_intf->rx_queues) {
1505                 DPAA_PMD_ERR("Failed to alloc mem for RX queues\n");
1506                 return -ENOMEM;
1507         }
1508
1509         memset(cgrid, 0, sizeof(cgrid));
1510         memset(cgrid_tx, 0, sizeof(cgrid_tx));
1511
1512         /* if DPAA_TX_TAILDROP_THRESHOLD is set, use that value; if 0, it means
1513          * Tx tail drop is disabled.
1514          */
1515         if (getenv("DPAA_TX_TAILDROP_THRESHOLD")) {
1516                 td_tx_threshold = atoi(getenv("DPAA_TX_TAILDROP_THRESHOLD"));
1517                 DPAA_PMD_DEBUG("Tail drop threshold env configured: %u",
1518                                td_tx_threshold);
1519                 /* if a very large value is being configured */
1520                 if (td_tx_threshold > UINT16_MAX)
1521                         td_tx_threshold = CGR_RX_PERFQ_THRESH;
1522         }
1523
1524         /* If congestion control is enabled globally*/
1525         if (td_threshold) {
1526                 dpaa_intf->cgr_rx = rte_zmalloc(NULL,
1527                         sizeof(struct qman_cgr) * num_rx_fqs, MAX_CACHELINE);
1528                 if (!dpaa_intf->cgr_rx) {
1529                         DPAA_PMD_ERR("Failed to alloc mem for cgr_rx\n");
1530                         ret = -ENOMEM;
1531                         goto free_rx;
1532                 }
1533
1534                 ret = qman_alloc_cgrid_range(&cgrid[0], num_rx_fqs, 1, 0);
1535                 if (ret != num_rx_fqs) {
1536                         DPAA_PMD_WARN("insufficient CGRIDs available");
1537                         ret = -EINVAL;
1538                         goto free_rx;
1539                 }
1540         } else {
1541                 dpaa_intf->cgr_rx = NULL;
1542         }
1543
1544         for (loop = 0; loop < num_rx_fqs; loop++) {
1545                 if (default_q)
1546                         fqid = cfg->rx_def;
1547                 else
1548                         fqid = DPAA_PCD_FQID_START + fman_intf->mac_idx *
1549                                 DPAA_PCD_FQID_MULTIPLIER + loop;
1550
1551                 if (dpaa_intf->cgr_rx)
1552                         dpaa_intf->cgr_rx[loop].cgrid = cgrid[loop];
1553
1554                 ret = dpaa_rx_queue_init(&dpaa_intf->rx_queues[loop],
1555                         dpaa_intf->cgr_rx ? &dpaa_intf->cgr_rx[loop] : NULL,
1556                         fqid);
1557                 if (ret)
1558                         goto free_rx;
1559                 dpaa_intf->rx_queues[loop].dpaa_intf = dpaa_intf;
1560         }
1561         dpaa_intf->nb_rx_queues = num_rx_fqs;
1562
1563         /* Initialise Tx FQs.free_rx Have as many Tx FQ's as number of cores */
1564         dpaa_intf->tx_queues = rte_zmalloc(NULL, sizeof(struct qman_fq) *
1565                 MAX_DPAA_CORES, MAX_CACHELINE);
1566         if (!dpaa_intf->tx_queues) {
1567                 DPAA_PMD_ERR("Failed to alloc mem for TX queues\n");
1568                 ret = -ENOMEM;
1569                 goto free_rx;
1570         }
1571
1572         /* If congestion control is enabled globally*/
1573         if (td_tx_threshold) {
1574                 dpaa_intf->cgr_tx = rte_zmalloc(NULL,
1575                         sizeof(struct qman_cgr) * MAX_DPAA_CORES,
1576                         MAX_CACHELINE);
1577                 if (!dpaa_intf->cgr_tx) {
1578                         DPAA_PMD_ERR("Failed to alloc mem for cgr_tx\n");
1579                         ret = -ENOMEM;
1580                         goto free_rx;
1581                 }
1582
1583                 ret = qman_alloc_cgrid_range(&cgrid_tx[0], MAX_DPAA_CORES,
1584                                              1, 0);
1585                 if (ret != MAX_DPAA_CORES) {
1586                         DPAA_PMD_WARN("insufficient CGRIDs available");
1587                         ret = -EINVAL;
1588                         goto free_rx;
1589                 }
1590         } else {
1591                 dpaa_intf->cgr_tx = NULL;
1592         }
1593
1594
1595         for (loop = 0; loop < MAX_DPAA_CORES; loop++) {
1596                 if (dpaa_intf->cgr_tx)
1597                         dpaa_intf->cgr_tx[loop].cgrid = cgrid_tx[loop];
1598
1599                 ret = dpaa_tx_queue_init(&dpaa_intf->tx_queues[loop],
1600                         fman_intf,
1601                         dpaa_intf->cgr_tx ? &dpaa_intf->cgr_tx[loop] : NULL);
1602                 if (ret)
1603                         goto free_tx;
1604                 dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf;
1605         }
1606         dpaa_intf->nb_tx_queues = MAX_DPAA_CORES;
1607
1608 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1609         dpaa_debug_queue_init(&dpaa_intf->debug_queues[
1610                 DPAA_DEBUG_FQ_RX_ERROR], fman_intf->fqid_rx_err);
1611         dpaa_intf->debug_queues[DPAA_DEBUG_FQ_RX_ERROR].dpaa_intf = dpaa_intf;
1612         dpaa_debug_queue_init(&dpaa_intf->debug_queues[
1613                 DPAA_DEBUG_FQ_TX_ERROR], fman_intf->fqid_tx_err);
1614         dpaa_intf->debug_queues[DPAA_DEBUG_FQ_TX_ERROR].dpaa_intf = dpaa_intf;
1615 #endif
1616
1617         DPAA_PMD_DEBUG("All frame queues created");
1618
1619         /* Get the initial configuration for flow control */
1620         dpaa_fc_set_default(dpaa_intf, fman_intf);
1621
1622         /* reset bpool list, initialize bpool dynamically */
1623         list_for_each_entry_safe(bp, tmp_bp, &cfg->fman_if->bpool_list, node) {
1624                 list_del(&bp->node);
1625                 rte_free(bp);
1626         }
1627
1628         /* Populate ethdev structure */
1629         eth_dev->dev_ops = &dpaa_devops;
1630         eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
1631         eth_dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
1632
1633         /* Allocate memory for storing MAC addresses */
1634         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr",
1635                 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER, 0);
1636         if (eth_dev->data->mac_addrs == NULL) {
1637                 DPAA_PMD_ERR("Failed to allocate %d bytes needed to "
1638                                                 "store MAC addresses",
1639                                 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER);
1640                 ret = -ENOMEM;
1641                 goto free_tx;
1642         }
1643
1644         /* copy the primary mac address */
1645         rte_ether_addr_copy(&fman_intf->mac_addr, &eth_dev->data->mac_addrs[0]);
1646         rte_ether_format_addr(eth_buf, sizeof(eth_buf), &fman_intf->mac_addr);
1647
1648         DPAA_PMD_INFO("net: dpaa: %s: %s", dpaa_device->name, eth_buf);
1649
1650         /* Disable RX mode */
1651         fman_if_discard_rx_errors(fman_intf);
1652         fman_if_disable_rx(fman_intf);
1653         /* Disable promiscuous mode */
1654         fman_if_promiscuous_disable(fman_intf);
1655         /* Disable multicast */
1656         fman_if_reset_mcast_filter_table(fman_intf);
1657         /* Reset interface statistics */
1658         fman_if_stats_reset(fman_intf);
1659         /* Disable SG by default */
1660         fman_if_set_sg(fman_intf, 0);
1661         fman_if_set_maxfrm(fman_intf, RTE_ETHER_MAX_LEN + VLAN_TAG_SIZE);
1662
1663         return 0;
1664
1665 free_tx:
1666         rte_free(dpaa_intf->tx_queues);
1667         dpaa_intf->tx_queues = NULL;
1668         dpaa_intf->nb_tx_queues = 0;
1669
1670 free_rx:
1671         rte_free(dpaa_intf->cgr_rx);
1672         rte_free(dpaa_intf->cgr_tx);
1673         rte_free(dpaa_intf->rx_queues);
1674         dpaa_intf->rx_queues = NULL;
1675         dpaa_intf->nb_rx_queues = 0;
1676         return ret;
1677 }
1678
1679 static int
1680 dpaa_dev_uninit(struct rte_eth_dev *dev)
1681 {
1682         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1683         int loop;
1684
1685         PMD_INIT_FUNC_TRACE();
1686
1687         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1688                 return -EPERM;
1689
1690         if (!dpaa_intf) {
1691                 DPAA_PMD_WARN("Already closed or not started");
1692                 return -1;
1693         }
1694
1695         dpaa_eth_dev_close(dev);
1696
1697         /* release configuration memory */
1698         if (dpaa_intf->fc_conf)
1699                 rte_free(dpaa_intf->fc_conf);
1700
1701         /* Release RX congestion Groups */
1702         if (dpaa_intf->cgr_rx) {
1703                 for (loop = 0; loop < dpaa_intf->nb_rx_queues; loop++)
1704                         qman_delete_cgr(&dpaa_intf->cgr_rx[loop]);
1705
1706                 qman_release_cgrid_range(dpaa_intf->cgr_rx[loop].cgrid,
1707                                          dpaa_intf->nb_rx_queues);
1708         }
1709
1710         rte_free(dpaa_intf->cgr_rx);
1711         dpaa_intf->cgr_rx = NULL;
1712
1713         /* Release TX congestion Groups */
1714         if (dpaa_intf->cgr_tx) {
1715                 for (loop = 0; loop < MAX_DPAA_CORES; loop++)
1716                         qman_delete_cgr(&dpaa_intf->cgr_tx[loop]);
1717
1718                 qman_release_cgrid_range(dpaa_intf->cgr_tx[loop].cgrid,
1719                                          MAX_DPAA_CORES);
1720                 rte_free(dpaa_intf->cgr_tx);
1721                 dpaa_intf->cgr_tx = NULL;
1722         }
1723
1724         rte_free(dpaa_intf->rx_queues);
1725         dpaa_intf->rx_queues = NULL;
1726
1727         rte_free(dpaa_intf->tx_queues);
1728         dpaa_intf->tx_queues = NULL;
1729
1730         dev->dev_ops = NULL;
1731         dev->rx_pkt_burst = NULL;
1732         dev->tx_pkt_burst = NULL;
1733
1734         return 0;
1735 }
1736
1737 static int
1738 rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv __rte_unused,
1739                struct rte_dpaa_device *dpaa_dev)
1740 {
1741         int diag;
1742         int ret;
1743         struct rte_eth_dev *eth_dev;
1744
1745         PMD_INIT_FUNC_TRACE();
1746
1747         if ((DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE) >
1748                 RTE_PKTMBUF_HEADROOM) {
1749                 DPAA_PMD_ERR(
1750                 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA Annotation req(%d)",
1751                 RTE_PKTMBUF_HEADROOM,
1752                 DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE);
1753
1754                 return -1;
1755         }
1756
1757         /* In case of secondary process, the device is already configured
1758          * and no further action is required, except portal initialization
1759          * and verifying secondary attachment to port name.
1760          */
1761         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1762                 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name);
1763                 if (!eth_dev)
1764                         return -ENOMEM;
1765                 eth_dev->device = &dpaa_dev->device;
1766                 eth_dev->dev_ops = &dpaa_devops;
1767
1768                 ret = dpaa_dev_init_secondary(eth_dev);
1769                 if (ret != 0) {
1770                         RTE_LOG(ERR, PMD, "secondary dev init failed\n");
1771                         return ret;
1772                 }
1773
1774                 rte_eth_dev_probing_finish(eth_dev);
1775                 return 0;
1776         }
1777
1778         if (!is_global_init && (rte_eal_process_type() == RTE_PROC_PRIMARY)) {
1779                 if (access("/tmp/fmc.bin", F_OK) == -1) {
1780                         DPAA_PMD_INFO("* FMC not configured.Enabling default mode");
1781                         default_q = 1;
1782                 }
1783
1784                 /* disabling the default push mode for LS1043 */
1785                 if (dpaa_svr_family == SVR_LS1043A_FAMILY)
1786                         dpaa_push_mode_max_queue = 0;
1787
1788                 /* if push mode queues to be enabled. Currenly we are allowing
1789                  * only one queue per thread.
1790                  */
1791                 if (getenv("DPAA_PUSH_QUEUES_NUMBER")) {
1792                         dpaa_push_mode_max_queue =
1793                                         atoi(getenv("DPAA_PUSH_QUEUES_NUMBER"));
1794                         if (dpaa_push_mode_max_queue > DPAA_MAX_PUSH_MODE_QUEUE)
1795                             dpaa_push_mode_max_queue = DPAA_MAX_PUSH_MODE_QUEUE;
1796                 }
1797
1798                 is_global_init = 1;
1799         }
1800
1801         if (unlikely(!DPAA_PER_LCORE_PORTAL)) {
1802                 ret = rte_dpaa_portal_init((void *)1);
1803                 if (ret) {
1804                         DPAA_PMD_ERR("Unable to initialize portal");
1805                         return ret;
1806                 }
1807         }
1808
1809         eth_dev = rte_eth_dev_allocate(dpaa_dev->name);
1810         if (!eth_dev)
1811                 return -ENOMEM;
1812
1813         eth_dev->data->dev_private =
1814                         rte_zmalloc("ethdev private structure",
1815                                         sizeof(struct dpaa_if),
1816                                         RTE_CACHE_LINE_SIZE);
1817         if (!eth_dev->data->dev_private) {
1818                 DPAA_PMD_ERR("Cannot allocate memzone for port data");
1819                 rte_eth_dev_release_port(eth_dev);
1820                 return -ENOMEM;
1821         }
1822
1823         eth_dev->device = &dpaa_dev->device;
1824         dpaa_dev->eth_dev = eth_dev;
1825
1826         qman_ern_register_cb(dpaa_free_mbuf);
1827
1828         if (dpaa_drv->drv_flags & RTE_DPAA_DRV_INTR_LSC)
1829                 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;
1830
1831         /* Invoke PMD device initialization function */
1832         diag = dpaa_dev_init(eth_dev);
1833         if (diag == 0) {
1834                 rte_eth_dev_probing_finish(eth_dev);
1835                 return 0;
1836         }
1837
1838         rte_eth_dev_release_port(eth_dev);
1839         return diag;
1840 }
1841
1842 static int
1843 rte_dpaa_remove(struct rte_dpaa_device *dpaa_dev)
1844 {
1845         struct rte_eth_dev *eth_dev;
1846
1847         PMD_INIT_FUNC_TRACE();
1848
1849         eth_dev = dpaa_dev->eth_dev;
1850         dpaa_dev_uninit(eth_dev);
1851
1852         rte_eth_dev_release_port(eth_dev);
1853
1854         return 0;
1855 }
1856
1857 static struct rte_dpaa_driver rte_dpaa_pmd = {
1858         .drv_flags = RTE_DPAA_DRV_INTR_LSC,
1859         .drv_type = FSL_DPAA_ETH,
1860         .probe = rte_dpaa_probe,
1861         .remove = rte_dpaa_remove,
1862 };
1863
1864 RTE_PMD_REGISTER_DPAA(net_dpaa, rte_dpaa_pmd);
1865 RTE_LOG_REGISTER(dpaa_logtype_pmd, pmd.net.dpaa, NOTICE);