drivers/net/dpaa/dpaa_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  *   Copyright 2016 Freescale Semiconductor, Inc. All rights reserved.
   4  *   Copyright 2017-2020 NXP
   5  *
   6  */
   7 /* System headers */
   8 #include <stdio.h>
   9 #include <inttypes.h>
  10 #include <unistd.h>
  11 #include <limits.h>
  12 #include <sched.h>
  13 #include <signal.h>
  14 #include <pthread.h>
  15 #include <sys/types.h>
  16 #include <sys/syscall.h>
  17
  18 #include <rte_string_fns.h>
  19 #include <rte_byteorder.h>
  20 #include <rte_common.h>
  21 #include <rte_interrupts.h>
  22 #include <rte_log.h>
  23 #include <rte_debug.h>
  24 #include <rte_pci.h>
  25 #include <rte_atomic.h>
  26 #include <rte_branch_prediction.h>
  27 #include <rte_memory.h>
  28 #include <rte_tailq.h>
  29 #include <rte_eal.h>
  30 #include <rte_alarm.h>
  31 #include <rte_ether.h>
  32 #include <rte_ethdev_driver.h>
  33 #include <rte_malloc.h>
  34 #include <rte_ring.h>
  35
  36 #include <rte_dpaa_bus.h>
  37 #include <rte_dpaa_logs.h>
  38 #include <dpaa_mempool.h>
  39
  40 #include <dpaa_ethdev.h>
  41 #include <dpaa_rxtx.h>
  42 #include <dpaa_flow.h>
  43 #include <rte_pmd_dpaa.h>
  44
  45 #include <fsl_usd.h>
  46 #include <fsl_qman.h>
  47 #include <fsl_bman.h>
  48 #include <fsl_fman.h>
  49 #include <process.h>
  50
  51 /* Supported Rx offloads */
  52 static uint64_t dev_rx_offloads_sup =
  53                 DEV_RX_OFFLOAD_JUMBO_FRAME |
  54                 DEV_RX_OFFLOAD_SCATTER;
  55
  56 /* Rx offloads which cannot be disabled */
  57 static uint64_t dev_rx_offloads_nodis =
  58                 DEV_RX_OFFLOAD_IPV4_CKSUM |
  59                 DEV_RX_OFFLOAD_UDP_CKSUM |
  60                 DEV_RX_OFFLOAD_TCP_CKSUM |
  61                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
  62                 DEV_RX_OFFLOAD_RSS_HASH;
  63
  64 /* Supported Tx offloads */
  65 static uint64_t dev_tx_offloads_sup =
  66                 DEV_TX_OFFLOAD_MT_LOCKFREE |
  67                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
  68
  69 /* Tx offloads which cannot be disabled */
  70 static uint64_t dev_tx_offloads_nodis =
  71                 DEV_TX_OFFLOAD_IPV4_CKSUM |
  72                 DEV_TX_OFFLOAD_UDP_CKSUM |
  73                 DEV_TX_OFFLOAD_TCP_CKSUM |
  74                 DEV_TX_OFFLOAD_SCTP_CKSUM |
  75                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
  76                 DEV_TX_OFFLOAD_MULTI_SEGS;
  77
  78 /* Keep track of whether QMAN and BMAN have been globally initialized */
  79 static int is_global_init;
  80 static int fmc_q = 1;   /* Indicates the use of static fmc for distribution */
  81 static int default_q;   /* use default queue - FMC is not executed*/
  82 /* At present we only allow up to 4 push mode queues as default - as each of
  83  * this queue need dedicated portal and we are short of portals.
  84  */
  85 #define DPAA_MAX_PUSH_MODE_QUEUE       8
  86 #define DPAA_DEFAULT_PUSH_MODE_QUEUE   4
  87
  88 static int dpaa_push_mode_max_queue = DPAA_DEFAULT_PUSH_MODE_QUEUE;
  89 static int dpaa_push_queue_idx; /* Queue index which are in push mode*/
  90
  91
  92 /* Per RX FQ Taildrop in frame count */
  93 static unsigned int td_threshold = CGR_RX_PERFQ_THRESH;
  94
  95 /* Per TX FQ Taildrop in frame count, disabled by default */
  96 static unsigned int td_tx_threshold;
  97
  98 struct rte_dpaa_xstats_name_off {
  99         char name[RTE_ETH_XSTATS_NAME_SIZE];
 100         uint32_t offset;
 101 };
 102
 103 static const struct rte_dpaa_xstats_name_off dpaa_xstats_strings[] = {
 104         {"rx_align_err",
 105                 offsetof(struct dpaa_if_stats, raln)},
 106         {"rx_valid_pause",
 107                 offsetof(struct dpaa_if_stats, rxpf)},
 108         {"rx_fcs_err",
 109                 offsetof(struct dpaa_if_stats, rfcs)},
 110         {"rx_vlan_frame",
 111                 offsetof(struct dpaa_if_stats, rvlan)},
 112         {"rx_frame_err",
 113                 offsetof(struct dpaa_if_stats, rerr)},
 114         {"rx_drop_err",
 115                 offsetof(struct dpaa_if_stats, rdrp)},
 116         {"rx_undersized",
 117                 offsetof(struct dpaa_if_stats, rund)},
 118         {"rx_oversize_err",
 119                 offsetof(struct dpaa_if_stats, rovr)},
 120         {"rx_fragment_pkt",
 121                 offsetof(struct dpaa_if_stats, rfrg)},
 122         {"tx_valid_pause",
 123                 offsetof(struct dpaa_if_stats, txpf)},
 124         {"tx_fcs_err",
 125                 offsetof(struct dpaa_if_stats, terr)},
 126         {"tx_vlan_frame",
 127                 offsetof(struct dpaa_if_stats, tvlan)},
 128         {"rx_undersized",
 129                 offsetof(struct dpaa_if_stats, tund)},
 130 };
 131
 132 static struct rte_dpaa_driver rte_dpaa_pmd;
 133
 134 static int
 135 dpaa_eth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info);
 136
 137 static int dpaa_eth_link_update(struct rte_eth_dev *dev,
 138                                 int wait_to_complete __rte_unused);
 139
 140 static void dpaa_interrupt_handler(void *param);
 141
 142 static inline void
 143 dpaa_poll_queue_default_config(struct qm_mcc_initfq *opts)
 144 {
 145         memset(opts, 0, sizeof(struct qm_mcc_initfq));
 146         opts->we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
 147         opts->fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | QM_FQCTRL_CTXASTASHING |
 148                            QM_FQCTRL_PREFERINCACHE;
 149         opts->fqd.context_a.stashing.exclusive = 0;
 150         if (dpaa_svr_family != SVR_LS1046A_FAMILY)
 151                 opts->fqd.context_a.stashing.annotation_cl =
 152                                                 DPAA_IF_RX_ANNOTATION_STASH;
 153         opts->fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
 154         opts->fqd.context_a.stashing.context_cl = DPAA_IF_RX_CONTEXT_STASH;
 155 }
 156
 157 static int
 158 dpaa_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 159 {
 160         uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
 161                                 + VLAN_TAG_SIZE;
 162         uint32_t buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
 163
 164         PMD_INIT_FUNC_TRACE();
 165
 166         if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA_MAX_RX_PKT_LEN)
 167                 return -EINVAL;
 168         /*
 169          * Refuse mtu that requires the support of scattered packets
 170          * when this feature has not been enabled before.
 171          */
 172         if (dev->data->min_rx_buf_size &&
 173                 !dev->data->scattered_rx && frame_size > buffsz) {
 174                 DPAA_PMD_ERR("SG not enabled, will not fit in one buffer");
 175                 return -EINVAL;
 176         }
 177
 178         /* check <seg size> * <max_seg>  >= max_frame */
 179         if (dev->data->min_rx_buf_size && dev->data->scattered_rx &&
 180                 (frame_size > buffsz * DPAA_SGT_MAX_ENTRIES)) {
 181                 DPAA_PMD_ERR("Too big to fit for Max SG list %d",
 182                                 buffsz * DPAA_SGT_MAX_ENTRIES);
 183                 return -EINVAL;
 184         }
 185
 186         if (frame_size > RTE_ETHER_MAX_LEN)
 187                 dev->data->dev_conf.rxmode.offloads |=
 188                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 189         else
 190                 dev->data->dev_conf.rxmode.offloads &=
 191                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 192
 193         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 194
 195         fman_if_set_maxfrm(dev->process_private, frame_size);
 196
 197         return 0;
 198 }
 199
 200 static int
 201 dpaa_eth_dev_configure(struct rte_eth_dev *dev)
 202 {
 203         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 204         uint64_t rx_offloads = eth_conf->rxmode.offloads;
 205         uint64_t tx_offloads = eth_conf->txmode.offloads;
 206         struct rte_device *rdev = dev->device;
 207         struct rte_dpaa_device *dpaa_dev;
 208         struct fman_if *fif = dev->process_private;
 209         struct __fman_if *__fif;
 210         struct rte_intr_handle *intr_handle;
 211         int ret;
 212
 213         PMD_INIT_FUNC_TRACE();
 214
 215         dpaa_dev = container_of(rdev, struct rte_dpaa_device, device);
 216         intr_handle = &dpaa_dev->intr_handle;
 217         __fif = container_of(fif, struct __fman_if, __if);
 218
 219         /* Rx offloads which are enabled by default */
 220         if (dev_rx_offloads_nodis & ~rx_offloads) {
 221                 DPAA_PMD_INFO(
 222                 "Some of rx offloads enabled by default - requested 0x%" PRIx64
 223                 " fixed are 0x%" PRIx64,
 224                 rx_offloads, dev_rx_offloads_nodis);
 225         }
 226
 227         /* Tx offloads which are enabled by default */
 228         if (dev_tx_offloads_nodis & ~tx_offloads) {
 229                 DPAA_PMD_INFO(
 230                 "Some of tx offloads enabled by default - requested 0x%" PRIx64
 231                 " fixed are 0x%" PRIx64,
 232                 tx_offloads, dev_tx_offloads_nodis);
 233         }
 234
 235         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 236                 uint32_t max_len;
 237
 238                 DPAA_PMD_DEBUG("enabling jumbo");
 239
 240                 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <=
 241                     DPAA_MAX_RX_PKT_LEN)
 242                         max_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
 243                 else {
 244                         DPAA_PMD_INFO("enabling jumbo override conf max len=%d "
 245                                 "supported is %d",
 246                                 dev->data->dev_conf.rxmode.max_rx_pkt_len,
 247                                 DPAA_MAX_RX_PKT_LEN);
 248                         max_len = DPAA_MAX_RX_PKT_LEN;
 249                 }
 250
 251                 fman_if_set_maxfrm(dev->process_private, max_len);
 252                 dev->data->mtu = max_len
 253                         - RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE;
 254         }
 255
 256         if (rx_offloads & DEV_RX_OFFLOAD_SCATTER) {
 257                 DPAA_PMD_DEBUG("enabling scatter mode");
 258                 fman_if_set_sg(dev->process_private, 1);
 259                 dev->data->scattered_rx = 1;
 260         }
 261
 262         /* if the interrupts were configured on this devices*/
 263         if (intr_handle && intr_handle->fd) {
 264                 if (dev->data->dev_conf.intr_conf.lsc != 0)
 265                         rte_intr_callback_register(intr_handle,
 266                                            dpaa_interrupt_handler,
 267                                            (void *)dev);
 268
 269                 ret = dpaa_intr_enable(__fif->node_name, intr_handle->fd);
 270                 if (ret) {
 271                         if (dev->data->dev_conf.intr_conf.lsc != 0) {
 272                                 rte_intr_callback_unregister(intr_handle,
 273                                         dpaa_interrupt_handler,
 274                                         (void *)dev);
 275                                 if (ret == EINVAL)
 276                                         printf("Failed to enable interrupt: Not Supported\n");
 277                                 else
 278                                         printf("Failed to enable interrupt\n");
 279                         }
 280                         dev->data->dev_conf.intr_conf.lsc = 0;
 281                         dev->data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC;
 282                 }
 283         }
 284         return 0;
 285 }
 286
 287 static const uint32_t *
 288 dpaa_supported_ptypes_get(struct rte_eth_dev *dev)
 289 {
 290         static const uint32_t ptypes[] = {
 291                 RTE_PTYPE_L2_ETHER,
 292                 RTE_PTYPE_L2_ETHER_VLAN,
 293                 RTE_PTYPE_L2_ETHER_ARP,
 294                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
 295                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
 296                 RTE_PTYPE_L4_ICMP,
 297                 RTE_PTYPE_L4_TCP,
 298                 RTE_PTYPE_L4_UDP,
 299                 RTE_PTYPE_L4_FRAG,
 300                 RTE_PTYPE_L4_TCP,
 301                 RTE_PTYPE_L4_UDP,
 302                 RTE_PTYPE_L4_SCTP
 303         };
 304
 305         PMD_INIT_FUNC_TRACE();
 306
 307         if (dev->rx_pkt_burst == dpaa_eth_queue_rx)
 308                 return ptypes;
 309         return NULL;
 310 }
 311
 312 static void dpaa_interrupt_handler(void *param)
 313 {
 314         struct rte_eth_dev *dev = param;
 315         struct rte_device *rdev = dev->device;
 316         struct rte_dpaa_device *dpaa_dev;
 317         struct rte_intr_handle *intr_handle;
 318         uint64_t buf;
 319         int bytes_read;
 320
 321         dpaa_dev = container_of(rdev, struct rte_dpaa_device, device);
 322         intr_handle = &dpaa_dev->intr_handle;
 323
 324         bytes_read = read(intr_handle->fd, &buf, sizeof(uint64_t));
 325         if (bytes_read < 0)
 326                 DPAA_PMD_ERR("Error reading eventfd\n");
 327         dpaa_eth_link_update(dev, 0);
 328         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
 329 }
 330
 331 static int dpaa_eth_dev_start(struct rte_eth_dev *dev)
 332 {
 333         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 334
 335         PMD_INIT_FUNC_TRACE();
 336
 337         /* Change tx callback to the real one */
 338         if (dpaa_intf->cgr_tx)
 339                 dev->tx_pkt_burst = dpaa_eth_queue_tx_slow;
 340         else
 341                 dev->tx_pkt_burst = dpaa_eth_queue_tx;
 342
 343         fman_if_enable_rx(dev->process_private);
 344
 345         return 0;
 346 }
 347
 348 static void dpaa_eth_dev_stop(struct rte_eth_dev *dev)
 349 {
 350         struct fman_if *fif = dev->process_private;
 351
 352         PMD_INIT_FUNC_TRACE();
 353
 354         fman_if_disable_rx(fif);
 355         dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
 356 }
 357
 358 static void dpaa_eth_dev_close(struct rte_eth_dev *dev)
 359 {
 360         struct fman_if *fif = dev->process_private;
 361         struct __fman_if *__fif;
 362         struct rte_device *rdev = dev->device;
 363         struct rte_dpaa_device *dpaa_dev;
 364         struct rte_intr_handle *intr_handle;
 365
 366         PMD_INIT_FUNC_TRACE();
 367
 368         dpaa_dev = container_of(rdev, struct rte_dpaa_device, device);
 369         intr_handle = &dpaa_dev->intr_handle;
 370         __fif = container_of(fif, struct __fman_if, __if);
 371
 372         dpaa_eth_dev_stop(dev);
 373
 374         if (intr_handle && intr_handle->fd &&
 375             dev->data->dev_conf.intr_conf.lsc != 0) {
 376                 dpaa_intr_disable(__fif->node_name);
 377                 rte_intr_callback_unregister(intr_handle,
 378                                              dpaa_interrupt_handler,
 379                                              (void *)dev);
 380         }
 381 }
 382
 383 static int
 384 dpaa_fw_version_get(struct rte_eth_dev *dev __rte_unused,
 385                      char *fw_version,
 386                      size_t fw_size)
 387 {
 388         int ret;
 389         FILE *svr_file = NULL;
 390         unsigned int svr_ver = 0;
 391
 392         PMD_INIT_FUNC_TRACE();
 393
 394         svr_file = fopen(DPAA_SOC_ID_FILE, "r");
 395         if (!svr_file) {
 396                 DPAA_PMD_ERR("Unable to open SoC device");
 397                 return -ENOTSUP; /* Not supported on this infra */
 398         }
 399         if (fscanf(svr_file, "svr:%x", &svr_ver) > 0)
 400                 dpaa_svr_family = svr_ver & SVR_MASK;
 401         else
 402                 DPAA_PMD_ERR("Unable to read SoC device");
 403
 404         fclose(svr_file);
 405
 406         ret = snprintf(fw_version, fw_size, "SVR:%x-fman-v%x",
 407                        svr_ver, fman_ip_rev);
 408         ret += 1; /* add the size of '\0' */
 409
 410         if (fw_size < (uint32_t)ret)
 411                 return ret;
 412         else
 413                 return 0;
 414 }
 415
 416 static int dpaa_eth_dev_info(struct rte_eth_dev *dev,
 417                              struct rte_eth_dev_info *dev_info)
 418 {
 419         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 420         struct fman_if *fif = dev->process_private;
 421
 422         DPAA_PMD_DEBUG(": %s", dpaa_intf->name);
 423
 424         dev_info->max_rx_queues = dpaa_intf->nb_rx_queues;
 425         dev_info->max_tx_queues = dpaa_intf->nb_tx_queues;
 426         dev_info->max_rx_pktlen = DPAA_MAX_RX_PKT_LEN;
 427         dev_info->max_mac_addrs = DPAA_MAX_MAC_FILTER;
 428         dev_info->max_hash_mac_addrs = 0;
 429         dev_info->max_vfs = 0;
 430         dev_info->max_vmdq_pools = ETH_16_POOLS;
 431         dev_info->flow_type_rss_offloads = DPAA_RSS_OFFLOAD_ALL;
 432
 433         if (fif->mac_type == fman_mac_1g) {
 434                 dev_info->speed_capa = ETH_LINK_SPEED_1G;
 435         } else if (fif->mac_type == fman_mac_2_5g) {
 436                 dev_info->speed_capa = ETH_LINK_SPEED_1G
 437                                         | ETH_LINK_SPEED_2_5G;
 438         } else if (fif->mac_type == fman_mac_10g) {
 439                 dev_info->speed_capa = ETH_LINK_SPEED_1G
 440                                         | ETH_LINK_SPEED_2_5G
 441                                         | ETH_LINK_SPEED_10G;
 442         } else {
 443                 DPAA_PMD_ERR("invalid link_speed: %s, %d",
 444                              dpaa_intf->name, fif->mac_type);
 445                 return -EINVAL;
 446         }
 447
 448         dev_info->rx_offload_capa = dev_rx_offloads_sup |
 449                                         dev_rx_offloads_nodis;
 450         dev_info->tx_offload_capa = dev_tx_offloads_sup |
 451                                         dev_tx_offloads_nodis;
 452         dev_info->default_rxportconf.burst_size = DPAA_DEF_RX_BURST_SIZE;
 453         dev_info->default_txportconf.burst_size = DPAA_DEF_TX_BURST_SIZE;
 454         dev_info->default_rxportconf.nb_queues = 1;
 455         dev_info->default_txportconf.nb_queues = 1;
 456         dev_info->default_txportconf.ring_size = CGR_TX_CGR_THRESH;
 457         dev_info->default_rxportconf.ring_size = CGR_RX_PERFQ_THRESH;
 458
 459         return 0;
 460 }
 461
 462 static int
 463 dpaa_dev_rx_burst_mode_get(struct rte_eth_dev *dev,
 464                         __rte_unused uint16_t queue_id,
 465                         struct rte_eth_burst_mode *mode)
 466 {
 467         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 468         int ret = -EINVAL;
 469         unsigned int i;
 470         const struct burst_info {
 471                 uint64_t flags;
 472                 const char *output;
 473         } rx_offload_map[] = {
 474                         {DEV_RX_OFFLOAD_JUMBO_FRAME, " Jumbo frame,"},
 475                         {DEV_RX_OFFLOAD_SCATTER, " Scattered,"},
 476                         {DEV_RX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"},
 477                         {DEV_RX_OFFLOAD_UDP_CKSUM, " UDP csum,"},
 478                         {DEV_RX_OFFLOAD_TCP_CKSUM, " TCP csum,"},
 479                         {DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
 480                         {DEV_RX_OFFLOAD_RSS_HASH, " RSS,"}
 481         };
 482
 483         /* Update Rx offload info */
 484         for (i = 0; i < RTE_DIM(rx_offload_map); i++) {
 485                 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) {
 486                         snprintf(mode->info, sizeof(mode->info), "%s",
 487                                 rx_offload_map[i].output);
 488                         ret = 0;
 489                         break;
 490                 }
 491         }
 492         return ret;
 493 }
 494
 495 static int
 496 dpaa_dev_tx_burst_mode_get(struct rte_eth_dev *dev,
 497                         __rte_unused uint16_t queue_id,
 498                         struct rte_eth_burst_mode *mode)
 499 {
 500         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 501         int ret = -EINVAL;
 502         unsigned int i;
 503         const struct burst_info {
 504                 uint64_t flags;
 505                 const char *output;
 506         } tx_offload_map[] = {
 507                         {DEV_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"},
 508                         {DEV_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"},
 509                         {DEV_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"},
 510                         {DEV_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"},
 511                         {DEV_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"},
 512                         {DEV_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
 513                         {DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
 514                         {DEV_TX_OFFLOAD_MULTI_SEGS, " Scattered,"}
 515         };
 516
 517         /* Update Tx offload info */
 518         for (i = 0; i < RTE_DIM(tx_offload_map); i++) {
 519                 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) {
 520                         snprintf(mode->info, sizeof(mode->info), "%s",
 521                                 tx_offload_map[i].output);
 522                         ret = 0;
 523                         break;
 524                 }
 525         }
 526         return ret;
 527 }
 528
 529 static int dpaa_eth_link_update(struct rte_eth_dev *dev,
 530                                 int wait_to_complete __rte_unused)
 531 {
 532         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 533         struct rte_eth_link *link = &dev->data->dev_link;
 534         struct fman_if *fif = dev->process_private;
 535         struct __fman_if *__fif = container_of(fif, struct __fman_if, __if);
 536         int ret;
 537
 538         PMD_INIT_FUNC_TRACE();
 539
 540         if (fif->mac_type == fman_mac_1g)
 541                 link->link_speed = ETH_SPEED_NUM_1G;
 542         else if (fif->mac_type == fman_mac_2_5g)
 543                 link->link_speed = ETH_SPEED_NUM_2_5G;
 544         else if (fif->mac_type == fman_mac_10g)
 545                 link->link_speed = ETH_SPEED_NUM_10G;
 546         else
 547                 DPAA_PMD_ERR("invalid link_speed: %s, %d",
 548                              dpaa_intf->name, fif->mac_type);
 549
 550         if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC) {
 551                 ret = dpaa_get_link_status(__fif->node_name);
 552                 if (ret < 0)
 553                         return ret;
 554                 link->link_status = ret;
 555         } else {
 556                 link->link_status = dpaa_intf->valid;
 557         }
 558
 559         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 560         link->link_autoneg = ETH_LINK_AUTONEG;
 561
 562         DPAA_PMD_INFO("Port %d Link is %s\n", dev->data->port_id,
 563                       link->link_status ? "Up" : "Down");
 564         return 0;
 565 }
 566
 567 static int dpaa_eth_stats_get(struct rte_eth_dev *dev,
 568                                struct rte_eth_stats *stats)
 569 {
 570         PMD_INIT_FUNC_TRACE();
 571
 572         fman_if_stats_get(dev->process_private, stats);
 573         return 0;
 574 }
 575
 576 static int dpaa_eth_stats_reset(struct rte_eth_dev *dev)
 577 {
 578         PMD_INIT_FUNC_TRACE();
 579
 580         fman_if_stats_reset(dev->process_private);
 581
 582         return 0;
 583 }
 584
 585 static int
 586 dpaa_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
 587                     unsigned int n)
 588 {
 589         unsigned int i = 0, num = RTE_DIM(dpaa_xstats_strings);
 590         uint64_t values[sizeof(struct dpaa_if_stats) / 8];
 591
 592         if (n < num)
 593                 return num;
 594
 595         if (xstats == NULL)
 596                 return 0;
 597
 598         fman_if_stats_get_all(dev->process_private, values,
 599                               sizeof(struct dpaa_if_stats) / 8);
 600
 601         for (i = 0; i < num; i++) {
 602                 xstats[i].id = i;
 603                 xstats[i].value = values[dpaa_xstats_strings[i].offset / 8];
 604         }
 605         return i;
 606 }
 607
 608 static int
 609 dpaa_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 610                       struct rte_eth_xstat_name *xstats_names,
 611                       unsigned int limit)
 612 {
 613         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 614
 615         if (limit < stat_cnt)
 616                 return stat_cnt;
 617
 618         if (xstats_names != NULL)
 619                 for (i = 0; i < stat_cnt; i++)
 620                         strlcpy(xstats_names[i].name,
 621                                 dpaa_xstats_strings[i].name,
 622                                 sizeof(xstats_names[i].name));
 623
 624         return stat_cnt;
 625 }
 626
 627 static int
 628 dpaa_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 629                       uint64_t *values, unsigned int n)
 630 {
 631         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 632         uint64_t values_copy[sizeof(struct dpaa_if_stats) / 8];
 633
 634         if (!ids) {
 635                 if (n < stat_cnt)
 636                         return stat_cnt;
 637
 638                 if (!values)
 639                         return 0;
 640
 641                 fman_if_stats_get_all(dev->process_private, values_copy,
 642                                       sizeof(struct dpaa_if_stats) / 8);
 643
 644                 for (i = 0; i < stat_cnt; i++)
 645                         values[i] =
 646                                 values_copy[dpaa_xstats_strings[i].offset / 8];
 647
 648                 return stat_cnt;
 649         }
 650
 651         dpaa_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
 652
 653         for (i = 0; i < n; i++) {
 654                 if (ids[i] >= stat_cnt) {
 655                         DPAA_PMD_ERR("id value isn't valid");
 656                         return -1;
 657                 }
 658                 values[i] = values_copy[ids[i]];
 659         }
 660         return n;
 661 }
 662
 663 static int
 664 dpaa_xstats_get_names_by_id(
 665         struct rte_eth_dev *dev,
 666         struct rte_eth_xstat_name *xstats_names,
 667         const uint64_t *ids,
 668         unsigned int limit)
 669 {
 670         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 671         struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
 672
 673         if (!ids)
 674                 return dpaa_xstats_get_names(dev, xstats_names, limit);
 675
 676         dpaa_xstats_get_names(dev, xstats_names_copy, limit);
 677
 678         for (i = 0; i < limit; i++) {
 679                 if (ids[i] >= stat_cnt) {
 680                         DPAA_PMD_ERR("id value isn't valid");
 681                         return -1;
 682                 }
 683                 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
 684         }
 685         return limit;
 686 }
 687
 688 static int dpaa_eth_promiscuous_enable(struct rte_eth_dev *dev)
 689 {
 690         PMD_INIT_FUNC_TRACE();
 691
 692         fman_if_promiscuous_enable(dev->process_private);
 693
 694         return 0;
 695 }
 696
 697 static int dpaa_eth_promiscuous_disable(struct rte_eth_dev *dev)
 698 {
 699         PMD_INIT_FUNC_TRACE();
 700
 701         fman_if_promiscuous_disable(dev->process_private);
 702
 703         return 0;
 704 }
 705
 706 static int dpaa_eth_multicast_enable(struct rte_eth_dev *dev)
 707 {
 708         PMD_INIT_FUNC_TRACE();
 709
 710         fman_if_set_mcast_filter_table(dev->process_private);
 711
 712         return 0;
 713 }
 714
 715 static int dpaa_eth_multicast_disable(struct rte_eth_dev *dev)
 716 {
 717         PMD_INIT_FUNC_TRACE();
 718
 719         fman_if_reset_mcast_filter_table(dev->process_private);
 720
 721         return 0;
 722 }
 723
 724 static
 725 int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 726                             uint16_t nb_desc,
 727                             unsigned int socket_id __rte_unused,
 728                             const struct rte_eth_rxconf *rx_conf,
 729                             struct rte_mempool *mp)
 730 {
 731         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 732         struct fman_if *fif = dev->process_private;
 733         struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_idx];
 734         struct qm_mcc_initfq opts = {0};
 735         u32 flags = 0;
 736         int ret;
 737         u32 buffsz = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
 738
 739         PMD_INIT_FUNC_TRACE();
 740
 741         if (queue_idx >= dev->data->nb_rx_queues) {
 742                 rte_errno = EOVERFLOW;
 743                 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
 744                       (void *)dev, queue_idx, dev->data->nb_rx_queues);
 745                 return -rte_errno;
 746         }
 747
 748         /* Rx deferred start is not supported */
 749         if (rx_conf->rx_deferred_start) {
 750                 DPAA_PMD_ERR("%p:Rx deferred start not supported", (void *)dev);
 751                 return -EINVAL;
 752         }
 753         rxq->nb_desc = UINT16_MAX;
 754         rxq->offloads = rx_conf->offloads;
 755
 756         DPAA_PMD_INFO("Rx queue setup for queue index: %d fq_id (0x%x)",
 757                         queue_idx, rxq->fqid);
 758
 759         /* Max packet can fit in single buffer */
 760         if (dev->data->dev_conf.rxmode.max_rx_pkt_len <= buffsz) {
 761                 ;
 762         } else if (dev->data->dev_conf.rxmode.offloads &
 763                         DEV_RX_OFFLOAD_SCATTER) {
 764                 if (dev->data->dev_conf.rxmode.max_rx_pkt_len >
 765                         buffsz * DPAA_SGT_MAX_ENTRIES) {
 766                         DPAA_PMD_ERR("max RxPkt size %d too big to fit "
 767                                 "MaxSGlist %d",
 768                                 dev->data->dev_conf.rxmode.max_rx_pkt_len,
 769                                 buffsz * DPAA_SGT_MAX_ENTRIES);
 770                         rte_errno = EOVERFLOW;
 771                         return -rte_errno;
 772                 }
 773         } else {
 774                 DPAA_PMD_WARN("The requested maximum Rx packet size (%u) is"
 775                      " larger than a single mbuf (%u) and scattered"
 776                      " mode has not been requested",
 777                      dev->data->dev_conf.rxmode.max_rx_pkt_len,
 778                      buffsz - RTE_PKTMBUF_HEADROOM);
 779         }
 780
 781         if (!dpaa_intf->bp_info || dpaa_intf->bp_info->mp != mp) {
 782                 struct fman_if_ic_params icp;
 783                 uint32_t fd_offset;
 784                 uint32_t bp_size;
 785
 786                 if (!mp->pool_data) {
 787                         DPAA_PMD_ERR("Not an offloaded buffer pool!");
 788                         return -1;
 789                 }
 790                 dpaa_intf->bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp);
 791
 792                 memset(&icp, 0, sizeof(icp));
 793                 /* set ICEOF for to the default value , which is 0*/
 794                 icp.iciof = DEFAULT_ICIOF;
 795                 icp.iceof = DEFAULT_RX_ICEOF;
 796                 icp.icsz = DEFAULT_ICSZ;
 797                 fman_if_set_ic_params(fif, &icp);
 798
 799                 fd_offset = RTE_PKTMBUF_HEADROOM + DPAA_HW_BUF_RESERVE;
 800                 fman_if_set_fdoff(fif, fd_offset);
 801
 802                 /* Buffer pool size should be equal to Dataroom Size*/
 803                 bp_size = rte_pktmbuf_data_room_size(mp);
 804                 fman_if_set_bp(fif, mp->size,
 805                                dpaa_intf->bp_info->bpid, bp_size);
 806                 dpaa_intf->valid = 1;
 807                 DPAA_PMD_DEBUG("if:%s fd_offset = %d offset = %d",
 808                                 dpaa_intf->name, fd_offset,
 809                                 fman_if_get_fdoff(fif));
 810         }
 811         DPAA_PMD_DEBUG("if:%s sg_on = %d, max_frm =%d", dpaa_intf->name,
 812                 fman_if_get_sg_enable(fif),
 813                 dev->data->dev_conf.rxmode.max_rx_pkt_len);
 814         /* checking if push mode only, no error check for now */
 815         if (!rxq->is_static &&
 816             dpaa_push_mode_max_queue > dpaa_push_queue_idx) {
 817                 struct qman_portal *qp;
 818                 int q_fd;
 819
 820                 dpaa_push_queue_idx++;
 821                 opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
 822                 opts.fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK |
 823                                    QM_FQCTRL_CTXASTASHING |
 824                                    QM_FQCTRL_PREFERINCACHE;
 825                 opts.fqd.context_a.stashing.exclusive = 0;
 826                 /* In muticore scenario stashing becomes a bottleneck on LS1046.
 827                  * So do not enable stashing in this case
 828                  */
 829                 if (dpaa_svr_family != SVR_LS1046A_FAMILY)
 830                         opts.fqd.context_a.stashing.annotation_cl =
 831                                                 DPAA_IF_RX_ANNOTATION_STASH;
 832                 opts.fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
 833                 opts.fqd.context_a.stashing.context_cl =
 834                                                 DPAA_IF_RX_CONTEXT_STASH;
 835
 836                 /*Create a channel and associate given queue with the channel*/
 837                 qman_alloc_pool_range((u32 *)&rxq->ch_id, 1, 1, 0);
 838                 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
 839                 opts.fqd.dest.channel = rxq->ch_id;
 840                 opts.fqd.dest.wq = DPAA_IF_RX_PRIORITY;
 841                 flags = QMAN_INITFQ_FLAG_SCHED;
 842
 843                 /* Configure tail drop */
 844                 if (dpaa_intf->cgr_rx) {
 845                         opts.we_mask |= QM_INITFQ_WE_CGID;
 846                         opts.fqd.cgid = dpaa_intf->cgr_rx[queue_idx].cgrid;
 847                         opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
 848                 }
 849                 ret = qman_init_fq(rxq, flags, &opts);
 850                 if (ret) {
 851                         DPAA_PMD_ERR("Channel/Q association failed. fqid 0x%x "
 852                                 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
 853                         return ret;
 854                 }
 855                 if (dpaa_svr_family == SVR_LS1043A_FAMILY) {
 856                         rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb_no_prefetch;
 857                 } else {
 858                         rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb;
 859                         rxq->cb.dqrr_prepare = dpaa_rx_cb_prepare;
 860                 }
 861
 862                 rxq->is_static = true;
 863
 864                 /* Allocate qman specific portals */
 865                 qp = fsl_qman_fq_portal_create(&q_fd);
 866                 if (!qp) {
 867                         DPAA_PMD_ERR("Unable to alloc fq portal");
 868                         return -1;
 869                 }
 870                 rxq->qp = qp;
 871
 872                 /* Set up the device interrupt handler */
 873                 if (!dev->intr_handle) {
 874                         struct rte_dpaa_device *dpaa_dev;
 875                         struct rte_device *rdev = dev->device;
 876
 877                         dpaa_dev = container_of(rdev, struct rte_dpaa_device,
 878                                                 device);
 879                         dev->intr_handle = &dpaa_dev->intr_handle;
 880                         dev->intr_handle->intr_vec = rte_zmalloc(NULL,
 881                                         dpaa_push_mode_max_queue, 0);
 882                         if (!dev->intr_handle->intr_vec) {
 883                                 DPAA_PMD_ERR("intr_vec alloc failed");
 884                                 return -ENOMEM;
 885                         }
 886                         dev->intr_handle->nb_efd = dpaa_push_mode_max_queue;
 887                         dev->intr_handle->max_intr = dpaa_push_mode_max_queue;
 888                 }
 889
 890                 dev->intr_handle->type = RTE_INTR_HANDLE_EXT;
 891                 dev->intr_handle->intr_vec[queue_idx] = queue_idx + 1;
 892                 dev->intr_handle->efds[queue_idx] = q_fd;
 893                 rxq->q_fd = q_fd;
 894         }
 895         rxq->bp_array = rte_dpaa_bpid_info;
 896         dev->data->rx_queues[queue_idx] = rxq;
 897
 898         /* configure the CGR size as per the desc size */
 899         if (dpaa_intf->cgr_rx) {
 900                 struct qm_mcc_initcgr cgr_opts = {0};
 901
 902                 rxq->nb_desc = nb_desc;
 903                 /* Enable tail drop with cgr on this queue */
 904                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, nb_desc, 0);
 905                 ret = qman_modify_cgr(dpaa_intf->cgr_rx, 0, &cgr_opts);
 906                 if (ret) {
 907                         DPAA_PMD_WARN(
 908                                 "rx taildrop modify fail on fqid %d (ret=%d)",
 909                                 rxq->fqid, ret);
 910                 }
 911         }
 912
 913         return 0;
 914 }
 915
 916 int
 917 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev,
 918                 int eth_rx_queue_id,
 919                 u16 ch_id,
 920                 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
 921 {
 922         int ret;
 923         u32 flags = 0;
 924         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 925         struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
 926         struct qm_mcc_initfq opts = {0};
 927
 928         if (dpaa_push_mode_max_queue)
 929                 DPAA_PMD_WARN("PUSH mode q and EVENTDEV are not compatible\n"
 930                               "PUSH mode already enabled for first %d queues.\n"
 931                               "To disable set DPAA_PUSH_QUEUES_NUMBER to 0\n",
 932                               dpaa_push_mode_max_queue);
 933
 934         dpaa_poll_queue_default_config(&opts);
 935
 936         switch (queue_conf->ev.sched_type) {
 937         case RTE_SCHED_TYPE_ATOMIC:
 938                 opts.fqd.fq_ctrl |= QM_FQCTRL_HOLDACTIVE;
 939                 /* Reset FQCTRL_AVOIDBLOCK bit as it is unnecessary
 940                  * configuration with HOLD_ACTIVE setting
 941                  */
 942                 opts.fqd.fq_ctrl &= (~QM_FQCTRL_AVOIDBLOCK);
 943                 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_atomic;
 944                 break;
 945         case RTE_SCHED_TYPE_ORDERED:
 946                 DPAA_PMD_ERR("Ordered queue schedule type is not supported\n");
 947                 return -1;
 948         default:
 949                 opts.fqd.fq_ctrl |= QM_FQCTRL_AVOIDBLOCK;
 950                 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_parallel;
 951                 break;
 952         }
 953
 954         opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
 955         opts.fqd.dest.channel = ch_id;
 956         opts.fqd.dest.wq = queue_conf->ev.priority;
 957
 958         if (dpaa_intf->cgr_rx) {
 959                 opts.we_mask |= QM_INITFQ_WE_CGID;
 960                 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
 961                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
 962         }
 963
 964         flags = QMAN_INITFQ_FLAG_SCHED;
 965
 966         ret = qman_init_fq(rxq, flags, &opts);
 967         if (ret) {
 968                 DPAA_PMD_ERR("Ev-Channel/Q association failed. fqid 0x%x "
 969                                 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
 970                 return ret;
 971         }
 972
 973         /* copy configuration which needs to be filled during dequeue */
 974         memcpy(&rxq->ev, &queue_conf->ev, sizeof(struct rte_event));
 975         dev->data->rx_queues[eth_rx_queue_id] = rxq;
 976
 977         return ret;
 978 }
 979
 980 int
 981 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev,
 982                 int eth_rx_queue_id)
 983 {
 984         struct qm_mcc_initfq opts;
 985         int ret;
 986         u32 flags = 0;
 987         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 988         struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
 989
 990         dpaa_poll_queue_default_config(&opts);
 991
 992         if (dpaa_intf->cgr_rx) {
 993                 opts.we_mask |= QM_INITFQ_WE_CGID;
 994                 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
 995                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
 996         }
 997
 998         ret = qman_init_fq(rxq, flags, &opts);
 999         if (ret) {
1000                 DPAA_PMD_ERR("init rx fqid %d failed with ret: %d",
1001                              rxq->fqid, ret);
1002         }
1003
1004         rxq->cb.dqrr_dpdk_cb = NULL;
1005         dev->data->rx_queues[eth_rx_queue_id] = NULL;
1006
1007         return 0;
1008 }
1009
1010 static
1011 void dpaa_eth_rx_queue_release(void *rxq __rte_unused)
1012 {
1013         PMD_INIT_FUNC_TRACE();
1014 }
1015
1016 static
1017 int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1018                             uint16_t nb_desc __rte_unused,
1019                 unsigned int socket_id __rte_unused,
1020                 const struct rte_eth_txconf *tx_conf)
1021 {
1022         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1023         struct qman_fq *txq = &dpaa_intf->tx_queues[queue_idx];
1024
1025         PMD_INIT_FUNC_TRACE();
1026
1027         /* Tx deferred start is not supported */
1028         if (tx_conf->tx_deferred_start) {
1029                 DPAA_PMD_ERR("%p:Tx deferred start not supported", (void *)dev);
1030                 return -EINVAL;
1031         }
1032         txq->nb_desc = UINT16_MAX;
1033         txq->offloads = tx_conf->offloads;
1034
1035         if (queue_idx >= dev->data->nb_tx_queues) {
1036                 rte_errno = EOVERFLOW;
1037                 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
1038                       (void *)dev, queue_idx, dev->data->nb_tx_queues);
1039                 return -rte_errno;
1040         }
1041
1042         DPAA_PMD_INFO("Tx queue setup for queue index: %d fq_id (0x%x)",
1043                         queue_idx, txq->fqid);
1044         dev->data->tx_queues[queue_idx] = txq;
1045
1046         return 0;
1047 }
1048
1049 static void dpaa_eth_tx_queue_release(void *txq __rte_unused)
1050 {
1051         PMD_INIT_FUNC_TRACE();
1052 }
1053
1054 static uint32_t
1055 dpaa_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1056 {
1057         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1058         struct qman_fq *rxq = &dpaa_intf->rx_queues[rx_queue_id];
1059         u32 frm_cnt = 0;
1060
1061         PMD_INIT_FUNC_TRACE();
1062
1063         if (qman_query_fq_frm_cnt(rxq, &frm_cnt) == 0) {
1064                 DPAA_PMD_DEBUG("RX frame count for q(%d) is %u",
1065                                rx_queue_id, frm_cnt);
1066         }
1067         return frm_cnt;
1068 }
1069
1070 static int dpaa_link_down(struct rte_eth_dev *dev)
1071 {
1072         struct fman_if *fif = dev->process_private;
1073         struct __fman_if *__fif;
1074
1075         PMD_INIT_FUNC_TRACE();
1076
1077         __fif = container_of(fif, struct __fman_if, __if);
1078
1079         if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC)
1080                 dpaa_update_link_status(__fif->node_name, ETH_LINK_DOWN);
1081         else
1082                 dpaa_eth_dev_stop(dev);
1083         return 0;
1084 }
1085
1086 static int dpaa_link_up(struct rte_eth_dev *dev)
1087 {
1088         struct fman_if *fif = dev->process_private;
1089         struct __fman_if *__fif;
1090
1091         PMD_INIT_FUNC_TRACE();
1092
1093         __fif = container_of(fif, struct __fman_if, __if);
1094
1095         if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC)
1096                 dpaa_update_link_status(__fif->node_name, ETH_LINK_UP);
1097         else
1098                 dpaa_eth_dev_start(dev);
1099         return 0;
1100 }
1101
1102 static int
1103 dpaa_flow_ctrl_set(struct rte_eth_dev *dev,
1104                    struct rte_eth_fc_conf *fc_conf)
1105 {
1106         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1107         struct rte_eth_fc_conf *net_fc;
1108
1109         PMD_INIT_FUNC_TRACE();
1110
1111         if (!(dpaa_intf->fc_conf)) {
1112                 dpaa_intf->fc_conf = rte_zmalloc(NULL,
1113                         sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
1114                 if (!dpaa_intf->fc_conf) {
1115                         DPAA_PMD_ERR("unable to save flow control info");
1116                         return -ENOMEM;
1117                 }
1118         }
1119         net_fc = dpaa_intf->fc_conf;
1120
1121         if (fc_conf->high_water < fc_conf->low_water) {
1122                 DPAA_PMD_ERR("Incorrect Flow Control Configuration");
1123                 return -EINVAL;
1124         }
1125
1126         if (fc_conf->mode == RTE_FC_NONE) {
1127                 return 0;
1128         } else if (fc_conf->mode == RTE_FC_TX_PAUSE ||
1129                  fc_conf->mode == RTE_FC_FULL) {
1130                 fman_if_set_fc_threshold(dev->process_private,
1131                                          fc_conf->high_water,
1132                                          fc_conf->low_water,
1133                                          dpaa_intf->bp_info->bpid);
1134                 if (fc_conf->pause_time)
1135                         fman_if_set_fc_quanta(dev->process_private,
1136                                               fc_conf->pause_time);
1137         }
1138
1139         /* Save the information in dpaa device */
1140         net_fc->pause_time = fc_conf->pause_time;
1141         net_fc->high_water = fc_conf->high_water;
1142         net_fc->low_water = fc_conf->low_water;
1143         net_fc->send_xon = fc_conf->send_xon;
1144         net_fc->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
1145         net_fc->mode = fc_conf->mode;
1146         net_fc->autoneg = fc_conf->autoneg;
1147
1148         return 0;
1149 }
1150
1151 static int
1152 dpaa_flow_ctrl_get(struct rte_eth_dev *dev,
1153                    struct rte_eth_fc_conf *fc_conf)
1154 {
1155         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1156         struct rte_eth_fc_conf *net_fc = dpaa_intf->fc_conf;
1157         int ret;
1158
1159         PMD_INIT_FUNC_TRACE();
1160
1161         if (net_fc) {
1162                 fc_conf->pause_time = net_fc->pause_time;
1163                 fc_conf->high_water = net_fc->high_water;
1164                 fc_conf->low_water = net_fc->low_water;
1165                 fc_conf->send_xon = net_fc->send_xon;
1166                 fc_conf->mac_ctrl_frame_fwd = net_fc->mac_ctrl_frame_fwd;
1167                 fc_conf->mode = net_fc->mode;
1168                 fc_conf->autoneg = net_fc->autoneg;
1169                 return 0;
1170         }
1171         ret = fman_if_get_fc_threshold(dev->process_private);
1172         if (ret) {
1173                 fc_conf->mode = RTE_FC_TX_PAUSE;
1174                 fc_conf->pause_time =
1175                         fman_if_get_fc_quanta(dev->process_private);
1176         } else {
1177                 fc_conf->mode = RTE_FC_NONE;
1178         }
1179
1180         return 0;
1181 }
1182
1183 static int
1184 dpaa_dev_add_mac_addr(struct rte_eth_dev *dev,
1185                              struct rte_ether_addr *addr,
1186                              uint32_t index,
1187                              __rte_unused uint32_t pool)
1188 {
1189         int ret;
1190
1191         PMD_INIT_FUNC_TRACE();
1192
1193         ret = fman_if_add_mac_addr(dev->process_private,
1194                                    addr->addr_bytes, index);
1195
1196         if (ret)
1197                 DPAA_PMD_ERR("Adding the MAC ADDR failed: err = %d", ret);
1198         return 0;
1199 }
1200
1201 static void
1202 dpaa_dev_remove_mac_addr(struct rte_eth_dev *dev,
1203                           uint32_t index)
1204 {
1205         PMD_INIT_FUNC_TRACE();
1206
1207         fman_if_clear_mac_addr(dev->process_private, index);
1208 }
1209
1210 static int
1211 dpaa_dev_set_mac_addr(struct rte_eth_dev *dev,
1212                        struct rte_ether_addr *addr)
1213 {
1214         int ret;
1215
1216         PMD_INIT_FUNC_TRACE();
1217
1218         ret = fman_if_add_mac_addr(dev->process_private, addr->addr_bytes, 0);
1219         if (ret)
1220                 DPAA_PMD_ERR("Setting the MAC ADDR failed %d", ret);
1221
1222         return ret;
1223 }
1224
1225 static int dpaa_dev_queue_intr_enable(struct rte_eth_dev *dev,
1226                                       uint16_t queue_id)
1227 {
1228         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1229         struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id];
1230
1231         if (!rxq->is_static)
1232                 return -EINVAL;
1233
1234         return qman_fq_portal_irqsource_add(rxq->qp, QM_PIRQ_DQRI);
1235 }
1236
1237 static int dpaa_dev_queue_intr_disable(struct rte_eth_dev *dev,
1238                                        uint16_t queue_id)
1239 {
1240         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1241         struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id];
1242         uint32_t temp;
1243         ssize_t temp1;
1244
1245         if (!rxq->is_static)
1246                 return -EINVAL;
1247
1248         qman_fq_portal_irqsource_remove(rxq->qp, ~0);
1249
1250         temp1 = read(rxq->q_fd, &temp, sizeof(temp));
1251         if (temp1 != sizeof(temp))
1252                 DPAA_PMD_ERR("irq read error");
1253
1254         qman_fq_portal_thread_irq(rxq->qp);
1255
1256         return 0;
1257 }
1258
1259 static void
1260 dpaa_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1261         struct rte_eth_rxq_info *qinfo)
1262 {
1263         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1264         struct qman_fq *rxq;
1265
1266         rxq = dev->data->rx_queues[queue_id];
1267
1268         qinfo->mp = dpaa_intf->bp_info->mp;
1269         qinfo->scattered_rx = dev->data->scattered_rx;
1270         qinfo->nb_desc = rxq->nb_desc;
1271         qinfo->conf.rx_free_thresh = 1;
1272         qinfo->conf.rx_drop_en = 1;
1273         qinfo->conf.rx_deferred_start = 0;
1274         qinfo->conf.offloads = rxq->offloads;
1275 }
1276
1277 static void
1278 dpaa_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1279         struct rte_eth_txq_info *qinfo)
1280 {
1281         struct qman_fq *txq;
1282
1283         txq = dev->data->tx_queues[queue_id];
1284
1285         qinfo->nb_desc = txq->nb_desc;
1286         qinfo->conf.tx_thresh.pthresh = 0;
1287         qinfo->conf.tx_thresh.hthresh = 0;
1288         qinfo->conf.tx_thresh.wthresh = 0;
1289
1290         qinfo->conf.tx_free_thresh = 0;
1291         qinfo->conf.tx_rs_thresh = 0;
1292         qinfo->conf.offloads = txq->offloads;
1293         qinfo->conf.tx_deferred_start = 0;
1294 }
1295
1296 static struct eth_dev_ops dpaa_devops = {
1297         .dev_configure            = dpaa_eth_dev_configure,
1298         .dev_start                = dpaa_eth_dev_start,
1299         .dev_stop                 = dpaa_eth_dev_stop,
1300         .dev_close                = dpaa_eth_dev_close,
1301         .dev_infos_get            = dpaa_eth_dev_info,
1302         .dev_supported_ptypes_get = dpaa_supported_ptypes_get,
1303
1304         .rx_queue_setup           = dpaa_eth_rx_queue_setup,
1305         .tx_queue_setup           = dpaa_eth_tx_queue_setup,
1306         .rx_queue_release         = dpaa_eth_rx_queue_release,
1307         .tx_queue_release         = dpaa_eth_tx_queue_release,
1308         .rx_queue_count           = dpaa_dev_rx_queue_count,
1309         .rx_burst_mode_get        = dpaa_dev_rx_burst_mode_get,
1310         .tx_burst_mode_get        = dpaa_dev_tx_burst_mode_get,
1311         .rxq_info_get             = dpaa_rxq_info_get,
1312         .txq_info_get             = dpaa_txq_info_get,
1313
1314         .flow_ctrl_get            = dpaa_flow_ctrl_get,
1315         .flow_ctrl_set            = dpaa_flow_ctrl_set,
1316
1317         .link_update              = dpaa_eth_link_update,
1318         .stats_get                = dpaa_eth_stats_get,
1319         .xstats_get               = dpaa_dev_xstats_get,
1320         .xstats_get_by_id         = dpaa_xstats_get_by_id,
1321         .xstats_get_names_by_id   = dpaa_xstats_get_names_by_id,
1322         .xstats_get_names         = dpaa_xstats_get_names,
1323         .xstats_reset             = dpaa_eth_stats_reset,
1324         .stats_reset              = dpaa_eth_stats_reset,
1325         .promiscuous_enable       = dpaa_eth_promiscuous_enable,
1326         .promiscuous_disable      = dpaa_eth_promiscuous_disable,
1327         .allmulticast_enable      = dpaa_eth_multicast_enable,
1328         .allmulticast_disable     = dpaa_eth_multicast_disable,
1329         .mtu_set                  = dpaa_mtu_set,
1330         .dev_set_link_down        = dpaa_link_down,
1331         .dev_set_link_up          = dpaa_link_up,
1332         .mac_addr_add             = dpaa_dev_add_mac_addr,
1333         .mac_addr_remove          = dpaa_dev_remove_mac_addr,
1334         .mac_addr_set             = dpaa_dev_set_mac_addr,
1335
1336         .fw_version_get           = dpaa_fw_version_get,
1337
1338         .rx_queue_intr_enable     = dpaa_dev_queue_intr_enable,
1339         .rx_queue_intr_disable    = dpaa_dev_queue_intr_disable,
1340 };
1341
1342 static bool
1343 is_device_supported(struct rte_eth_dev *dev, struct rte_dpaa_driver *drv)
1344 {
1345         if (strcmp(dev->device->driver->name,
1346                    drv->driver.name))
1347                 return false;
1348
1349         return true;
1350 }
1351
1352 static bool
1353 is_dpaa_supported(struct rte_eth_dev *dev)
1354 {
1355         return is_device_supported(dev, &rte_dpaa_pmd);
1356 }
1357
1358 int
1359 rte_pmd_dpaa_set_tx_loopback(uint8_t port, uint8_t on)
1360 {
1361         struct rte_eth_dev *dev;
1362
1363         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
1364
1365         dev = &rte_eth_devices[port];
1366
1367         if (!is_dpaa_supported(dev))
1368                 return -ENOTSUP;
1369
1370         if (on)
1371                 fman_if_loopback_enable(dev->process_private);
1372         else
1373                 fman_if_loopback_disable(dev->process_private);
1374
1375         return 0;
1376 }
1377
1378 static int dpaa_fc_set_default(struct dpaa_if *dpaa_intf,
1379                                struct fman_if *fman_intf)
1380 {
1381         struct rte_eth_fc_conf *fc_conf;
1382         int ret;
1383
1384         PMD_INIT_FUNC_TRACE();
1385
1386         if (!(dpaa_intf->fc_conf)) {
1387                 dpaa_intf->fc_conf = rte_zmalloc(NULL,
1388                         sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
1389                 if (!dpaa_intf->fc_conf) {
1390                         DPAA_PMD_ERR("unable to save flow control info");
1391                         return -ENOMEM;
1392                 }
1393         }
1394         fc_conf = dpaa_intf->fc_conf;
1395         ret = fman_if_get_fc_threshold(fman_intf);
1396         if (ret) {
1397                 fc_conf->mode = RTE_FC_TX_PAUSE;
1398                 fc_conf->pause_time = fman_if_get_fc_quanta(fman_intf);
1399         } else {
1400                 fc_conf->mode = RTE_FC_NONE;
1401         }
1402
1403         return 0;
1404 }
1405
1406 /* Initialise an Rx FQ */
1407 static int dpaa_rx_queue_init(struct qman_fq *fq, struct qman_cgr *cgr_rx,
1408                               uint32_t fqid)
1409 {
1410         struct qm_mcc_initfq opts = {0};
1411         int ret;
1412         u32 flags = QMAN_FQ_FLAG_NO_ENQUEUE;
1413         struct qm_mcc_initcgr cgr_opts = {
1414                 .we_mask = QM_CGR_WE_CS_THRES |
1415                                 QM_CGR_WE_CSTD_EN |
1416                                 QM_CGR_WE_MODE,
1417                 .cgr = {
1418                         .cstd_en = QM_CGR_EN,
1419                         .mode = QMAN_CGR_MODE_FRAME
1420                 }
1421         };
1422
1423         if (fmc_q || default_q) {
1424                 ret = qman_reserve_fqid(fqid);
1425                 if (ret) {
1426                         DPAA_PMD_ERR("reserve rx fqid 0x%x failed, ret: %d",
1427                                      fqid, ret);
1428                         return -EINVAL;
1429                 }
1430         }
1431
1432         DPAA_PMD_DEBUG("creating rx fq %p, fqid 0x%x", fq, fqid);
1433         ret = qman_create_fq(fqid, flags, fq);
1434         if (ret) {
1435                 DPAA_PMD_ERR("create rx fqid 0x%x failed with ret: %d",
1436                         fqid, ret);
1437                 return ret;
1438         }
1439         fq->is_static = false;
1440
1441         dpaa_poll_queue_default_config(&opts);
1442
1443         if (cgr_rx) {
1444                 /* Enable tail drop with cgr on this queue */
1445                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, td_threshold, 0);
1446                 cgr_rx->cb = NULL;
1447                 ret = qman_create_cgr(cgr_rx, QMAN_CGR_FLAG_USE_INIT,
1448                                       &cgr_opts);
1449                 if (ret) {
1450                         DPAA_PMD_WARN(
1451                                 "rx taildrop init fail on rx fqid 0x%x(ret=%d)",
1452                                 fq->fqid, ret);
1453                         goto without_cgr;
1454                 }
1455                 opts.we_mask |= QM_INITFQ_WE_CGID;
1456                 opts.fqd.cgid = cgr_rx->cgrid;
1457                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1458         }
1459 without_cgr:
1460         ret = qman_init_fq(fq, 0, &opts);
1461         if (ret)
1462                 DPAA_PMD_ERR("init rx fqid 0x%x failed with ret:%d", fqid, ret);
1463         return ret;
1464 }
1465
1466 /* Initialise a Tx FQ */
1467 static int dpaa_tx_queue_init(struct qman_fq *fq,
1468                               struct fman_if *fman_intf,
1469                               struct qman_cgr *cgr_tx)
1470 {
1471         struct qm_mcc_initfq opts = {0};
1472         struct qm_mcc_initcgr cgr_opts = {
1473                 .we_mask = QM_CGR_WE_CS_THRES |
1474                                 QM_CGR_WE_CSTD_EN |
1475                                 QM_CGR_WE_MODE,
1476                 .cgr = {
1477                         .cstd_en = QM_CGR_EN,
1478                         .mode = QMAN_CGR_MODE_FRAME
1479                 }
1480         };
1481         int ret;
1482
1483         ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID |
1484                              QMAN_FQ_FLAG_TO_DCPORTAL, fq);
1485         if (ret) {
1486                 DPAA_PMD_ERR("create tx fq failed with ret: %d", ret);
1487                 return ret;
1488         }
1489         opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL |
1490                        QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA;
1491         opts.fqd.dest.channel = fman_intf->tx_channel_id;
1492         opts.fqd.dest.wq = DPAA_IF_TX_PRIORITY;
1493         opts.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE;
1494         opts.fqd.context_b = 0;
1495         /* no tx-confirmation */
1496         opts.fqd.context_a.hi = 0x80000000 | fman_dealloc_bufs_mask_hi;
1497         opts.fqd.context_a.lo = 0 | fman_dealloc_bufs_mask_lo;
1498         DPAA_PMD_DEBUG("init tx fq %p, fqid 0x%x", fq, fq->fqid);
1499
1500         if (cgr_tx) {
1501                 /* Enable tail drop with cgr on this queue */
1502                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres,
1503                                       td_tx_threshold, 0);
1504                 cgr_tx->cb = NULL;
1505                 ret = qman_create_cgr(cgr_tx, QMAN_CGR_FLAG_USE_INIT,
1506                                       &cgr_opts);
1507                 if (ret) {
1508                         DPAA_PMD_WARN(
1509                                 "rx taildrop init fail on rx fqid 0x%x(ret=%d)",
1510                                 fq->fqid, ret);
1511                         goto without_cgr;
1512                 }
1513                 opts.we_mask |= QM_INITFQ_WE_CGID;
1514                 opts.fqd.cgid = cgr_tx->cgrid;
1515                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1516                 DPAA_PMD_DEBUG("Tx FQ tail drop enabled, threshold = %d\n",
1517                                 td_tx_threshold);
1518         }
1519 without_cgr:
1520         ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts);
1521         if (ret)
1522                 DPAA_PMD_ERR("init tx fqid 0x%x failed %d", fq->fqid, ret);
1523         return ret;
1524 }
1525
1526 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1527 /* Initialise a DEBUG FQ ([rt]x_error, rx_default). */
1528 static int dpaa_debug_queue_init(struct qman_fq *fq, uint32_t fqid)
1529 {
1530         struct qm_mcc_initfq opts = {0};
1531         int ret;
1532
1533         PMD_INIT_FUNC_TRACE();
1534
1535         ret = qman_reserve_fqid(fqid);
1536         if (ret) {
1537                 DPAA_PMD_ERR("Reserve debug fqid %d failed with ret: %d",
1538                         fqid, ret);
1539                 return -EINVAL;
1540         }
1541         /* "map" this Rx FQ to one of the interfaces Tx FQID */
1542         DPAA_PMD_DEBUG("Creating debug fq %p, fqid %d", fq, fqid);
1543         ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq);
1544         if (ret) {
1545                 DPAA_PMD_ERR("create debug fqid %d failed with ret: %d",
1546                         fqid, ret);
1547                 return ret;
1548         }
1549         opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL;
1550         opts.fqd.dest.wq = DPAA_IF_DEBUG_PRIORITY;
1551         ret = qman_init_fq(fq, 0, &opts);
1552         if (ret)
1553                 DPAA_PMD_ERR("init debug fqid %d failed with ret: %d",
1554                             fqid, ret);
1555         return ret;
1556 }
1557 #endif
1558
1559 /* Initialise a network interface */
1560 static int
1561 dpaa_dev_init_secondary(struct rte_eth_dev *eth_dev)
1562 {
1563         struct rte_dpaa_device *dpaa_device;
1564         struct fm_eth_port_cfg *cfg;
1565         struct dpaa_if *dpaa_intf;
1566         struct fman_if *fman_intf;
1567         int dev_id;
1568
1569         PMD_INIT_FUNC_TRACE();
1570
1571         dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1572         dev_id = dpaa_device->id.dev_id;
1573         cfg = dpaa_get_eth_port_cfg(dev_id);
1574         fman_intf = cfg->fman_if;
1575         eth_dev->process_private = fman_intf;
1576
1577         /* Plugging of UCODE burst API not supported in Secondary */
1578         dpaa_intf = eth_dev->data->dev_private;
1579         eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
1580         if (dpaa_intf->cgr_tx)
1581                 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx_slow;
1582         else
1583                 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx;
1584 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP
1585         qman_set_fq_lookup_table(
1586                 dpaa_intf->rx_queues->qman_fq_lookup_table);
1587 #endif
1588
1589         return 0;
1590 }
1591
1592 /* Initialise a network interface */
1593 static int
1594 dpaa_dev_init(struct rte_eth_dev *eth_dev)
1595 {
1596         int num_rx_fqs, fqid;
1597         int loop, ret = 0;
1598         int dev_id;
1599         struct rte_dpaa_device *dpaa_device;
1600         struct dpaa_if *dpaa_intf;
1601         struct fm_eth_port_cfg *cfg;
1602         struct fman_if *fman_intf;
1603         struct fman_if_bpool *bp, *tmp_bp;
1604         uint32_t cgrid[DPAA_MAX_NUM_PCD_QUEUES];
1605         uint32_t cgrid_tx[MAX_DPAA_CORES];
1606         uint32_t dev_rx_fqids[DPAA_MAX_NUM_PCD_QUEUES];
1607
1608         PMD_INIT_FUNC_TRACE();
1609
1610         dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1611         dev_id = dpaa_device->id.dev_id;
1612         dpaa_intf = eth_dev->data->dev_private;
1613         cfg = dpaa_get_eth_port_cfg(dev_id);
1614         fman_intf = cfg->fman_if;
1615
1616         dpaa_intf->name = dpaa_device->name;
1617
1618         /* save fman_if & cfg in the interface struture */
1619         eth_dev->process_private = fman_intf;
1620         dpaa_intf->ifid = dev_id;
1621         dpaa_intf->cfg = cfg;
1622
1623         memset((char *)dev_rx_fqids, 0,
1624                 sizeof(uint32_t) * DPAA_MAX_NUM_PCD_QUEUES);
1625
1626         /* Initialize Rx FQ's */
1627         if (default_q) {
1628                 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES;
1629         } else if (fmc_q) {
1630                 num_rx_fqs = 1;
1631         } else {
1632                 /* FMCLESS mode, load balance to multiple cores.*/
1633                 num_rx_fqs = rte_lcore_count();
1634         }
1635
1636         /* Each device can not have more than DPAA_MAX_NUM_PCD_QUEUES RX
1637          * queues.
1638          */
1639         if (num_rx_fqs < 0 || num_rx_fqs > DPAA_MAX_NUM_PCD_QUEUES) {
1640                 DPAA_PMD_ERR("Invalid number of RX queues\n");
1641                 return -EINVAL;
1642         }
1643
1644         if (num_rx_fqs > 0) {
1645                 dpaa_intf->rx_queues = rte_zmalloc(NULL,
1646                         sizeof(struct qman_fq) * num_rx_fqs, MAX_CACHELINE);
1647                 if (!dpaa_intf->rx_queues) {
1648                         DPAA_PMD_ERR("Failed to alloc mem for RX queues\n");
1649                         return -ENOMEM;
1650                 }
1651         } else {
1652                 dpaa_intf->rx_queues = NULL;
1653         }
1654
1655         memset(cgrid, 0, sizeof(cgrid));
1656         memset(cgrid_tx, 0, sizeof(cgrid_tx));
1657
1658         /* if DPAA_TX_TAILDROP_THRESHOLD is set, use that value; if 0, it means
1659          * Tx tail drop is disabled.
1660          */
1661         if (getenv("DPAA_TX_TAILDROP_THRESHOLD")) {
1662                 td_tx_threshold = atoi(getenv("DPAA_TX_TAILDROP_THRESHOLD"));
1663                 DPAA_PMD_DEBUG("Tail drop threshold env configured: %u",
1664                                td_tx_threshold);
1665                 /* if a very large value is being configured */
1666                 if (td_tx_threshold > UINT16_MAX)
1667                         td_tx_threshold = CGR_RX_PERFQ_THRESH;
1668         }
1669
1670         /* If congestion control is enabled globally*/
1671         if (num_rx_fqs > 0 && td_threshold) {
1672                 dpaa_intf->cgr_rx = rte_zmalloc(NULL,
1673                         sizeof(struct qman_cgr) * num_rx_fqs, MAX_CACHELINE);
1674                 if (!dpaa_intf->cgr_rx) {
1675                         DPAA_PMD_ERR("Failed to alloc mem for cgr_rx\n");
1676                         ret = -ENOMEM;
1677                         goto free_rx;
1678                 }
1679
1680                 ret = qman_alloc_cgrid_range(&cgrid[0], num_rx_fqs, 1, 0);
1681                 if (ret != num_rx_fqs) {
1682                         DPAA_PMD_WARN("insufficient CGRIDs available");
1683                         ret = -EINVAL;
1684                         goto free_rx;
1685                 }
1686         } else {
1687                 dpaa_intf->cgr_rx = NULL;
1688         }
1689
1690         if (!fmc_q && !default_q) {
1691                 ret = qman_alloc_fqid_range(dev_rx_fqids, num_rx_fqs,
1692                                             num_rx_fqs, 0);
1693                 if (ret < 0) {
1694                         DPAA_PMD_ERR("Failed to alloc rx fqid's\n");
1695                         goto free_rx;
1696                 }
1697         }
1698
1699         for (loop = 0; loop < num_rx_fqs; loop++) {
1700                 if (default_q)
1701                         fqid = cfg->rx_def;
1702                 else
1703                         fqid = dev_rx_fqids[loop];
1704
1705                 if (dpaa_intf->cgr_rx)
1706                         dpaa_intf->cgr_rx[loop].cgrid = cgrid[loop];
1707
1708                 ret = dpaa_rx_queue_init(&dpaa_intf->rx_queues[loop],
1709                         dpaa_intf->cgr_rx ? &dpaa_intf->cgr_rx[loop] : NULL,
1710                         fqid);
1711                 if (ret)
1712                         goto free_rx;
1713                 dpaa_intf->rx_queues[loop].dpaa_intf = dpaa_intf;
1714         }
1715         dpaa_intf->nb_rx_queues = num_rx_fqs;
1716
1717         /* Initialise Tx FQs.free_rx Have as many Tx FQ's as number of cores */
1718         dpaa_intf->tx_queues = rte_zmalloc(NULL, sizeof(struct qman_fq) *
1719                 MAX_DPAA_CORES, MAX_CACHELINE);
1720         if (!dpaa_intf->tx_queues) {
1721                 DPAA_PMD_ERR("Failed to alloc mem for TX queues\n");
1722                 ret = -ENOMEM;
1723                 goto free_rx;
1724         }
1725
1726         /* If congestion control is enabled globally*/
1727         if (td_tx_threshold) {
1728                 dpaa_intf->cgr_tx = rte_zmalloc(NULL,
1729                         sizeof(struct qman_cgr) * MAX_DPAA_CORES,
1730                         MAX_CACHELINE);
1731                 if (!dpaa_intf->cgr_tx) {
1732                         DPAA_PMD_ERR("Failed to alloc mem for cgr_tx\n");
1733                         ret = -ENOMEM;
1734                         goto free_rx;
1735                 }
1736
1737                 ret = qman_alloc_cgrid_range(&cgrid_tx[0], MAX_DPAA_CORES,
1738                                              1, 0);
1739                 if (ret != MAX_DPAA_CORES) {
1740                         DPAA_PMD_WARN("insufficient CGRIDs available");
1741                         ret = -EINVAL;
1742                         goto free_rx;
1743                 }
1744         } else {
1745                 dpaa_intf->cgr_tx = NULL;
1746         }
1747
1748
1749         for (loop = 0; loop < MAX_DPAA_CORES; loop++) {
1750                 if (dpaa_intf->cgr_tx)
1751                         dpaa_intf->cgr_tx[loop].cgrid = cgrid_tx[loop];
1752
1753                 ret = dpaa_tx_queue_init(&dpaa_intf->tx_queues[loop],
1754                         fman_intf,
1755                         dpaa_intf->cgr_tx ? &dpaa_intf->cgr_tx[loop] : NULL);
1756                 if (ret)
1757                         goto free_tx;
1758                 dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf;
1759         }
1760         dpaa_intf->nb_tx_queues = MAX_DPAA_CORES;
1761
1762 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1763         dpaa_debug_queue_init(&dpaa_intf->debug_queues[
1764                 DPAA_DEBUG_FQ_RX_ERROR], fman_intf->fqid_rx_err);
1765         dpaa_intf->debug_queues[DPAA_DEBUG_FQ_RX_ERROR].dpaa_intf = dpaa_intf;
1766         dpaa_debug_queue_init(&dpaa_intf->debug_queues[
1767                 DPAA_DEBUG_FQ_TX_ERROR], fman_intf->fqid_tx_err);
1768         dpaa_intf->debug_queues[DPAA_DEBUG_FQ_TX_ERROR].dpaa_intf = dpaa_intf;
1769 #endif
1770
1771         DPAA_PMD_DEBUG("All frame queues created");
1772
1773         /* Get the initial configuration for flow control */
1774         dpaa_fc_set_default(dpaa_intf, fman_intf);
1775
1776         /* reset bpool list, initialize bpool dynamically */
1777         list_for_each_entry_safe(bp, tmp_bp, &cfg->fman_if->bpool_list, node) {
1778                 list_del(&bp->node);
1779                 rte_free(bp);
1780         }
1781
1782         /* Populate ethdev structure */
1783         eth_dev->dev_ops = &dpaa_devops;
1784         eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
1785         eth_dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
1786
1787         /* Allocate memory for storing MAC addresses */
1788         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr",
1789                 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER, 0);
1790         if (eth_dev->data->mac_addrs == NULL) {
1791                 DPAA_PMD_ERR("Failed to allocate %d bytes needed to "
1792                                                 "store MAC addresses",
1793                                 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER);
1794                 ret = -ENOMEM;
1795                 goto free_tx;
1796         }
1797
1798         /* copy the primary mac address */
1799         rte_ether_addr_copy(&fman_intf->mac_addr, &eth_dev->data->mac_addrs[0]);
1800
1801         RTE_LOG(INFO, PMD, "net: dpaa: %s: %02x:%02x:%02x:%02x:%02x:%02x\n",
1802                 dpaa_device->name,
1803                 fman_intf->mac_addr.addr_bytes[0],
1804                 fman_intf->mac_addr.addr_bytes[1],
1805                 fman_intf->mac_addr.addr_bytes[2],
1806                 fman_intf->mac_addr.addr_bytes[3],
1807                 fman_intf->mac_addr.addr_bytes[4],
1808                 fman_intf->mac_addr.addr_bytes[5]);
1809
1810
1811         /* Disable RX mode */
1812         fman_if_discard_rx_errors(fman_intf);
1813         fman_if_disable_rx(fman_intf);
1814         /* Disable promiscuous mode */
1815         fman_if_promiscuous_disable(fman_intf);
1816         /* Disable multicast */
1817         fman_if_reset_mcast_filter_table(fman_intf);
1818         /* Reset interface statistics */
1819         fman_if_stats_reset(fman_intf);
1820         /* Disable SG by default */
1821         fman_if_set_sg(fman_intf, 0);
1822         fman_if_set_maxfrm(fman_intf, RTE_ETHER_MAX_LEN + VLAN_TAG_SIZE);
1823
1824         return 0;
1825
1826 free_tx:
1827         rte_free(dpaa_intf->tx_queues);
1828         dpaa_intf->tx_queues = NULL;
1829         dpaa_intf->nb_tx_queues = 0;
1830
1831 free_rx:
1832         rte_free(dpaa_intf->cgr_rx);
1833         rte_free(dpaa_intf->cgr_tx);
1834         rte_free(dpaa_intf->rx_queues);
1835         dpaa_intf->rx_queues = NULL;
1836         dpaa_intf->nb_rx_queues = 0;
1837         return ret;
1838 }
1839
1840 static int
1841 dpaa_dev_uninit(struct rte_eth_dev *dev)
1842 {
1843         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1844         int loop;
1845
1846         PMD_INIT_FUNC_TRACE();
1847
1848         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1849                 return -EPERM;
1850
1851         if (!dpaa_intf) {
1852                 DPAA_PMD_WARN("Already closed or not started");
1853                 return -1;
1854         }
1855
1856         /* DPAA FM deconfig */
1857         if (!(default_q || fmc_q)) {
1858                 if (dpaa_fm_deconfig(dpaa_intf, dev->process_private))
1859                         DPAA_PMD_WARN("DPAA FM deconfig failed\n");
1860         }
1861
1862         dpaa_eth_dev_close(dev);
1863
1864         /* release configuration memory */
1865         if (dpaa_intf->fc_conf)
1866                 rte_free(dpaa_intf->fc_conf);
1867
1868         /* Release RX congestion Groups */
1869         if (dpaa_intf->cgr_rx) {
1870                 for (loop = 0; loop < dpaa_intf->nb_rx_queues; loop++)
1871                         qman_delete_cgr(&dpaa_intf->cgr_rx[loop]);
1872
1873                 qman_release_cgrid_range(dpaa_intf->cgr_rx[loop].cgrid,
1874                                          dpaa_intf->nb_rx_queues);
1875         }
1876
1877         rte_free(dpaa_intf->cgr_rx);
1878         dpaa_intf->cgr_rx = NULL;
1879
1880         /* Release TX congestion Groups */
1881         if (dpaa_intf->cgr_tx) {
1882                 for (loop = 0; loop < MAX_DPAA_CORES; loop++)
1883                         qman_delete_cgr(&dpaa_intf->cgr_tx[loop]);
1884
1885                 qman_release_cgrid_range(dpaa_intf->cgr_tx[loop].cgrid,
1886                                          MAX_DPAA_CORES);
1887                 rte_free(dpaa_intf->cgr_tx);
1888                 dpaa_intf->cgr_tx = NULL;
1889         }
1890
1891         rte_free(dpaa_intf->rx_queues);
1892         dpaa_intf->rx_queues = NULL;
1893
1894         rte_free(dpaa_intf->tx_queues);
1895         dpaa_intf->tx_queues = NULL;
1896
1897         dev->dev_ops = NULL;
1898         dev->rx_pkt_burst = NULL;
1899         dev->tx_pkt_burst = NULL;
1900
1901         return 0;
1902 }
1903
1904 static int
1905 rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv,
1906                struct rte_dpaa_device *dpaa_dev)
1907 {
1908         int diag;
1909         int ret;
1910         struct rte_eth_dev *eth_dev;
1911
1912         PMD_INIT_FUNC_TRACE();
1913
1914         if ((DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE) >
1915                 RTE_PKTMBUF_HEADROOM) {
1916                 DPAA_PMD_ERR(
1917                 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA Annotation req(%d)",
1918                 RTE_PKTMBUF_HEADROOM,
1919                 DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE);
1920
1921                 return -1;
1922         }
1923
1924         /* In case of secondary process, the device is already configured
1925          * and no further action is required, except portal initialization
1926          * and verifying secondary attachment to port name.
1927          */
1928         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1929                 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name);
1930                 if (!eth_dev)
1931                         return -ENOMEM;
1932                 eth_dev->device = &dpaa_dev->device;
1933                 eth_dev->dev_ops = &dpaa_devops;
1934
1935                 ret = dpaa_dev_init_secondary(eth_dev);
1936                 if (ret != 0) {
1937                         RTE_LOG(ERR, PMD, "secondary dev init failed\n");
1938                         return ret;
1939                 }
1940
1941                 rte_eth_dev_probing_finish(eth_dev);
1942                 return 0;
1943         }
1944
1945         if (!is_global_init && (rte_eal_process_type() == RTE_PROC_PRIMARY)) {
1946                 if (access("/tmp/fmc.bin", F_OK) == -1) {
1947                         DPAA_PMD_INFO("* FMC not configured.Enabling default mode");
1948                         default_q = 1;
1949                 }
1950
1951                 if (!(default_q || fmc_q)) {
1952                         if (dpaa_fm_init()) {
1953                                 DPAA_PMD_ERR("FM init failed\n");
1954                                 return -1;
1955                         }
1956                 }
1957
1958                 /* disabling the default push mode for LS1043 */
1959                 if (dpaa_svr_family == SVR_LS1043A_FAMILY)
1960                         dpaa_push_mode_max_queue = 0;
1961
1962                 /* if push mode queues to be enabled. Currenly we are allowing
1963                  * only one queue per thread.
1964                  */
1965                 if (getenv("DPAA_PUSH_QUEUES_NUMBER")) {
1966                         dpaa_push_mode_max_queue =
1967                                         atoi(getenv("DPAA_PUSH_QUEUES_NUMBER"));
1968                         if (dpaa_push_mode_max_queue > DPAA_MAX_PUSH_MODE_QUEUE)
1969                             dpaa_push_mode_max_queue = DPAA_MAX_PUSH_MODE_QUEUE;
1970                 }
1971
1972                 is_global_init = 1;
1973         }
1974
1975         if (unlikely(!DPAA_PER_LCORE_PORTAL)) {
1976                 ret = rte_dpaa_portal_init((void *)1);
1977                 if (ret) {
1978                         DPAA_PMD_ERR("Unable to initialize portal");
1979                         return ret;
1980                 }
1981         }
1982
1983         eth_dev = rte_eth_dev_allocate(dpaa_dev->name);
1984         if (!eth_dev)
1985                 return -ENOMEM;
1986
1987         eth_dev->data->dev_private =
1988                         rte_zmalloc("ethdev private structure",
1989                                         sizeof(struct dpaa_if),
1990                                         RTE_CACHE_LINE_SIZE);
1991         if (!eth_dev->data->dev_private) {
1992                 DPAA_PMD_ERR("Cannot allocate memzone for port data");
1993                 rte_eth_dev_release_port(eth_dev);
1994                 return -ENOMEM;
1995         }
1996
1997         eth_dev->device = &dpaa_dev->device;
1998         dpaa_dev->eth_dev = eth_dev;
1999
2000         qman_ern_register_cb(dpaa_free_mbuf);
2001
2002         if (dpaa_drv->drv_flags & RTE_DPAA_DRV_INTR_LSC)
2003                 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;
2004
2005         /* Invoke PMD device initialization function */
2006         diag = dpaa_dev_init(eth_dev);
2007         if (diag == 0) {
2008                 rte_eth_dev_probing_finish(eth_dev);
2009                 return 0;
2010         }
2011
2012         rte_eth_dev_release_port(eth_dev);
2013         return diag;
2014 }
2015
2016 static int
2017 rte_dpaa_remove(struct rte_dpaa_device *dpaa_dev)
2018 {
2019         struct rte_eth_dev *eth_dev;
2020
2021         PMD_INIT_FUNC_TRACE();
2022
2023         eth_dev = dpaa_dev->eth_dev;
2024         dpaa_dev_uninit(eth_dev);
2025
2026         rte_eth_dev_release_port(eth_dev);
2027
2028         return 0;
2029 }
2030
2031 static void __attribute__((destructor(102))) dpaa_finish(void)
2032 {
2033         /* For secondary, primary will do all the cleanup */
2034         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2035                 return;
2036
2037         if (!(default_q || fmc_q)) {
2038                 unsigned int i;
2039
2040                 for (i = 0; i < RTE_MAX_ETHPORTS; i++) {
2041                         if (rte_eth_devices[i].dev_ops == &dpaa_devops) {
2042                                 struct rte_eth_dev *dev = &rte_eth_devices[i];
2043                                 struct dpaa_if *dpaa_intf =
2044                                         dev->data->dev_private;
2045                                 struct fman_if *fif =
2046                                         dev->process_private;
2047                                 if (dpaa_intf->port_handle)
2048                                         if (dpaa_fm_deconfig(dpaa_intf, fif))
2049                                                 DPAA_PMD_WARN("DPAA FM "
2050                                                         "deconfig failed\n");
2051                         }
2052                 }
2053                 if (is_global_init)
2054                         if (dpaa_fm_term())
2055                                 DPAA_PMD_WARN("DPAA FM term failed\n");
2056
2057                 is_global_init = 0;
2058
2059                 DPAA_PMD_INFO("DPAA fman cleaned up");
2060         }
2061 }
2062
2063 static struct rte_dpaa_driver rte_dpaa_pmd = {
2064         .drv_flags = RTE_DPAA_DRV_INTR_LSC,
2065         .drv_type = FSL_DPAA_ETH,
2066         .probe = rte_dpaa_probe,
2067         .remove = rte_dpaa_remove,
2068 };
2069
2070 RTE_PMD_REGISTER_DPAA(net_dpaa, rte_dpaa_pmd);
2071 RTE_LOG_REGISTER(dpaa_logtype_pmd, pmd.net.dpaa, NOTICE);