drivers/net/dpaa/dpaa_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  *   Copyright 2016 Freescale Semiconductor, Inc. All rights reserved.
   4  *   Copyright 2017-2020 NXP
   5  *
   6  */
   7 /* System headers */
   8 #include <stdio.h>
   9 #include <inttypes.h>
  10 #include <unistd.h>
  11 #include <limits.h>
  12 #include <sched.h>
  13 #include <signal.h>
  14 #include <pthread.h>
  15 #include <sys/types.h>
  16 #include <sys/syscall.h>
  17
  18 #include <rte_string_fns.h>
  19 #include <rte_byteorder.h>
  20 #include <rte_common.h>
  21 #include <rte_interrupts.h>
  22 #include <rte_log.h>
  23 #include <rte_debug.h>
  24 #include <rte_pci.h>
  25 #include <rte_atomic.h>
  26 #include <rte_branch_prediction.h>
  27 #include <rte_memory.h>
  28 #include <rte_tailq.h>
  29 #include <rte_eal.h>
  30 #include <rte_alarm.h>
  31 #include <rte_ether.h>
  32 #include <rte_ethdev_driver.h>
  33 #include <rte_malloc.h>
  34 #include <rte_ring.h>
  35
  36 #include <rte_dpaa_bus.h>
  37 #include <rte_dpaa_logs.h>
  38 #include <dpaa_mempool.h>
  39
  40 #include <dpaa_ethdev.h>
  41 #include <dpaa_rxtx.h>
  42 #include <dpaa_flow.h>
  43 #include <rte_pmd_dpaa.h>
  44
  45 #include <fsl_usd.h>
  46 #include <fsl_qman.h>
  47 #include <fsl_bman.h>
  48 #include <fsl_fman.h>
  49 #include <process.h>
  50 #include <fmlib/fm_ext.h>
  51
  52 /* Supported Rx offloads */
  53 static uint64_t dev_rx_offloads_sup =
  54                 DEV_RX_OFFLOAD_JUMBO_FRAME |
  55                 DEV_RX_OFFLOAD_SCATTER;
  56
  57 /* Rx offloads which cannot be disabled */
  58 static uint64_t dev_rx_offloads_nodis =
  59                 DEV_RX_OFFLOAD_IPV4_CKSUM |
  60                 DEV_RX_OFFLOAD_UDP_CKSUM |
  61                 DEV_RX_OFFLOAD_TCP_CKSUM |
  62                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
  63                 DEV_RX_OFFLOAD_RSS_HASH;
  64
  65 /* Supported Tx offloads */
  66 static uint64_t dev_tx_offloads_sup =
  67                 DEV_TX_OFFLOAD_MT_LOCKFREE |
  68                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
  69
  70 /* Tx offloads which cannot be disabled */
  71 static uint64_t dev_tx_offloads_nodis =
  72                 DEV_TX_OFFLOAD_IPV4_CKSUM |
  73                 DEV_TX_OFFLOAD_UDP_CKSUM |
  74                 DEV_TX_OFFLOAD_TCP_CKSUM |
  75                 DEV_TX_OFFLOAD_SCTP_CKSUM |
  76                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
  77                 DEV_TX_OFFLOAD_MULTI_SEGS;
  78
  79 /* Keep track of whether QMAN and BMAN have been globally initialized */
  80 static int is_global_init;
  81 static int fmc_q = 1;   /* Indicates the use of static fmc for distribution */
  82 static int default_q;   /* use default queue - FMC is not executed*/
  83 /* At present we only allow up to 4 push mode queues as default - as each of
  84  * this queue need dedicated portal and we are short of portals.
  85  */
  86 #define DPAA_MAX_PUSH_MODE_QUEUE       8
  87 #define DPAA_DEFAULT_PUSH_MODE_QUEUE   4
  88
  89 static int dpaa_push_mode_max_queue = DPAA_DEFAULT_PUSH_MODE_QUEUE;
  90 static int dpaa_push_queue_idx; /* Queue index which are in push mode*/
  91
  92
  93 /* Per RX FQ Taildrop in frame count */
  94 static unsigned int td_threshold = CGR_RX_PERFQ_THRESH;
  95
  96 /* Per TX FQ Taildrop in frame count, disabled by default */
  97 static unsigned int td_tx_threshold;
  98
  99 struct rte_dpaa_xstats_name_off {
 100         char name[RTE_ETH_XSTATS_NAME_SIZE];
 101         uint32_t offset;
 102 };
 103
 104 static const struct rte_dpaa_xstats_name_off dpaa_xstats_strings[] = {
 105         {"rx_align_err",
 106                 offsetof(struct dpaa_if_stats, raln)},
 107         {"rx_valid_pause",
 108                 offsetof(struct dpaa_if_stats, rxpf)},
 109         {"rx_fcs_err",
 110                 offsetof(struct dpaa_if_stats, rfcs)},
 111         {"rx_vlan_frame",
 112                 offsetof(struct dpaa_if_stats, rvlan)},
 113         {"rx_frame_err",
 114                 offsetof(struct dpaa_if_stats, rerr)},
 115         {"rx_drop_err",
 116                 offsetof(struct dpaa_if_stats, rdrp)},
 117         {"rx_undersized",
 118                 offsetof(struct dpaa_if_stats, rund)},
 119         {"rx_oversize_err",
 120                 offsetof(struct dpaa_if_stats, rovr)},
 121         {"rx_fragment_pkt",
 122                 offsetof(struct dpaa_if_stats, rfrg)},
 123         {"tx_valid_pause",
 124                 offsetof(struct dpaa_if_stats, txpf)},
 125         {"tx_fcs_err",
 126                 offsetof(struct dpaa_if_stats, terr)},
 127         {"tx_vlan_frame",
 128                 offsetof(struct dpaa_if_stats, tvlan)},
 129         {"rx_undersized",
 130                 offsetof(struct dpaa_if_stats, tund)},
 131 };
 132
 133 static struct rte_dpaa_driver rte_dpaa_pmd;
 134
 135 static int
 136 dpaa_eth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info);
 137
 138 static int dpaa_eth_link_update(struct rte_eth_dev *dev,
 139                                 int wait_to_complete __rte_unused);
 140
 141 static void dpaa_interrupt_handler(void *param);
 142
 143 static inline void
 144 dpaa_poll_queue_default_config(struct qm_mcc_initfq *opts)
 145 {
 146         memset(opts, 0, sizeof(struct qm_mcc_initfq));
 147         opts->we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
 148         opts->fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | QM_FQCTRL_CTXASTASHING |
 149                            QM_FQCTRL_PREFERINCACHE;
 150         opts->fqd.context_a.stashing.exclusive = 0;
 151         if (dpaa_svr_family != SVR_LS1046A_FAMILY)
 152                 opts->fqd.context_a.stashing.annotation_cl =
 153                                                 DPAA_IF_RX_ANNOTATION_STASH;
 154         opts->fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
 155         opts->fqd.context_a.stashing.context_cl = DPAA_IF_RX_CONTEXT_STASH;
 156 }
 157
 158 static int
 159 dpaa_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 160 {
 161         uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
 162                                 + VLAN_TAG_SIZE;
 163         uint32_t buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
 164
 165         PMD_INIT_FUNC_TRACE();
 166
 167         if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA_MAX_RX_PKT_LEN)
 168                 return -EINVAL;
 169         /*
 170          * Refuse mtu that requires the support of scattered packets
 171          * when this feature has not been enabled before.
 172          */
 173         if (dev->data->min_rx_buf_size &&
 174                 !dev->data->scattered_rx && frame_size > buffsz) {
 175                 DPAA_PMD_ERR("SG not enabled, will not fit in one buffer");
 176                 return -EINVAL;
 177         }
 178
 179         /* check <seg size> * <max_seg>  >= max_frame */
 180         if (dev->data->min_rx_buf_size && dev->data->scattered_rx &&
 181                 (frame_size > buffsz * DPAA_SGT_MAX_ENTRIES)) {
 182                 DPAA_PMD_ERR("Too big to fit for Max SG list %d",
 183                                 buffsz * DPAA_SGT_MAX_ENTRIES);
 184                 return -EINVAL;
 185         }
 186
 187         if (frame_size > RTE_ETHER_MAX_LEN)
 188                 dev->data->dev_conf.rxmode.offloads |=
 189                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 190         else
 191                 dev->data->dev_conf.rxmode.offloads &=
 192                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 193
 194         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 195
 196         fman_if_set_maxfrm(dev->process_private, frame_size);
 197
 198         return 0;
 199 }
 200
 201 static int
 202 dpaa_eth_dev_configure(struct rte_eth_dev *dev)
 203 {
 204         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 205         uint64_t rx_offloads = eth_conf->rxmode.offloads;
 206         uint64_t tx_offloads = eth_conf->txmode.offloads;
 207         struct rte_device *rdev = dev->device;
 208         struct rte_dpaa_device *dpaa_dev;
 209         struct fman_if *fif = dev->process_private;
 210         struct __fman_if *__fif;
 211         struct rte_intr_handle *intr_handle;
 212         int ret;
 213
 214         PMD_INIT_FUNC_TRACE();
 215
 216         dpaa_dev = container_of(rdev, struct rte_dpaa_device, device);
 217         intr_handle = &dpaa_dev->intr_handle;
 218         __fif = container_of(fif, struct __fman_if, __if);
 219
 220         /* Rx offloads which are enabled by default */
 221         if (dev_rx_offloads_nodis & ~rx_offloads) {
 222                 DPAA_PMD_INFO(
 223                 "Some of rx offloads enabled by default - requested 0x%" PRIx64
 224                 " fixed are 0x%" PRIx64,
 225                 rx_offloads, dev_rx_offloads_nodis);
 226         }
 227
 228         /* Tx offloads which are enabled by default */
 229         if (dev_tx_offloads_nodis & ~tx_offloads) {
 230                 DPAA_PMD_INFO(
 231                 "Some of tx offloads enabled by default - requested 0x%" PRIx64
 232                 " fixed are 0x%" PRIx64,
 233                 tx_offloads, dev_tx_offloads_nodis);
 234         }
 235
 236         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 237                 uint32_t max_len;
 238
 239                 DPAA_PMD_DEBUG("enabling jumbo");
 240
 241                 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <=
 242                     DPAA_MAX_RX_PKT_LEN)
 243                         max_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
 244                 else {
 245                         DPAA_PMD_INFO("enabling jumbo override conf max len=%d "
 246                                 "supported is %d",
 247                                 dev->data->dev_conf.rxmode.max_rx_pkt_len,
 248                                 DPAA_MAX_RX_PKT_LEN);
 249                         max_len = DPAA_MAX_RX_PKT_LEN;
 250                 }
 251
 252                 fman_if_set_maxfrm(dev->process_private, max_len);
 253                 dev->data->mtu = max_len
 254                         - RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE;
 255         }
 256
 257         if (rx_offloads & DEV_RX_OFFLOAD_SCATTER) {
 258                 DPAA_PMD_DEBUG("enabling scatter mode");
 259                 fman_if_set_sg(dev->process_private, 1);
 260                 dev->data->scattered_rx = 1;
 261         }
 262
 263         if (!(default_q || fmc_q)) {
 264                 if (dpaa_fm_config(dev,
 265                         eth_conf->rx_adv_conf.rss_conf.rss_hf)) {
 266                         dpaa_write_fm_config_to_file();
 267                         DPAA_PMD_ERR("FM port configuration: Failed\n");
 268                         return -1;
 269                 }
 270                 dpaa_write_fm_config_to_file();
 271         }
 272
 273         /* if the interrupts were configured on this devices*/
 274         if (intr_handle && intr_handle->fd) {
 275                 if (dev->data->dev_conf.intr_conf.lsc != 0)
 276                         rte_intr_callback_register(intr_handle,
 277                                            dpaa_interrupt_handler,
 278                                            (void *)dev);
 279
 280                 ret = dpaa_intr_enable(__fif->node_name, intr_handle->fd);
 281                 if (ret) {
 282                         if (dev->data->dev_conf.intr_conf.lsc != 0) {
 283                                 rte_intr_callback_unregister(intr_handle,
 284                                         dpaa_interrupt_handler,
 285                                         (void *)dev);
 286                                 if (ret == EINVAL)
 287                                         printf("Failed to enable interrupt: Not Supported\n");
 288                                 else
 289                                         printf("Failed to enable interrupt\n");
 290                         }
 291                         dev->data->dev_conf.intr_conf.lsc = 0;
 292                         dev->data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC;
 293                 }
 294         }
 295         return 0;
 296 }
 297
 298 static const uint32_t *
 299 dpaa_supported_ptypes_get(struct rte_eth_dev *dev)
 300 {
 301         static const uint32_t ptypes[] = {
 302                 RTE_PTYPE_L2_ETHER,
 303                 RTE_PTYPE_L2_ETHER_VLAN,
 304                 RTE_PTYPE_L2_ETHER_ARP,
 305                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
 306                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
 307                 RTE_PTYPE_L4_ICMP,
 308                 RTE_PTYPE_L4_TCP,
 309                 RTE_PTYPE_L4_UDP,
 310                 RTE_PTYPE_L4_FRAG,
 311                 RTE_PTYPE_L4_TCP,
 312                 RTE_PTYPE_L4_UDP,
 313                 RTE_PTYPE_L4_SCTP
 314         };
 315
 316         PMD_INIT_FUNC_TRACE();
 317
 318         if (dev->rx_pkt_burst == dpaa_eth_queue_rx)
 319                 return ptypes;
 320         return NULL;
 321 }
 322
 323 static void dpaa_interrupt_handler(void *param)
 324 {
 325         struct rte_eth_dev *dev = param;
 326         struct rte_device *rdev = dev->device;
 327         struct rte_dpaa_device *dpaa_dev;
 328         struct rte_intr_handle *intr_handle;
 329         uint64_t buf;
 330         int bytes_read;
 331
 332         dpaa_dev = container_of(rdev, struct rte_dpaa_device, device);
 333         intr_handle = &dpaa_dev->intr_handle;
 334
 335         bytes_read = read(intr_handle->fd, &buf, sizeof(uint64_t));
 336         if (bytes_read < 0)
 337                 DPAA_PMD_ERR("Error reading eventfd\n");
 338         dpaa_eth_link_update(dev, 0);
 339         rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
 340 }
 341
 342 static int dpaa_eth_dev_start(struct rte_eth_dev *dev)
 343 {
 344         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 345
 346         PMD_INIT_FUNC_TRACE();
 347
 348         if (!(default_q || fmc_q))
 349                 dpaa_write_fm_config_to_file();
 350
 351         /* Change tx callback to the real one */
 352         if (dpaa_intf->cgr_tx)
 353                 dev->tx_pkt_burst = dpaa_eth_queue_tx_slow;
 354         else
 355                 dev->tx_pkt_burst = dpaa_eth_queue_tx;
 356
 357         fman_if_enable_rx(dev->process_private);
 358
 359         return 0;
 360 }
 361
 362 static void dpaa_eth_dev_stop(struct rte_eth_dev *dev)
 363 {
 364         struct fman_if *fif = dev->process_private;
 365
 366         PMD_INIT_FUNC_TRACE();
 367
 368         if (!fif->is_shared_mac)
 369                 fman_if_disable_rx(fif);
 370         dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
 371 }
 372
 373 static int dpaa_eth_dev_close(struct rte_eth_dev *dev)
 374 {
 375         struct fman_if *fif = dev->process_private;
 376         struct __fman_if *__fif;
 377         struct rte_device *rdev = dev->device;
 378         struct rte_dpaa_device *dpaa_dev;
 379         struct rte_intr_handle *intr_handle;
 380         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 381         int loop;
 382
 383         PMD_INIT_FUNC_TRACE();
 384
 385         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 386                 return 0;
 387
 388         if (!dpaa_intf) {
 389                 DPAA_PMD_WARN("Already closed or not started");
 390                 return -1;
 391         }
 392
 393         /* DPAA FM deconfig */
 394         if (!(default_q || fmc_q)) {
 395                 if (dpaa_fm_deconfig(dpaa_intf, dev->process_private))
 396                         DPAA_PMD_WARN("DPAA FM deconfig failed\n");
 397         }
 398
 399         dpaa_dev = container_of(rdev, struct rte_dpaa_device, device);
 400         intr_handle = &dpaa_dev->intr_handle;
 401         __fif = container_of(fif, struct __fman_if, __if);
 402
 403         dpaa_eth_dev_stop(dev);
 404
 405         if (intr_handle && intr_handle->fd &&
 406             dev->data->dev_conf.intr_conf.lsc != 0) {
 407                 dpaa_intr_disable(__fif->node_name);
 408                 rte_intr_callback_unregister(intr_handle,
 409                                              dpaa_interrupt_handler,
 410                                              (void *)dev);
 411         }
 412
 413         /* release configuration memory */
 414         if (dpaa_intf->fc_conf)
 415                 rte_free(dpaa_intf->fc_conf);
 416
 417         /* Release RX congestion Groups */
 418         if (dpaa_intf->cgr_rx) {
 419                 for (loop = 0; loop < dpaa_intf->nb_rx_queues; loop++)
 420                         qman_delete_cgr(&dpaa_intf->cgr_rx[loop]);
 421
 422                 qman_release_cgrid_range(dpaa_intf->cgr_rx[loop].cgrid,
 423                                          dpaa_intf->nb_rx_queues);
 424         }
 425
 426         rte_free(dpaa_intf->cgr_rx);
 427         dpaa_intf->cgr_rx = NULL;
 428         /* Release TX congestion Groups */
 429         if (dpaa_intf->cgr_tx) {
 430                 for (loop = 0; loop < MAX_DPAA_CORES; loop++)
 431                         qman_delete_cgr(&dpaa_intf->cgr_tx[loop]);
 432
 433                 qman_release_cgrid_range(dpaa_intf->cgr_tx[loop].cgrid,
 434                                          MAX_DPAA_CORES);
 435                 rte_free(dpaa_intf->cgr_tx);
 436                 dpaa_intf->cgr_tx = NULL;
 437         }
 438
 439         rte_free(dpaa_intf->rx_queues);
 440         dpaa_intf->rx_queues = NULL;
 441
 442         rte_free(dpaa_intf->tx_queues);
 443         dpaa_intf->tx_queues = NULL;
 444
 445         dev->dev_ops = NULL;
 446         dev->rx_pkt_burst = NULL;
 447         dev->tx_pkt_burst = NULL;
 448
 449         return 0;
 450 }
 451
 452 static int
 453 dpaa_fw_version_get(struct rte_eth_dev *dev __rte_unused,
 454                      char *fw_version,
 455                      size_t fw_size)
 456 {
 457         int ret;
 458         FILE *svr_file = NULL;
 459         unsigned int svr_ver = 0;
 460
 461         PMD_INIT_FUNC_TRACE();
 462
 463         svr_file = fopen(DPAA_SOC_ID_FILE, "r");
 464         if (!svr_file) {
 465                 DPAA_PMD_ERR("Unable to open SoC device");
 466                 return -ENOTSUP; /* Not supported on this infra */
 467         }
 468         if (fscanf(svr_file, "svr:%x", &svr_ver) > 0)
 469                 dpaa_svr_family = svr_ver & SVR_MASK;
 470         else
 471                 DPAA_PMD_ERR("Unable to read SoC device");
 472
 473         fclose(svr_file);
 474
 475         ret = snprintf(fw_version, fw_size, "SVR:%x-fman-v%x",
 476                        svr_ver, fman_ip_rev);
 477         ret += 1; /* add the size of '\0' */
 478
 479         if (fw_size < (uint32_t)ret)
 480                 return ret;
 481         else
 482                 return 0;
 483 }
 484
 485 static int dpaa_eth_dev_info(struct rte_eth_dev *dev,
 486                              struct rte_eth_dev_info *dev_info)
 487 {
 488         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 489         struct fman_if *fif = dev->process_private;
 490
 491         DPAA_PMD_DEBUG(": %s", dpaa_intf->name);
 492
 493         dev_info->max_rx_queues = dpaa_intf->nb_rx_queues;
 494         dev_info->max_tx_queues = dpaa_intf->nb_tx_queues;
 495         dev_info->max_rx_pktlen = DPAA_MAX_RX_PKT_LEN;
 496         dev_info->max_mac_addrs = DPAA_MAX_MAC_FILTER;
 497         dev_info->max_hash_mac_addrs = 0;
 498         dev_info->max_vfs = 0;
 499         dev_info->max_vmdq_pools = ETH_16_POOLS;
 500         dev_info->flow_type_rss_offloads = DPAA_RSS_OFFLOAD_ALL;
 501
 502         if (fif->mac_type == fman_mac_1g) {
 503                 dev_info->speed_capa = ETH_LINK_SPEED_1G;
 504         } else if (fif->mac_type == fman_mac_2_5g) {
 505                 dev_info->speed_capa = ETH_LINK_SPEED_1G
 506                                         | ETH_LINK_SPEED_2_5G;
 507         } else if (fif->mac_type == fman_mac_10g) {
 508                 dev_info->speed_capa = ETH_LINK_SPEED_1G
 509                                         | ETH_LINK_SPEED_2_5G
 510                                         | ETH_LINK_SPEED_10G;
 511         } else {
 512                 DPAA_PMD_ERR("invalid link_speed: %s, %d",
 513                              dpaa_intf->name, fif->mac_type);
 514                 return -EINVAL;
 515         }
 516
 517         dev_info->rx_offload_capa = dev_rx_offloads_sup |
 518                                         dev_rx_offloads_nodis;
 519         dev_info->tx_offload_capa = dev_tx_offloads_sup |
 520                                         dev_tx_offloads_nodis;
 521         dev_info->default_rxportconf.burst_size = DPAA_DEF_RX_BURST_SIZE;
 522         dev_info->default_txportconf.burst_size = DPAA_DEF_TX_BURST_SIZE;
 523         dev_info->default_rxportconf.nb_queues = 1;
 524         dev_info->default_txportconf.nb_queues = 1;
 525         dev_info->default_txportconf.ring_size = CGR_TX_CGR_THRESH;
 526         dev_info->default_rxportconf.ring_size = CGR_RX_PERFQ_THRESH;
 527
 528         return 0;
 529 }
 530
 531 static int
 532 dpaa_dev_rx_burst_mode_get(struct rte_eth_dev *dev,
 533                         __rte_unused uint16_t queue_id,
 534                         struct rte_eth_burst_mode *mode)
 535 {
 536         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 537         int ret = -EINVAL;
 538         unsigned int i;
 539         const struct burst_info {
 540                 uint64_t flags;
 541                 const char *output;
 542         } rx_offload_map[] = {
 543                         {DEV_RX_OFFLOAD_JUMBO_FRAME, " Jumbo frame,"},
 544                         {DEV_RX_OFFLOAD_SCATTER, " Scattered,"},
 545                         {DEV_RX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"},
 546                         {DEV_RX_OFFLOAD_UDP_CKSUM, " UDP csum,"},
 547                         {DEV_RX_OFFLOAD_TCP_CKSUM, " TCP csum,"},
 548                         {DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
 549                         {DEV_RX_OFFLOAD_RSS_HASH, " RSS,"}
 550         };
 551
 552         /* Update Rx offload info */
 553         for (i = 0; i < RTE_DIM(rx_offload_map); i++) {
 554                 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) {
 555                         snprintf(mode->info, sizeof(mode->info), "%s",
 556                                 rx_offload_map[i].output);
 557                         ret = 0;
 558                         break;
 559                 }
 560         }
 561         return ret;
 562 }
 563
 564 static int
 565 dpaa_dev_tx_burst_mode_get(struct rte_eth_dev *dev,
 566                         __rte_unused uint16_t queue_id,
 567                         struct rte_eth_burst_mode *mode)
 568 {
 569         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 570         int ret = -EINVAL;
 571         unsigned int i;
 572         const struct burst_info {
 573                 uint64_t flags;
 574                 const char *output;
 575         } tx_offload_map[] = {
 576                         {DEV_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"},
 577                         {DEV_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"},
 578                         {DEV_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"},
 579                         {DEV_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"},
 580                         {DEV_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"},
 581                         {DEV_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
 582                         {DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
 583                         {DEV_TX_OFFLOAD_MULTI_SEGS, " Scattered,"}
 584         };
 585
 586         /* Update Tx offload info */
 587         for (i = 0; i < RTE_DIM(tx_offload_map); i++) {
 588                 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) {
 589                         snprintf(mode->info, sizeof(mode->info), "%s",
 590                                 tx_offload_map[i].output);
 591                         ret = 0;
 592                         break;
 593                 }
 594         }
 595         return ret;
 596 }
 597
 598 static int dpaa_eth_link_update(struct rte_eth_dev *dev,
 599                                 int wait_to_complete __rte_unused)
 600 {
 601         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 602         struct rte_eth_link *link = &dev->data->dev_link;
 603         struct fman_if *fif = dev->process_private;
 604         struct __fman_if *__fif = container_of(fif, struct __fman_if, __if);
 605         int ret;
 606
 607         PMD_INIT_FUNC_TRACE();
 608
 609         if (fif->mac_type == fman_mac_1g)
 610                 link->link_speed = ETH_SPEED_NUM_1G;
 611         else if (fif->mac_type == fman_mac_2_5g)
 612                 link->link_speed = ETH_SPEED_NUM_2_5G;
 613         else if (fif->mac_type == fman_mac_10g)
 614                 link->link_speed = ETH_SPEED_NUM_10G;
 615         else
 616                 DPAA_PMD_ERR("invalid link_speed: %s, %d",
 617                              dpaa_intf->name, fif->mac_type);
 618
 619         if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC) {
 620                 ret = dpaa_get_link_status(__fif->node_name);
 621                 if (ret < 0)
 622                         return ret;
 623                 link->link_status = ret;
 624         } else {
 625                 link->link_status = dpaa_intf->valid;
 626         }
 627
 628         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 629         link->link_autoneg = ETH_LINK_AUTONEG;
 630
 631         DPAA_PMD_INFO("Port %d Link is %s\n", dev->data->port_id,
 632                       link->link_status ? "Up" : "Down");
 633         return 0;
 634 }
 635
 636 static int dpaa_eth_stats_get(struct rte_eth_dev *dev,
 637                                struct rte_eth_stats *stats)
 638 {
 639         PMD_INIT_FUNC_TRACE();
 640
 641         fman_if_stats_get(dev->process_private, stats);
 642         return 0;
 643 }
 644
 645 static int dpaa_eth_stats_reset(struct rte_eth_dev *dev)
 646 {
 647         PMD_INIT_FUNC_TRACE();
 648
 649         fman_if_stats_reset(dev->process_private);
 650
 651         return 0;
 652 }
 653
 654 static int
 655 dpaa_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
 656                     unsigned int n)
 657 {
 658         unsigned int i = 0, num = RTE_DIM(dpaa_xstats_strings);
 659         uint64_t values[sizeof(struct dpaa_if_stats) / 8];
 660
 661         if (n < num)
 662                 return num;
 663
 664         if (xstats == NULL)
 665                 return 0;
 666
 667         fman_if_stats_get_all(dev->process_private, values,
 668                               sizeof(struct dpaa_if_stats) / 8);
 669
 670         for (i = 0; i < num; i++) {
 671                 xstats[i].id = i;
 672                 xstats[i].value = values[dpaa_xstats_strings[i].offset / 8];
 673         }
 674         return i;
 675 }
 676
 677 static int
 678 dpaa_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 679                       struct rte_eth_xstat_name *xstats_names,
 680                       unsigned int limit)
 681 {
 682         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 683
 684         if (limit < stat_cnt)
 685                 return stat_cnt;
 686
 687         if (xstats_names != NULL)
 688                 for (i = 0; i < stat_cnt; i++)
 689                         strlcpy(xstats_names[i].name,
 690                                 dpaa_xstats_strings[i].name,
 691                                 sizeof(xstats_names[i].name));
 692
 693         return stat_cnt;
 694 }
 695
 696 static int
 697 dpaa_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 698                       uint64_t *values, unsigned int n)
 699 {
 700         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 701         uint64_t values_copy[sizeof(struct dpaa_if_stats) / 8];
 702
 703         if (!ids) {
 704                 if (n < stat_cnt)
 705                         return stat_cnt;
 706
 707                 if (!values)
 708                         return 0;
 709
 710                 fman_if_stats_get_all(dev->process_private, values_copy,
 711                                       sizeof(struct dpaa_if_stats) / 8);
 712
 713                 for (i = 0; i < stat_cnt; i++)
 714                         values[i] =
 715                                 values_copy[dpaa_xstats_strings[i].offset / 8];
 716
 717                 return stat_cnt;
 718         }
 719
 720         dpaa_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
 721
 722         for (i = 0; i < n; i++) {
 723                 if (ids[i] >= stat_cnt) {
 724                         DPAA_PMD_ERR("id value isn't valid");
 725                         return -1;
 726                 }
 727                 values[i] = values_copy[ids[i]];
 728         }
 729         return n;
 730 }
 731
 732 static int
 733 dpaa_xstats_get_names_by_id(
 734         struct rte_eth_dev *dev,
 735         struct rte_eth_xstat_name *xstats_names,
 736         const uint64_t *ids,
 737         unsigned int limit)
 738 {
 739         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 740         struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
 741
 742         if (!ids)
 743                 return dpaa_xstats_get_names(dev, xstats_names, limit);
 744
 745         dpaa_xstats_get_names(dev, xstats_names_copy, limit);
 746
 747         for (i = 0; i < limit; i++) {
 748                 if (ids[i] >= stat_cnt) {
 749                         DPAA_PMD_ERR("id value isn't valid");
 750                         return -1;
 751                 }
 752                 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
 753         }
 754         return limit;
 755 }
 756
 757 static int dpaa_eth_promiscuous_enable(struct rte_eth_dev *dev)
 758 {
 759         PMD_INIT_FUNC_TRACE();
 760
 761         fman_if_promiscuous_enable(dev->process_private);
 762
 763         return 0;
 764 }
 765
 766 static int dpaa_eth_promiscuous_disable(struct rte_eth_dev *dev)
 767 {
 768         PMD_INIT_FUNC_TRACE();
 769
 770         fman_if_promiscuous_disable(dev->process_private);
 771
 772         return 0;
 773 }
 774
 775 static int dpaa_eth_multicast_enable(struct rte_eth_dev *dev)
 776 {
 777         PMD_INIT_FUNC_TRACE();
 778
 779         fman_if_set_mcast_filter_table(dev->process_private);
 780
 781         return 0;
 782 }
 783
 784 static int dpaa_eth_multicast_disable(struct rte_eth_dev *dev)
 785 {
 786         PMD_INIT_FUNC_TRACE();
 787
 788         fman_if_reset_mcast_filter_table(dev->process_private);
 789
 790         return 0;
 791 }
 792
 793 static void dpaa_fman_if_pool_setup(struct rte_eth_dev *dev)
 794 {
 795         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 796         struct fman_if_ic_params icp;
 797         uint32_t fd_offset;
 798         uint32_t bp_size;
 799
 800         memset(&icp, 0, sizeof(icp));
 801         /* set ICEOF for to the default value , which is 0*/
 802         icp.iciof = DEFAULT_ICIOF;
 803         icp.iceof = DEFAULT_RX_ICEOF;
 804         icp.icsz = DEFAULT_ICSZ;
 805         fman_if_set_ic_params(dev->process_private, &icp);
 806
 807         fd_offset = RTE_PKTMBUF_HEADROOM + DPAA_HW_BUF_RESERVE;
 808         fman_if_set_fdoff(dev->process_private, fd_offset);
 809
 810         /* Buffer pool size should be equal to Dataroom Size*/
 811         bp_size = rte_pktmbuf_data_room_size(dpaa_intf->bp_info->mp);
 812
 813         fman_if_set_bp(dev->process_private,
 814                        dpaa_intf->bp_info->mp->size,
 815                        dpaa_intf->bp_info->bpid, bp_size);
 816 }
 817
 818 static inline int dpaa_eth_rx_queue_bp_check(struct rte_eth_dev *dev,
 819                                              int8_t vsp_id, uint32_t bpid)
 820 {
 821         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 822         struct fman_if *fif = dev->process_private;
 823
 824         if (fif->num_profiles) {
 825                 if (vsp_id < 0)
 826                         vsp_id = fif->base_profile_id;
 827         } else {
 828                 if (vsp_id < 0)
 829                         vsp_id = 0;
 830         }
 831
 832         if (dpaa_intf->vsp_bpid[vsp_id] &&
 833                 bpid != dpaa_intf->vsp_bpid[vsp_id]) {
 834                 DPAA_PMD_ERR("Various MPs are assigned to RXQs with same VSP");
 835
 836                 return -1;
 837         }
 838
 839         return 0;
 840 }
 841
 842 static
 843 int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 844                             uint16_t nb_desc,
 845                             unsigned int socket_id __rte_unused,
 846                             const struct rte_eth_rxconf *rx_conf,
 847                             struct rte_mempool *mp)
 848 {
 849         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 850         struct fman_if *fif = dev->process_private;
 851         struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_idx];
 852         struct qm_mcc_initfq opts = {0};
 853         u32 flags = 0;
 854         int ret;
 855         u32 buffsz = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
 856
 857         PMD_INIT_FUNC_TRACE();
 858
 859         if (queue_idx >= dev->data->nb_rx_queues) {
 860                 rte_errno = EOVERFLOW;
 861                 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
 862                       (void *)dev, queue_idx, dev->data->nb_rx_queues);
 863                 return -rte_errno;
 864         }
 865
 866         /* Rx deferred start is not supported */
 867         if (rx_conf->rx_deferred_start) {
 868                 DPAA_PMD_ERR("%p:Rx deferred start not supported", (void *)dev);
 869                 return -EINVAL;
 870         }
 871         rxq->nb_desc = UINT16_MAX;
 872         rxq->offloads = rx_conf->offloads;
 873
 874         DPAA_PMD_INFO("Rx queue setup for queue index: %d fq_id (0x%x)",
 875                         queue_idx, rxq->fqid);
 876
 877         if (!fif->num_profiles) {
 878                 if (dpaa_intf->bp_info && dpaa_intf->bp_info->bp &&
 879                         dpaa_intf->bp_info->mp != mp) {
 880                         DPAA_PMD_WARN("Multiple pools on same interface not"
 881                                       " supported");
 882                         return -EINVAL;
 883                 }
 884         } else {
 885                 if (dpaa_eth_rx_queue_bp_check(dev, rxq->vsp_id,
 886                         DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid)) {
 887                         return -EINVAL;
 888                 }
 889         }
 890
 891         /* Max packet can fit in single buffer */
 892         if (dev->data->dev_conf.rxmode.max_rx_pkt_len <= buffsz) {
 893                 ;
 894         } else if (dev->data->dev_conf.rxmode.offloads &
 895                         DEV_RX_OFFLOAD_SCATTER) {
 896                 if (dev->data->dev_conf.rxmode.max_rx_pkt_len >
 897                         buffsz * DPAA_SGT_MAX_ENTRIES) {
 898                         DPAA_PMD_ERR("max RxPkt size %d too big to fit "
 899                                 "MaxSGlist %d",
 900                                 dev->data->dev_conf.rxmode.max_rx_pkt_len,
 901                                 buffsz * DPAA_SGT_MAX_ENTRIES);
 902                         rte_errno = EOVERFLOW;
 903                         return -rte_errno;
 904                 }
 905         } else {
 906                 DPAA_PMD_WARN("The requested maximum Rx packet size (%u) is"
 907                      " larger than a single mbuf (%u) and scattered"
 908                      " mode has not been requested",
 909                      dev->data->dev_conf.rxmode.max_rx_pkt_len,
 910                      buffsz - RTE_PKTMBUF_HEADROOM);
 911         }
 912
 913         dpaa_intf->bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp);
 914
 915         /* For shared interface, it's done in kernel, skip.*/
 916         if (!fif->is_shared_mac)
 917                 dpaa_fman_if_pool_setup(dev);
 918
 919         if (fif->num_profiles) {
 920                 int8_t vsp_id = rxq->vsp_id;
 921
 922                 if (vsp_id >= 0) {
 923                         ret = dpaa_port_vsp_update(dpaa_intf, fmc_q, vsp_id,
 924                                         DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid,
 925                                         fif);
 926                         if (ret) {
 927                                 DPAA_PMD_ERR("dpaa_port_vsp_update failed");
 928                                 return ret;
 929                         }
 930                 } else {
 931                         DPAA_PMD_INFO("Base profile is associated to"
 932                                 " RXQ fqid:%d\r\n", rxq->fqid);
 933                         if (fif->is_shared_mac) {
 934                                 DPAA_PMD_ERR("Fatal: Base profile is associated"
 935                                              " to shared interface on DPDK.");
 936                                 return -EINVAL;
 937                         }
 938                         dpaa_intf->vsp_bpid[fif->base_profile_id] =
 939                                 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid;
 940                 }
 941         } else {
 942                 dpaa_intf->vsp_bpid[0] =
 943                         DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid;
 944         }
 945
 946         dpaa_intf->valid = 1;
 947         DPAA_PMD_DEBUG("if:%s sg_on = %d, max_frm =%d", dpaa_intf->name,
 948                 fman_if_get_sg_enable(fif),
 949                 dev->data->dev_conf.rxmode.max_rx_pkt_len);
 950         /* checking if push mode only, no error check for now */
 951         if (!rxq->is_static &&
 952             dpaa_push_mode_max_queue > dpaa_push_queue_idx) {
 953                 struct qman_portal *qp;
 954                 int q_fd;
 955
 956                 dpaa_push_queue_idx++;
 957                 opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
 958                 opts.fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK |
 959                                    QM_FQCTRL_CTXASTASHING |
 960                                    QM_FQCTRL_PREFERINCACHE;
 961                 opts.fqd.context_a.stashing.exclusive = 0;
 962                 /* In muticore scenario stashing becomes a bottleneck on LS1046.
 963                  * So do not enable stashing in this case
 964                  */
 965                 if (dpaa_svr_family != SVR_LS1046A_FAMILY)
 966                         opts.fqd.context_a.stashing.annotation_cl =
 967                                                 DPAA_IF_RX_ANNOTATION_STASH;
 968                 opts.fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
 969                 opts.fqd.context_a.stashing.context_cl =
 970                                                 DPAA_IF_RX_CONTEXT_STASH;
 971
 972                 /*Create a channel and associate given queue with the channel*/
 973                 qman_alloc_pool_range((u32 *)&rxq->ch_id, 1, 1, 0);
 974                 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
 975                 opts.fqd.dest.channel = rxq->ch_id;
 976                 opts.fqd.dest.wq = DPAA_IF_RX_PRIORITY;
 977                 flags = QMAN_INITFQ_FLAG_SCHED;
 978
 979                 /* Configure tail drop */
 980                 if (dpaa_intf->cgr_rx) {
 981                         opts.we_mask |= QM_INITFQ_WE_CGID;
 982                         opts.fqd.cgid = dpaa_intf->cgr_rx[queue_idx].cgrid;
 983                         opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
 984                 }
 985                 ret = qman_init_fq(rxq, flags, &opts);
 986                 if (ret) {
 987                         DPAA_PMD_ERR("Channel/Q association failed. fqid 0x%x "
 988                                 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
 989                         return ret;
 990                 }
 991                 if (dpaa_svr_family == SVR_LS1043A_FAMILY) {
 992                         rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb_no_prefetch;
 993                 } else {
 994                         rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb;
 995                         rxq->cb.dqrr_prepare = dpaa_rx_cb_prepare;
 996                 }
 997
 998                 rxq->is_static = true;
 999
1000                 /* Allocate qman specific portals */
1001                 qp = fsl_qman_fq_portal_create(&q_fd);
1002                 if (!qp) {
1003                         DPAA_PMD_ERR("Unable to alloc fq portal");
1004                         return -1;
1005                 }
1006                 rxq->qp = qp;
1007
1008                 /* Set up the device interrupt handler */
1009                 if (!dev->intr_handle) {
1010                         struct rte_dpaa_device *dpaa_dev;
1011                         struct rte_device *rdev = dev->device;
1012
1013                         dpaa_dev = container_of(rdev, struct rte_dpaa_device,
1014                                                 device);
1015                         dev->intr_handle = &dpaa_dev->intr_handle;
1016                         dev->intr_handle->intr_vec = rte_zmalloc(NULL,
1017                                         dpaa_push_mode_max_queue, 0);
1018                         if (!dev->intr_handle->intr_vec) {
1019                                 DPAA_PMD_ERR("intr_vec alloc failed");
1020                                 return -ENOMEM;
1021                         }
1022                         dev->intr_handle->nb_efd = dpaa_push_mode_max_queue;
1023                         dev->intr_handle->max_intr = dpaa_push_mode_max_queue;
1024                 }
1025
1026                 dev->intr_handle->type = RTE_INTR_HANDLE_EXT;
1027                 dev->intr_handle->intr_vec[queue_idx] = queue_idx + 1;
1028                 dev->intr_handle->efds[queue_idx] = q_fd;
1029                 rxq->q_fd = q_fd;
1030         }
1031         rxq->bp_array = rte_dpaa_bpid_info;
1032         dev->data->rx_queues[queue_idx] = rxq;
1033
1034         /* configure the CGR size as per the desc size */
1035         if (dpaa_intf->cgr_rx) {
1036                 struct qm_mcc_initcgr cgr_opts = {0};
1037
1038                 rxq->nb_desc = nb_desc;
1039                 /* Enable tail drop with cgr on this queue */
1040                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, nb_desc, 0);
1041                 ret = qman_modify_cgr(dpaa_intf->cgr_rx, 0, &cgr_opts);
1042                 if (ret) {
1043                         DPAA_PMD_WARN(
1044                                 "rx taildrop modify fail on fqid %d (ret=%d)",
1045                                 rxq->fqid, ret);
1046                 }
1047         }
1048         /* Enable main queue to receive error packets also by default */
1049         fman_if_set_err_fqid(fif, rxq->fqid);
1050         return 0;
1051 }
1052
1053 int
1054 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev,
1055                 int eth_rx_queue_id,
1056                 u16 ch_id,
1057                 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
1058 {
1059         int ret;
1060         u32 flags = 0;
1061         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1062         struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
1063         struct qm_mcc_initfq opts = {0};
1064
1065         if (dpaa_push_mode_max_queue)
1066                 DPAA_PMD_WARN("PUSH mode q and EVENTDEV are not compatible\n"
1067                               "PUSH mode already enabled for first %d queues.\n"
1068                               "To disable set DPAA_PUSH_QUEUES_NUMBER to 0\n",
1069                               dpaa_push_mode_max_queue);
1070
1071         dpaa_poll_queue_default_config(&opts);
1072
1073         switch (queue_conf->ev.sched_type) {
1074         case RTE_SCHED_TYPE_ATOMIC:
1075                 opts.fqd.fq_ctrl |= QM_FQCTRL_HOLDACTIVE;
1076                 /* Reset FQCTRL_AVOIDBLOCK bit as it is unnecessary
1077                  * configuration with HOLD_ACTIVE setting
1078                  */
1079                 opts.fqd.fq_ctrl &= (~QM_FQCTRL_AVOIDBLOCK);
1080                 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_atomic;
1081                 break;
1082         case RTE_SCHED_TYPE_ORDERED:
1083                 DPAA_PMD_ERR("Ordered queue schedule type is not supported\n");
1084                 return -1;
1085         default:
1086                 opts.fqd.fq_ctrl |= QM_FQCTRL_AVOIDBLOCK;
1087                 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_parallel;
1088                 break;
1089         }
1090
1091         opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
1092         opts.fqd.dest.channel = ch_id;
1093         opts.fqd.dest.wq = queue_conf->ev.priority;
1094
1095         if (dpaa_intf->cgr_rx) {
1096                 opts.we_mask |= QM_INITFQ_WE_CGID;
1097                 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
1098                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1099         }
1100
1101         flags = QMAN_INITFQ_FLAG_SCHED;
1102
1103         ret = qman_init_fq(rxq, flags, &opts);
1104         if (ret) {
1105                 DPAA_PMD_ERR("Ev-Channel/Q association failed. fqid 0x%x "
1106                                 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
1107                 return ret;
1108         }
1109
1110         /* copy configuration which needs to be filled during dequeue */
1111         memcpy(&rxq->ev, &queue_conf->ev, sizeof(struct rte_event));
1112         dev->data->rx_queues[eth_rx_queue_id] = rxq;
1113
1114         return ret;
1115 }
1116
1117 int
1118 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev,
1119                 int eth_rx_queue_id)
1120 {
1121         struct qm_mcc_initfq opts;
1122         int ret;
1123         u32 flags = 0;
1124         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1125         struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
1126
1127         dpaa_poll_queue_default_config(&opts);
1128
1129         if (dpaa_intf->cgr_rx) {
1130                 opts.we_mask |= QM_INITFQ_WE_CGID;
1131                 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
1132                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1133         }
1134
1135         ret = qman_init_fq(rxq, flags, &opts);
1136         if (ret) {
1137                 DPAA_PMD_ERR("init rx fqid %d failed with ret: %d",
1138                              rxq->fqid, ret);
1139         }
1140
1141         rxq->cb.dqrr_dpdk_cb = NULL;
1142         dev->data->rx_queues[eth_rx_queue_id] = NULL;
1143
1144         return 0;
1145 }
1146
1147 static
1148 void dpaa_eth_rx_queue_release(void *rxq __rte_unused)
1149 {
1150         PMD_INIT_FUNC_TRACE();
1151 }
1152
1153 static
1154 int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1155                             uint16_t nb_desc __rte_unused,
1156                 unsigned int socket_id __rte_unused,
1157                 const struct rte_eth_txconf *tx_conf)
1158 {
1159         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1160         struct qman_fq *txq = &dpaa_intf->tx_queues[queue_idx];
1161
1162         PMD_INIT_FUNC_TRACE();
1163
1164         /* Tx deferred start is not supported */
1165         if (tx_conf->tx_deferred_start) {
1166                 DPAA_PMD_ERR("%p:Tx deferred start not supported", (void *)dev);
1167                 return -EINVAL;
1168         }
1169         txq->nb_desc = UINT16_MAX;
1170         txq->offloads = tx_conf->offloads;
1171
1172         if (queue_idx >= dev->data->nb_tx_queues) {
1173                 rte_errno = EOVERFLOW;
1174                 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
1175                       (void *)dev, queue_idx, dev->data->nb_tx_queues);
1176                 return -rte_errno;
1177         }
1178
1179         DPAA_PMD_INFO("Tx queue setup for queue index: %d fq_id (0x%x)",
1180                         queue_idx, txq->fqid);
1181         dev->data->tx_queues[queue_idx] = txq;
1182
1183         return 0;
1184 }
1185
1186 static void dpaa_eth_tx_queue_release(void *txq __rte_unused)
1187 {
1188         PMD_INIT_FUNC_TRACE();
1189 }
1190
1191 static uint32_t
1192 dpaa_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1193 {
1194         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1195         struct qman_fq *rxq = &dpaa_intf->rx_queues[rx_queue_id];
1196         u32 frm_cnt = 0;
1197
1198         PMD_INIT_FUNC_TRACE();
1199
1200         if (qman_query_fq_frm_cnt(rxq, &frm_cnt) == 0) {
1201                 DPAA_PMD_DEBUG("RX frame count for q(%d) is %u",
1202                                rx_queue_id, frm_cnt);
1203         }
1204         return frm_cnt;
1205 }
1206
1207 static int dpaa_link_down(struct rte_eth_dev *dev)
1208 {
1209         struct fman_if *fif = dev->process_private;
1210         struct __fman_if *__fif;
1211
1212         PMD_INIT_FUNC_TRACE();
1213
1214         __fif = container_of(fif, struct __fman_if, __if);
1215
1216         if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC)
1217                 dpaa_update_link_status(__fif->node_name, ETH_LINK_DOWN);
1218         else
1219                 dpaa_eth_dev_stop(dev);
1220         return 0;
1221 }
1222
1223 static int dpaa_link_up(struct rte_eth_dev *dev)
1224 {
1225         struct fman_if *fif = dev->process_private;
1226         struct __fman_if *__fif;
1227
1228         PMD_INIT_FUNC_TRACE();
1229
1230         __fif = container_of(fif, struct __fman_if, __if);
1231
1232         if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC)
1233                 dpaa_update_link_status(__fif->node_name, ETH_LINK_UP);
1234         else
1235                 dpaa_eth_dev_start(dev);
1236         return 0;
1237 }
1238
1239 static int
1240 dpaa_flow_ctrl_set(struct rte_eth_dev *dev,
1241                    struct rte_eth_fc_conf *fc_conf)
1242 {
1243         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1244         struct rte_eth_fc_conf *net_fc;
1245
1246         PMD_INIT_FUNC_TRACE();
1247
1248         if (!(dpaa_intf->fc_conf)) {
1249                 dpaa_intf->fc_conf = rte_zmalloc(NULL,
1250                         sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
1251                 if (!dpaa_intf->fc_conf) {
1252                         DPAA_PMD_ERR("unable to save flow control info");
1253                         return -ENOMEM;
1254                 }
1255         }
1256         net_fc = dpaa_intf->fc_conf;
1257
1258         if (fc_conf->high_water < fc_conf->low_water) {
1259                 DPAA_PMD_ERR("Incorrect Flow Control Configuration");
1260                 return -EINVAL;
1261         }
1262
1263         if (fc_conf->mode == RTE_FC_NONE) {
1264                 return 0;
1265         } else if (fc_conf->mode == RTE_FC_TX_PAUSE ||
1266                  fc_conf->mode == RTE_FC_FULL) {
1267                 fman_if_set_fc_threshold(dev->process_private,
1268                                          fc_conf->high_water,
1269                                          fc_conf->low_water,
1270                                          dpaa_intf->bp_info->bpid);
1271                 if (fc_conf->pause_time)
1272                         fman_if_set_fc_quanta(dev->process_private,
1273                                               fc_conf->pause_time);
1274         }
1275
1276         /* Save the information in dpaa device */
1277         net_fc->pause_time = fc_conf->pause_time;
1278         net_fc->high_water = fc_conf->high_water;
1279         net_fc->low_water = fc_conf->low_water;
1280         net_fc->send_xon = fc_conf->send_xon;
1281         net_fc->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
1282         net_fc->mode = fc_conf->mode;
1283         net_fc->autoneg = fc_conf->autoneg;
1284
1285         return 0;
1286 }
1287
1288 static int
1289 dpaa_flow_ctrl_get(struct rte_eth_dev *dev,
1290                    struct rte_eth_fc_conf *fc_conf)
1291 {
1292         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1293         struct rte_eth_fc_conf *net_fc = dpaa_intf->fc_conf;
1294         int ret;
1295
1296         PMD_INIT_FUNC_TRACE();
1297
1298         if (net_fc) {
1299                 fc_conf->pause_time = net_fc->pause_time;
1300                 fc_conf->high_water = net_fc->high_water;
1301                 fc_conf->low_water = net_fc->low_water;
1302                 fc_conf->send_xon = net_fc->send_xon;
1303                 fc_conf->mac_ctrl_frame_fwd = net_fc->mac_ctrl_frame_fwd;
1304                 fc_conf->mode = net_fc->mode;
1305                 fc_conf->autoneg = net_fc->autoneg;
1306                 return 0;
1307         }
1308         ret = fman_if_get_fc_threshold(dev->process_private);
1309         if (ret) {
1310                 fc_conf->mode = RTE_FC_TX_PAUSE;
1311                 fc_conf->pause_time =
1312                         fman_if_get_fc_quanta(dev->process_private);
1313         } else {
1314                 fc_conf->mode = RTE_FC_NONE;
1315         }
1316
1317         return 0;
1318 }
1319
1320 static int
1321 dpaa_dev_add_mac_addr(struct rte_eth_dev *dev,
1322                              struct rte_ether_addr *addr,
1323                              uint32_t index,
1324                              __rte_unused uint32_t pool)
1325 {
1326         int ret;
1327
1328         PMD_INIT_FUNC_TRACE();
1329
1330         ret = fman_if_add_mac_addr(dev->process_private,
1331                                    addr->addr_bytes, index);
1332
1333         if (ret)
1334                 DPAA_PMD_ERR("Adding the MAC ADDR failed: err = %d", ret);
1335         return 0;
1336 }
1337
1338 static void
1339 dpaa_dev_remove_mac_addr(struct rte_eth_dev *dev,
1340                           uint32_t index)
1341 {
1342         PMD_INIT_FUNC_TRACE();
1343
1344         fman_if_clear_mac_addr(dev->process_private, index);
1345 }
1346
1347 static int
1348 dpaa_dev_set_mac_addr(struct rte_eth_dev *dev,
1349                        struct rte_ether_addr *addr)
1350 {
1351         int ret;
1352
1353         PMD_INIT_FUNC_TRACE();
1354
1355         ret = fman_if_add_mac_addr(dev->process_private, addr->addr_bytes, 0);
1356         if (ret)
1357                 DPAA_PMD_ERR("Setting the MAC ADDR failed %d", ret);
1358
1359         return ret;
1360 }
1361
1362 static int
1363 dpaa_dev_rss_hash_update(struct rte_eth_dev *dev,
1364                          struct rte_eth_rss_conf *rss_conf)
1365 {
1366         struct rte_eth_dev_data *data = dev->data;
1367         struct rte_eth_conf *eth_conf = &data->dev_conf;
1368
1369         PMD_INIT_FUNC_TRACE();
1370
1371         if (!(default_q || fmc_q)) {
1372                 if (dpaa_fm_config(dev, rss_conf->rss_hf)) {
1373                         DPAA_PMD_ERR("FM port configuration: Failed\n");
1374                         return -1;
1375                 }
1376                 eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf;
1377         } else {
1378                 DPAA_PMD_ERR("Function not supported\n");
1379                 return -ENOTSUP;
1380         }
1381         return 0;
1382 }
1383
1384 static int
1385 dpaa_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
1386                            struct rte_eth_rss_conf *rss_conf)
1387 {
1388         struct rte_eth_dev_data *data = dev->data;
1389         struct rte_eth_conf *eth_conf = &data->dev_conf;
1390
1391         /* dpaa does not support rss_key, so length should be 0*/
1392         rss_conf->rss_key_len = 0;
1393         rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf;
1394         return 0;
1395 }
1396
1397 static int dpaa_dev_queue_intr_enable(struct rte_eth_dev *dev,
1398                                       uint16_t queue_id)
1399 {
1400         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1401         struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id];
1402
1403         if (!rxq->is_static)
1404                 return -EINVAL;
1405
1406         return qman_fq_portal_irqsource_add(rxq->qp, QM_PIRQ_DQRI);
1407 }
1408
1409 static int dpaa_dev_queue_intr_disable(struct rte_eth_dev *dev,
1410                                        uint16_t queue_id)
1411 {
1412         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1413         struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id];
1414         uint32_t temp;
1415         ssize_t temp1;
1416
1417         if (!rxq->is_static)
1418                 return -EINVAL;
1419
1420         qman_fq_portal_irqsource_remove(rxq->qp, ~0);
1421
1422         temp1 = read(rxq->q_fd, &temp, sizeof(temp));
1423         if (temp1 != sizeof(temp))
1424                 DPAA_PMD_ERR("irq read error");
1425
1426         qman_fq_portal_thread_irq(rxq->qp);
1427
1428         return 0;
1429 }
1430
1431 static void
1432 dpaa_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1433         struct rte_eth_rxq_info *qinfo)
1434 {
1435         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1436         struct qman_fq *rxq;
1437
1438         rxq = dev->data->rx_queues[queue_id];
1439
1440         qinfo->mp = dpaa_intf->bp_info->mp;
1441         qinfo->scattered_rx = dev->data->scattered_rx;
1442         qinfo->nb_desc = rxq->nb_desc;
1443         qinfo->conf.rx_free_thresh = 1;
1444         qinfo->conf.rx_drop_en = 1;
1445         qinfo->conf.rx_deferred_start = 0;
1446         qinfo->conf.offloads = rxq->offloads;
1447 }
1448
1449 static void
1450 dpaa_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1451         struct rte_eth_txq_info *qinfo)
1452 {
1453         struct qman_fq *txq;
1454
1455         txq = dev->data->tx_queues[queue_id];
1456
1457         qinfo->nb_desc = txq->nb_desc;
1458         qinfo->conf.tx_thresh.pthresh = 0;
1459         qinfo->conf.tx_thresh.hthresh = 0;
1460         qinfo->conf.tx_thresh.wthresh = 0;
1461
1462         qinfo->conf.tx_free_thresh = 0;
1463         qinfo->conf.tx_rs_thresh = 0;
1464         qinfo->conf.offloads = txq->offloads;
1465         qinfo->conf.tx_deferred_start = 0;
1466 }
1467
1468 static struct eth_dev_ops dpaa_devops = {
1469         .dev_configure            = dpaa_eth_dev_configure,
1470         .dev_start                = dpaa_eth_dev_start,
1471         .dev_stop                 = dpaa_eth_dev_stop,
1472         .dev_close                = dpaa_eth_dev_close,
1473         .dev_infos_get            = dpaa_eth_dev_info,
1474         .dev_supported_ptypes_get = dpaa_supported_ptypes_get,
1475
1476         .rx_queue_setup           = dpaa_eth_rx_queue_setup,
1477         .tx_queue_setup           = dpaa_eth_tx_queue_setup,
1478         .rx_queue_release         = dpaa_eth_rx_queue_release,
1479         .tx_queue_release         = dpaa_eth_tx_queue_release,
1480         .rx_burst_mode_get        = dpaa_dev_rx_burst_mode_get,
1481         .tx_burst_mode_get        = dpaa_dev_tx_burst_mode_get,
1482         .rxq_info_get             = dpaa_rxq_info_get,
1483         .txq_info_get             = dpaa_txq_info_get,
1484
1485         .flow_ctrl_get            = dpaa_flow_ctrl_get,
1486         .flow_ctrl_set            = dpaa_flow_ctrl_set,
1487
1488         .link_update              = dpaa_eth_link_update,
1489         .stats_get                = dpaa_eth_stats_get,
1490         .xstats_get               = dpaa_dev_xstats_get,
1491         .xstats_get_by_id         = dpaa_xstats_get_by_id,
1492         .xstats_get_names_by_id   = dpaa_xstats_get_names_by_id,
1493         .xstats_get_names         = dpaa_xstats_get_names,
1494         .xstats_reset             = dpaa_eth_stats_reset,
1495         .stats_reset              = dpaa_eth_stats_reset,
1496         .promiscuous_enable       = dpaa_eth_promiscuous_enable,
1497         .promiscuous_disable      = dpaa_eth_promiscuous_disable,
1498         .allmulticast_enable      = dpaa_eth_multicast_enable,
1499         .allmulticast_disable     = dpaa_eth_multicast_disable,
1500         .mtu_set                  = dpaa_mtu_set,
1501         .dev_set_link_down        = dpaa_link_down,
1502         .dev_set_link_up          = dpaa_link_up,
1503         .mac_addr_add             = dpaa_dev_add_mac_addr,
1504         .mac_addr_remove          = dpaa_dev_remove_mac_addr,
1505         .mac_addr_set             = dpaa_dev_set_mac_addr,
1506
1507         .fw_version_get           = dpaa_fw_version_get,
1508
1509         .rx_queue_intr_enable     = dpaa_dev_queue_intr_enable,
1510         .rx_queue_intr_disable    = dpaa_dev_queue_intr_disable,
1511         .rss_hash_update          = dpaa_dev_rss_hash_update,
1512         .rss_hash_conf_get        = dpaa_dev_rss_hash_conf_get,
1513 };
1514
1515 static bool
1516 is_device_supported(struct rte_eth_dev *dev, struct rte_dpaa_driver *drv)
1517 {
1518         if (strcmp(dev->device->driver->name,
1519                    drv->driver.name))
1520                 return false;
1521
1522         return true;
1523 }
1524
1525 static bool
1526 is_dpaa_supported(struct rte_eth_dev *dev)
1527 {
1528         return is_device_supported(dev, &rte_dpaa_pmd);
1529 }
1530
1531 int
1532 rte_pmd_dpaa_set_tx_loopback(uint16_t port, uint8_t on)
1533 {
1534         struct rte_eth_dev *dev;
1535
1536         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
1537
1538         dev = &rte_eth_devices[port];
1539
1540         if (!is_dpaa_supported(dev))
1541                 return -ENOTSUP;
1542
1543         if (on)
1544                 fman_if_loopback_enable(dev->process_private);
1545         else
1546                 fman_if_loopback_disable(dev->process_private);
1547
1548         return 0;
1549 }
1550
1551 static int dpaa_fc_set_default(struct dpaa_if *dpaa_intf,
1552                                struct fman_if *fman_intf)
1553 {
1554         struct rte_eth_fc_conf *fc_conf;
1555         int ret;
1556
1557         PMD_INIT_FUNC_TRACE();
1558
1559         if (!(dpaa_intf->fc_conf)) {
1560                 dpaa_intf->fc_conf = rte_zmalloc(NULL,
1561                         sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
1562                 if (!dpaa_intf->fc_conf) {
1563                         DPAA_PMD_ERR("unable to save flow control info");
1564                         return -ENOMEM;
1565                 }
1566         }
1567         fc_conf = dpaa_intf->fc_conf;
1568         ret = fman_if_get_fc_threshold(fman_intf);
1569         if (ret) {
1570                 fc_conf->mode = RTE_FC_TX_PAUSE;
1571                 fc_conf->pause_time = fman_if_get_fc_quanta(fman_intf);
1572         } else {
1573                 fc_conf->mode = RTE_FC_NONE;
1574         }
1575
1576         return 0;
1577 }
1578
1579 /* Initialise an Rx FQ */
1580 static int dpaa_rx_queue_init(struct qman_fq *fq, struct qman_cgr *cgr_rx,
1581                               uint32_t fqid)
1582 {
1583         struct qm_mcc_initfq opts = {0};
1584         int ret;
1585         u32 flags = QMAN_FQ_FLAG_NO_ENQUEUE;
1586         struct qm_mcc_initcgr cgr_opts = {
1587                 .we_mask = QM_CGR_WE_CS_THRES |
1588                                 QM_CGR_WE_CSTD_EN |
1589                                 QM_CGR_WE_MODE,
1590                 .cgr = {
1591                         .cstd_en = QM_CGR_EN,
1592                         .mode = QMAN_CGR_MODE_FRAME
1593                 }
1594         };
1595
1596         if (fmc_q || default_q) {
1597                 ret = qman_reserve_fqid(fqid);
1598                 if (ret) {
1599                         DPAA_PMD_ERR("reserve rx fqid 0x%x failed, ret: %d",
1600                                      fqid, ret);
1601                         return -EINVAL;
1602                 }
1603         }
1604
1605         DPAA_PMD_DEBUG("creating rx fq %p, fqid 0x%x", fq, fqid);
1606         ret = qman_create_fq(fqid, flags, fq);
1607         if (ret) {
1608                 DPAA_PMD_ERR("create rx fqid 0x%x failed with ret: %d",
1609                         fqid, ret);
1610                 return ret;
1611         }
1612         fq->is_static = false;
1613
1614         dpaa_poll_queue_default_config(&opts);
1615
1616         if (cgr_rx) {
1617                 /* Enable tail drop with cgr on this queue */
1618                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, td_threshold, 0);
1619                 cgr_rx->cb = NULL;
1620                 ret = qman_create_cgr(cgr_rx, QMAN_CGR_FLAG_USE_INIT,
1621                                       &cgr_opts);
1622                 if (ret) {
1623                         DPAA_PMD_WARN(
1624                                 "rx taildrop init fail on rx fqid 0x%x(ret=%d)",
1625                                 fq->fqid, ret);
1626                         goto without_cgr;
1627                 }
1628                 opts.we_mask |= QM_INITFQ_WE_CGID;
1629                 opts.fqd.cgid = cgr_rx->cgrid;
1630                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1631         }
1632 without_cgr:
1633         ret = qman_init_fq(fq, 0, &opts);
1634         if (ret)
1635                 DPAA_PMD_ERR("init rx fqid 0x%x failed with ret:%d", fqid, ret);
1636         return ret;
1637 }
1638
1639 /* Initialise a Tx FQ */
1640 static int dpaa_tx_queue_init(struct qman_fq *fq,
1641                               struct fman_if *fman_intf,
1642                               struct qman_cgr *cgr_tx)
1643 {
1644         struct qm_mcc_initfq opts = {0};
1645         struct qm_mcc_initcgr cgr_opts = {
1646                 .we_mask = QM_CGR_WE_CS_THRES |
1647                                 QM_CGR_WE_CSTD_EN |
1648                                 QM_CGR_WE_MODE,
1649                 .cgr = {
1650                         .cstd_en = QM_CGR_EN,
1651                         .mode = QMAN_CGR_MODE_FRAME
1652                 }
1653         };
1654         int ret;
1655
1656         ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID |
1657                              QMAN_FQ_FLAG_TO_DCPORTAL, fq);
1658         if (ret) {
1659                 DPAA_PMD_ERR("create tx fq failed with ret: %d", ret);
1660                 return ret;
1661         }
1662         opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL |
1663                        QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA;
1664         opts.fqd.dest.channel = fman_intf->tx_channel_id;
1665         opts.fqd.dest.wq = DPAA_IF_TX_PRIORITY;
1666         opts.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE;
1667         opts.fqd.context_b = 0;
1668         /* no tx-confirmation */
1669         opts.fqd.context_a.hi = 0x80000000 | fman_dealloc_bufs_mask_hi;
1670         opts.fqd.context_a.lo = 0 | fman_dealloc_bufs_mask_lo;
1671         DPAA_PMD_DEBUG("init tx fq %p, fqid 0x%x", fq, fq->fqid);
1672
1673         if (cgr_tx) {
1674                 /* Enable tail drop with cgr on this queue */
1675                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres,
1676                                       td_tx_threshold, 0);
1677                 cgr_tx->cb = NULL;
1678                 ret = qman_create_cgr(cgr_tx, QMAN_CGR_FLAG_USE_INIT,
1679                                       &cgr_opts);
1680                 if (ret) {
1681                         DPAA_PMD_WARN(
1682                                 "rx taildrop init fail on rx fqid 0x%x(ret=%d)",
1683                                 fq->fqid, ret);
1684                         goto without_cgr;
1685                 }
1686                 opts.we_mask |= QM_INITFQ_WE_CGID;
1687                 opts.fqd.cgid = cgr_tx->cgrid;
1688                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1689                 DPAA_PMD_DEBUG("Tx FQ tail drop enabled, threshold = %d\n",
1690                                 td_tx_threshold);
1691         }
1692 without_cgr:
1693         ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts);
1694         if (ret)
1695                 DPAA_PMD_ERR("init tx fqid 0x%x failed %d", fq->fqid, ret);
1696         return ret;
1697 }
1698
1699 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1700 /* Initialise a DEBUG FQ ([rt]x_error, rx_default). */
1701 static int dpaa_debug_queue_init(struct qman_fq *fq, uint32_t fqid)
1702 {
1703         struct qm_mcc_initfq opts = {0};
1704         int ret;
1705
1706         PMD_INIT_FUNC_TRACE();
1707
1708         ret = qman_reserve_fqid(fqid);
1709         if (ret) {
1710                 DPAA_PMD_ERR("Reserve debug fqid %d failed with ret: %d",
1711                         fqid, ret);
1712                 return -EINVAL;
1713         }
1714         /* "map" this Rx FQ to one of the interfaces Tx FQID */
1715         DPAA_PMD_DEBUG("Creating debug fq %p, fqid %d", fq, fqid);
1716         ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq);
1717         if (ret) {
1718                 DPAA_PMD_ERR("create debug fqid %d failed with ret: %d",
1719                         fqid, ret);
1720                 return ret;
1721         }
1722         opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL;
1723         opts.fqd.dest.wq = DPAA_IF_DEBUG_PRIORITY;
1724         ret = qman_init_fq(fq, 0, &opts);
1725         if (ret)
1726                 DPAA_PMD_ERR("init debug fqid %d failed with ret: %d",
1727                             fqid, ret);
1728         return ret;
1729 }
1730 #endif
1731
1732 /* Initialise a network interface */
1733 static int
1734 dpaa_dev_init_secondary(struct rte_eth_dev *eth_dev)
1735 {
1736         struct rte_dpaa_device *dpaa_device;
1737         struct fm_eth_port_cfg *cfg;
1738         struct dpaa_if *dpaa_intf;
1739         struct fman_if *fman_intf;
1740         int dev_id;
1741
1742         PMD_INIT_FUNC_TRACE();
1743
1744         dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1745         dev_id = dpaa_device->id.dev_id;
1746         cfg = dpaa_get_eth_port_cfg(dev_id);
1747         fman_intf = cfg->fman_if;
1748         eth_dev->process_private = fman_intf;
1749
1750         /* Plugging of UCODE burst API not supported in Secondary */
1751         dpaa_intf = eth_dev->data->dev_private;
1752         eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
1753         if (dpaa_intf->cgr_tx)
1754                 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx_slow;
1755         else
1756                 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx;
1757 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP
1758         qman_set_fq_lookup_table(
1759                 dpaa_intf->rx_queues->qman_fq_lookup_table);
1760 #endif
1761
1762         return 0;
1763 }
1764
1765 /* Initialise a network interface */
1766 static int
1767 dpaa_dev_init(struct rte_eth_dev *eth_dev)
1768 {
1769         int num_rx_fqs, fqid;
1770         int loop, ret = 0;
1771         int dev_id;
1772         struct rte_dpaa_device *dpaa_device;
1773         struct dpaa_if *dpaa_intf;
1774         struct fm_eth_port_cfg *cfg;
1775         struct fman_if *fman_intf;
1776         struct fman_if_bpool *bp, *tmp_bp;
1777         uint32_t cgrid[DPAA_MAX_NUM_PCD_QUEUES];
1778         uint32_t cgrid_tx[MAX_DPAA_CORES];
1779         uint32_t dev_rx_fqids[DPAA_MAX_NUM_PCD_QUEUES];
1780         int8_t dev_vspids[DPAA_MAX_NUM_PCD_QUEUES];
1781         int8_t vsp_id = -1;
1782
1783         PMD_INIT_FUNC_TRACE();
1784
1785         dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1786         dev_id = dpaa_device->id.dev_id;
1787         dpaa_intf = eth_dev->data->dev_private;
1788         cfg = dpaa_get_eth_port_cfg(dev_id);
1789         fman_intf = cfg->fman_if;
1790
1791         dpaa_intf->name = dpaa_device->name;
1792
1793         /* save fman_if & cfg in the interface struture */
1794         eth_dev->process_private = fman_intf;
1795         dpaa_intf->ifid = dev_id;
1796         dpaa_intf->cfg = cfg;
1797
1798         memset((char *)dev_rx_fqids, 0,
1799                 sizeof(uint32_t) * DPAA_MAX_NUM_PCD_QUEUES);
1800
1801         memset(dev_vspids, -1, DPAA_MAX_NUM_PCD_QUEUES);
1802
1803         /* Initialize Rx FQ's */
1804         if (default_q) {
1805                 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES;
1806         } else if (fmc_q) {
1807                 num_rx_fqs = dpaa_port_fmc_init(fman_intf, dev_rx_fqids,
1808                                                 dev_vspids,
1809                                                 DPAA_MAX_NUM_PCD_QUEUES);
1810                 if (num_rx_fqs < 0) {
1811                         DPAA_PMD_ERR("%s FMC initializes failed!",
1812                                 dpaa_intf->name);
1813                         goto free_rx;
1814                 }
1815                 if (!num_rx_fqs) {
1816                         DPAA_PMD_WARN("%s is not configured by FMC.",
1817                                 dpaa_intf->name);
1818                 }
1819         } else {
1820                 /* FMCLESS mode, load balance to multiple cores.*/
1821                 num_rx_fqs = rte_lcore_count();
1822         }
1823
1824         /* Each device can not have more than DPAA_MAX_NUM_PCD_QUEUES RX
1825          * queues.
1826          */
1827         if (num_rx_fqs < 0 || num_rx_fqs > DPAA_MAX_NUM_PCD_QUEUES) {
1828                 DPAA_PMD_ERR("Invalid number of RX queues\n");
1829                 return -EINVAL;
1830         }
1831
1832         if (num_rx_fqs > 0) {
1833                 dpaa_intf->rx_queues = rte_zmalloc(NULL,
1834                         sizeof(struct qman_fq) * num_rx_fqs, MAX_CACHELINE);
1835                 if (!dpaa_intf->rx_queues) {
1836                         DPAA_PMD_ERR("Failed to alloc mem for RX queues\n");
1837                         return -ENOMEM;
1838                 }
1839         } else {
1840                 dpaa_intf->rx_queues = NULL;
1841         }
1842
1843         memset(cgrid, 0, sizeof(cgrid));
1844         memset(cgrid_tx, 0, sizeof(cgrid_tx));
1845
1846         /* if DPAA_TX_TAILDROP_THRESHOLD is set, use that value; if 0, it means
1847          * Tx tail drop is disabled.
1848          */
1849         if (getenv("DPAA_TX_TAILDROP_THRESHOLD")) {
1850                 td_tx_threshold = atoi(getenv("DPAA_TX_TAILDROP_THRESHOLD"));
1851                 DPAA_PMD_DEBUG("Tail drop threshold env configured: %u",
1852                                td_tx_threshold);
1853                 /* if a very large value is being configured */
1854                 if (td_tx_threshold > UINT16_MAX)
1855                         td_tx_threshold = CGR_RX_PERFQ_THRESH;
1856         }
1857
1858         /* If congestion control is enabled globally*/
1859         if (num_rx_fqs > 0 && td_threshold) {
1860                 dpaa_intf->cgr_rx = rte_zmalloc(NULL,
1861                         sizeof(struct qman_cgr) * num_rx_fqs, MAX_CACHELINE);
1862                 if (!dpaa_intf->cgr_rx) {
1863                         DPAA_PMD_ERR("Failed to alloc mem for cgr_rx\n");
1864                         ret = -ENOMEM;
1865                         goto free_rx;
1866                 }
1867
1868                 ret = qman_alloc_cgrid_range(&cgrid[0], num_rx_fqs, 1, 0);
1869                 if (ret != num_rx_fqs) {
1870                         DPAA_PMD_WARN("insufficient CGRIDs available");
1871                         ret = -EINVAL;
1872                         goto free_rx;
1873                 }
1874         } else {
1875                 dpaa_intf->cgr_rx = NULL;
1876         }
1877
1878         if (!fmc_q && !default_q) {
1879                 ret = qman_alloc_fqid_range(dev_rx_fqids, num_rx_fqs,
1880                                             num_rx_fqs, 0);
1881                 if (ret < 0) {
1882                         DPAA_PMD_ERR("Failed to alloc rx fqid's\n");
1883                         goto free_rx;
1884                 }
1885         }
1886
1887         for (loop = 0; loop < num_rx_fqs; loop++) {
1888                 if (default_q)
1889                         fqid = cfg->rx_def;
1890                 else
1891                         fqid = dev_rx_fqids[loop];
1892
1893                 vsp_id = dev_vspids[loop];
1894
1895                 if (dpaa_intf->cgr_rx)
1896                         dpaa_intf->cgr_rx[loop].cgrid = cgrid[loop];
1897
1898                 ret = dpaa_rx_queue_init(&dpaa_intf->rx_queues[loop],
1899                         dpaa_intf->cgr_rx ? &dpaa_intf->cgr_rx[loop] : NULL,
1900                         fqid);
1901                 if (ret)
1902                         goto free_rx;
1903                 dpaa_intf->rx_queues[loop].vsp_id = vsp_id;
1904                 dpaa_intf->rx_queues[loop].dpaa_intf = dpaa_intf;
1905         }
1906         dpaa_intf->nb_rx_queues = num_rx_fqs;
1907
1908         /* Initialise Tx FQs.free_rx Have as many Tx FQ's as number of cores */
1909         dpaa_intf->tx_queues = rte_zmalloc(NULL, sizeof(struct qman_fq) *
1910                 MAX_DPAA_CORES, MAX_CACHELINE);
1911         if (!dpaa_intf->tx_queues) {
1912                 DPAA_PMD_ERR("Failed to alloc mem for TX queues\n");
1913                 ret = -ENOMEM;
1914                 goto free_rx;
1915         }
1916
1917         /* If congestion control is enabled globally*/
1918         if (td_tx_threshold) {
1919                 dpaa_intf->cgr_tx = rte_zmalloc(NULL,
1920                         sizeof(struct qman_cgr) * MAX_DPAA_CORES,
1921                         MAX_CACHELINE);
1922                 if (!dpaa_intf->cgr_tx) {
1923                         DPAA_PMD_ERR("Failed to alloc mem for cgr_tx\n");
1924                         ret = -ENOMEM;
1925                         goto free_rx;
1926                 }
1927
1928                 ret = qman_alloc_cgrid_range(&cgrid_tx[0], MAX_DPAA_CORES,
1929                                              1, 0);
1930                 if (ret != MAX_DPAA_CORES) {
1931                         DPAA_PMD_WARN("insufficient CGRIDs available");
1932                         ret = -EINVAL;
1933                         goto free_rx;
1934                 }
1935         } else {
1936                 dpaa_intf->cgr_tx = NULL;
1937         }
1938
1939
1940         for (loop = 0; loop < MAX_DPAA_CORES; loop++) {
1941                 if (dpaa_intf->cgr_tx)
1942                         dpaa_intf->cgr_tx[loop].cgrid = cgrid_tx[loop];
1943
1944                 ret = dpaa_tx_queue_init(&dpaa_intf->tx_queues[loop],
1945                         fman_intf,
1946                         dpaa_intf->cgr_tx ? &dpaa_intf->cgr_tx[loop] : NULL);
1947                 if (ret)
1948                         goto free_tx;
1949                 dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf;
1950         }
1951         dpaa_intf->nb_tx_queues = MAX_DPAA_CORES;
1952
1953 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1954         ret = dpaa_debug_queue_init(&dpaa_intf->debug_queues
1955                         [DPAA_DEBUG_FQ_RX_ERROR], fman_intf->fqid_rx_err);
1956         if (ret) {
1957                 DPAA_PMD_ERR("DPAA RX ERROR queue init failed!");
1958                 goto free_tx;
1959         }
1960         dpaa_intf->debug_queues[DPAA_DEBUG_FQ_RX_ERROR].dpaa_intf = dpaa_intf;
1961         ret = dpaa_debug_queue_init(&dpaa_intf->debug_queues
1962                         [DPAA_DEBUG_FQ_TX_ERROR], fman_intf->fqid_tx_err);
1963         if (ret) {
1964                 DPAA_PMD_ERR("DPAA TX ERROR queue init failed!");
1965                 goto free_tx;
1966         }
1967         dpaa_intf->debug_queues[DPAA_DEBUG_FQ_TX_ERROR].dpaa_intf = dpaa_intf;
1968 #endif
1969
1970         DPAA_PMD_DEBUG("All frame queues created");
1971
1972         /* Get the initial configuration for flow control */
1973         dpaa_fc_set_default(dpaa_intf, fman_intf);
1974
1975         /* reset bpool list, initialize bpool dynamically */
1976         list_for_each_entry_safe(bp, tmp_bp, &cfg->fman_if->bpool_list, node) {
1977                 list_del(&bp->node);
1978                 rte_free(bp);
1979         }
1980
1981         /* Populate ethdev structure */
1982         eth_dev->dev_ops = &dpaa_devops;
1983         eth_dev->rx_queue_count = dpaa_dev_rx_queue_count;
1984         eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
1985         eth_dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
1986
1987         /* Allocate memory for storing MAC addresses */
1988         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr",
1989                 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER, 0);
1990         if (eth_dev->data->mac_addrs == NULL) {
1991                 DPAA_PMD_ERR("Failed to allocate %d bytes needed to "
1992                                                 "store MAC addresses",
1993                                 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER);
1994                 ret = -ENOMEM;
1995                 goto free_tx;
1996         }
1997
1998         /* copy the primary mac address */
1999         rte_ether_addr_copy(&fman_intf->mac_addr, &eth_dev->data->mac_addrs[0]);
2000
2001         RTE_LOG(INFO, PMD, "net: dpaa: %s: %02x:%02x:%02x:%02x:%02x:%02x\n",
2002                 dpaa_device->name,
2003                 fman_intf->mac_addr.addr_bytes[0],
2004                 fman_intf->mac_addr.addr_bytes[1],
2005                 fman_intf->mac_addr.addr_bytes[2],
2006                 fman_intf->mac_addr.addr_bytes[3],
2007                 fman_intf->mac_addr.addr_bytes[4],
2008                 fman_intf->mac_addr.addr_bytes[5]);
2009
2010         if (!fman_intf->is_shared_mac) {
2011                 /* Configure error packet handling */
2012                 fman_if_receive_rx_errors(fman_intf,
2013                         FM_FD_RX_STATUS_ERR_MASK);
2014                 /* Disable RX mode */
2015                 fman_if_disable_rx(fman_intf);
2016                 /* Disable promiscuous mode */
2017                 fman_if_promiscuous_disable(fman_intf);
2018                 /* Disable multicast */
2019                 fman_if_reset_mcast_filter_table(fman_intf);
2020                 /* Reset interface statistics */
2021                 fman_if_stats_reset(fman_intf);
2022                 /* Disable SG by default */
2023                 fman_if_set_sg(fman_intf, 0);
2024                 fman_if_set_maxfrm(fman_intf,
2025                                    RTE_ETHER_MAX_LEN + VLAN_TAG_SIZE);
2026         }
2027
2028         return 0;
2029
2030 free_tx:
2031         rte_free(dpaa_intf->tx_queues);
2032         dpaa_intf->tx_queues = NULL;
2033         dpaa_intf->nb_tx_queues = 0;
2034
2035 free_rx:
2036         rte_free(dpaa_intf->cgr_rx);
2037         rte_free(dpaa_intf->cgr_tx);
2038         rte_free(dpaa_intf->rx_queues);
2039         dpaa_intf->rx_queues = NULL;
2040         dpaa_intf->nb_rx_queues = 0;
2041         return ret;
2042 }
2043
2044 static int
2045 rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv,
2046                struct rte_dpaa_device *dpaa_dev)
2047 {
2048         int diag;
2049         int ret;
2050         struct rte_eth_dev *eth_dev;
2051
2052         PMD_INIT_FUNC_TRACE();
2053
2054         if ((DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE) >
2055                 RTE_PKTMBUF_HEADROOM) {
2056                 DPAA_PMD_ERR(
2057                 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA Annotation req(%d)",
2058                 RTE_PKTMBUF_HEADROOM,
2059                 DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE);
2060
2061                 return -1;
2062         }
2063
2064         /* In case of secondary process, the device is already configured
2065          * and no further action is required, except portal initialization
2066          * and verifying secondary attachment to port name.
2067          */
2068         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2069                 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name);
2070                 if (!eth_dev)
2071                         return -ENOMEM;
2072                 eth_dev->device = &dpaa_dev->device;
2073                 eth_dev->dev_ops = &dpaa_devops;
2074
2075                 ret = dpaa_dev_init_secondary(eth_dev);
2076                 if (ret != 0) {
2077                         RTE_LOG(ERR, PMD, "secondary dev init failed\n");
2078                         return ret;
2079                 }
2080
2081                 rte_eth_dev_probing_finish(eth_dev);
2082                 return 0;
2083         }
2084
2085         if (!is_global_init && (rte_eal_process_type() == RTE_PROC_PRIMARY)) {
2086                 if (access("/tmp/fmc.bin", F_OK) == -1) {
2087                         DPAA_PMD_INFO("* FMC not configured.Enabling default mode");
2088                         default_q = 1;
2089                 }
2090
2091                 if (!(default_q || fmc_q)) {
2092                         if (dpaa_fm_init()) {
2093                                 DPAA_PMD_ERR("FM init failed\n");
2094                                 return -1;
2095                         }
2096                 }
2097
2098                 /* disabling the default push mode for LS1043 */
2099                 if (dpaa_svr_family == SVR_LS1043A_FAMILY)
2100                         dpaa_push_mode_max_queue = 0;
2101
2102                 /* if push mode queues to be enabled. Currenly we are allowing
2103                  * only one queue per thread.
2104                  */
2105                 if (getenv("DPAA_PUSH_QUEUES_NUMBER")) {
2106                         dpaa_push_mode_max_queue =
2107                                         atoi(getenv("DPAA_PUSH_QUEUES_NUMBER"));
2108                         if (dpaa_push_mode_max_queue > DPAA_MAX_PUSH_MODE_QUEUE)
2109                             dpaa_push_mode_max_queue = DPAA_MAX_PUSH_MODE_QUEUE;
2110                 }
2111
2112                 is_global_init = 1;
2113         }
2114
2115         if (unlikely(!DPAA_PER_LCORE_PORTAL)) {
2116                 ret = rte_dpaa_portal_init((void *)1);
2117                 if (ret) {
2118                         DPAA_PMD_ERR("Unable to initialize portal");
2119                         return ret;
2120                 }
2121         }
2122
2123         eth_dev = rte_eth_dev_allocate(dpaa_dev->name);
2124         if (!eth_dev)
2125                 return -ENOMEM;
2126
2127         eth_dev->data->dev_private =
2128                         rte_zmalloc("ethdev private structure",
2129                                         sizeof(struct dpaa_if),
2130                                         RTE_CACHE_LINE_SIZE);
2131         if (!eth_dev->data->dev_private) {
2132                 DPAA_PMD_ERR("Cannot allocate memzone for port data");
2133                 rte_eth_dev_release_port(eth_dev);
2134                 return -ENOMEM;
2135         }
2136
2137         eth_dev->device = &dpaa_dev->device;
2138         dpaa_dev->eth_dev = eth_dev;
2139
2140         qman_ern_register_cb(dpaa_free_mbuf);
2141
2142         if (dpaa_drv->drv_flags & RTE_DPAA_DRV_INTR_LSC)
2143                 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;
2144
2145         /* Invoke PMD device initialization function */
2146         diag = dpaa_dev_init(eth_dev);
2147         if (diag == 0) {
2148                 rte_eth_dev_probing_finish(eth_dev);
2149                 return 0;
2150         }
2151
2152         rte_eth_dev_release_port(eth_dev);
2153         return diag;
2154 }
2155
2156 static int
2157 rte_dpaa_remove(struct rte_dpaa_device *dpaa_dev)
2158 {
2159         struct rte_eth_dev *eth_dev;
2160         int ret;
2161
2162         PMD_INIT_FUNC_TRACE();
2163
2164         eth_dev = dpaa_dev->eth_dev;
2165         dpaa_eth_dev_close(eth_dev);
2166         ret = rte_eth_dev_release_port(eth_dev);
2167
2168         return ret;
2169 }
2170
2171 static void __attribute__((destructor(102))) dpaa_finish(void)
2172 {
2173         /* For secondary, primary will do all the cleanup */
2174         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2175                 return;
2176
2177         if (!(default_q || fmc_q)) {
2178                 unsigned int i;
2179
2180                 for (i = 0; i < RTE_MAX_ETHPORTS; i++) {
2181                         if (rte_eth_devices[i].dev_ops == &dpaa_devops) {
2182                                 struct rte_eth_dev *dev = &rte_eth_devices[i];
2183                                 struct dpaa_if *dpaa_intf =
2184                                         dev->data->dev_private;
2185                                 struct fman_if *fif =
2186                                         dev->process_private;
2187                                 if (dpaa_intf->port_handle)
2188                                         if (dpaa_fm_deconfig(dpaa_intf, fif))
2189                                                 DPAA_PMD_WARN("DPAA FM "
2190                                                         "deconfig failed\n");
2191                                 if (fif->num_profiles) {
2192                                         if (dpaa_port_vsp_cleanup(dpaa_intf,
2193                                                                   fif))
2194                                                 DPAA_PMD_WARN("DPAA FM vsp cleanup failed\n");
2195                                 }
2196                         }
2197                 }
2198                 if (is_global_init)
2199                         if (dpaa_fm_term())
2200                                 DPAA_PMD_WARN("DPAA FM term failed\n");
2201
2202                 is_global_init = 0;
2203
2204                 DPAA_PMD_INFO("DPAA fman cleaned up");
2205         }
2206 }
2207
2208 static struct rte_dpaa_driver rte_dpaa_pmd = {
2209         .drv_flags = RTE_DPAA_DRV_INTR_LSC,
2210         .drv_type = FSL_DPAA_ETH,
2211         .probe = rte_dpaa_probe,
2212         .remove = rte_dpaa_remove,
2213 };
2214
2215 RTE_PMD_REGISTER_DPAA(net_dpaa, rte_dpaa_pmd);
2216 RTE_LOG_REGISTER(dpaa_logtype_pmd, pmd.net.dpaa, NOTICE);