drivers/net/dpaa/dpaa_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  *   Copyright 2016 Freescale Semiconductor, Inc. All rights reserved.
   4  *   Copyright 2017-2020 NXP
   5  *
   6  */
   7 /* System headers */
   8 #include <stdio.h>
   9 #include <inttypes.h>
  10 #include <unistd.h>
  11 #include <limits.h>
  12 #include <sched.h>
  13 #include <signal.h>
  14 #include <pthread.h>
  15 #include <sys/types.h>
  16 #include <sys/syscall.h>
  17
  18 #include <rte_string_fns.h>
  19 #include <rte_byteorder.h>
  20 #include <rte_common.h>
  21 #include <rte_interrupts.h>
  22 #include <rte_log.h>
  23 #include <rte_debug.h>
  24 #include <rte_pci.h>
  25 #include <rte_atomic.h>
  26 #include <rte_branch_prediction.h>
  27 #include <rte_memory.h>
  28 #include <rte_tailq.h>
  29 #include <rte_eal.h>
  30 #include <rte_alarm.h>
  31 #include <rte_ether.h>
  32 #include <rte_ethdev_driver.h>
  33 #include <rte_malloc.h>
  34 #include <rte_ring.h>
  35
  36 #include <rte_dpaa_bus.h>
  37 #include <rte_dpaa_logs.h>
  38 #include <dpaa_mempool.h>
  39
  40 #include <dpaa_ethdev.h>
  41 #include <dpaa_rxtx.h>
  42 #include <dpaa_flow.h>
  43 #include <rte_pmd_dpaa.h>
  44
  45 #include <fsl_usd.h>
  46 #include <fsl_qman.h>
  47 #include <fsl_bman.h>
  48 #include <fsl_fman.h>
  49 #include <process.h>
  50
  51 /* Supported Rx offloads */
  52 static uint64_t dev_rx_offloads_sup =
  53                 DEV_RX_OFFLOAD_JUMBO_FRAME |
  54                 DEV_RX_OFFLOAD_SCATTER;
  55
  56 /* Rx offloads which cannot be disabled */
  57 static uint64_t dev_rx_offloads_nodis =
  58                 DEV_RX_OFFLOAD_IPV4_CKSUM |
  59                 DEV_RX_OFFLOAD_UDP_CKSUM |
  60                 DEV_RX_OFFLOAD_TCP_CKSUM |
  61                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
  62                 DEV_RX_OFFLOAD_RSS_HASH;
  63
  64 /* Supported Tx offloads */
  65 static uint64_t dev_tx_offloads_sup =
  66                 DEV_TX_OFFLOAD_MT_LOCKFREE |
  67                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
  68
  69 /* Tx offloads which cannot be disabled */
  70 static uint64_t dev_tx_offloads_nodis =
  71                 DEV_TX_OFFLOAD_IPV4_CKSUM |
  72                 DEV_TX_OFFLOAD_UDP_CKSUM |
  73                 DEV_TX_OFFLOAD_TCP_CKSUM |
  74                 DEV_TX_OFFLOAD_SCTP_CKSUM |
  75                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
  76                 DEV_TX_OFFLOAD_MULTI_SEGS;
  77
  78 /* Keep track of whether QMAN and BMAN have been globally initialized */
  79 static int is_global_init;
  80 static int fmc_q = 1;   /* Indicates the use of static fmc for distribution */
  81 static int default_q;   /* use default queue - FMC is not executed*/
  82 /* At present we only allow up to 4 push mode queues as default - as each of
  83  * this queue need dedicated portal and we are short of portals.
  84  */
  85 #define DPAA_MAX_PUSH_MODE_QUEUE       8
  86 #define DPAA_DEFAULT_PUSH_MODE_QUEUE   4
  87
  88 static int dpaa_push_mode_max_queue = DPAA_DEFAULT_PUSH_MODE_QUEUE;
  89 static int dpaa_push_queue_idx; /* Queue index which are in push mode*/
  90
  91
  92 /* Per RX FQ Taildrop in frame count */
  93 static unsigned int td_threshold = CGR_RX_PERFQ_THRESH;
  94
  95 /* Per TX FQ Taildrop in frame count, disabled by default */
  96 static unsigned int td_tx_threshold;
  97
  98 struct rte_dpaa_xstats_name_off {
  99         char name[RTE_ETH_XSTATS_NAME_SIZE];
 100         uint32_t offset;
 101 };
 102
 103 static const struct rte_dpaa_xstats_name_off dpaa_xstats_strings[] = {
 104         {"rx_align_err",
 105                 offsetof(struct dpaa_if_stats, raln)},
 106         {"rx_valid_pause",
 107                 offsetof(struct dpaa_if_stats, rxpf)},
 108         {"rx_fcs_err",
 109                 offsetof(struct dpaa_if_stats, rfcs)},
 110         {"rx_vlan_frame",
 111                 offsetof(struct dpaa_if_stats, rvlan)},
 112         {"rx_frame_err",
 113                 offsetof(struct dpaa_if_stats, rerr)},
 114         {"rx_drop_err",
 115                 offsetof(struct dpaa_if_stats, rdrp)},
 116         {"rx_undersized",
 117                 offsetof(struct dpaa_if_stats, rund)},
 118         {"rx_oversize_err",
 119                 offsetof(struct dpaa_if_stats, rovr)},
 120         {"rx_fragment_pkt",
 121                 offsetof(struct dpaa_if_stats, rfrg)},
 122         {"tx_valid_pause",
 123                 offsetof(struct dpaa_if_stats, txpf)},
 124         {"tx_fcs_err",
 125                 offsetof(struct dpaa_if_stats, terr)},
 126         {"tx_vlan_frame",
 127                 offsetof(struct dpaa_if_stats, tvlan)},
 128         {"rx_undersized",
 129                 offsetof(struct dpaa_if_stats, tund)},
 130 };
 131
 132 static struct rte_dpaa_driver rte_dpaa_pmd;
 133
 134 static int
 135 dpaa_eth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info);
 136
 137 static int dpaa_eth_link_update(struct rte_eth_dev *dev,
 138                                 int wait_to_complete __rte_unused);
 139
 140 static void dpaa_interrupt_handler(void *param);
 141
 142 static inline void
 143 dpaa_poll_queue_default_config(struct qm_mcc_initfq *opts)
 144 {
 145         memset(opts, 0, sizeof(struct qm_mcc_initfq));
 146         opts->we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
 147         opts->fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | QM_FQCTRL_CTXASTASHING |
 148                            QM_FQCTRL_PREFERINCACHE;
 149         opts->fqd.context_a.stashing.exclusive = 0;
 150         if (dpaa_svr_family != SVR_LS1046A_FAMILY)
 151                 opts->fqd.context_a.stashing.annotation_cl =
 152                                                 DPAA_IF_RX_ANNOTATION_STASH;
 153         opts->fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
 154         opts->fqd.context_a.stashing.context_cl = DPAA_IF_RX_CONTEXT_STASH;
 155 }
 156
 157 static int
 158 dpaa_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 159 {
 160         uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
 161                                 + VLAN_TAG_SIZE;
 162         uint32_t buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
 163
 164         PMD_INIT_FUNC_TRACE();
 165
 166         if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA_MAX_RX_PKT_LEN)
 167                 return -EINVAL;
 168         /*
 169          * Refuse mtu that requires the support of scattered packets
 170          * when this feature has not been enabled before.
 171          */
 172         if (dev->data->min_rx_buf_size &&
 173                 !dev->data->scattered_rx && frame_size > buffsz) {
 174                 DPAA_PMD_ERR("SG not enabled, will not fit in one buffer");
 175                 return -EINVAL;
 176         }
 177
 178         /* check <seg size> * <max_seg>  >= max_frame */
 179         if (dev->data->min_rx_buf_size && dev->data->scattered_rx &&
 180                 (frame_size > buffsz * DPAA_SGT_MAX_ENTRIES)) {
 181                 DPAA_PMD_ERR("Too big to fit for Max SG list %d",
 182                                 buffsz * DPAA_SGT_MAX_ENTRIES);
 183                 return -EINVAL;
 184         }
 185
 186         if (frame_size > RTE_ETHER_MAX_LEN)
 187                 dev->data->dev_conf.rxmode.offloads |=
 188                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 189         else
 190                 dev->data->dev_conf.rxmode.offloads &=
 191                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 192
 193         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 194
 195         fman_if_set_maxfrm(dev->process_private, frame_size);
 196
 197         return 0;
 198 }
 199
 200 static int
 201 dpaa_eth_dev_configure(struct rte_eth_dev *dev)
 202 {
 203         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 204         uint64_t rx_offloads = eth_conf->rxmode.offloads;
 205         uint64_t tx_offloads = eth_conf->txmode.offloads;
 206         struct rte_device *rdev = dev->device;
 207         struct rte_dpaa_device *dpaa_dev;
 208         struct fman_if *fif = dev->process_private;
 209         struct __fman_if *__fif;
 210         struct rte_intr_handle *intr_handle;
 211         int ret;
 212
 213         PMD_INIT_FUNC_TRACE();
 214
 215         dpaa_dev = container_of(rdev, struct rte_dpaa_device, device);
 216         intr_handle = &dpaa_dev->intr_handle;
 217         __fif = container_of(fif, struct __fman_if, __if);
 218
 219         /* Rx offloads which are enabled by default */
 220         if (dev_rx_offloads_nodis & ~rx_offloads) {
 221                 DPAA_PMD_INFO(
 222                 "Some of rx offloads enabled by default - requested 0x%" PRIx64
 223                 " fixed are 0x%" PRIx64,
 224                 rx_offloads, dev_rx_offloads_nodis);
 225         }
 226
 227         /* Tx offloads which are enabled by default */
 228         if (dev_tx_offloads_nodis & ~tx_offloads) {
 229                 DPAA_PMD_INFO(
 230                 "Some of tx offloads enabled by default - requested 0x%" PRIx64
 231                 " fixed are 0x%" PRIx64,
 232                 tx_offloads, dev_tx_offloads_nodis);
 233         }
 234
 235         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 236                 uint32_t max_len;
 237
 238                 DPAA_PMD_DEBUG("enabling jumbo");
 239
 240                 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <=
 241                     DPAA_MAX_RX_PKT_LEN)
 242                         max_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
 243                 else {
 244                         DPAA_PMD_INFO("enabling jumbo override conf max len=%d "
 245                                 "supported is %d",
 246                                 dev->data->dev_conf.rxmode.max_rx_pkt_len,
 247                                 DPAA_MAX_RX_PKT_LEN);
 248                         max_len = DPAA_MAX_RX_PKT_LEN;
 249                 }
 250
 251                 fman_if_set_maxfrm(dev->process_private, max_len);
 252                 dev->data->mtu = max_len
 253                         - RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE;
 254         }
 255
 256         if (rx_offloads & DEV_RX_OFFLOAD_SCATTER) {
 257                 DPAA_PMD_DEBUG("enabling scatter mode");
 258                 fman_if_set_sg(dev->process_private, 1);
 259                 dev->data->scattered_rx = 1;
 260         }
 261
 262         /* if the interrupts were configured on this devices*/
 263         if (intr_handle && intr_handle->fd) {
 264                 if (dev->data->dev_conf.intr_conf.lsc != 0)
 265                         rte_intr_callback_register(intr_handle,
 266                                            dpaa_interrupt_handler,
 267                                            (void *)dev);
 268
 269                 ret = dpaa_intr_enable(__fif->node_name, intr_handle->fd);
 270                 if (ret) {
 271                         if (dev->data->dev_conf.intr_conf.lsc != 0) {
 272                                 rte_intr_callback_unregister(intr_handle,
 273                                         dpaa_interrupt_handler,
 274                                         (void *)dev);
 275                                 if (ret == EINVAL)
 276                                         printf("Failed to enable interrupt: Not Supported\n");
 277                                 else
 278                                         printf("Failed to enable interrupt\n");
 279                         }
 280                         dev->data->dev_conf.intr_conf.lsc = 0;
 281                         dev->data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC;
 282                 }
 283         }
 284         return 0;
 285 }
 286
 287 static const uint32_t *
 288 dpaa_supported_ptypes_get(struct rte_eth_dev *dev)
 289 {
 290         static const uint32_t ptypes[] = {
 291                 RTE_PTYPE_L2_ETHER,
 292                 RTE_PTYPE_L2_ETHER_VLAN,
 293                 RTE_PTYPE_L2_ETHER_ARP,
 294                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
 295                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
 296                 RTE_PTYPE_L4_ICMP,
 297                 RTE_PTYPE_L4_TCP,
 298                 RTE_PTYPE_L4_UDP,
 299                 RTE_PTYPE_L4_FRAG,
 300                 RTE_PTYPE_L4_TCP,
 301                 RTE_PTYPE_L4_UDP,
 302                 RTE_PTYPE_L4_SCTP
 303         };
 304
 305         PMD_INIT_FUNC_TRACE();
 306
 307         if (dev->rx_pkt_burst == dpaa_eth_queue_rx)
 308                 return ptypes;
 309         return NULL;
 310 }
 311
 312 static void dpaa_interrupt_handler(void *param)
 313 {
 314         struct rte_eth_dev *dev = param;
 315         struct rte_device *rdev = dev->device;
 316         struct rte_dpaa_device *dpaa_dev;
 317         struct rte_intr_handle *intr_handle;
 318         uint64_t buf;
 319         int bytes_read;
 320
 321         dpaa_dev = container_of(rdev, struct rte_dpaa_device, device);
 322         intr_handle = &dpaa_dev->intr_handle;
 323
 324         bytes_read = read(intr_handle->fd, &buf, sizeof(uint64_t));
 325         if (bytes_read < 0)
 326                 DPAA_PMD_ERR("Error reading eventfd\n");
 327         dpaa_eth_link_update(dev, 0);
 328         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
 329 }
 330
 331 static int dpaa_eth_dev_start(struct rte_eth_dev *dev)
 332 {
 333         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 334
 335         PMD_INIT_FUNC_TRACE();
 336
 337         /* Change tx callback to the real one */
 338         if (dpaa_intf->cgr_tx)
 339                 dev->tx_pkt_burst = dpaa_eth_queue_tx_slow;
 340         else
 341                 dev->tx_pkt_burst = dpaa_eth_queue_tx;
 342
 343         fman_if_enable_rx(dev->process_private);
 344
 345         return 0;
 346 }
 347
 348 static void dpaa_eth_dev_stop(struct rte_eth_dev *dev)
 349 {
 350         struct fman_if *fif = dev->process_private;
 351
 352         PMD_INIT_FUNC_TRACE();
 353
 354         if (!fif->is_shared_mac)
 355                 fman_if_disable_rx(fif);
 356         dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
 357 }
 358
 359 static void dpaa_eth_dev_close(struct rte_eth_dev *dev)
 360 {
 361         struct fman_if *fif = dev->process_private;
 362         struct __fman_if *__fif;
 363         struct rte_device *rdev = dev->device;
 364         struct rte_dpaa_device *dpaa_dev;
 365         struct rte_intr_handle *intr_handle;
 366
 367         PMD_INIT_FUNC_TRACE();
 368
 369         dpaa_dev = container_of(rdev, struct rte_dpaa_device, device);
 370         intr_handle = &dpaa_dev->intr_handle;
 371         __fif = container_of(fif, struct __fman_if, __if);
 372
 373         dpaa_eth_dev_stop(dev);
 374
 375         if (intr_handle && intr_handle->fd &&
 376             dev->data->dev_conf.intr_conf.lsc != 0) {
 377                 dpaa_intr_disable(__fif->node_name);
 378                 rte_intr_callback_unregister(intr_handle,
 379                                              dpaa_interrupt_handler,
 380                                              (void *)dev);
 381         }
 382 }
 383
 384 static int
 385 dpaa_fw_version_get(struct rte_eth_dev *dev __rte_unused,
 386                      char *fw_version,
 387                      size_t fw_size)
 388 {
 389         int ret;
 390         FILE *svr_file = NULL;
 391         unsigned int svr_ver = 0;
 392
 393         PMD_INIT_FUNC_TRACE();
 394
 395         svr_file = fopen(DPAA_SOC_ID_FILE, "r");
 396         if (!svr_file) {
 397                 DPAA_PMD_ERR("Unable to open SoC device");
 398                 return -ENOTSUP; /* Not supported on this infra */
 399         }
 400         if (fscanf(svr_file, "svr:%x", &svr_ver) > 0)
 401                 dpaa_svr_family = svr_ver & SVR_MASK;
 402         else
 403                 DPAA_PMD_ERR("Unable to read SoC device");
 404
 405         fclose(svr_file);
 406
 407         ret = snprintf(fw_version, fw_size, "SVR:%x-fman-v%x",
 408                        svr_ver, fman_ip_rev);
 409         ret += 1; /* add the size of '\0' */
 410
 411         if (fw_size < (uint32_t)ret)
 412                 return ret;
 413         else
 414                 return 0;
 415 }
 416
 417 static int dpaa_eth_dev_info(struct rte_eth_dev *dev,
 418                              struct rte_eth_dev_info *dev_info)
 419 {
 420         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 421         struct fman_if *fif = dev->process_private;
 422
 423         DPAA_PMD_DEBUG(": %s", dpaa_intf->name);
 424
 425         dev_info->max_rx_queues = dpaa_intf->nb_rx_queues;
 426         dev_info->max_tx_queues = dpaa_intf->nb_tx_queues;
 427         dev_info->max_rx_pktlen = DPAA_MAX_RX_PKT_LEN;
 428         dev_info->max_mac_addrs = DPAA_MAX_MAC_FILTER;
 429         dev_info->max_hash_mac_addrs = 0;
 430         dev_info->max_vfs = 0;
 431         dev_info->max_vmdq_pools = ETH_16_POOLS;
 432         dev_info->flow_type_rss_offloads = DPAA_RSS_OFFLOAD_ALL;
 433
 434         if (fif->mac_type == fman_mac_1g) {
 435                 dev_info->speed_capa = ETH_LINK_SPEED_1G;
 436         } else if (fif->mac_type == fman_mac_2_5g) {
 437                 dev_info->speed_capa = ETH_LINK_SPEED_1G
 438                                         | ETH_LINK_SPEED_2_5G;
 439         } else if (fif->mac_type == fman_mac_10g) {
 440                 dev_info->speed_capa = ETH_LINK_SPEED_1G
 441                                         | ETH_LINK_SPEED_2_5G
 442                                         | ETH_LINK_SPEED_10G;
 443         } else {
 444                 DPAA_PMD_ERR("invalid link_speed: %s, %d",
 445                              dpaa_intf->name, fif->mac_type);
 446                 return -EINVAL;
 447         }
 448
 449         dev_info->rx_offload_capa = dev_rx_offloads_sup |
 450                                         dev_rx_offloads_nodis;
 451         dev_info->tx_offload_capa = dev_tx_offloads_sup |
 452                                         dev_tx_offloads_nodis;
 453         dev_info->default_rxportconf.burst_size = DPAA_DEF_RX_BURST_SIZE;
 454         dev_info->default_txportconf.burst_size = DPAA_DEF_TX_BURST_SIZE;
 455         dev_info->default_rxportconf.nb_queues = 1;
 456         dev_info->default_txportconf.nb_queues = 1;
 457         dev_info->default_txportconf.ring_size = CGR_TX_CGR_THRESH;
 458         dev_info->default_rxportconf.ring_size = CGR_RX_PERFQ_THRESH;
 459
 460         return 0;
 461 }
 462
 463 static int
 464 dpaa_dev_rx_burst_mode_get(struct rte_eth_dev *dev,
 465                         __rte_unused uint16_t queue_id,
 466                         struct rte_eth_burst_mode *mode)
 467 {
 468         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 469         int ret = -EINVAL;
 470         unsigned int i;
 471         const struct burst_info {
 472                 uint64_t flags;
 473                 const char *output;
 474         } rx_offload_map[] = {
 475                         {DEV_RX_OFFLOAD_JUMBO_FRAME, " Jumbo frame,"},
 476                         {DEV_RX_OFFLOAD_SCATTER, " Scattered,"},
 477                         {DEV_RX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"},
 478                         {DEV_RX_OFFLOAD_UDP_CKSUM, " UDP csum,"},
 479                         {DEV_RX_OFFLOAD_TCP_CKSUM, " TCP csum,"},
 480                         {DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
 481                         {DEV_RX_OFFLOAD_RSS_HASH, " RSS,"}
 482         };
 483
 484         /* Update Rx offload info */
 485         for (i = 0; i < RTE_DIM(rx_offload_map); i++) {
 486                 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) {
 487                         snprintf(mode->info, sizeof(mode->info), "%s",
 488                                 rx_offload_map[i].output);
 489                         ret = 0;
 490                         break;
 491                 }
 492         }
 493         return ret;
 494 }
 495
 496 static int
 497 dpaa_dev_tx_burst_mode_get(struct rte_eth_dev *dev,
 498                         __rte_unused uint16_t queue_id,
 499                         struct rte_eth_burst_mode *mode)
 500 {
 501         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 502         int ret = -EINVAL;
 503         unsigned int i;
 504         const struct burst_info {
 505                 uint64_t flags;
 506                 const char *output;
 507         } tx_offload_map[] = {
 508                         {DEV_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"},
 509                         {DEV_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"},
 510                         {DEV_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"},
 511                         {DEV_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"},
 512                         {DEV_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"},
 513                         {DEV_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
 514                         {DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
 515                         {DEV_TX_OFFLOAD_MULTI_SEGS, " Scattered,"}
 516         };
 517
 518         /* Update Tx offload info */
 519         for (i = 0; i < RTE_DIM(tx_offload_map); i++) {
 520                 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) {
 521                         snprintf(mode->info, sizeof(mode->info), "%s",
 522                                 tx_offload_map[i].output);
 523                         ret = 0;
 524                         break;
 525                 }
 526         }
 527         return ret;
 528 }
 529
 530 static int dpaa_eth_link_update(struct rte_eth_dev *dev,
 531                                 int wait_to_complete __rte_unused)
 532 {
 533         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 534         struct rte_eth_link *link = &dev->data->dev_link;
 535         struct fman_if *fif = dev->process_private;
 536         struct __fman_if *__fif = container_of(fif, struct __fman_if, __if);
 537         int ret;
 538
 539         PMD_INIT_FUNC_TRACE();
 540
 541         if (fif->mac_type == fman_mac_1g)
 542                 link->link_speed = ETH_SPEED_NUM_1G;
 543         else if (fif->mac_type == fman_mac_2_5g)
 544                 link->link_speed = ETH_SPEED_NUM_2_5G;
 545         else if (fif->mac_type == fman_mac_10g)
 546                 link->link_speed = ETH_SPEED_NUM_10G;
 547         else
 548                 DPAA_PMD_ERR("invalid link_speed: %s, %d",
 549                              dpaa_intf->name, fif->mac_type);
 550
 551         if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC) {
 552                 ret = dpaa_get_link_status(__fif->node_name);
 553                 if (ret < 0)
 554                         return ret;
 555                 link->link_status = ret;
 556         } else {
 557                 link->link_status = dpaa_intf->valid;
 558         }
 559
 560         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 561         link->link_autoneg = ETH_LINK_AUTONEG;
 562
 563         DPAA_PMD_INFO("Port %d Link is %s\n", dev->data->port_id,
 564                       link->link_status ? "Up" : "Down");
 565         return 0;
 566 }
 567
 568 static int dpaa_eth_stats_get(struct rte_eth_dev *dev,
 569                                struct rte_eth_stats *stats)
 570 {
 571         PMD_INIT_FUNC_TRACE();
 572
 573         fman_if_stats_get(dev->process_private, stats);
 574         return 0;
 575 }
 576
 577 static int dpaa_eth_stats_reset(struct rte_eth_dev *dev)
 578 {
 579         PMD_INIT_FUNC_TRACE();
 580
 581         fman_if_stats_reset(dev->process_private);
 582
 583         return 0;
 584 }
 585
 586 static int
 587 dpaa_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
 588                     unsigned int n)
 589 {
 590         unsigned int i = 0, num = RTE_DIM(dpaa_xstats_strings);
 591         uint64_t values[sizeof(struct dpaa_if_stats) / 8];
 592
 593         if (n < num)
 594                 return num;
 595
 596         if (xstats == NULL)
 597                 return 0;
 598
 599         fman_if_stats_get_all(dev->process_private, values,
 600                               sizeof(struct dpaa_if_stats) / 8);
 601
 602         for (i = 0; i < num; i++) {
 603                 xstats[i].id = i;
 604                 xstats[i].value = values[dpaa_xstats_strings[i].offset / 8];
 605         }
 606         return i;
 607 }
 608
 609 static int
 610 dpaa_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 611                       struct rte_eth_xstat_name *xstats_names,
 612                       unsigned int limit)
 613 {
 614         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 615
 616         if (limit < stat_cnt)
 617                 return stat_cnt;
 618
 619         if (xstats_names != NULL)
 620                 for (i = 0; i < stat_cnt; i++)
 621                         strlcpy(xstats_names[i].name,
 622                                 dpaa_xstats_strings[i].name,
 623                                 sizeof(xstats_names[i].name));
 624
 625         return stat_cnt;
 626 }
 627
 628 static int
 629 dpaa_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 630                       uint64_t *values, unsigned int n)
 631 {
 632         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 633         uint64_t values_copy[sizeof(struct dpaa_if_stats) / 8];
 634
 635         if (!ids) {
 636                 if (n < stat_cnt)
 637                         return stat_cnt;
 638
 639                 if (!values)
 640                         return 0;
 641
 642                 fman_if_stats_get_all(dev->process_private, values_copy,
 643                                       sizeof(struct dpaa_if_stats) / 8);
 644
 645                 for (i = 0; i < stat_cnt; i++)
 646                         values[i] =
 647                                 values_copy[dpaa_xstats_strings[i].offset / 8];
 648
 649                 return stat_cnt;
 650         }
 651
 652         dpaa_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
 653
 654         for (i = 0; i < n; i++) {
 655                 if (ids[i] >= stat_cnt) {
 656                         DPAA_PMD_ERR("id value isn't valid");
 657                         return -1;
 658                 }
 659                 values[i] = values_copy[ids[i]];
 660         }
 661         return n;
 662 }
 663
 664 static int
 665 dpaa_xstats_get_names_by_id(
 666         struct rte_eth_dev *dev,
 667         struct rte_eth_xstat_name *xstats_names,
 668         const uint64_t *ids,
 669         unsigned int limit)
 670 {
 671         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 672         struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
 673
 674         if (!ids)
 675                 return dpaa_xstats_get_names(dev, xstats_names, limit);
 676
 677         dpaa_xstats_get_names(dev, xstats_names_copy, limit);
 678
 679         for (i = 0; i < limit; i++) {
 680                 if (ids[i] >= stat_cnt) {
 681                         DPAA_PMD_ERR("id value isn't valid");
 682                         return -1;
 683                 }
 684                 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
 685         }
 686         return limit;
 687 }
 688
 689 static int dpaa_eth_promiscuous_enable(struct rte_eth_dev *dev)
 690 {
 691         PMD_INIT_FUNC_TRACE();
 692
 693         fman_if_promiscuous_enable(dev->process_private);
 694
 695         return 0;
 696 }
 697
 698 static int dpaa_eth_promiscuous_disable(struct rte_eth_dev *dev)
 699 {
 700         PMD_INIT_FUNC_TRACE();
 701
 702         fman_if_promiscuous_disable(dev->process_private);
 703
 704         return 0;
 705 }
 706
 707 static int dpaa_eth_multicast_enable(struct rte_eth_dev *dev)
 708 {
 709         PMD_INIT_FUNC_TRACE();
 710
 711         fman_if_set_mcast_filter_table(dev->process_private);
 712
 713         return 0;
 714 }
 715
 716 static int dpaa_eth_multicast_disable(struct rte_eth_dev *dev)
 717 {
 718         PMD_INIT_FUNC_TRACE();
 719
 720         fman_if_reset_mcast_filter_table(dev->process_private);
 721
 722         return 0;
 723 }
 724
 725 static void dpaa_fman_if_pool_setup(struct rte_eth_dev *dev)
 726 {
 727         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 728         struct fman_if_ic_params icp;
 729         uint32_t fd_offset;
 730         uint32_t bp_size;
 731
 732         memset(&icp, 0, sizeof(icp));
 733         /* set ICEOF for to the default value , which is 0*/
 734         icp.iciof = DEFAULT_ICIOF;
 735         icp.iceof = DEFAULT_RX_ICEOF;
 736         icp.icsz = DEFAULT_ICSZ;
 737         fman_if_set_ic_params(dev->process_private, &icp);
 738
 739         fd_offset = RTE_PKTMBUF_HEADROOM + DPAA_HW_BUF_RESERVE;
 740         fman_if_set_fdoff(dev->process_private, fd_offset);
 741
 742         /* Buffer pool size should be equal to Dataroom Size*/
 743         bp_size = rte_pktmbuf_data_room_size(dpaa_intf->bp_info->mp);
 744
 745         fman_if_set_bp(dev->process_private,
 746                        dpaa_intf->bp_info->mp->size,
 747                        dpaa_intf->bp_info->bpid, bp_size);
 748 }
 749
 750 static inline int dpaa_eth_rx_queue_bp_check(struct rte_eth_dev *dev,
 751                                              int8_t vsp_id, uint32_t bpid)
 752 {
 753         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 754         struct fman_if *fif = dev->process_private;
 755
 756         if (fif->num_profiles) {
 757                 if (vsp_id < 0)
 758                         vsp_id = fif->base_profile_id;
 759         } else {
 760                 if (vsp_id < 0)
 761                         vsp_id = 0;
 762         }
 763
 764         if (dpaa_intf->vsp_bpid[vsp_id] &&
 765                 bpid != dpaa_intf->vsp_bpid[vsp_id]) {
 766                 DPAA_PMD_ERR("Various MPs are assigned to RXQs with same VSP");
 767
 768                 return -1;
 769         }
 770
 771         return 0;
 772 }
 773
 774 static
 775 int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 776                             uint16_t nb_desc,
 777                             unsigned int socket_id __rte_unused,
 778                             const struct rte_eth_rxconf *rx_conf,
 779                             struct rte_mempool *mp)
 780 {
 781         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 782         struct fman_if *fif = dev->process_private;
 783         struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_idx];
 784         struct qm_mcc_initfq opts = {0};
 785         u32 flags = 0;
 786         int ret;
 787         u32 buffsz = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
 788
 789         PMD_INIT_FUNC_TRACE();
 790
 791         if (queue_idx >= dev->data->nb_rx_queues) {
 792                 rte_errno = EOVERFLOW;
 793                 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
 794                       (void *)dev, queue_idx, dev->data->nb_rx_queues);
 795                 return -rte_errno;
 796         }
 797
 798         /* Rx deferred start is not supported */
 799         if (rx_conf->rx_deferred_start) {
 800                 DPAA_PMD_ERR("%p:Rx deferred start not supported", (void *)dev);
 801                 return -EINVAL;
 802         }
 803         rxq->nb_desc = UINT16_MAX;
 804         rxq->offloads = rx_conf->offloads;
 805
 806         DPAA_PMD_INFO("Rx queue setup for queue index: %d fq_id (0x%x)",
 807                         queue_idx, rxq->fqid);
 808
 809         if (!fif->num_profiles) {
 810                 if (dpaa_intf->bp_info && dpaa_intf->bp_info->bp &&
 811                         dpaa_intf->bp_info->mp != mp) {
 812                         DPAA_PMD_WARN("Multiple pools on same interface not"
 813                                       " supported");
 814                         return -EINVAL;
 815                 }
 816         } else {
 817                 if (dpaa_eth_rx_queue_bp_check(dev, rxq->vsp_id,
 818                         DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid)) {
 819                         return -EINVAL;
 820                 }
 821         }
 822
 823         /* Max packet can fit in single buffer */
 824         if (dev->data->dev_conf.rxmode.max_rx_pkt_len <= buffsz) {
 825                 ;
 826         } else if (dev->data->dev_conf.rxmode.offloads &
 827                         DEV_RX_OFFLOAD_SCATTER) {
 828                 if (dev->data->dev_conf.rxmode.max_rx_pkt_len >
 829                         buffsz * DPAA_SGT_MAX_ENTRIES) {
 830                         DPAA_PMD_ERR("max RxPkt size %d too big to fit "
 831                                 "MaxSGlist %d",
 832                                 dev->data->dev_conf.rxmode.max_rx_pkt_len,
 833                                 buffsz * DPAA_SGT_MAX_ENTRIES);
 834                         rte_errno = EOVERFLOW;
 835                         return -rte_errno;
 836                 }
 837         } else {
 838                 DPAA_PMD_WARN("The requested maximum Rx packet size (%u) is"
 839                      " larger than a single mbuf (%u) and scattered"
 840                      " mode has not been requested",
 841                      dev->data->dev_conf.rxmode.max_rx_pkt_len,
 842                      buffsz - RTE_PKTMBUF_HEADROOM);
 843         }
 844
 845         dpaa_intf->bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp);
 846
 847         /* For shared interface, it's done in kernel, skip.*/
 848         if (!fif->is_shared_mac)
 849                 dpaa_fman_if_pool_setup(dev);
 850
 851         if (fif->num_profiles) {
 852                 int8_t vsp_id = rxq->vsp_id;
 853
 854                 if (vsp_id >= 0) {
 855                         ret = dpaa_port_vsp_update(dpaa_intf, fmc_q, vsp_id,
 856                                         DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid,
 857                                         fif);
 858                         if (ret) {
 859                                 DPAA_PMD_ERR("dpaa_port_vsp_update failed");
 860                                 return ret;
 861                         }
 862                 } else {
 863                         DPAA_PMD_INFO("Base profile is associated to"
 864                                 " RXQ fqid:%d\r\n", rxq->fqid);
 865                         if (fif->is_shared_mac) {
 866                                 DPAA_PMD_ERR("Fatal: Base profile is associated"
 867                                              " to shared interface on DPDK.");
 868                                 return -EINVAL;
 869                         }
 870                         dpaa_intf->vsp_bpid[fif->base_profile_id] =
 871                                 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid;
 872                 }
 873         } else {
 874                 dpaa_intf->vsp_bpid[0] =
 875                         DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid;
 876         }
 877
 878         dpaa_intf->valid = 1;
 879         DPAA_PMD_DEBUG("if:%s sg_on = %d, max_frm =%d", dpaa_intf->name,
 880                 fman_if_get_sg_enable(fif),
 881                 dev->data->dev_conf.rxmode.max_rx_pkt_len);
 882         /* checking if push mode only, no error check for now */
 883         if (!rxq->is_static &&
 884             dpaa_push_mode_max_queue > dpaa_push_queue_idx) {
 885                 struct qman_portal *qp;
 886                 int q_fd;
 887
 888                 dpaa_push_queue_idx++;
 889                 opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
 890                 opts.fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK |
 891                                    QM_FQCTRL_CTXASTASHING |
 892                                    QM_FQCTRL_PREFERINCACHE;
 893                 opts.fqd.context_a.stashing.exclusive = 0;
 894                 /* In muticore scenario stashing becomes a bottleneck on LS1046.
 895                  * So do not enable stashing in this case
 896                  */
 897                 if (dpaa_svr_family != SVR_LS1046A_FAMILY)
 898                         opts.fqd.context_a.stashing.annotation_cl =
 899                                                 DPAA_IF_RX_ANNOTATION_STASH;
 900                 opts.fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
 901                 opts.fqd.context_a.stashing.context_cl =
 902                                                 DPAA_IF_RX_CONTEXT_STASH;
 903
 904                 /*Create a channel and associate given queue with the channel*/
 905                 qman_alloc_pool_range((u32 *)&rxq->ch_id, 1, 1, 0);
 906                 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
 907                 opts.fqd.dest.channel = rxq->ch_id;
 908                 opts.fqd.dest.wq = DPAA_IF_RX_PRIORITY;
 909                 flags = QMAN_INITFQ_FLAG_SCHED;
 910
 911                 /* Configure tail drop */
 912                 if (dpaa_intf->cgr_rx) {
 913                         opts.we_mask |= QM_INITFQ_WE_CGID;
 914                         opts.fqd.cgid = dpaa_intf->cgr_rx[queue_idx].cgrid;
 915                         opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
 916                 }
 917                 ret = qman_init_fq(rxq, flags, &opts);
 918                 if (ret) {
 919                         DPAA_PMD_ERR("Channel/Q association failed. fqid 0x%x "
 920                                 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
 921                         return ret;
 922                 }
 923                 if (dpaa_svr_family == SVR_LS1043A_FAMILY) {
 924                         rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb_no_prefetch;
 925                 } else {
 926                         rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb;
 927                         rxq->cb.dqrr_prepare = dpaa_rx_cb_prepare;
 928                 }
 929
 930                 rxq->is_static = true;
 931
 932                 /* Allocate qman specific portals */
 933                 qp = fsl_qman_fq_portal_create(&q_fd);
 934                 if (!qp) {
 935                         DPAA_PMD_ERR("Unable to alloc fq portal");
 936                         return -1;
 937                 }
 938                 rxq->qp = qp;
 939
 940                 /* Set up the device interrupt handler */
 941                 if (!dev->intr_handle) {
 942                         struct rte_dpaa_device *dpaa_dev;
 943                         struct rte_device *rdev = dev->device;
 944
 945                         dpaa_dev = container_of(rdev, struct rte_dpaa_device,
 946                                                 device);
 947                         dev->intr_handle = &dpaa_dev->intr_handle;
 948                         dev->intr_handle->intr_vec = rte_zmalloc(NULL,
 949                                         dpaa_push_mode_max_queue, 0);
 950                         if (!dev->intr_handle->intr_vec) {
 951                                 DPAA_PMD_ERR("intr_vec alloc failed");
 952                                 return -ENOMEM;
 953                         }
 954                         dev->intr_handle->nb_efd = dpaa_push_mode_max_queue;
 955                         dev->intr_handle->max_intr = dpaa_push_mode_max_queue;
 956                 }
 957
 958                 dev->intr_handle->type = RTE_INTR_HANDLE_EXT;
 959                 dev->intr_handle->intr_vec[queue_idx] = queue_idx + 1;
 960                 dev->intr_handle->efds[queue_idx] = q_fd;
 961                 rxq->q_fd = q_fd;
 962         }
 963         rxq->bp_array = rte_dpaa_bpid_info;
 964         dev->data->rx_queues[queue_idx] = rxq;
 965
 966         /* configure the CGR size as per the desc size */
 967         if (dpaa_intf->cgr_rx) {
 968                 struct qm_mcc_initcgr cgr_opts = {0};
 969
 970                 rxq->nb_desc = nb_desc;
 971                 /* Enable tail drop with cgr on this queue */
 972                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, nb_desc, 0);
 973                 ret = qman_modify_cgr(dpaa_intf->cgr_rx, 0, &cgr_opts);
 974                 if (ret) {
 975                         DPAA_PMD_WARN(
 976                                 "rx taildrop modify fail on fqid %d (ret=%d)",
 977                                 rxq->fqid, ret);
 978                 }
 979         }
 980
 981         return 0;
 982 }
 983
 984 int
 985 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev,
 986                 int eth_rx_queue_id,
 987                 u16 ch_id,
 988                 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
 989 {
 990         int ret;
 991         u32 flags = 0;
 992         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 993         struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
 994         struct qm_mcc_initfq opts = {0};
 995
 996         if (dpaa_push_mode_max_queue)
 997                 DPAA_PMD_WARN("PUSH mode q and EVENTDEV are not compatible\n"
 998                               "PUSH mode already enabled for first %d queues.\n"
 999                               "To disable set DPAA_PUSH_QUEUES_NUMBER to 0\n",
1000                               dpaa_push_mode_max_queue);
1001
1002         dpaa_poll_queue_default_config(&opts);
1003
1004         switch (queue_conf->ev.sched_type) {
1005         case RTE_SCHED_TYPE_ATOMIC:
1006                 opts.fqd.fq_ctrl |= QM_FQCTRL_HOLDACTIVE;
1007                 /* Reset FQCTRL_AVOIDBLOCK bit as it is unnecessary
1008                  * configuration with HOLD_ACTIVE setting
1009                  */
1010                 opts.fqd.fq_ctrl &= (~QM_FQCTRL_AVOIDBLOCK);
1011                 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_atomic;
1012                 break;
1013         case RTE_SCHED_TYPE_ORDERED:
1014                 DPAA_PMD_ERR("Ordered queue schedule type is not supported\n");
1015                 return -1;
1016         default:
1017                 opts.fqd.fq_ctrl |= QM_FQCTRL_AVOIDBLOCK;
1018                 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_parallel;
1019                 break;
1020         }
1021
1022         opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
1023         opts.fqd.dest.channel = ch_id;
1024         opts.fqd.dest.wq = queue_conf->ev.priority;
1025
1026         if (dpaa_intf->cgr_rx) {
1027                 opts.we_mask |= QM_INITFQ_WE_CGID;
1028                 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
1029                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1030         }
1031
1032         flags = QMAN_INITFQ_FLAG_SCHED;
1033
1034         ret = qman_init_fq(rxq, flags, &opts);
1035         if (ret) {
1036                 DPAA_PMD_ERR("Ev-Channel/Q association failed. fqid 0x%x "
1037                                 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
1038                 return ret;
1039         }
1040
1041         /* copy configuration which needs to be filled during dequeue */
1042         memcpy(&rxq->ev, &queue_conf->ev, sizeof(struct rte_event));
1043         dev->data->rx_queues[eth_rx_queue_id] = rxq;
1044
1045         return ret;
1046 }
1047
1048 int
1049 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev,
1050                 int eth_rx_queue_id)
1051 {
1052         struct qm_mcc_initfq opts;
1053         int ret;
1054         u32 flags = 0;
1055         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1056         struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
1057
1058         dpaa_poll_queue_default_config(&opts);
1059
1060         if (dpaa_intf->cgr_rx) {
1061                 opts.we_mask |= QM_INITFQ_WE_CGID;
1062                 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
1063                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1064         }
1065
1066         ret = qman_init_fq(rxq, flags, &opts);
1067         if (ret) {
1068                 DPAA_PMD_ERR("init rx fqid %d failed with ret: %d",
1069                              rxq->fqid, ret);
1070         }
1071
1072         rxq->cb.dqrr_dpdk_cb = NULL;
1073         dev->data->rx_queues[eth_rx_queue_id] = NULL;
1074
1075         return 0;
1076 }
1077
1078 static
1079 void dpaa_eth_rx_queue_release(void *rxq __rte_unused)
1080 {
1081         PMD_INIT_FUNC_TRACE();
1082 }
1083
1084 static
1085 int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1086                             uint16_t nb_desc __rte_unused,
1087                 unsigned int socket_id __rte_unused,
1088                 const struct rte_eth_txconf *tx_conf)
1089 {
1090         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1091         struct qman_fq *txq = &dpaa_intf->tx_queues[queue_idx];
1092
1093         PMD_INIT_FUNC_TRACE();
1094
1095         /* Tx deferred start is not supported */
1096         if (tx_conf->tx_deferred_start) {
1097                 DPAA_PMD_ERR("%p:Tx deferred start not supported", (void *)dev);
1098                 return -EINVAL;
1099         }
1100         txq->nb_desc = UINT16_MAX;
1101         txq->offloads = tx_conf->offloads;
1102
1103         if (queue_idx >= dev->data->nb_tx_queues) {
1104                 rte_errno = EOVERFLOW;
1105                 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
1106                       (void *)dev, queue_idx, dev->data->nb_tx_queues);
1107                 return -rte_errno;
1108         }
1109
1110         DPAA_PMD_INFO("Tx queue setup for queue index: %d fq_id (0x%x)",
1111                         queue_idx, txq->fqid);
1112         dev->data->tx_queues[queue_idx] = txq;
1113
1114         return 0;
1115 }
1116
1117 static void dpaa_eth_tx_queue_release(void *txq __rte_unused)
1118 {
1119         PMD_INIT_FUNC_TRACE();
1120 }
1121
1122 static uint32_t
1123 dpaa_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1124 {
1125         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1126         struct qman_fq *rxq = &dpaa_intf->rx_queues[rx_queue_id];
1127         u32 frm_cnt = 0;
1128
1129         PMD_INIT_FUNC_TRACE();
1130
1131         if (qman_query_fq_frm_cnt(rxq, &frm_cnt) == 0) {
1132                 DPAA_PMD_DEBUG("RX frame count for q(%d) is %u",
1133                                rx_queue_id, frm_cnt);
1134         }
1135         return frm_cnt;
1136 }
1137
1138 static int dpaa_link_down(struct rte_eth_dev *dev)
1139 {
1140         struct fman_if *fif = dev->process_private;
1141         struct __fman_if *__fif;
1142
1143         PMD_INIT_FUNC_TRACE();
1144
1145         __fif = container_of(fif, struct __fman_if, __if);
1146
1147         if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC)
1148                 dpaa_update_link_status(__fif->node_name, ETH_LINK_DOWN);
1149         else
1150                 dpaa_eth_dev_stop(dev);
1151         return 0;
1152 }
1153
1154 static int dpaa_link_up(struct rte_eth_dev *dev)
1155 {
1156         struct fman_if *fif = dev->process_private;
1157         struct __fman_if *__fif;
1158
1159         PMD_INIT_FUNC_TRACE();
1160
1161         __fif = container_of(fif, struct __fman_if, __if);
1162
1163         if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC)
1164                 dpaa_update_link_status(__fif->node_name, ETH_LINK_UP);
1165         else
1166                 dpaa_eth_dev_start(dev);
1167         return 0;
1168 }
1169
1170 static int
1171 dpaa_flow_ctrl_set(struct rte_eth_dev *dev,
1172                    struct rte_eth_fc_conf *fc_conf)
1173 {
1174         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1175         struct rte_eth_fc_conf *net_fc;
1176
1177         PMD_INIT_FUNC_TRACE();
1178
1179         if (!(dpaa_intf->fc_conf)) {
1180                 dpaa_intf->fc_conf = rte_zmalloc(NULL,
1181                         sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
1182                 if (!dpaa_intf->fc_conf) {
1183                         DPAA_PMD_ERR("unable to save flow control info");
1184                         return -ENOMEM;
1185                 }
1186         }
1187         net_fc = dpaa_intf->fc_conf;
1188
1189         if (fc_conf->high_water < fc_conf->low_water) {
1190                 DPAA_PMD_ERR("Incorrect Flow Control Configuration");
1191                 return -EINVAL;
1192         }
1193
1194         if (fc_conf->mode == RTE_FC_NONE) {
1195                 return 0;
1196         } else if (fc_conf->mode == RTE_FC_TX_PAUSE ||
1197                  fc_conf->mode == RTE_FC_FULL) {
1198                 fman_if_set_fc_threshold(dev->process_private,
1199                                          fc_conf->high_water,
1200                                          fc_conf->low_water,
1201                                          dpaa_intf->bp_info->bpid);
1202                 if (fc_conf->pause_time)
1203                         fman_if_set_fc_quanta(dev->process_private,
1204                                               fc_conf->pause_time);
1205         }
1206
1207         /* Save the information in dpaa device */
1208         net_fc->pause_time = fc_conf->pause_time;
1209         net_fc->high_water = fc_conf->high_water;
1210         net_fc->low_water = fc_conf->low_water;
1211         net_fc->send_xon = fc_conf->send_xon;
1212         net_fc->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
1213         net_fc->mode = fc_conf->mode;
1214         net_fc->autoneg = fc_conf->autoneg;
1215
1216         return 0;
1217 }
1218
1219 static int
1220 dpaa_flow_ctrl_get(struct rte_eth_dev *dev,
1221                    struct rte_eth_fc_conf *fc_conf)
1222 {
1223         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1224         struct rte_eth_fc_conf *net_fc = dpaa_intf->fc_conf;
1225         int ret;
1226
1227         PMD_INIT_FUNC_TRACE();
1228
1229         if (net_fc) {
1230                 fc_conf->pause_time = net_fc->pause_time;
1231                 fc_conf->high_water = net_fc->high_water;
1232                 fc_conf->low_water = net_fc->low_water;
1233                 fc_conf->send_xon = net_fc->send_xon;
1234                 fc_conf->mac_ctrl_frame_fwd = net_fc->mac_ctrl_frame_fwd;
1235                 fc_conf->mode = net_fc->mode;
1236                 fc_conf->autoneg = net_fc->autoneg;
1237                 return 0;
1238         }
1239         ret = fman_if_get_fc_threshold(dev->process_private);
1240         if (ret) {
1241                 fc_conf->mode = RTE_FC_TX_PAUSE;
1242                 fc_conf->pause_time =
1243                         fman_if_get_fc_quanta(dev->process_private);
1244         } else {
1245                 fc_conf->mode = RTE_FC_NONE;
1246         }
1247
1248         return 0;
1249 }
1250
1251 static int
1252 dpaa_dev_add_mac_addr(struct rte_eth_dev *dev,
1253                              struct rte_ether_addr *addr,
1254                              uint32_t index,
1255                              __rte_unused uint32_t pool)
1256 {
1257         int ret;
1258
1259         PMD_INIT_FUNC_TRACE();
1260
1261         ret = fman_if_add_mac_addr(dev->process_private,
1262                                    addr->addr_bytes, index);
1263
1264         if (ret)
1265                 DPAA_PMD_ERR("Adding the MAC ADDR failed: err = %d", ret);
1266         return 0;
1267 }
1268
1269 static void
1270 dpaa_dev_remove_mac_addr(struct rte_eth_dev *dev,
1271                           uint32_t index)
1272 {
1273         PMD_INIT_FUNC_TRACE();
1274
1275         fman_if_clear_mac_addr(dev->process_private, index);
1276 }
1277
1278 static int
1279 dpaa_dev_set_mac_addr(struct rte_eth_dev *dev,
1280                        struct rte_ether_addr *addr)
1281 {
1282         int ret;
1283
1284         PMD_INIT_FUNC_TRACE();
1285
1286         ret = fman_if_add_mac_addr(dev->process_private, addr->addr_bytes, 0);
1287         if (ret)
1288                 DPAA_PMD_ERR("Setting the MAC ADDR failed %d", ret);
1289
1290         return ret;
1291 }
1292
1293 static int dpaa_dev_queue_intr_enable(struct rte_eth_dev *dev,
1294                                       uint16_t queue_id)
1295 {
1296         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1297         struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id];
1298
1299         if (!rxq->is_static)
1300                 return -EINVAL;
1301
1302         return qman_fq_portal_irqsource_add(rxq->qp, QM_PIRQ_DQRI);
1303 }
1304
1305 static int dpaa_dev_queue_intr_disable(struct rte_eth_dev *dev,
1306                                        uint16_t queue_id)
1307 {
1308         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1309         struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id];
1310         uint32_t temp;
1311         ssize_t temp1;
1312
1313         if (!rxq->is_static)
1314                 return -EINVAL;
1315
1316         qman_fq_portal_irqsource_remove(rxq->qp, ~0);
1317
1318         temp1 = read(rxq->q_fd, &temp, sizeof(temp));
1319         if (temp1 != sizeof(temp))
1320                 DPAA_PMD_ERR("irq read error");
1321
1322         qman_fq_portal_thread_irq(rxq->qp);
1323
1324         return 0;
1325 }
1326
1327 static void
1328 dpaa_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1329         struct rte_eth_rxq_info *qinfo)
1330 {
1331         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1332         struct qman_fq *rxq;
1333
1334         rxq = dev->data->rx_queues[queue_id];
1335
1336         qinfo->mp = dpaa_intf->bp_info->mp;
1337         qinfo->scattered_rx = dev->data->scattered_rx;
1338         qinfo->nb_desc = rxq->nb_desc;
1339         qinfo->conf.rx_free_thresh = 1;
1340         qinfo->conf.rx_drop_en = 1;
1341         qinfo->conf.rx_deferred_start = 0;
1342         qinfo->conf.offloads = rxq->offloads;
1343 }
1344
1345 static void
1346 dpaa_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1347         struct rte_eth_txq_info *qinfo)
1348 {
1349         struct qman_fq *txq;
1350
1351         txq = dev->data->tx_queues[queue_id];
1352
1353         qinfo->nb_desc = txq->nb_desc;
1354         qinfo->conf.tx_thresh.pthresh = 0;
1355         qinfo->conf.tx_thresh.hthresh = 0;
1356         qinfo->conf.tx_thresh.wthresh = 0;
1357
1358         qinfo->conf.tx_free_thresh = 0;
1359         qinfo->conf.tx_rs_thresh = 0;
1360         qinfo->conf.offloads = txq->offloads;
1361         qinfo->conf.tx_deferred_start = 0;
1362 }
1363
1364 static struct eth_dev_ops dpaa_devops = {
1365         .dev_configure            = dpaa_eth_dev_configure,
1366         .dev_start                = dpaa_eth_dev_start,
1367         .dev_stop                 = dpaa_eth_dev_stop,
1368         .dev_close                = dpaa_eth_dev_close,
1369         .dev_infos_get            = dpaa_eth_dev_info,
1370         .dev_supported_ptypes_get = dpaa_supported_ptypes_get,
1371
1372         .rx_queue_setup           = dpaa_eth_rx_queue_setup,
1373         .tx_queue_setup           = dpaa_eth_tx_queue_setup,
1374         .rx_queue_release         = dpaa_eth_rx_queue_release,
1375         .tx_queue_release         = dpaa_eth_tx_queue_release,
1376         .rx_queue_count           = dpaa_dev_rx_queue_count,
1377         .rx_burst_mode_get        = dpaa_dev_rx_burst_mode_get,
1378         .tx_burst_mode_get        = dpaa_dev_tx_burst_mode_get,
1379         .rxq_info_get             = dpaa_rxq_info_get,
1380         .txq_info_get             = dpaa_txq_info_get,
1381
1382         .flow_ctrl_get            = dpaa_flow_ctrl_get,
1383         .flow_ctrl_set            = dpaa_flow_ctrl_set,
1384
1385         .link_update              = dpaa_eth_link_update,
1386         .stats_get                = dpaa_eth_stats_get,
1387         .xstats_get               = dpaa_dev_xstats_get,
1388         .xstats_get_by_id         = dpaa_xstats_get_by_id,
1389         .xstats_get_names_by_id   = dpaa_xstats_get_names_by_id,
1390         .xstats_get_names         = dpaa_xstats_get_names,
1391         .xstats_reset             = dpaa_eth_stats_reset,
1392         .stats_reset              = dpaa_eth_stats_reset,
1393         .promiscuous_enable       = dpaa_eth_promiscuous_enable,
1394         .promiscuous_disable      = dpaa_eth_promiscuous_disable,
1395         .allmulticast_enable      = dpaa_eth_multicast_enable,
1396         .allmulticast_disable     = dpaa_eth_multicast_disable,
1397         .mtu_set                  = dpaa_mtu_set,
1398         .dev_set_link_down        = dpaa_link_down,
1399         .dev_set_link_up          = dpaa_link_up,
1400         .mac_addr_add             = dpaa_dev_add_mac_addr,
1401         .mac_addr_remove          = dpaa_dev_remove_mac_addr,
1402         .mac_addr_set             = dpaa_dev_set_mac_addr,
1403
1404         .fw_version_get           = dpaa_fw_version_get,
1405
1406         .rx_queue_intr_enable     = dpaa_dev_queue_intr_enable,
1407         .rx_queue_intr_disable    = dpaa_dev_queue_intr_disable,
1408 };
1409
1410 static bool
1411 is_device_supported(struct rte_eth_dev *dev, struct rte_dpaa_driver *drv)
1412 {
1413         if (strcmp(dev->device->driver->name,
1414                    drv->driver.name))
1415                 return false;
1416
1417         return true;
1418 }
1419
1420 static bool
1421 is_dpaa_supported(struct rte_eth_dev *dev)
1422 {
1423         return is_device_supported(dev, &rte_dpaa_pmd);
1424 }
1425
1426 int
1427 rte_pmd_dpaa_set_tx_loopback(uint8_t port, uint8_t on)
1428 {
1429         struct rte_eth_dev *dev;
1430
1431         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
1432
1433         dev = &rte_eth_devices[port];
1434
1435         if (!is_dpaa_supported(dev))
1436                 return -ENOTSUP;
1437
1438         if (on)
1439                 fman_if_loopback_enable(dev->process_private);
1440         else
1441                 fman_if_loopback_disable(dev->process_private);
1442
1443         return 0;
1444 }
1445
1446 static int dpaa_fc_set_default(struct dpaa_if *dpaa_intf,
1447                                struct fman_if *fman_intf)
1448 {
1449         struct rte_eth_fc_conf *fc_conf;
1450         int ret;
1451
1452         PMD_INIT_FUNC_TRACE();
1453
1454         if (!(dpaa_intf->fc_conf)) {
1455                 dpaa_intf->fc_conf = rte_zmalloc(NULL,
1456                         sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
1457                 if (!dpaa_intf->fc_conf) {
1458                         DPAA_PMD_ERR("unable to save flow control info");
1459                         return -ENOMEM;
1460                 }
1461         }
1462         fc_conf = dpaa_intf->fc_conf;
1463         ret = fman_if_get_fc_threshold(fman_intf);
1464         if (ret) {
1465                 fc_conf->mode = RTE_FC_TX_PAUSE;
1466                 fc_conf->pause_time = fman_if_get_fc_quanta(fman_intf);
1467         } else {
1468                 fc_conf->mode = RTE_FC_NONE;
1469         }
1470
1471         return 0;
1472 }
1473
1474 /* Initialise an Rx FQ */
1475 static int dpaa_rx_queue_init(struct qman_fq *fq, struct qman_cgr *cgr_rx,
1476                               uint32_t fqid)
1477 {
1478         struct qm_mcc_initfq opts = {0};
1479         int ret;
1480         u32 flags = QMAN_FQ_FLAG_NO_ENQUEUE;
1481         struct qm_mcc_initcgr cgr_opts = {
1482                 .we_mask = QM_CGR_WE_CS_THRES |
1483                                 QM_CGR_WE_CSTD_EN |
1484                                 QM_CGR_WE_MODE,
1485                 .cgr = {
1486                         .cstd_en = QM_CGR_EN,
1487                         .mode = QMAN_CGR_MODE_FRAME
1488                 }
1489         };
1490
1491         if (fmc_q || default_q) {
1492                 ret = qman_reserve_fqid(fqid);
1493                 if (ret) {
1494                         DPAA_PMD_ERR("reserve rx fqid 0x%x failed, ret: %d",
1495                                      fqid, ret);
1496                         return -EINVAL;
1497                 }
1498         }
1499
1500         DPAA_PMD_DEBUG("creating rx fq %p, fqid 0x%x", fq, fqid);
1501         ret = qman_create_fq(fqid, flags, fq);
1502         if (ret) {
1503                 DPAA_PMD_ERR("create rx fqid 0x%x failed with ret: %d",
1504                         fqid, ret);
1505                 return ret;
1506         }
1507         fq->is_static = false;
1508
1509         dpaa_poll_queue_default_config(&opts);
1510
1511         if (cgr_rx) {
1512                 /* Enable tail drop with cgr on this queue */
1513                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, td_threshold, 0);
1514                 cgr_rx->cb = NULL;
1515                 ret = qman_create_cgr(cgr_rx, QMAN_CGR_FLAG_USE_INIT,
1516                                       &cgr_opts);
1517                 if (ret) {
1518                         DPAA_PMD_WARN(
1519                                 "rx taildrop init fail on rx fqid 0x%x(ret=%d)",
1520                                 fq->fqid, ret);
1521                         goto without_cgr;
1522                 }
1523                 opts.we_mask |= QM_INITFQ_WE_CGID;
1524                 opts.fqd.cgid = cgr_rx->cgrid;
1525                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1526         }
1527 without_cgr:
1528         ret = qman_init_fq(fq, 0, &opts);
1529         if (ret)
1530                 DPAA_PMD_ERR("init rx fqid 0x%x failed with ret:%d", fqid, ret);
1531         return ret;
1532 }
1533
1534 /* Initialise a Tx FQ */
1535 static int dpaa_tx_queue_init(struct qman_fq *fq,
1536                               struct fman_if *fman_intf,
1537                               struct qman_cgr *cgr_tx)
1538 {
1539         struct qm_mcc_initfq opts = {0};
1540         struct qm_mcc_initcgr cgr_opts = {
1541                 .we_mask = QM_CGR_WE_CS_THRES |
1542                                 QM_CGR_WE_CSTD_EN |
1543                                 QM_CGR_WE_MODE,
1544                 .cgr = {
1545                         .cstd_en = QM_CGR_EN,
1546                         .mode = QMAN_CGR_MODE_FRAME
1547                 }
1548         };
1549         int ret;
1550
1551         ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID |
1552                              QMAN_FQ_FLAG_TO_DCPORTAL, fq);
1553         if (ret) {
1554                 DPAA_PMD_ERR("create tx fq failed with ret: %d", ret);
1555                 return ret;
1556         }
1557         opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL |
1558                        QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA;
1559         opts.fqd.dest.channel = fman_intf->tx_channel_id;
1560         opts.fqd.dest.wq = DPAA_IF_TX_PRIORITY;
1561         opts.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE;
1562         opts.fqd.context_b = 0;
1563         /* no tx-confirmation */
1564         opts.fqd.context_a.hi = 0x80000000 | fman_dealloc_bufs_mask_hi;
1565         opts.fqd.context_a.lo = 0 | fman_dealloc_bufs_mask_lo;
1566         DPAA_PMD_DEBUG("init tx fq %p, fqid 0x%x", fq, fq->fqid);
1567
1568         if (cgr_tx) {
1569                 /* Enable tail drop with cgr on this queue */
1570                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres,
1571                                       td_tx_threshold, 0);
1572                 cgr_tx->cb = NULL;
1573                 ret = qman_create_cgr(cgr_tx, QMAN_CGR_FLAG_USE_INIT,
1574                                       &cgr_opts);
1575                 if (ret) {
1576                         DPAA_PMD_WARN(
1577                                 "rx taildrop init fail on rx fqid 0x%x(ret=%d)",
1578                                 fq->fqid, ret);
1579                         goto without_cgr;
1580                 }
1581                 opts.we_mask |= QM_INITFQ_WE_CGID;
1582                 opts.fqd.cgid = cgr_tx->cgrid;
1583                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1584                 DPAA_PMD_DEBUG("Tx FQ tail drop enabled, threshold = %d\n",
1585                                 td_tx_threshold);
1586         }
1587 without_cgr:
1588         ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts);
1589         if (ret)
1590                 DPAA_PMD_ERR("init tx fqid 0x%x failed %d", fq->fqid, ret);
1591         return ret;
1592 }
1593
1594 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1595 /* Initialise a DEBUG FQ ([rt]x_error, rx_default). */
1596 static int dpaa_debug_queue_init(struct qman_fq *fq, uint32_t fqid)
1597 {
1598         struct qm_mcc_initfq opts = {0};
1599         int ret;
1600
1601         PMD_INIT_FUNC_TRACE();
1602
1603         ret = qman_reserve_fqid(fqid);
1604         if (ret) {
1605                 DPAA_PMD_ERR("Reserve debug fqid %d failed with ret: %d",
1606                         fqid, ret);
1607                 return -EINVAL;
1608         }
1609         /* "map" this Rx FQ to one of the interfaces Tx FQID */
1610         DPAA_PMD_DEBUG("Creating debug fq %p, fqid %d", fq, fqid);
1611         ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq);
1612         if (ret) {
1613                 DPAA_PMD_ERR("create debug fqid %d failed with ret: %d",
1614                         fqid, ret);
1615                 return ret;
1616         }
1617         opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL;
1618         opts.fqd.dest.wq = DPAA_IF_DEBUG_PRIORITY;
1619         ret = qman_init_fq(fq, 0, &opts);
1620         if (ret)
1621                 DPAA_PMD_ERR("init debug fqid %d failed with ret: %d",
1622                             fqid, ret);
1623         return ret;
1624 }
1625 #endif
1626
1627 /* Initialise a network interface */
1628 static int
1629 dpaa_dev_init_secondary(struct rte_eth_dev *eth_dev)
1630 {
1631         struct rte_dpaa_device *dpaa_device;
1632         struct fm_eth_port_cfg *cfg;
1633         struct dpaa_if *dpaa_intf;
1634         struct fman_if *fman_intf;
1635         int dev_id;
1636
1637         PMD_INIT_FUNC_TRACE();
1638
1639         dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1640         dev_id = dpaa_device->id.dev_id;
1641         cfg = dpaa_get_eth_port_cfg(dev_id);
1642         fman_intf = cfg->fman_if;
1643         eth_dev->process_private = fman_intf;
1644
1645         /* Plugging of UCODE burst API not supported in Secondary */
1646         dpaa_intf = eth_dev->data->dev_private;
1647         eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
1648         if (dpaa_intf->cgr_tx)
1649                 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx_slow;
1650         else
1651                 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx;
1652 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP
1653         qman_set_fq_lookup_table(
1654                 dpaa_intf->rx_queues->qman_fq_lookup_table);
1655 #endif
1656
1657         return 0;
1658 }
1659
1660 /* Initialise a network interface */
1661 static int
1662 dpaa_dev_init(struct rte_eth_dev *eth_dev)
1663 {
1664         int num_rx_fqs, fqid;
1665         int loop, ret = 0;
1666         int dev_id;
1667         struct rte_dpaa_device *dpaa_device;
1668         struct dpaa_if *dpaa_intf;
1669         struct fm_eth_port_cfg *cfg;
1670         struct fman_if *fman_intf;
1671         struct fman_if_bpool *bp, *tmp_bp;
1672         uint32_t cgrid[DPAA_MAX_NUM_PCD_QUEUES];
1673         uint32_t cgrid_tx[MAX_DPAA_CORES];
1674         uint32_t dev_rx_fqids[DPAA_MAX_NUM_PCD_QUEUES];
1675         int8_t dev_vspids[DPAA_MAX_NUM_PCD_QUEUES];
1676         int8_t vsp_id = -1;
1677
1678         PMD_INIT_FUNC_TRACE();
1679
1680         dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1681         dev_id = dpaa_device->id.dev_id;
1682         dpaa_intf = eth_dev->data->dev_private;
1683         cfg = dpaa_get_eth_port_cfg(dev_id);
1684         fman_intf = cfg->fman_if;
1685
1686         dpaa_intf->name = dpaa_device->name;
1687
1688         /* save fman_if & cfg in the interface struture */
1689         eth_dev->process_private = fman_intf;
1690         dpaa_intf->ifid = dev_id;
1691         dpaa_intf->cfg = cfg;
1692
1693         memset((char *)dev_rx_fqids, 0,
1694                 sizeof(uint32_t) * DPAA_MAX_NUM_PCD_QUEUES);
1695
1696         memset(dev_vspids, -1, DPAA_MAX_NUM_PCD_QUEUES);
1697
1698         /* Initialize Rx FQ's */
1699         if (default_q) {
1700                 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES;
1701         } else if (fmc_q) {
1702                 num_rx_fqs = 1;
1703         } else {
1704                 /* FMCLESS mode, load balance to multiple cores.*/
1705                 num_rx_fqs = rte_lcore_count();
1706         }
1707
1708         /* Each device can not have more than DPAA_MAX_NUM_PCD_QUEUES RX
1709          * queues.
1710          */
1711         if (num_rx_fqs < 0 || num_rx_fqs > DPAA_MAX_NUM_PCD_QUEUES) {
1712                 DPAA_PMD_ERR("Invalid number of RX queues\n");
1713                 return -EINVAL;
1714         }
1715
1716         if (num_rx_fqs > 0) {
1717                 dpaa_intf->rx_queues = rte_zmalloc(NULL,
1718                         sizeof(struct qman_fq) * num_rx_fqs, MAX_CACHELINE);
1719                 if (!dpaa_intf->rx_queues) {
1720                         DPAA_PMD_ERR("Failed to alloc mem for RX queues\n");
1721                         return -ENOMEM;
1722                 }
1723         } else {
1724                 dpaa_intf->rx_queues = NULL;
1725         }
1726
1727         memset(cgrid, 0, sizeof(cgrid));
1728         memset(cgrid_tx, 0, sizeof(cgrid_tx));
1729
1730         /* if DPAA_TX_TAILDROP_THRESHOLD is set, use that value; if 0, it means
1731          * Tx tail drop is disabled.
1732          */
1733         if (getenv("DPAA_TX_TAILDROP_THRESHOLD")) {
1734                 td_tx_threshold = atoi(getenv("DPAA_TX_TAILDROP_THRESHOLD"));
1735                 DPAA_PMD_DEBUG("Tail drop threshold env configured: %u",
1736                                td_tx_threshold);
1737                 /* if a very large value is being configured */
1738                 if (td_tx_threshold > UINT16_MAX)
1739                         td_tx_threshold = CGR_RX_PERFQ_THRESH;
1740         }
1741
1742         /* If congestion control is enabled globally*/
1743         if (num_rx_fqs > 0 && td_threshold) {
1744                 dpaa_intf->cgr_rx = rte_zmalloc(NULL,
1745                         sizeof(struct qman_cgr) * num_rx_fqs, MAX_CACHELINE);
1746                 if (!dpaa_intf->cgr_rx) {
1747                         DPAA_PMD_ERR("Failed to alloc mem for cgr_rx\n");
1748                         ret = -ENOMEM;
1749                         goto free_rx;
1750                 }
1751
1752                 ret = qman_alloc_cgrid_range(&cgrid[0], num_rx_fqs, 1, 0);
1753                 if (ret != num_rx_fqs) {
1754                         DPAA_PMD_WARN("insufficient CGRIDs available");
1755                         ret = -EINVAL;
1756                         goto free_rx;
1757                 }
1758         } else {
1759                 dpaa_intf->cgr_rx = NULL;
1760         }
1761
1762         if (!fmc_q && !default_q) {
1763                 ret = qman_alloc_fqid_range(dev_rx_fqids, num_rx_fqs,
1764                                             num_rx_fqs, 0);
1765                 if (ret < 0) {
1766                         DPAA_PMD_ERR("Failed to alloc rx fqid's\n");
1767                         goto free_rx;
1768                 }
1769         }
1770
1771         for (loop = 0; loop < num_rx_fqs; loop++) {
1772                 if (default_q)
1773                         fqid = cfg->rx_def;
1774                 else
1775                         fqid = dev_rx_fqids[loop];
1776
1777                 vsp_id = dev_vspids[loop];
1778
1779                 if (dpaa_intf->cgr_rx)
1780                         dpaa_intf->cgr_rx[loop].cgrid = cgrid[loop];
1781
1782                 ret = dpaa_rx_queue_init(&dpaa_intf->rx_queues[loop],
1783                         dpaa_intf->cgr_rx ? &dpaa_intf->cgr_rx[loop] : NULL,
1784                         fqid);
1785                 if (ret)
1786                         goto free_rx;
1787                 dpaa_intf->rx_queues[loop].vsp_id = vsp_id;
1788                 dpaa_intf->rx_queues[loop].dpaa_intf = dpaa_intf;
1789         }
1790         dpaa_intf->nb_rx_queues = num_rx_fqs;
1791
1792         /* Initialise Tx FQs.free_rx Have as many Tx FQ's as number of cores */
1793         dpaa_intf->tx_queues = rte_zmalloc(NULL, sizeof(struct qman_fq) *
1794                 MAX_DPAA_CORES, MAX_CACHELINE);
1795         if (!dpaa_intf->tx_queues) {
1796                 DPAA_PMD_ERR("Failed to alloc mem for TX queues\n");
1797                 ret = -ENOMEM;
1798                 goto free_rx;
1799         }
1800
1801         /* If congestion control is enabled globally*/
1802         if (td_tx_threshold) {
1803                 dpaa_intf->cgr_tx = rte_zmalloc(NULL,
1804                         sizeof(struct qman_cgr) * MAX_DPAA_CORES,
1805                         MAX_CACHELINE);
1806                 if (!dpaa_intf->cgr_tx) {
1807                         DPAA_PMD_ERR("Failed to alloc mem for cgr_tx\n");
1808                         ret = -ENOMEM;
1809                         goto free_rx;
1810                 }
1811
1812                 ret = qman_alloc_cgrid_range(&cgrid_tx[0], MAX_DPAA_CORES,
1813                                              1, 0);
1814                 if (ret != MAX_DPAA_CORES) {
1815                         DPAA_PMD_WARN("insufficient CGRIDs available");
1816                         ret = -EINVAL;
1817                         goto free_rx;
1818                 }
1819         } else {
1820                 dpaa_intf->cgr_tx = NULL;
1821         }
1822
1823
1824         for (loop = 0; loop < MAX_DPAA_CORES; loop++) {
1825                 if (dpaa_intf->cgr_tx)
1826                         dpaa_intf->cgr_tx[loop].cgrid = cgrid_tx[loop];
1827
1828                 ret = dpaa_tx_queue_init(&dpaa_intf->tx_queues[loop],
1829                         fman_intf,
1830                         dpaa_intf->cgr_tx ? &dpaa_intf->cgr_tx[loop] : NULL);
1831                 if (ret)
1832                         goto free_tx;
1833                 dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf;
1834         }
1835         dpaa_intf->nb_tx_queues = MAX_DPAA_CORES;
1836
1837 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1838         dpaa_debug_queue_init(&dpaa_intf->debug_queues[
1839                 DPAA_DEBUG_FQ_RX_ERROR], fman_intf->fqid_rx_err);
1840         dpaa_intf->debug_queues[DPAA_DEBUG_FQ_RX_ERROR].dpaa_intf = dpaa_intf;
1841         dpaa_debug_queue_init(&dpaa_intf->debug_queues[
1842                 DPAA_DEBUG_FQ_TX_ERROR], fman_intf->fqid_tx_err);
1843         dpaa_intf->debug_queues[DPAA_DEBUG_FQ_TX_ERROR].dpaa_intf = dpaa_intf;
1844 #endif
1845
1846         DPAA_PMD_DEBUG("All frame queues created");
1847
1848         /* Get the initial configuration for flow control */
1849         dpaa_fc_set_default(dpaa_intf, fman_intf);
1850
1851         /* reset bpool list, initialize bpool dynamically */
1852         list_for_each_entry_safe(bp, tmp_bp, &cfg->fman_if->bpool_list, node) {
1853                 list_del(&bp->node);
1854                 rte_free(bp);
1855         }
1856
1857         /* Populate ethdev structure */
1858         eth_dev->dev_ops = &dpaa_devops;
1859         eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
1860         eth_dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
1861
1862         /* Allocate memory for storing MAC addresses */
1863         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr",
1864                 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER, 0);
1865         if (eth_dev->data->mac_addrs == NULL) {
1866                 DPAA_PMD_ERR("Failed to allocate %d bytes needed to "
1867                                                 "store MAC addresses",
1868                                 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER);
1869                 ret = -ENOMEM;
1870                 goto free_tx;
1871         }
1872
1873         /* copy the primary mac address */
1874         rte_ether_addr_copy(&fman_intf->mac_addr, &eth_dev->data->mac_addrs[0]);
1875
1876         RTE_LOG(INFO, PMD, "net: dpaa: %s: %02x:%02x:%02x:%02x:%02x:%02x\n",
1877                 dpaa_device->name,
1878                 fman_intf->mac_addr.addr_bytes[0],
1879                 fman_intf->mac_addr.addr_bytes[1],
1880                 fman_intf->mac_addr.addr_bytes[2],
1881                 fman_intf->mac_addr.addr_bytes[3],
1882                 fman_intf->mac_addr.addr_bytes[4],
1883                 fman_intf->mac_addr.addr_bytes[5]);
1884
1885         if (!fman_intf->is_shared_mac) {
1886                 /* Disable RX mode */
1887                 fman_if_discard_rx_errors(fman_intf);
1888                 fman_if_disable_rx(fman_intf);
1889                 /* Disable promiscuous mode */
1890                 fman_if_promiscuous_disable(fman_intf);
1891                 /* Disable multicast */
1892                 fman_if_reset_mcast_filter_table(fman_intf);
1893                 /* Reset interface statistics */
1894                 fman_if_stats_reset(fman_intf);
1895                 /* Disable SG by default */
1896                 fman_if_set_sg(fman_intf, 0);
1897                 fman_if_set_maxfrm(fman_intf,
1898                                    RTE_ETHER_MAX_LEN + VLAN_TAG_SIZE);
1899         }
1900
1901         return 0;
1902
1903 free_tx:
1904         rte_free(dpaa_intf->tx_queues);
1905         dpaa_intf->tx_queues = NULL;
1906         dpaa_intf->nb_tx_queues = 0;
1907
1908 free_rx:
1909         rte_free(dpaa_intf->cgr_rx);
1910         rte_free(dpaa_intf->cgr_tx);
1911         rte_free(dpaa_intf->rx_queues);
1912         dpaa_intf->rx_queues = NULL;
1913         dpaa_intf->nb_rx_queues = 0;
1914         return ret;
1915 }
1916
1917 static int
1918 dpaa_dev_uninit(struct rte_eth_dev *dev)
1919 {
1920         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1921         int loop;
1922
1923         PMD_INIT_FUNC_TRACE();
1924
1925         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1926                 return -EPERM;
1927
1928         if (!dpaa_intf) {
1929                 DPAA_PMD_WARN("Already closed or not started");
1930                 return -1;
1931         }
1932
1933         /* DPAA FM deconfig */
1934         if (!(default_q || fmc_q)) {
1935                 if (dpaa_fm_deconfig(dpaa_intf, dev->process_private))
1936                         DPAA_PMD_WARN("DPAA FM deconfig failed\n");
1937         }
1938
1939         dpaa_eth_dev_close(dev);
1940
1941         /* release configuration memory */
1942         if (dpaa_intf->fc_conf)
1943                 rte_free(dpaa_intf->fc_conf);
1944
1945         /* Release RX congestion Groups */
1946         if (dpaa_intf->cgr_rx) {
1947                 for (loop = 0; loop < dpaa_intf->nb_rx_queues; loop++)
1948                         qman_delete_cgr(&dpaa_intf->cgr_rx[loop]);
1949
1950                 qman_release_cgrid_range(dpaa_intf->cgr_rx[loop].cgrid,
1951                                          dpaa_intf->nb_rx_queues);
1952         }
1953
1954         rte_free(dpaa_intf->cgr_rx);
1955         dpaa_intf->cgr_rx = NULL;
1956
1957         /* Release TX congestion Groups */
1958         if (dpaa_intf->cgr_tx) {
1959                 for (loop = 0; loop < MAX_DPAA_CORES; loop++)
1960                         qman_delete_cgr(&dpaa_intf->cgr_tx[loop]);
1961
1962                 qman_release_cgrid_range(dpaa_intf->cgr_tx[loop].cgrid,
1963                                          MAX_DPAA_CORES);
1964                 rte_free(dpaa_intf->cgr_tx);
1965                 dpaa_intf->cgr_tx = NULL;
1966         }
1967
1968         rte_free(dpaa_intf->rx_queues);
1969         dpaa_intf->rx_queues = NULL;
1970
1971         rte_free(dpaa_intf->tx_queues);
1972         dpaa_intf->tx_queues = NULL;
1973
1974         dev->dev_ops = NULL;
1975         dev->rx_pkt_burst = NULL;
1976         dev->tx_pkt_burst = NULL;
1977
1978         return 0;
1979 }
1980
1981 static int
1982 rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv,
1983                struct rte_dpaa_device *dpaa_dev)
1984 {
1985         int diag;
1986         int ret;
1987         struct rte_eth_dev *eth_dev;
1988
1989         PMD_INIT_FUNC_TRACE();
1990
1991         if ((DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE) >
1992                 RTE_PKTMBUF_HEADROOM) {
1993                 DPAA_PMD_ERR(
1994                 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA Annotation req(%d)",
1995                 RTE_PKTMBUF_HEADROOM,
1996                 DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE);
1997
1998                 return -1;
1999         }
2000
2001         /* In case of secondary process, the device is already configured
2002          * and no further action is required, except portal initialization
2003          * and verifying secondary attachment to port name.
2004          */
2005         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2006                 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name);
2007                 if (!eth_dev)
2008                         return -ENOMEM;
2009                 eth_dev->device = &dpaa_dev->device;
2010                 eth_dev->dev_ops = &dpaa_devops;
2011
2012                 ret = dpaa_dev_init_secondary(eth_dev);
2013                 if (ret != 0) {
2014                         RTE_LOG(ERR, PMD, "secondary dev init failed\n");
2015                         return ret;
2016                 }
2017
2018                 rte_eth_dev_probing_finish(eth_dev);
2019                 return 0;
2020         }
2021
2022         if (!is_global_init && (rte_eal_process_type() == RTE_PROC_PRIMARY)) {
2023                 if (access("/tmp/fmc.bin", F_OK) == -1) {
2024                         DPAA_PMD_INFO("* FMC not configured.Enabling default mode");
2025                         default_q = 1;
2026                 }
2027
2028                 if (!(default_q || fmc_q)) {
2029                         if (dpaa_fm_init()) {
2030                                 DPAA_PMD_ERR("FM init failed\n");
2031                                 return -1;
2032                         }
2033                 }
2034
2035                 /* disabling the default push mode for LS1043 */
2036                 if (dpaa_svr_family == SVR_LS1043A_FAMILY)
2037                         dpaa_push_mode_max_queue = 0;
2038
2039                 /* if push mode queues to be enabled. Currenly we are allowing
2040                  * only one queue per thread.
2041                  */
2042                 if (getenv("DPAA_PUSH_QUEUES_NUMBER")) {
2043                         dpaa_push_mode_max_queue =
2044                                         atoi(getenv("DPAA_PUSH_QUEUES_NUMBER"));
2045                         if (dpaa_push_mode_max_queue > DPAA_MAX_PUSH_MODE_QUEUE)
2046                             dpaa_push_mode_max_queue = DPAA_MAX_PUSH_MODE_QUEUE;
2047                 }
2048
2049                 is_global_init = 1;
2050         }
2051
2052         if (unlikely(!DPAA_PER_LCORE_PORTAL)) {
2053                 ret = rte_dpaa_portal_init((void *)1);
2054                 if (ret) {
2055                         DPAA_PMD_ERR("Unable to initialize portal");
2056                         return ret;
2057                 }
2058         }
2059
2060         eth_dev = rte_eth_dev_allocate(dpaa_dev->name);
2061         if (!eth_dev)
2062                 return -ENOMEM;
2063
2064         eth_dev->data->dev_private =
2065                         rte_zmalloc("ethdev private structure",
2066                                         sizeof(struct dpaa_if),
2067                                         RTE_CACHE_LINE_SIZE);
2068         if (!eth_dev->data->dev_private) {
2069                 DPAA_PMD_ERR("Cannot allocate memzone for port data");
2070                 rte_eth_dev_release_port(eth_dev);
2071                 return -ENOMEM;
2072         }
2073
2074         eth_dev->device = &dpaa_dev->device;
2075         dpaa_dev->eth_dev = eth_dev;
2076
2077         qman_ern_register_cb(dpaa_free_mbuf);
2078
2079         if (dpaa_drv->drv_flags & RTE_DPAA_DRV_INTR_LSC)
2080                 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;
2081
2082         /* Invoke PMD device initialization function */
2083         diag = dpaa_dev_init(eth_dev);
2084         if (diag == 0) {
2085                 rte_eth_dev_probing_finish(eth_dev);
2086                 return 0;
2087         }
2088
2089         rte_eth_dev_release_port(eth_dev);
2090         return diag;
2091 }
2092
2093 static int
2094 rte_dpaa_remove(struct rte_dpaa_device *dpaa_dev)
2095 {
2096         struct rte_eth_dev *eth_dev;
2097
2098         PMD_INIT_FUNC_TRACE();
2099
2100         eth_dev = dpaa_dev->eth_dev;
2101         dpaa_dev_uninit(eth_dev);
2102
2103         rte_eth_dev_release_port(eth_dev);
2104
2105         return 0;
2106 }
2107
2108 static void __attribute__((destructor(102))) dpaa_finish(void)
2109 {
2110         /* For secondary, primary will do all the cleanup */
2111         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2112                 return;
2113
2114         if (!(default_q || fmc_q)) {
2115                 unsigned int i;
2116
2117                 for (i = 0; i < RTE_MAX_ETHPORTS; i++) {
2118                         if (rte_eth_devices[i].dev_ops == &dpaa_devops) {
2119                                 struct rte_eth_dev *dev = &rte_eth_devices[i];
2120                                 struct dpaa_if *dpaa_intf =
2121                                         dev->data->dev_private;
2122                                 struct fman_if *fif =
2123                                         dev->process_private;
2124                                 if (dpaa_intf->port_handle)
2125                                         if (dpaa_fm_deconfig(dpaa_intf, fif))
2126                                                 DPAA_PMD_WARN("DPAA FM "
2127                                                         "deconfig failed\n");
2128                                 if (fif->num_profiles) {
2129                                         if (dpaa_port_vsp_cleanup(dpaa_intf,
2130                                                                   fif))
2131                                                 DPAA_PMD_WARN("DPAA FM vsp cleanup failed\n");
2132                                 }
2133                         }
2134                 }
2135                 if (is_global_init)
2136                         if (dpaa_fm_term())
2137                                 DPAA_PMD_WARN("DPAA FM term failed\n");
2138
2139                 is_global_init = 0;
2140
2141                 DPAA_PMD_INFO("DPAA fman cleaned up");
2142         }
2143 }
2144
2145 static struct rte_dpaa_driver rte_dpaa_pmd = {
2146         .drv_flags = RTE_DPAA_DRV_INTR_LSC,
2147         .drv_type = FSL_DPAA_ETH,
2148         .probe = rte_dpaa_probe,
2149         .remove = rte_dpaa_remove,
2150 };
2151
2152 RTE_PMD_REGISTER_DPAA(net_dpaa, rte_dpaa_pmd);
2153 RTE_LOG_REGISTER(dpaa_logtype_pmd, pmd.net.dpaa, NOTICE);