1 /* * SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
4 * Copyright 2016-2021 NXP
12 #include <ethdev_driver.h>
13 #include <rte_malloc.h>
14 #include <rte_memcpy.h>
15 #include <rte_string_fns.h>
16 #include <rte_cycles.h>
17 #include <rte_kvargs.h>
19 #include <rte_fslmc.h>
20 #include <rte_flow_driver.h>
22 #include "dpaa2_pmd_logs.h"
23 #include <fslmc_vfio.h>
24 #include <dpaa2_hw_pvt.h>
25 #include <dpaa2_hw_mempool.h>
26 #include <dpaa2_hw_dpio.h>
27 #include <mc/fsl_dpmng.h>
28 #include "dpaa2_ethdev.h"
29 #include "dpaa2_sparser.h"
30 #include <fsl_qbman_debug.h>
32 #define DRIVER_LOOPBACK_MODE "drv_loopback"
33 #define DRIVER_NO_PREFETCH_MODE "drv_no_prefetch"
34 #define DRIVER_TX_CONF "drv_tx_conf"
35 #define DRIVER_ERROR_QUEUE "drv_err_queue"
36 #define CHECK_INTERVAL 100 /* 100ms */
37 #define MAX_REPEAT_TIME 90 /* 9s (90 * 100ms) in total */
39 /* Supported Rx offloads */
40 static uint64_t dev_rx_offloads_sup =
41 RTE_ETH_RX_OFFLOAD_CHECKSUM |
42 RTE_ETH_RX_OFFLOAD_SCTP_CKSUM |
43 RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM |
44 RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM |
45 RTE_ETH_RX_OFFLOAD_VLAN_STRIP |
46 RTE_ETH_RX_OFFLOAD_VLAN_FILTER |
47 RTE_ETH_RX_OFFLOAD_TIMESTAMP;
49 /* Rx offloads which cannot be disabled */
50 static uint64_t dev_rx_offloads_nodis =
51 RTE_ETH_RX_OFFLOAD_RSS_HASH |
52 RTE_ETH_RX_OFFLOAD_SCATTER;
54 /* Supported Tx offloads */
55 static uint64_t dev_tx_offloads_sup =
56 RTE_ETH_TX_OFFLOAD_VLAN_INSERT |
57 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |
58 RTE_ETH_TX_OFFLOAD_UDP_CKSUM |
59 RTE_ETH_TX_OFFLOAD_TCP_CKSUM |
60 RTE_ETH_TX_OFFLOAD_SCTP_CKSUM |
61 RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM |
62 RTE_ETH_TX_OFFLOAD_MT_LOCKFREE |
63 RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE;
65 /* Tx offloads which cannot be disabled */
66 static uint64_t dev_tx_offloads_nodis =
67 RTE_ETH_TX_OFFLOAD_MULTI_SEGS;
69 /* enable timestamp in mbuf */
70 bool dpaa2_enable_ts[RTE_MAX_ETHPORTS];
71 uint64_t dpaa2_timestamp_rx_dynflag;
72 int dpaa2_timestamp_dynfield_offset = -1;
74 /* Enable error queue */
75 bool dpaa2_enable_err_queue;
77 struct rte_dpaa2_xstats_name_off {
78 char name[RTE_ETH_XSTATS_NAME_SIZE];
79 uint8_t page_id; /* dpni statistics page id */
80 uint8_t stats_id; /* stats id in the given page */
83 static const struct rte_dpaa2_xstats_name_off dpaa2_xstats_strings[] = {
84 {"ingress_multicast_frames", 0, 2},
85 {"ingress_multicast_bytes", 0, 3},
86 {"ingress_broadcast_frames", 0, 4},
87 {"ingress_broadcast_bytes", 0, 5},
88 {"egress_multicast_frames", 1, 2},
89 {"egress_multicast_bytes", 1, 3},
90 {"egress_broadcast_frames", 1, 4},
91 {"egress_broadcast_bytes", 1, 5},
92 {"ingress_filtered_frames", 2, 0},
93 {"ingress_discarded_frames", 2, 1},
94 {"ingress_nobuffer_discards", 2, 2},
95 {"egress_discarded_frames", 2, 3},
96 {"egress_confirmed_frames", 2, 4},
97 {"cgr_reject_frames", 4, 0},
98 {"cgr_reject_bytes", 4, 1},
101 static struct rte_dpaa2_driver rte_dpaa2_pmd;
102 static int dpaa2_dev_link_update(struct rte_eth_dev *dev,
103 int wait_to_complete);
104 static int dpaa2_dev_set_link_up(struct rte_eth_dev *dev);
105 static int dpaa2_dev_set_link_down(struct rte_eth_dev *dev);
106 static int dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
109 dpaa2_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
112 struct dpaa2_dev_priv *priv = dev->data->dev_private;
113 struct fsl_mc_io *dpni = dev->process_private;
115 PMD_INIT_FUNC_TRACE();
118 DPAA2_PMD_ERR("dpni is NULL");
123 ret = dpni_add_vlan_id(dpni, CMD_PRI_LOW, priv->token,
126 ret = dpni_remove_vlan_id(dpni, CMD_PRI_LOW,
127 priv->token, vlan_id);
130 DPAA2_PMD_ERR("ret = %d Unable to add/rem vlan %d hwid =%d",
131 ret, vlan_id, priv->hw_id);
137 dpaa2_vlan_offload_set(struct rte_eth_dev *dev, int mask)
139 struct dpaa2_dev_priv *priv = dev->data->dev_private;
140 struct fsl_mc_io *dpni = dev->process_private;
143 PMD_INIT_FUNC_TRACE();
145 if (mask & RTE_ETH_VLAN_FILTER_MASK) {
146 /* VLAN Filter not avaialble */
147 if (!priv->max_vlan_filters) {
148 DPAA2_PMD_INFO("VLAN filter not available");
152 if (dev->data->dev_conf.rxmode.offloads &
153 RTE_ETH_RX_OFFLOAD_VLAN_FILTER)
154 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
157 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
160 DPAA2_PMD_INFO("Unable to set vlan filter = %d", ret);
167 dpaa2_vlan_tpid_set(struct rte_eth_dev *dev,
168 enum rte_vlan_type vlan_type __rte_unused,
171 struct dpaa2_dev_priv *priv = dev->data->dev_private;
172 struct fsl_mc_io *dpni = dev->process_private;
175 PMD_INIT_FUNC_TRACE();
177 /* nothing to be done for standard vlan tpids */
178 if (tpid == 0x8100 || tpid == 0x88A8)
181 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
184 DPAA2_PMD_INFO("Unable to set vlan tpid = %d", ret);
185 /* if already configured tpids, remove them first */
187 struct dpni_custom_tpid_cfg tpid_list = {0};
189 ret = dpni_get_custom_tpid(dpni, CMD_PRI_LOW,
190 priv->token, &tpid_list);
193 ret = dpni_remove_custom_tpid(dpni, CMD_PRI_LOW,
194 priv->token, tpid_list.tpid1);
197 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
205 dpaa2_fw_version_get(struct rte_eth_dev *dev,
210 struct fsl_mc_io *dpni = dev->process_private;
211 struct mc_soc_version mc_plat_info = {0};
212 struct mc_version mc_ver_info = {0};
214 PMD_INIT_FUNC_TRACE();
216 if (mc_get_soc_version(dpni, CMD_PRI_LOW, &mc_plat_info))
217 DPAA2_PMD_WARN("\tmc_get_soc_version failed");
219 if (mc_get_version(dpni, CMD_PRI_LOW, &mc_ver_info))
220 DPAA2_PMD_WARN("\tmc_get_version failed");
222 ret = snprintf(fw_version, fw_size,
227 mc_ver_info.revision);
231 ret += 1; /* add the size of '\0' */
232 if (fw_size < (size_t)ret)
239 dpaa2_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
241 struct dpaa2_dev_priv *priv = dev->data->dev_private;
243 PMD_INIT_FUNC_TRACE();
245 dev_info->max_mac_addrs = priv->max_mac_filters;
246 dev_info->max_rx_pktlen = DPAA2_MAX_RX_PKT_LEN;
247 dev_info->min_rx_bufsize = DPAA2_MIN_RX_BUF_SIZE;
248 dev_info->max_rx_queues = (uint16_t)priv->nb_rx_queues;
249 dev_info->max_tx_queues = (uint16_t)priv->nb_tx_queues;
250 dev_info->rx_offload_capa = dev_rx_offloads_sup |
251 dev_rx_offloads_nodis;
252 dev_info->tx_offload_capa = dev_tx_offloads_sup |
253 dev_tx_offloads_nodis;
254 dev_info->speed_capa = RTE_ETH_LINK_SPEED_1G |
255 RTE_ETH_LINK_SPEED_2_5G |
256 RTE_ETH_LINK_SPEED_10G;
258 dev_info->max_hash_mac_addrs = 0;
259 dev_info->max_vfs = 0;
260 dev_info->max_vmdq_pools = RTE_ETH_16_POOLS;
261 dev_info->flow_type_rss_offloads = DPAA2_RSS_OFFLOAD_ALL;
263 dev_info->default_rxportconf.burst_size = dpaa2_dqrr_size;
264 /* same is rx size for best perf */
265 dev_info->default_txportconf.burst_size = dpaa2_dqrr_size;
267 dev_info->default_rxportconf.nb_queues = 1;
268 dev_info->default_txportconf.nb_queues = 1;
269 dev_info->default_txportconf.ring_size = CONG_ENTER_TX_THRESHOLD;
270 dev_info->default_rxportconf.ring_size = DPAA2_RX_DEFAULT_NBDESC;
272 if (dpaa2_svr_family == SVR_LX2160A) {
273 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_25G |
274 RTE_ETH_LINK_SPEED_40G |
275 RTE_ETH_LINK_SPEED_50G |
276 RTE_ETH_LINK_SPEED_100G;
283 dpaa2_dev_rx_burst_mode_get(struct rte_eth_dev *dev,
284 __rte_unused uint16_t queue_id,
285 struct rte_eth_burst_mode *mode)
287 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
290 const struct burst_info {
293 } rx_offload_map[] = {
294 {RTE_ETH_RX_OFFLOAD_CHECKSUM, " Checksum,"},
295 {RTE_ETH_RX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
296 {RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
297 {RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM, " Outer UDP csum,"},
298 {RTE_ETH_RX_OFFLOAD_VLAN_STRIP, " VLAN strip,"},
299 {RTE_ETH_RX_OFFLOAD_VLAN_FILTER, " VLAN filter,"},
300 {RTE_ETH_RX_OFFLOAD_TIMESTAMP, " Timestamp,"},
301 {RTE_ETH_RX_OFFLOAD_RSS_HASH, " RSS,"},
302 {RTE_ETH_RX_OFFLOAD_SCATTER, " Scattered,"}
305 /* Update Rx offload info */
306 for (i = 0; i < RTE_DIM(rx_offload_map); i++) {
307 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) {
308 snprintf(mode->info, sizeof(mode->info), "%s",
309 rx_offload_map[i].output);
318 dpaa2_dev_tx_burst_mode_get(struct rte_eth_dev *dev,
319 __rte_unused uint16_t queue_id,
320 struct rte_eth_burst_mode *mode)
322 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
325 const struct burst_info {
328 } tx_offload_map[] = {
329 {RTE_ETH_TX_OFFLOAD_VLAN_INSERT, " VLAN Insert,"},
330 {RTE_ETH_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"},
331 {RTE_ETH_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"},
332 {RTE_ETH_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"},
333 {RTE_ETH_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
334 {RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
335 {RTE_ETH_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"},
336 {RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"},
337 {RTE_ETH_TX_OFFLOAD_MULTI_SEGS, " Scattered,"}
340 /* Update Tx offload info */
341 for (i = 0; i < RTE_DIM(tx_offload_map); i++) {
342 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) {
343 snprintf(mode->info, sizeof(mode->info), "%s",
344 tx_offload_map[i].output);
353 dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev)
355 struct dpaa2_dev_priv *priv = dev->data->dev_private;
358 uint8_t num_rxqueue_per_tc;
359 struct dpaa2_queue *mc_q, *mcq;
362 struct dpaa2_queue *dpaa2_q;
364 PMD_INIT_FUNC_TRACE();
366 num_rxqueue_per_tc = (priv->nb_rx_queues / priv->num_rx_tc);
367 if (priv->flags & DPAA2_TX_CONF_ENABLE)
368 tot_queues = priv->nb_rx_queues + 2 * priv->nb_tx_queues;
370 tot_queues = priv->nb_rx_queues + priv->nb_tx_queues;
371 mc_q = rte_malloc(NULL, sizeof(struct dpaa2_queue) * tot_queues,
372 RTE_CACHE_LINE_SIZE);
374 DPAA2_PMD_ERR("Memory allocation failed for rx/tx queues");
378 for (i = 0; i < priv->nb_rx_queues; i++) {
379 mc_q->eth_data = dev->data;
380 priv->rx_vq[i] = mc_q++;
381 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
382 dpaa2_q->q_storage = rte_malloc("dq_storage",
383 sizeof(struct queue_storage_info_t),
384 RTE_CACHE_LINE_SIZE);
385 if (!dpaa2_q->q_storage)
388 memset(dpaa2_q->q_storage, 0,
389 sizeof(struct queue_storage_info_t));
390 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
394 if (dpaa2_enable_err_queue) {
395 priv->rx_err_vq = rte_zmalloc("dpni_rx_err",
396 sizeof(struct dpaa2_queue), 0);
398 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq;
399 dpaa2_q->q_storage = rte_malloc("err_dq_storage",
400 sizeof(struct queue_storage_info_t) *
402 RTE_CACHE_LINE_SIZE);
403 if (!dpaa2_q->q_storage)
406 memset(dpaa2_q->q_storage, 0,
407 sizeof(struct queue_storage_info_t));
408 for (i = 0; i < RTE_MAX_LCORE; i++)
409 if (dpaa2_alloc_dq_storage(&dpaa2_q->q_storage[i]))
413 for (i = 0; i < priv->nb_tx_queues; i++) {
414 mc_q->eth_data = dev->data;
415 mc_q->flow_id = 0xffff;
416 priv->tx_vq[i] = mc_q++;
417 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
418 dpaa2_q->cscn = rte_malloc(NULL,
419 sizeof(struct qbman_result), 16);
424 if (priv->flags & DPAA2_TX_CONF_ENABLE) {
425 /*Setup tx confirmation queues*/
426 for (i = 0; i < priv->nb_tx_queues; i++) {
427 mc_q->eth_data = dev->data;
430 priv->tx_conf_vq[i] = mc_q++;
431 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
433 rte_malloc("dq_storage",
434 sizeof(struct queue_storage_info_t),
435 RTE_CACHE_LINE_SIZE);
436 if (!dpaa2_q->q_storage)
439 memset(dpaa2_q->q_storage, 0,
440 sizeof(struct queue_storage_info_t));
441 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
447 for (dist_idx = 0; dist_idx < priv->nb_rx_queues; dist_idx++) {
448 mcq = (struct dpaa2_queue *)priv->rx_vq[vq_id];
449 mcq->tc_index = dist_idx / num_rxqueue_per_tc;
450 mcq->flow_id = dist_idx % num_rxqueue_per_tc;
458 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
459 rte_free(dpaa2_q->q_storage);
460 priv->tx_conf_vq[i--] = NULL;
462 i = priv->nb_tx_queues;
466 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
467 rte_free(dpaa2_q->cscn);
468 priv->tx_vq[i--] = NULL;
470 i = priv->nb_rx_queues;
473 mc_q = priv->rx_vq[0];
475 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
476 dpaa2_free_dq_storage(dpaa2_q->q_storage);
477 rte_free(dpaa2_q->q_storage);
478 priv->rx_vq[i--] = NULL;
481 if (dpaa2_enable_err_queue) {
482 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq;
483 if (dpaa2_q->q_storage)
484 dpaa2_free_dq_storage(dpaa2_q->q_storage);
485 rte_free(dpaa2_q->q_storage);
493 dpaa2_free_rx_tx_queues(struct rte_eth_dev *dev)
495 struct dpaa2_dev_priv *priv = dev->data->dev_private;
496 struct dpaa2_queue *dpaa2_q;
499 PMD_INIT_FUNC_TRACE();
501 /* Queue allocation base */
502 if (priv->rx_vq[0]) {
503 /* cleaning up queue storage */
504 for (i = 0; i < priv->nb_rx_queues; i++) {
505 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
506 if (dpaa2_q->q_storage)
507 rte_free(dpaa2_q->q_storage);
509 /* cleanup tx queue cscn */
510 for (i = 0; i < priv->nb_tx_queues; i++) {
511 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
512 rte_free(dpaa2_q->cscn);
514 if (priv->flags & DPAA2_TX_CONF_ENABLE) {
515 /* cleanup tx conf queue storage */
516 for (i = 0; i < priv->nb_tx_queues; i++) {
517 dpaa2_q = (struct dpaa2_queue *)
519 rte_free(dpaa2_q->q_storage);
522 /*free memory for all queues (RX+TX) */
523 rte_free(priv->rx_vq[0]);
524 priv->rx_vq[0] = NULL;
529 dpaa2_eth_dev_configure(struct rte_eth_dev *dev)
531 struct dpaa2_dev_priv *priv = dev->data->dev_private;
532 struct fsl_mc_io *dpni = dev->process_private;
533 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
534 uint64_t rx_offloads = eth_conf->rxmode.offloads;
535 uint64_t tx_offloads = eth_conf->txmode.offloads;
536 int rx_l3_csum_offload = false;
537 int rx_l4_csum_offload = false;
538 int tx_l3_csum_offload = false;
539 int tx_l4_csum_offload = false;
541 uint32_t max_rx_pktlen;
543 PMD_INIT_FUNC_TRACE();
545 /* Rx offloads which are enabled by default */
546 if (dev_rx_offloads_nodis & ~rx_offloads) {
548 "Some of rx offloads enabled by default - requested 0x%" PRIx64
549 " fixed are 0x%" PRIx64,
550 rx_offloads, dev_rx_offloads_nodis);
553 /* Tx offloads which are enabled by default */
554 if (dev_tx_offloads_nodis & ~tx_offloads) {
556 "Some of tx offloads enabled by default - requested 0x%" PRIx64
557 " fixed are 0x%" PRIx64,
558 tx_offloads, dev_tx_offloads_nodis);
561 max_rx_pktlen = eth_conf->rxmode.mtu + RTE_ETHER_HDR_LEN +
562 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
563 if (max_rx_pktlen <= DPAA2_MAX_RX_PKT_LEN) {
564 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW,
565 priv->token, max_rx_pktlen - RTE_ETHER_CRC_LEN);
567 DPAA2_PMD_ERR("Unable to set mtu. check config");
570 DPAA2_PMD_INFO("MTU configured for the device: %d",
576 if (eth_conf->rxmode.mq_mode == RTE_ETH_MQ_RX_RSS) {
577 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
578 ret = dpaa2_setup_flow_dist(dev,
579 eth_conf->rx_adv_conf.rss_conf.rss_hf,
583 "Unable to set flow distribution on tc%d."
584 "Check queue config", tc_index);
590 if (rx_offloads & RTE_ETH_RX_OFFLOAD_IPV4_CKSUM)
591 rx_l3_csum_offload = true;
593 if ((rx_offloads & RTE_ETH_RX_OFFLOAD_UDP_CKSUM) ||
594 (rx_offloads & RTE_ETH_RX_OFFLOAD_TCP_CKSUM) ||
595 (rx_offloads & RTE_ETH_RX_OFFLOAD_SCTP_CKSUM))
596 rx_l4_csum_offload = true;
598 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
599 DPNI_OFF_RX_L3_CSUM, rx_l3_csum_offload);
601 DPAA2_PMD_ERR("Error to set RX l3 csum:Error = %d", ret);
605 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
606 DPNI_OFF_RX_L4_CSUM, rx_l4_csum_offload);
608 DPAA2_PMD_ERR("Error to get RX l4 csum:Error = %d", ret);
612 #if !defined(RTE_LIBRTE_IEEE1588)
613 if (rx_offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)
616 ret = rte_mbuf_dyn_rx_timestamp_register(
617 &dpaa2_timestamp_dynfield_offset,
618 &dpaa2_timestamp_rx_dynflag);
620 DPAA2_PMD_ERR("Error to register timestamp field/flag");
623 dpaa2_enable_ts[dev->data->port_id] = true;
626 if (tx_offloads & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM)
627 tx_l3_csum_offload = true;
629 if ((tx_offloads & RTE_ETH_TX_OFFLOAD_UDP_CKSUM) ||
630 (tx_offloads & RTE_ETH_TX_OFFLOAD_TCP_CKSUM) ||
631 (tx_offloads & RTE_ETH_TX_OFFLOAD_SCTP_CKSUM))
632 tx_l4_csum_offload = true;
634 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
635 DPNI_OFF_TX_L3_CSUM, tx_l3_csum_offload);
637 DPAA2_PMD_ERR("Error to set TX l3 csum:Error = %d", ret);
641 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
642 DPNI_OFF_TX_L4_CSUM, tx_l4_csum_offload);
644 DPAA2_PMD_ERR("Error to get TX l4 csum:Error = %d", ret);
648 /* Enabling hash results in FD requires setting DPNI_FLCTYPE_HASH in
649 * dpni_set_offload API. Setting this FLCTYPE for DPNI sets the FD[SC]
650 * to 0 for LS2 in the hardware thus disabling data/annotation
651 * stashing. For LX2 this is fixed in hardware and thus hash result and
652 * parse results can be received in FD using this option.
654 if (dpaa2_svr_family == SVR_LX2160A) {
655 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
656 DPNI_FLCTYPE_HASH, true);
658 DPAA2_PMD_ERR("Error setting FLCTYPE: Err = %d", ret);
663 if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)
664 dpaa2_vlan_offload_set(dev, RTE_ETH_VLAN_FILTER_MASK);
671 /* Function to setup RX flow information. It contains traffic class ID,
672 * flow ID, destination configuration etc.
675 dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev,
676 uint16_t rx_queue_id,
678 unsigned int socket_id __rte_unused,
679 const struct rte_eth_rxconf *rx_conf,
680 struct rte_mempool *mb_pool)
682 struct dpaa2_dev_priv *priv = dev->data->dev_private;
683 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
684 struct dpaa2_queue *dpaa2_q;
685 struct dpni_queue cfg;
691 PMD_INIT_FUNC_TRACE();
693 DPAA2_PMD_DEBUG("dev =%p, queue =%d, pool = %p, conf =%p",
694 dev, rx_queue_id, mb_pool, rx_conf);
696 /* Rx deferred start is not supported */
697 if (rx_conf->rx_deferred_start) {
698 DPAA2_PMD_ERR("%p:Rx deferred start not supported",
703 if (!priv->bp_list || priv->bp_list->mp != mb_pool) {
704 bpid = mempool_to_bpid(mb_pool);
705 ret = dpaa2_attach_bp_list(priv,
706 rte_dpaa2_bpid_info[bpid].bp_list);
710 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];
711 dpaa2_q->mb_pool = mb_pool; /**< mbuf pool to populate RX ring. */
712 dpaa2_q->bp_array = rte_dpaa2_bpid_info;
713 dpaa2_q->nb_desc = UINT16_MAX;
714 dpaa2_q->offloads = rx_conf->offloads;
716 /*Get the flow id from given VQ id*/
717 flow_id = dpaa2_q->flow_id;
718 memset(&cfg, 0, sizeof(struct dpni_queue));
720 options = options | DPNI_QUEUE_OPT_USER_CTX;
721 cfg.user_context = (size_t)(dpaa2_q);
723 /* check if a private cgr available. */
724 for (i = 0; i < priv->max_cgs; i++) {
725 if (!priv->cgid_in_use[i]) {
726 priv->cgid_in_use[i] = 1;
731 if (i < priv->max_cgs) {
732 options |= DPNI_QUEUE_OPT_SET_CGID;
734 dpaa2_q->cgid = cfg.cgid;
736 dpaa2_q->cgid = 0xff;
739 /*if ls2088 or rev2 device, enable the stashing */
741 if ((dpaa2_svr_family & 0xffff0000) != SVR_LS2080A) {
742 options |= DPNI_QUEUE_OPT_FLC;
743 cfg.flc.stash_control = true;
744 cfg.flc.value &= 0xFFFFFFFFFFFFFFC0;
745 /* 00 00 00 - last 6 bit represent annotation, context stashing,
746 * data stashing setting 01 01 00 (0x14)
747 * (in following order ->DS AS CS)
748 * to enable 1 line data, 1 line annotation.
749 * For LX2, this setting should be 01 00 00 (0x10)
751 if ((dpaa2_svr_family & 0xffff0000) == SVR_LX2160A)
752 cfg.flc.value |= 0x10;
754 cfg.flc.value |= 0x14;
756 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_RX,
757 dpaa2_q->tc_index, flow_id, options, &cfg);
759 DPAA2_PMD_ERR("Error in setting the rx flow: = %d", ret);
763 if (!(priv->flags & DPAA2_RX_TAILDROP_OFF)) {
764 struct dpni_taildrop taildrop;
767 dpaa2_q->nb_desc = nb_rx_desc;
768 /* Private CGR will use tail drop length as nb_rx_desc.
769 * for rest cases we can use standard byte based tail drop.
770 * There is no HW restriction, but number of CGRs are limited,
771 * hence this restriction is placed.
773 if (dpaa2_q->cgid != 0xff) {
774 /*enabling per rx queue congestion control */
775 taildrop.threshold = nb_rx_desc;
776 taildrop.units = DPNI_CONGESTION_UNIT_FRAMES;
778 DPAA2_PMD_DEBUG("Enabling CG Tail Drop on queue = %d",
780 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
781 DPNI_CP_CONGESTION_GROUP,
784 dpaa2_q->cgid, &taildrop);
786 /*enabling per rx queue congestion control */
787 taildrop.threshold = CONG_THRESHOLD_RX_BYTES_Q;
788 taildrop.units = DPNI_CONGESTION_UNIT_BYTES;
789 taildrop.oal = CONG_RX_OAL;
790 DPAA2_PMD_DEBUG("Enabling Byte based Drop on queue= %d",
792 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
793 DPNI_CP_QUEUE, DPNI_QUEUE_RX,
794 dpaa2_q->tc_index, flow_id,
798 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
802 } else { /* Disable tail Drop */
803 struct dpni_taildrop taildrop = {0};
804 DPAA2_PMD_INFO("Tail drop is disabled on queue");
807 if (dpaa2_q->cgid != 0xff) {
808 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
809 DPNI_CP_CONGESTION_GROUP, DPNI_QUEUE_RX,
811 dpaa2_q->cgid, &taildrop);
813 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
814 DPNI_CP_QUEUE, DPNI_QUEUE_RX,
815 dpaa2_q->tc_index, flow_id, &taildrop);
818 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
824 dev->data->rx_queues[rx_queue_id] = dpaa2_q;
829 dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev,
830 uint16_t tx_queue_id,
832 unsigned int socket_id __rte_unused,
833 const struct rte_eth_txconf *tx_conf)
835 struct dpaa2_dev_priv *priv = dev->data->dev_private;
836 struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)
837 priv->tx_vq[tx_queue_id];
838 struct dpaa2_queue *dpaa2_tx_conf_q = (struct dpaa2_queue *)
839 priv->tx_conf_vq[tx_queue_id];
840 struct fsl_mc_io *dpni = dev->process_private;
841 struct dpni_queue tx_conf_cfg;
842 struct dpni_queue tx_flow_cfg;
843 uint8_t options = 0, flow_id;
844 struct dpni_queue_id qid;
848 PMD_INIT_FUNC_TRACE();
850 /* Tx deferred start is not supported */
851 if (tx_conf->tx_deferred_start) {
852 DPAA2_PMD_ERR("%p:Tx deferred start not supported",
857 dpaa2_q->nb_desc = UINT16_MAX;
858 dpaa2_q->offloads = tx_conf->offloads;
860 /* Return if queue already configured */
861 if (dpaa2_q->flow_id != 0xffff) {
862 dev->data->tx_queues[tx_queue_id] = dpaa2_q;
866 memset(&tx_conf_cfg, 0, sizeof(struct dpni_queue));
867 memset(&tx_flow_cfg, 0, sizeof(struct dpni_queue));
872 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_TX,
873 tc_id, flow_id, options, &tx_flow_cfg);
875 DPAA2_PMD_ERR("Error in setting the tx flow: "
876 "tc_id=%d, flow=%d err=%d",
877 tc_id, flow_id, ret);
881 dpaa2_q->flow_id = flow_id;
883 if (tx_queue_id == 0) {
884 /*Set tx-conf and error configuration*/
885 if (priv->flags & DPAA2_TX_CONF_ENABLE)
886 ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
890 ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
894 DPAA2_PMD_ERR("Error in set tx conf mode settings: "
899 dpaa2_q->tc_index = tc_id;
901 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
902 DPNI_QUEUE_TX, dpaa2_q->tc_index,
903 dpaa2_q->flow_id, &tx_flow_cfg, &qid);
905 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
908 dpaa2_q->fqid = qid.fqid;
910 if (!(priv->flags & DPAA2_TX_CGR_OFF)) {
911 struct dpni_congestion_notification_cfg cong_notif_cfg = {0};
913 dpaa2_q->nb_desc = nb_tx_desc;
915 cong_notif_cfg.units = DPNI_CONGESTION_UNIT_FRAMES;
916 cong_notif_cfg.threshold_entry = nb_tx_desc;
917 /* Notify that the queue is not congested when the data in
918 * the queue is below this thershold.(90% of value)
920 cong_notif_cfg.threshold_exit = (nb_tx_desc * 9) / 10;
921 cong_notif_cfg.message_ctx = 0;
922 cong_notif_cfg.message_iova =
923 (size_t)DPAA2_VADDR_TO_IOVA(dpaa2_q->cscn);
924 cong_notif_cfg.dest_cfg.dest_type = DPNI_DEST_NONE;
925 cong_notif_cfg.notification_mode =
926 DPNI_CONG_OPT_WRITE_MEM_ON_ENTER |
927 DPNI_CONG_OPT_WRITE_MEM_ON_EXIT |
928 DPNI_CONG_OPT_COHERENT_WRITE;
929 cong_notif_cfg.cg_point = DPNI_CP_QUEUE;
931 ret = dpni_set_congestion_notification(dpni, CMD_PRI_LOW,
938 "Error in setting tx congestion notification: "
943 dpaa2_q->cb_eqresp_free = dpaa2_dev_free_eqresp_buf;
944 dev->data->tx_queues[tx_queue_id] = dpaa2_q;
946 if (priv->flags & DPAA2_TX_CONF_ENABLE) {
947 dpaa2_q->tx_conf_queue = dpaa2_tx_conf_q;
948 options = options | DPNI_QUEUE_OPT_USER_CTX;
949 tx_conf_cfg.user_context = (size_t)(dpaa2_q);
950 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
951 DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
952 dpaa2_tx_conf_q->flow_id, options, &tx_conf_cfg);
954 DPAA2_PMD_ERR("Error in setting the tx conf flow: "
955 "tc_index=%d, flow=%d err=%d",
956 dpaa2_tx_conf_q->tc_index,
957 dpaa2_tx_conf_q->flow_id, ret);
961 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
962 DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
963 dpaa2_tx_conf_q->flow_id, &tx_conf_cfg, &qid);
965 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
968 dpaa2_tx_conf_q->fqid = qid.fqid;
974 dpaa2_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t rx_queue_id)
976 struct dpaa2_queue *dpaa2_q = dev->data->rx_queues[rx_queue_id];
977 struct dpaa2_dev_priv *priv = dpaa2_q->eth_data->dev_private;
978 struct fsl_mc_io *dpni =
979 (struct fsl_mc_io *)priv->eth_dev->process_private;
982 struct dpni_queue cfg;
984 memset(&cfg, 0, sizeof(struct dpni_queue));
985 PMD_INIT_FUNC_TRACE();
986 if (dpaa2_q->cgid != 0xff) {
987 options = DPNI_QUEUE_OPT_CLEAR_CGID;
988 cfg.cgid = dpaa2_q->cgid;
990 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
992 dpaa2_q->tc_index, dpaa2_q->flow_id,
995 DPAA2_PMD_ERR("Unable to clear CGR from q=%u err=%d",
997 priv->cgid_in_use[dpaa2_q->cgid] = 0;
998 dpaa2_q->cgid = 0xff;
1003 dpaa2_dev_rx_queue_count(void *rx_queue)
1006 struct dpaa2_queue *dpaa2_q;
1007 struct qbman_swp *swp;
1008 struct qbman_fq_query_np_rslt state;
1009 uint32_t frame_cnt = 0;
1011 if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
1012 ret = dpaa2_affine_qbman_swp();
1015 "Failed to allocate IO portal, tid: %d\n",
1020 swp = DPAA2_PER_LCORE_PORTAL;
1024 if (qbman_fq_query_state(swp, dpaa2_q->fqid, &state) == 0) {
1025 frame_cnt = qbman_fq_state_frame_count(&state);
1026 DPAA2_PMD_DP_DEBUG("RX frame count for q(%p) is %u",
1027 rx_queue, frame_cnt);
1032 static const uint32_t *
1033 dpaa2_supported_ptypes_get(struct rte_eth_dev *dev)
1035 static const uint32_t ptypes[] = {
1036 /*todo -= add more types */
1039 RTE_PTYPE_L3_IPV4_EXT,
1041 RTE_PTYPE_L3_IPV6_EXT,
1049 if (dev->rx_pkt_burst == dpaa2_dev_prefetch_rx ||
1050 dev->rx_pkt_burst == dpaa2_dev_rx ||
1051 dev->rx_pkt_burst == dpaa2_dev_loopback_rx)
1057 * Dpaa2 link Interrupt handler
1060 * The address of parameter (struct rte_eth_dev *) regsitered before.
1066 dpaa2_interrupt_handler(void *param)
1068 struct rte_eth_dev *dev = param;
1069 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1070 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1072 int irq_index = DPNI_IRQ_INDEX;
1073 unsigned int status = 0, clear = 0;
1075 PMD_INIT_FUNC_TRACE();
1078 DPAA2_PMD_ERR("dpni is NULL");
1082 ret = dpni_get_irq_status(dpni, CMD_PRI_LOW, priv->token,
1083 irq_index, &status);
1084 if (unlikely(ret)) {
1085 DPAA2_PMD_ERR("Can't get irq status (err %d)", ret);
1090 if (status & DPNI_IRQ_EVENT_LINK_CHANGED) {
1091 clear = DPNI_IRQ_EVENT_LINK_CHANGED;
1092 dpaa2_dev_link_update(dev, 0);
1093 /* calling all the apps registered for link status event */
1094 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1097 ret = dpni_clear_irq_status(dpni, CMD_PRI_LOW, priv->token,
1100 DPAA2_PMD_ERR("Can't clear irq status (err %d)", ret);
1104 dpaa2_eth_setup_irqs(struct rte_eth_dev *dev, int enable)
1107 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1108 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1109 int irq_index = DPNI_IRQ_INDEX;
1110 unsigned int mask = DPNI_IRQ_EVENT_LINK_CHANGED;
1112 PMD_INIT_FUNC_TRACE();
1114 err = dpni_set_irq_mask(dpni, CMD_PRI_LOW, priv->token,
1117 DPAA2_PMD_ERR("Error: dpni_set_irq_mask():%d (%s)", err,
1122 err = dpni_set_irq_enable(dpni, CMD_PRI_LOW, priv->token,
1125 DPAA2_PMD_ERR("Error: dpni_set_irq_enable():%d (%s)", err,
1132 dpaa2_dev_start(struct rte_eth_dev *dev)
1134 struct rte_device *rdev = dev->device;
1135 struct rte_dpaa2_device *dpaa2_dev;
1136 struct rte_eth_dev_data *data = dev->data;
1137 struct dpaa2_dev_priv *priv = data->dev_private;
1138 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1139 struct dpni_queue cfg;
1140 struct dpni_error_cfg err_cfg;
1142 struct dpni_queue_id qid;
1143 struct dpaa2_queue *dpaa2_q;
1145 struct rte_intr_handle *intr_handle;
1147 dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device);
1148 intr_handle = dpaa2_dev->intr_handle;
1150 PMD_INIT_FUNC_TRACE();
1152 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1154 DPAA2_PMD_ERR("Failure in enabling dpni %d device: err=%d",
1159 /* Power up the phy. Needed to make the link go UP */
1160 dpaa2_dev_set_link_up(dev);
1162 ret = dpni_get_qdid(dpni, CMD_PRI_LOW, priv->token,
1163 DPNI_QUEUE_TX, &qdid);
1165 DPAA2_PMD_ERR("Error in getting qdid: err=%d", ret);
1170 for (i = 0; i < data->nb_rx_queues; i++) {
1171 dpaa2_q = (struct dpaa2_queue *)data->rx_queues[i];
1172 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
1173 DPNI_QUEUE_RX, dpaa2_q->tc_index,
1174 dpaa2_q->flow_id, &cfg, &qid);
1176 DPAA2_PMD_ERR("Error in getting flow information: "
1180 dpaa2_q->fqid = qid.fqid;
1183 if (dpaa2_enable_err_queue) {
1184 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
1185 DPNI_QUEUE_RX_ERR, 0, 0, &cfg, &qid);
1187 DPAA2_PMD_ERR("Error getting rx err flow information: err=%d",
1191 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq;
1192 dpaa2_q->fqid = qid.fqid;
1193 dpaa2_q->eth_data = dev->data;
1195 err_cfg.errors = DPNI_ERROR_DISC;
1196 err_cfg.error_action = DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE;
1198 /* checksum errors, send them to normal path
1199 * and set it in annotation
1201 err_cfg.errors = DPNI_ERROR_L3CE | DPNI_ERROR_L4CE;
1203 /* if packet with parse error are not to be dropped */
1204 err_cfg.errors |= DPNI_ERROR_PHE;
1206 err_cfg.error_action = DPNI_ERROR_ACTION_CONTINUE;
1208 err_cfg.set_frame_annotation = true;
1210 ret = dpni_set_errors_behavior(dpni, CMD_PRI_LOW,
1211 priv->token, &err_cfg);
1213 DPAA2_PMD_ERR("Error to dpni_set_errors_behavior: code = %d",
1218 /* if the interrupts were configured on this devices*/
1219 if (intr_handle && rte_intr_fd_get(intr_handle) &&
1220 dev->data->dev_conf.intr_conf.lsc != 0) {
1221 /* Registering LSC interrupt handler */
1222 rte_intr_callback_register(intr_handle,
1223 dpaa2_interrupt_handler,
1226 /* enable vfio intr/eventfd mapping
1227 * Interrupt index 0 is required, so we can not use
1230 rte_dpaa2_intr_enable(intr_handle, DPNI_IRQ_INDEX);
1232 /* enable dpni_irqs */
1233 dpaa2_eth_setup_irqs(dev, 1);
1236 /* Change the tx burst function if ordered queues are used */
1237 if (priv->en_ordered)
1238 dev->tx_pkt_burst = dpaa2_dev_tx_ordered;
1244 * This routine disables all traffic on the adapter by issuing a
1245 * global reset on the MAC.
1248 dpaa2_dev_stop(struct rte_eth_dev *dev)
1250 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1251 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1253 struct rte_eth_link link;
1254 struct rte_intr_handle *intr_handle = dev->intr_handle;
1256 PMD_INIT_FUNC_TRACE();
1258 /* reset interrupt callback */
1259 if (intr_handle && rte_intr_fd_get(intr_handle) &&
1260 dev->data->dev_conf.intr_conf.lsc != 0) {
1261 /*disable dpni irqs */
1262 dpaa2_eth_setup_irqs(dev, 0);
1264 /* disable vfio intr before callback unregister */
1265 rte_dpaa2_intr_disable(intr_handle, DPNI_IRQ_INDEX);
1267 /* Unregistering LSC interrupt handler */
1268 rte_intr_callback_unregister(intr_handle,
1269 dpaa2_interrupt_handler,
1273 dpaa2_dev_set_link_down(dev);
1275 ret = dpni_disable(dpni, CMD_PRI_LOW, priv->token);
1277 DPAA2_PMD_ERR("Failure (ret %d) in disabling dpni %d dev",
1282 /* clear the recorded link status */
1283 memset(&link, 0, sizeof(link));
1284 rte_eth_linkstatus_set(dev, &link);
1290 dpaa2_dev_close(struct rte_eth_dev *dev)
1292 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1293 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1295 struct rte_eth_link link;
1297 PMD_INIT_FUNC_TRACE();
1299 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1303 DPAA2_PMD_WARN("Already closed or not started");
1307 dpaa2_tm_deinit(dev);
1308 dpaa2_flow_clean(dev);
1309 /* Clean the device first */
1310 ret = dpni_reset(dpni, CMD_PRI_LOW, priv->token);
1312 DPAA2_PMD_ERR("Failure cleaning dpni device: err=%d", ret);
1316 memset(&link, 0, sizeof(link));
1317 rte_eth_linkstatus_set(dev, &link);
1319 /* Free private queues memory */
1320 dpaa2_free_rx_tx_queues(dev);
1321 /* Close the device at underlying layer*/
1322 ret = dpni_close(dpni, CMD_PRI_LOW, priv->token);
1324 DPAA2_PMD_ERR("Failure closing dpni device with err code %d",
1328 /* Free the allocated memory for ethernet private data and dpni*/
1330 dev->process_private = NULL;
1333 for (i = 0; i < MAX_TCS; i++)
1334 rte_free((void *)(size_t)priv->extract.tc_extract_param[i]);
1336 if (priv->extract.qos_extract_param)
1337 rte_free((void *)(size_t)priv->extract.qos_extract_param);
1339 DPAA2_PMD_INFO("%s: netdev deleted", dev->data->name);
1344 dpaa2_dev_promiscuous_enable(
1345 struct rte_eth_dev *dev)
1348 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1349 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1351 PMD_INIT_FUNC_TRACE();
1354 DPAA2_PMD_ERR("dpni is NULL");
1358 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1360 DPAA2_PMD_ERR("Unable to enable U promisc mode %d", ret);
1362 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1364 DPAA2_PMD_ERR("Unable to enable M promisc mode %d", ret);
1370 dpaa2_dev_promiscuous_disable(
1371 struct rte_eth_dev *dev)
1374 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1375 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1377 PMD_INIT_FUNC_TRACE();
1380 DPAA2_PMD_ERR("dpni is NULL");
1384 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1386 DPAA2_PMD_ERR("Unable to disable U promisc mode %d", ret);
1388 if (dev->data->all_multicast == 0) {
1389 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW,
1390 priv->token, false);
1392 DPAA2_PMD_ERR("Unable to disable M promisc mode %d",
1400 dpaa2_dev_allmulticast_enable(
1401 struct rte_eth_dev *dev)
1404 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1405 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1407 PMD_INIT_FUNC_TRACE();
1410 DPAA2_PMD_ERR("dpni is NULL");
1414 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1416 DPAA2_PMD_ERR("Unable to enable multicast mode %d", ret);
1422 dpaa2_dev_allmulticast_disable(struct rte_eth_dev *dev)
1425 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1426 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1428 PMD_INIT_FUNC_TRACE();
1431 DPAA2_PMD_ERR("dpni is NULL");
1435 /* must remain on for all promiscuous */
1436 if (dev->data->promiscuous == 1)
1439 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1441 DPAA2_PMD_ERR("Unable to disable multicast mode %d", ret);
1447 dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1450 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1451 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1452 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
1455 PMD_INIT_FUNC_TRACE();
1458 DPAA2_PMD_ERR("dpni is NULL");
1462 /* Set the Max Rx frame length as 'mtu' +
1463 * Maximum Ethernet header length
1465 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, priv->token,
1466 frame_size - RTE_ETHER_CRC_LEN);
1468 DPAA2_PMD_ERR("Setting the max frame length failed");
1471 DPAA2_PMD_INFO("MTU configured for the device: %d", mtu);
1476 dpaa2_dev_add_mac_addr(struct rte_eth_dev *dev,
1477 struct rte_ether_addr *addr,
1478 __rte_unused uint32_t index,
1479 __rte_unused uint32_t pool)
1482 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1483 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1485 PMD_INIT_FUNC_TRACE();
1488 DPAA2_PMD_ERR("dpni is NULL");
1492 ret = dpni_add_mac_addr(dpni, CMD_PRI_LOW, priv->token,
1493 addr->addr_bytes, 0, 0, 0);
1496 "error: Adding the MAC ADDR failed: err = %d", ret);
1501 dpaa2_dev_remove_mac_addr(struct rte_eth_dev *dev,
1505 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1506 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1507 struct rte_eth_dev_data *data = dev->data;
1508 struct rte_ether_addr *macaddr;
1510 PMD_INIT_FUNC_TRACE();
1512 macaddr = &data->mac_addrs[index];
1515 DPAA2_PMD_ERR("dpni is NULL");
1519 ret = dpni_remove_mac_addr(dpni, CMD_PRI_LOW,
1520 priv->token, macaddr->addr_bytes);
1523 "error: Removing the MAC ADDR failed: err = %d", ret);
1527 dpaa2_dev_set_mac_addr(struct rte_eth_dev *dev,
1528 struct rte_ether_addr *addr)
1531 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1532 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1534 PMD_INIT_FUNC_TRACE();
1537 DPAA2_PMD_ERR("dpni is NULL");
1541 ret = dpni_set_primary_mac_addr(dpni, CMD_PRI_LOW,
1542 priv->token, addr->addr_bytes);
1546 "error: Setting the MAC ADDR failed %d", ret);
1552 int dpaa2_dev_stats_get(struct rte_eth_dev *dev,
1553 struct rte_eth_stats *stats)
1555 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1556 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1558 uint8_t page0 = 0, page1 = 1, page2 = 2;
1559 union dpni_statistics value;
1561 struct dpaa2_queue *dpaa2_rxq, *dpaa2_txq;
1563 memset(&value, 0, sizeof(union dpni_statistics));
1565 PMD_INIT_FUNC_TRACE();
1568 DPAA2_PMD_ERR("dpni is NULL");
1573 DPAA2_PMD_ERR("stats is NULL");
1577 /*Get Counters from page_0*/
1578 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1583 stats->ipackets = value.page_0.ingress_all_frames;
1584 stats->ibytes = value.page_0.ingress_all_bytes;
1586 /*Get Counters from page_1*/
1587 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1592 stats->opackets = value.page_1.egress_all_frames;
1593 stats->obytes = value.page_1.egress_all_bytes;
1595 /*Get Counters from page_2*/
1596 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1601 /* Ingress drop frame count due to configured rules */
1602 stats->ierrors = value.page_2.ingress_filtered_frames;
1603 /* Ingress drop frame count due to error */
1604 stats->ierrors += value.page_2.ingress_discarded_frames;
1606 stats->oerrors = value.page_2.egress_discarded_frames;
1607 stats->imissed = value.page_2.ingress_nobuffer_discards;
1609 /* Fill in per queue stats */
1610 for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) &&
1611 (i < priv->nb_rx_queues || i < priv->nb_tx_queues); ++i) {
1612 dpaa2_rxq = (struct dpaa2_queue *)priv->rx_vq[i];
1613 dpaa2_txq = (struct dpaa2_queue *)priv->tx_vq[i];
1615 stats->q_ipackets[i] = dpaa2_rxq->rx_pkts;
1617 stats->q_opackets[i] = dpaa2_txq->tx_pkts;
1619 /* Byte counting is not implemented */
1620 stats->q_ibytes[i] = 0;
1621 stats->q_obytes[i] = 0;
1627 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1632 dpaa2_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1635 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1636 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1638 union dpni_statistics value[5] = {};
1639 unsigned int i = 0, num = RTE_DIM(dpaa2_xstats_strings);
1647 /* Get Counters from page_0*/
1648 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1653 /* Get Counters from page_1*/
1654 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1659 /* Get Counters from page_2*/
1660 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1665 for (i = 0; i < priv->max_cgs; i++) {
1666 if (!priv->cgid_in_use[i]) {
1667 /* Get Counters from page_4*/
1668 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW,
1677 for (i = 0; i < num; i++) {
1679 xstats[i].value = value[dpaa2_xstats_strings[i].page_id].
1680 raw.counter[dpaa2_xstats_strings[i].stats_id];
1684 DPAA2_PMD_ERR("Error in obtaining extended stats (%d)", retcode);
1689 dpaa2_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1690 struct rte_eth_xstat_name *xstats_names,
1693 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1695 if (limit < stat_cnt)
1698 if (xstats_names != NULL)
1699 for (i = 0; i < stat_cnt; i++)
1700 strlcpy(xstats_names[i].name,
1701 dpaa2_xstats_strings[i].name,
1702 sizeof(xstats_names[i].name));
1708 dpaa2_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1709 uint64_t *values, unsigned int n)
1711 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1712 uint64_t values_copy[stat_cnt];
1715 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1716 struct fsl_mc_io *dpni =
1717 (struct fsl_mc_io *)dev->process_private;
1719 union dpni_statistics value[5] = {};
1727 /* Get Counters from page_0*/
1728 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1733 /* Get Counters from page_1*/
1734 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1739 /* Get Counters from page_2*/
1740 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1745 /* Get Counters from page_4*/
1746 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1751 for (i = 0; i < stat_cnt; i++) {
1752 values[i] = value[dpaa2_xstats_strings[i].page_id].
1753 raw.counter[dpaa2_xstats_strings[i].stats_id];
1758 dpaa2_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
1760 for (i = 0; i < n; i++) {
1761 if (ids[i] >= stat_cnt) {
1762 DPAA2_PMD_ERR("xstats id value isn't valid");
1765 values[i] = values_copy[ids[i]];
1771 dpaa2_xstats_get_names_by_id(
1772 struct rte_eth_dev *dev,
1773 const uint64_t *ids,
1774 struct rte_eth_xstat_name *xstats_names,
1777 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1778 struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
1781 return dpaa2_xstats_get_names(dev, xstats_names, limit);
1783 dpaa2_xstats_get_names(dev, xstats_names_copy, limit);
1785 for (i = 0; i < limit; i++) {
1786 if (ids[i] >= stat_cnt) {
1787 DPAA2_PMD_ERR("xstats id value isn't valid");
1790 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
1796 dpaa2_dev_stats_reset(struct rte_eth_dev *dev)
1798 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1799 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1802 struct dpaa2_queue *dpaa2_q;
1804 PMD_INIT_FUNC_TRACE();
1807 DPAA2_PMD_ERR("dpni is NULL");
1811 retcode = dpni_reset_statistics(dpni, CMD_PRI_LOW, priv->token);
1815 /* Reset the per queue stats in dpaa2_queue structure */
1816 for (i = 0; i < priv->nb_rx_queues; i++) {
1817 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
1819 dpaa2_q->rx_pkts = 0;
1822 for (i = 0; i < priv->nb_tx_queues; i++) {
1823 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
1825 dpaa2_q->tx_pkts = 0;
1831 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1835 /* return 0 means link status changed, -1 means not changed */
1837 dpaa2_dev_link_update(struct rte_eth_dev *dev,
1838 int wait_to_complete)
1841 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1842 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1843 struct rte_eth_link link;
1844 struct dpni_link_state state = {0};
1848 DPAA2_PMD_ERR("dpni is NULL");
1852 for (count = 0; count <= MAX_REPEAT_TIME; count++) {
1853 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token,
1856 DPAA2_PMD_DEBUG("error: dpni_get_link_state %d", ret);
1859 if (state.up == RTE_ETH_LINK_DOWN &&
1861 rte_delay_ms(CHECK_INTERVAL);
1866 memset(&link, 0, sizeof(struct rte_eth_link));
1867 link.link_status = state.up;
1868 link.link_speed = state.rate;
1870 if (state.options & DPNI_LINK_OPT_HALF_DUPLEX)
1871 link.link_duplex = RTE_ETH_LINK_HALF_DUPLEX;
1873 link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
1875 ret = rte_eth_linkstatus_set(dev, &link);
1877 DPAA2_PMD_DEBUG("No change in status");
1879 DPAA2_PMD_INFO("Port %d Link is %s\n", dev->data->port_id,
1880 link.link_status ? "Up" : "Down");
1886 * Toggle the DPNI to enable, if not already enabled.
1887 * This is not strictly PHY up/down - it is more of logical toggling.
1890 dpaa2_dev_set_link_up(struct rte_eth_dev *dev)
1893 struct dpaa2_dev_priv *priv;
1894 struct fsl_mc_io *dpni;
1896 struct dpni_link_state state = {0};
1898 priv = dev->data->dev_private;
1899 dpni = (struct fsl_mc_io *)dev->process_private;
1902 DPAA2_PMD_ERR("dpni is NULL");
1906 /* Check if DPNI is currently enabled */
1907 ret = dpni_is_enabled(dpni, CMD_PRI_LOW, priv->token, &en);
1909 /* Unable to obtain dpni status; Not continuing */
1910 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1914 /* Enable link if not already enabled */
1916 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1918 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1922 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1924 DPAA2_PMD_DEBUG("Unable to get link state (%d)", ret);
1928 /* changing tx burst function to start enqueues */
1929 dev->tx_pkt_burst = dpaa2_dev_tx;
1930 dev->data->dev_link.link_status = state.up;
1931 dev->data->dev_link.link_speed = state.rate;
1934 DPAA2_PMD_INFO("Port %d Link is Up", dev->data->port_id);
1936 DPAA2_PMD_INFO("Port %d Link is Down", dev->data->port_id);
1941 * Toggle the DPNI to disable, if not already disabled.
1942 * This is not strictly PHY up/down - it is more of logical toggling.
1945 dpaa2_dev_set_link_down(struct rte_eth_dev *dev)
1948 struct dpaa2_dev_priv *priv;
1949 struct fsl_mc_io *dpni;
1950 int dpni_enabled = 0;
1953 PMD_INIT_FUNC_TRACE();
1955 priv = dev->data->dev_private;
1956 dpni = (struct fsl_mc_io *)dev->process_private;
1959 DPAA2_PMD_ERR("Device has not yet been configured");
1963 /*changing tx burst function to avoid any more enqueues */
1964 dev->tx_pkt_burst = dummy_dev_tx;
1966 /* Loop while dpni_disable() attempts to drain the egress FQs
1967 * and confirm them back to us.
1970 ret = dpni_disable(dpni, 0, priv->token);
1972 DPAA2_PMD_ERR("dpni disable failed (%d)", ret);
1975 ret = dpni_is_enabled(dpni, 0, priv->token, &dpni_enabled);
1977 DPAA2_PMD_ERR("dpni enable check failed (%d)", ret);
1981 /* Allow the MC some slack */
1982 rte_delay_us(100 * 1000);
1983 } while (dpni_enabled && --retries);
1986 DPAA2_PMD_WARN("Retry count exceeded disabling dpni");
1987 /* todo- we may have to manually cleanup queues.
1990 DPAA2_PMD_INFO("Port %d Link DOWN successful",
1991 dev->data->port_id);
1994 dev->data->dev_link.link_status = 0;
2000 dpaa2_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2003 struct dpaa2_dev_priv *priv;
2004 struct fsl_mc_io *dpni;
2005 struct dpni_link_state state = {0};
2007 PMD_INIT_FUNC_TRACE();
2009 priv = dev->data->dev_private;
2010 dpni = (struct fsl_mc_io *)dev->process_private;
2012 if (dpni == NULL || fc_conf == NULL) {
2013 DPAA2_PMD_ERR("device not configured");
2017 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
2019 DPAA2_PMD_ERR("error: dpni_get_link_state %d", ret);
2023 memset(fc_conf, 0, sizeof(struct rte_eth_fc_conf));
2024 if (state.options & DPNI_LINK_OPT_PAUSE) {
2025 /* DPNI_LINK_OPT_PAUSE set
2026 * if ASYM_PAUSE not set,
2027 * RX Side flow control (handle received Pause frame)
2028 * TX side flow control (send Pause frame)
2029 * if ASYM_PAUSE set,
2030 * RX Side flow control (handle received Pause frame)
2031 * No TX side flow control (send Pause frame disabled)
2033 if (!(state.options & DPNI_LINK_OPT_ASYM_PAUSE))
2034 fc_conf->mode = RTE_ETH_FC_FULL;
2036 fc_conf->mode = RTE_ETH_FC_RX_PAUSE;
2038 /* DPNI_LINK_OPT_PAUSE not set
2039 * if ASYM_PAUSE set,
2040 * TX side flow control (send Pause frame)
2041 * No RX side flow control (No action on pause frame rx)
2042 * if ASYM_PAUSE not set,
2043 * Flow control disabled
2045 if (state.options & DPNI_LINK_OPT_ASYM_PAUSE)
2046 fc_conf->mode = RTE_ETH_FC_TX_PAUSE;
2048 fc_conf->mode = RTE_ETH_FC_NONE;
2055 dpaa2_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2058 struct dpaa2_dev_priv *priv;
2059 struct fsl_mc_io *dpni;
2060 struct dpni_link_state state = {0};
2061 struct dpni_link_cfg cfg = {0};
2063 PMD_INIT_FUNC_TRACE();
2065 priv = dev->data->dev_private;
2066 dpni = (struct fsl_mc_io *)dev->process_private;
2069 DPAA2_PMD_ERR("dpni is NULL");
2073 /* It is necessary to obtain the current state before setting fc_conf
2074 * as MC would return error in case rate, autoneg or duplex values are
2077 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
2079 DPAA2_PMD_ERR("Unable to get link state (err=%d)", ret);
2083 /* Disable link before setting configuration */
2084 dpaa2_dev_set_link_down(dev);
2086 /* Based on fc_conf, update cfg */
2087 cfg.rate = state.rate;
2088 cfg.options = state.options;
2090 /* update cfg with fc_conf */
2091 switch (fc_conf->mode) {
2092 case RTE_ETH_FC_FULL:
2093 /* Full flow control;
2094 * OPT_PAUSE set, ASYM_PAUSE not set
2096 cfg.options |= DPNI_LINK_OPT_PAUSE;
2097 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
2099 case RTE_ETH_FC_TX_PAUSE:
2100 /* Enable RX flow control
2101 * OPT_PAUSE not set;
2104 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
2105 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
2107 case RTE_ETH_FC_RX_PAUSE:
2108 /* Enable TX Flow control
2112 cfg.options |= DPNI_LINK_OPT_PAUSE;
2113 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
2115 case RTE_ETH_FC_NONE:
2116 /* Disable Flow control
2118 * ASYM_PAUSE not set
2120 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
2121 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
2124 DPAA2_PMD_ERR("Incorrect Flow control flag (%d)",
2129 ret = dpni_set_link_cfg(dpni, CMD_PRI_LOW, priv->token, &cfg);
2131 DPAA2_PMD_ERR("Unable to set Link configuration (err=%d)",
2135 dpaa2_dev_set_link_up(dev);
2141 dpaa2_dev_rss_hash_update(struct rte_eth_dev *dev,
2142 struct rte_eth_rss_conf *rss_conf)
2144 struct rte_eth_dev_data *data = dev->data;
2145 struct dpaa2_dev_priv *priv = data->dev_private;
2146 struct rte_eth_conf *eth_conf = &data->dev_conf;
2149 PMD_INIT_FUNC_TRACE();
2151 if (rss_conf->rss_hf) {
2152 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
2153 ret = dpaa2_setup_flow_dist(dev, rss_conf->rss_hf,
2156 DPAA2_PMD_ERR("Unable to set flow dist on tc%d",
2162 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
2163 ret = dpaa2_remove_flow_dist(dev, tc_index);
2166 "Unable to remove flow dist on tc%d",
2172 eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf;
2177 dpaa2_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2178 struct rte_eth_rss_conf *rss_conf)
2180 struct rte_eth_dev_data *data = dev->data;
2181 struct rte_eth_conf *eth_conf = &data->dev_conf;
2183 /* dpaa2 does not support rss_key, so length should be 0*/
2184 rss_conf->rss_key_len = 0;
2185 rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf;
2189 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev,
2190 int eth_rx_queue_id,
2191 struct dpaa2_dpcon_dev *dpcon,
2192 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
2194 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2195 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2196 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2197 uint8_t flow_id = dpaa2_ethq->flow_id;
2198 struct dpni_queue cfg;
2199 uint8_t options, priority;
2202 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_PARALLEL)
2203 dpaa2_ethq->cb = dpaa2_dev_process_parallel_event;
2204 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC)
2205 dpaa2_ethq->cb = dpaa2_dev_process_atomic_event;
2206 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED)
2207 dpaa2_ethq->cb = dpaa2_dev_process_ordered_event;
2211 priority = (RTE_EVENT_DEV_PRIORITY_LOWEST / queue_conf->ev.priority) *
2212 (dpcon->num_priorities - 1);
2214 memset(&cfg, 0, sizeof(struct dpni_queue));
2215 options = DPNI_QUEUE_OPT_DEST;
2216 cfg.destination.type = DPNI_DEST_DPCON;
2217 cfg.destination.id = dpcon->dpcon_id;
2218 cfg.destination.priority = priority;
2220 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) {
2221 options |= DPNI_QUEUE_OPT_HOLD_ACTIVE;
2222 cfg.destination.hold_active = 1;
2225 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED &&
2226 !eth_priv->en_ordered) {
2227 struct opr_cfg ocfg;
2229 /* Restoration window size = 256 frames */
2231 /* Restoration window size = 512 frames for LX2 */
2232 if (dpaa2_svr_family == SVR_LX2160A)
2234 /* Auto advance NESN window enabled */
2236 /* Late arrival window size disabled */
2238 /* ORL resource exhaustaion advance NESN disabled */
2240 /* Loose ordering enabled */
2242 eth_priv->en_loose_ordered = 1;
2243 /* Strict ordering enabled if explicitly set */
2244 if (getenv("DPAA2_STRICT_ORDERING_ENABLE")) {
2246 eth_priv->en_loose_ordered = 0;
2249 ret = dpni_set_opr(dpni, CMD_PRI_LOW, eth_priv->token,
2250 dpaa2_ethq->tc_index, flow_id,
2251 OPR_OPT_CREATE, &ocfg, 0);
2253 DPAA2_PMD_ERR("Error setting opr: ret: %d\n", ret);
2257 eth_priv->en_ordered = 1;
2260 options |= DPNI_QUEUE_OPT_USER_CTX;
2261 cfg.user_context = (size_t)(dpaa2_ethq);
2263 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2264 dpaa2_ethq->tc_index, flow_id, options, &cfg);
2266 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2270 memcpy(&dpaa2_ethq->ev, &queue_conf->ev, sizeof(struct rte_event));
2275 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev,
2276 int eth_rx_queue_id)
2278 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2279 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2280 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2281 uint8_t flow_id = dpaa2_ethq->flow_id;
2282 struct dpni_queue cfg;
2286 memset(&cfg, 0, sizeof(struct dpni_queue));
2287 options = DPNI_QUEUE_OPT_DEST;
2288 cfg.destination.type = DPNI_DEST_NONE;
2290 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2291 dpaa2_ethq->tc_index, flow_id, options, &cfg);
2293 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2299 dpaa2_dev_flow_ops_get(struct rte_eth_dev *dev,
2300 const struct rte_flow_ops **ops)
2305 *ops = &dpaa2_flow_ops;
2310 dpaa2_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2311 struct rte_eth_rxq_info *qinfo)
2313 struct dpaa2_queue *rxq;
2314 struct dpaa2_dev_priv *priv = dev->data->dev_private;
2315 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2316 uint16_t max_frame_length;
2318 rxq = (struct dpaa2_queue *)dev->data->rx_queues[queue_id];
2320 qinfo->mp = rxq->mb_pool;
2321 qinfo->scattered_rx = dev->data->scattered_rx;
2322 qinfo->nb_desc = rxq->nb_desc;
2323 if (dpni_get_max_frame_length(dpni, CMD_PRI_LOW, priv->token,
2324 &max_frame_length) == 0)
2325 qinfo->rx_buf_size = max_frame_length;
2327 qinfo->conf.rx_free_thresh = 1;
2328 qinfo->conf.rx_drop_en = 1;
2329 qinfo->conf.rx_deferred_start = 0;
2330 qinfo->conf.offloads = rxq->offloads;
2334 dpaa2_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2335 struct rte_eth_txq_info *qinfo)
2337 struct dpaa2_queue *txq;
2339 txq = dev->data->tx_queues[queue_id];
2341 qinfo->nb_desc = txq->nb_desc;
2342 qinfo->conf.tx_thresh.pthresh = 0;
2343 qinfo->conf.tx_thresh.hthresh = 0;
2344 qinfo->conf.tx_thresh.wthresh = 0;
2346 qinfo->conf.tx_free_thresh = 0;
2347 qinfo->conf.tx_rs_thresh = 0;
2348 qinfo->conf.offloads = txq->offloads;
2349 qinfo->conf.tx_deferred_start = 0;
2353 dpaa2_tm_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops)
2355 *(const void **)ops = &dpaa2_tm_ops;
2361 rte_pmd_dpaa2_thread_init(void)
2365 if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
2366 ret = dpaa2_affine_qbman_swp();
2369 "Failed to allocate IO portal, tid: %d\n",
2376 static struct eth_dev_ops dpaa2_ethdev_ops = {
2377 .dev_configure = dpaa2_eth_dev_configure,
2378 .dev_start = dpaa2_dev_start,
2379 .dev_stop = dpaa2_dev_stop,
2380 .dev_close = dpaa2_dev_close,
2381 .promiscuous_enable = dpaa2_dev_promiscuous_enable,
2382 .promiscuous_disable = dpaa2_dev_promiscuous_disable,
2383 .allmulticast_enable = dpaa2_dev_allmulticast_enable,
2384 .allmulticast_disable = dpaa2_dev_allmulticast_disable,
2385 .dev_set_link_up = dpaa2_dev_set_link_up,
2386 .dev_set_link_down = dpaa2_dev_set_link_down,
2387 .link_update = dpaa2_dev_link_update,
2388 .stats_get = dpaa2_dev_stats_get,
2389 .xstats_get = dpaa2_dev_xstats_get,
2390 .xstats_get_by_id = dpaa2_xstats_get_by_id,
2391 .xstats_get_names_by_id = dpaa2_xstats_get_names_by_id,
2392 .xstats_get_names = dpaa2_xstats_get_names,
2393 .stats_reset = dpaa2_dev_stats_reset,
2394 .xstats_reset = dpaa2_dev_stats_reset,
2395 .fw_version_get = dpaa2_fw_version_get,
2396 .dev_infos_get = dpaa2_dev_info_get,
2397 .dev_supported_ptypes_get = dpaa2_supported_ptypes_get,
2398 .mtu_set = dpaa2_dev_mtu_set,
2399 .vlan_filter_set = dpaa2_vlan_filter_set,
2400 .vlan_offload_set = dpaa2_vlan_offload_set,
2401 .vlan_tpid_set = dpaa2_vlan_tpid_set,
2402 .rx_queue_setup = dpaa2_dev_rx_queue_setup,
2403 .rx_queue_release = dpaa2_dev_rx_queue_release,
2404 .tx_queue_setup = dpaa2_dev_tx_queue_setup,
2405 .rx_burst_mode_get = dpaa2_dev_rx_burst_mode_get,
2406 .tx_burst_mode_get = dpaa2_dev_tx_burst_mode_get,
2407 .flow_ctrl_get = dpaa2_flow_ctrl_get,
2408 .flow_ctrl_set = dpaa2_flow_ctrl_set,
2409 .mac_addr_add = dpaa2_dev_add_mac_addr,
2410 .mac_addr_remove = dpaa2_dev_remove_mac_addr,
2411 .mac_addr_set = dpaa2_dev_set_mac_addr,
2412 .rss_hash_update = dpaa2_dev_rss_hash_update,
2413 .rss_hash_conf_get = dpaa2_dev_rss_hash_conf_get,
2414 .flow_ops_get = dpaa2_dev_flow_ops_get,
2415 .rxq_info_get = dpaa2_rxq_info_get,
2416 .txq_info_get = dpaa2_txq_info_get,
2417 .tm_ops_get = dpaa2_tm_ops_get,
2418 #if defined(RTE_LIBRTE_IEEE1588)
2419 .timesync_enable = dpaa2_timesync_enable,
2420 .timesync_disable = dpaa2_timesync_disable,
2421 .timesync_read_time = dpaa2_timesync_read_time,
2422 .timesync_write_time = dpaa2_timesync_write_time,
2423 .timesync_adjust_time = dpaa2_timesync_adjust_time,
2424 .timesync_read_rx_timestamp = dpaa2_timesync_read_rx_timestamp,
2425 .timesync_read_tx_timestamp = dpaa2_timesync_read_tx_timestamp,
2429 /* Populate the mac address from physically available (u-boot/firmware) and/or
2430 * one set by higher layers like MC (restool) etc.
2431 * Returns the table of MAC entries (multiple entries)
2434 populate_mac_addr(struct fsl_mc_io *dpni_dev, struct dpaa2_dev_priv *priv,
2435 struct rte_ether_addr *mac_entry)
2438 struct rte_ether_addr phy_mac, prime_mac;
2440 memset(&phy_mac, 0, sizeof(struct rte_ether_addr));
2441 memset(&prime_mac, 0, sizeof(struct rte_ether_addr));
2443 /* Get the physical device MAC address */
2444 ret = dpni_get_port_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2445 phy_mac.addr_bytes);
2447 DPAA2_PMD_ERR("DPNI get physical port MAC failed: %d", ret);
2451 ret = dpni_get_primary_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2452 prime_mac.addr_bytes);
2454 DPAA2_PMD_ERR("DPNI get Prime port MAC failed: %d", ret);
2458 /* Now that both MAC have been obtained, do:
2459 * if not_empty_mac(phy) && phy != Prime, overwrite prime with Phy
2461 * If empty_mac(phy), return prime.
2462 * if both are empty, create random MAC, set as prime and return
2464 if (!rte_is_zero_ether_addr(&phy_mac)) {
2465 /* If the addresses are not same, overwrite prime */
2466 if (!rte_is_same_ether_addr(&phy_mac, &prime_mac)) {
2467 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2469 phy_mac.addr_bytes);
2471 DPAA2_PMD_ERR("Unable to set MAC Address: %d",
2475 memcpy(&prime_mac, &phy_mac,
2476 sizeof(struct rte_ether_addr));
2478 } else if (rte_is_zero_ether_addr(&prime_mac)) {
2479 /* In case phys and prime, both are zero, create random MAC */
2480 rte_eth_random_addr(prime_mac.addr_bytes);
2481 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2483 prime_mac.addr_bytes);
2485 DPAA2_PMD_ERR("Unable to set MAC Address: %d", ret);
2490 /* prime_mac the final MAC address */
2491 memcpy(mac_entry, &prime_mac, sizeof(struct rte_ether_addr));
2499 check_devargs_handler(__rte_unused const char *key, const char *value,
2500 __rte_unused void *opaque)
2502 if (strcmp(value, "1"))
2509 dpaa2_get_devargs(struct rte_devargs *devargs, const char *key)
2511 struct rte_kvargs *kvlist;
2516 kvlist = rte_kvargs_parse(devargs->args, NULL);
2520 if (!rte_kvargs_count(kvlist, key)) {
2521 rte_kvargs_free(kvlist);
2525 if (rte_kvargs_process(kvlist, key,
2526 check_devargs_handler, NULL) < 0) {
2527 rte_kvargs_free(kvlist);
2530 rte_kvargs_free(kvlist);
2536 dpaa2_dev_init(struct rte_eth_dev *eth_dev)
2538 struct rte_device *dev = eth_dev->device;
2539 struct rte_dpaa2_device *dpaa2_dev;
2540 struct fsl_mc_io *dpni_dev;
2541 struct dpni_attr attr;
2542 struct dpaa2_dev_priv *priv = eth_dev->data->dev_private;
2543 struct dpni_buffer_layout layout;
2546 PMD_INIT_FUNC_TRACE();
2548 dpni_dev = rte_malloc(NULL, sizeof(struct fsl_mc_io), 0);
2550 DPAA2_PMD_ERR("Memory allocation failed for dpni device");
2553 dpni_dev->regs = dpaa2_get_mcp_ptr(MC_PORTAL_INDEX);
2554 eth_dev->process_private = (void *)dpni_dev;
2556 /* For secondary processes, the primary has done all the work */
2557 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2558 /* In case of secondary, only burst and ops API need to be
2561 eth_dev->dev_ops = &dpaa2_ethdev_ops;
2562 eth_dev->rx_queue_count = dpaa2_dev_rx_queue_count;
2563 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE))
2564 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2565 else if (dpaa2_get_devargs(dev->devargs,
2566 DRIVER_NO_PREFETCH_MODE))
2567 eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2569 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2570 eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2574 dpaa2_dev = container_of(dev, struct rte_dpaa2_device, device);
2576 hw_id = dpaa2_dev->object_id;
2577 ret = dpni_open(dpni_dev, CMD_PRI_LOW, hw_id, &priv->token);
2580 "Failure in opening dpni@%d with err code %d",
2586 /* Clean the device first */
2587 ret = dpni_reset(dpni_dev, CMD_PRI_LOW, priv->token);
2589 DPAA2_PMD_ERR("Failure cleaning dpni@%d with err code %d",
2594 ret = dpni_get_attributes(dpni_dev, CMD_PRI_LOW, priv->token, &attr);
2597 "Failure in get dpni@%d attribute, err code %d",
2602 priv->num_rx_tc = attr.num_rx_tcs;
2603 priv->qos_entries = attr.qos_entries;
2604 priv->fs_entries = attr.fs_entries;
2605 priv->dist_queues = attr.num_queues;
2607 /* only if the custom CG is enabled */
2608 if (attr.options & DPNI_OPT_CUSTOM_CG)
2609 priv->max_cgs = attr.num_cgs;
2613 for (i = 0; i < priv->max_cgs; i++)
2614 priv->cgid_in_use[i] = 0;
2616 for (i = 0; i < attr.num_rx_tcs; i++)
2617 priv->nb_rx_queues += attr.num_queues;
2619 /* Using number of TX queues as number of TX TCs */
2620 priv->nb_tx_queues = attr.num_tx_tcs;
2622 DPAA2_PMD_DEBUG("RX-TC= %d, rx_queues= %d, tx_queues=%d, max_cgs=%d",
2623 priv->num_rx_tc, priv->nb_rx_queues,
2624 priv->nb_tx_queues, priv->max_cgs);
2626 priv->hw = dpni_dev;
2627 priv->hw_id = hw_id;
2628 priv->options = attr.options;
2629 priv->max_mac_filters = attr.mac_filter_entries;
2630 priv->max_vlan_filters = attr.vlan_filter_entries;
2632 #if defined(RTE_LIBRTE_IEEE1588)
2633 printf("DPDK IEEE1588 is enabled\n");
2634 priv->flags |= DPAA2_TX_CONF_ENABLE;
2636 /* Used with ``fslmc:dpni.1,drv_tx_conf=1`` */
2637 if (dpaa2_get_devargs(dev->devargs, DRIVER_TX_CONF)) {
2638 priv->flags |= DPAA2_TX_CONF_ENABLE;
2639 DPAA2_PMD_INFO("TX_CONF Enabled");
2642 if (dpaa2_get_devargs(dev->devargs, DRIVER_ERROR_QUEUE)) {
2643 dpaa2_enable_err_queue = 1;
2644 DPAA2_PMD_INFO("Enable error queue");
2647 /* Allocate memory for hardware structure for queues */
2648 ret = dpaa2_alloc_rx_tx_queues(eth_dev);
2650 DPAA2_PMD_ERR("Queue allocation Failed");
2654 /* Allocate memory for storing MAC addresses.
2655 * Table of mac_filter_entries size is allocated so that RTE ether lib
2656 * can add MAC entries when rte_eth_dev_mac_addr_add is called.
2658 eth_dev->data->mac_addrs = rte_zmalloc("dpni",
2659 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries, 0);
2660 if (eth_dev->data->mac_addrs == NULL) {
2662 "Failed to allocate %d bytes needed to store MAC addresses",
2663 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries);
2668 ret = populate_mac_addr(dpni_dev, priv, ð_dev->data->mac_addrs[0]);
2670 DPAA2_PMD_ERR("Unable to fetch MAC Address for device");
2671 rte_free(eth_dev->data->mac_addrs);
2672 eth_dev->data->mac_addrs = NULL;
2676 /* ... tx buffer layout ... */
2677 memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2678 if (priv->flags & DPAA2_TX_CONF_ENABLE) {
2679 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
2680 DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2681 layout.pass_timestamp = true;
2683 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2685 layout.pass_frame_status = 1;
2686 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2687 DPNI_QUEUE_TX, &layout);
2689 DPAA2_PMD_ERR("Error (%d) in setting tx buffer layout", ret);
2693 /* ... tx-conf and error buffer layout ... */
2694 memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2695 if (priv->flags & DPAA2_TX_CONF_ENABLE) {
2696 layout.options = DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2697 layout.pass_timestamp = true;
2699 layout.options |= DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2700 layout.pass_frame_status = 1;
2701 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2702 DPNI_QUEUE_TX_CONFIRM, &layout);
2704 DPAA2_PMD_ERR("Error (%d) in setting tx-conf buffer layout",
2709 eth_dev->dev_ops = &dpaa2_ethdev_ops;
2711 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE)) {
2712 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2713 DPAA2_PMD_INFO("Loopback mode");
2714 } else if (dpaa2_get_devargs(dev->devargs, DRIVER_NO_PREFETCH_MODE)) {
2715 eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2716 DPAA2_PMD_INFO("No Prefetch mode");
2718 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2720 eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2722 /*Init fields w.r.t. classficaition*/
2723 memset(&priv->extract.qos_key_extract, 0,
2724 sizeof(struct dpaa2_key_extract));
2725 priv->extract.qos_extract_param = (size_t)rte_malloc(NULL, 256, 64);
2726 if (!priv->extract.qos_extract_param) {
2727 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow "
2728 " classificaiton ", ret);
2731 priv->extract.qos_key_extract.key_info.ipv4_src_offset =
2732 IP_ADDRESS_OFFSET_INVALID;
2733 priv->extract.qos_key_extract.key_info.ipv4_dst_offset =
2734 IP_ADDRESS_OFFSET_INVALID;
2735 priv->extract.qos_key_extract.key_info.ipv6_src_offset =
2736 IP_ADDRESS_OFFSET_INVALID;
2737 priv->extract.qos_key_extract.key_info.ipv6_dst_offset =
2738 IP_ADDRESS_OFFSET_INVALID;
2740 for (i = 0; i < MAX_TCS; i++) {
2741 memset(&priv->extract.tc_key_extract[i], 0,
2742 sizeof(struct dpaa2_key_extract));
2743 priv->extract.tc_extract_param[i] =
2744 (size_t)rte_malloc(NULL, 256, 64);
2745 if (!priv->extract.tc_extract_param[i]) {
2746 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow classificaiton",
2750 priv->extract.tc_key_extract[i].key_info.ipv4_src_offset =
2751 IP_ADDRESS_OFFSET_INVALID;
2752 priv->extract.tc_key_extract[i].key_info.ipv4_dst_offset =
2753 IP_ADDRESS_OFFSET_INVALID;
2754 priv->extract.tc_key_extract[i].key_info.ipv6_src_offset =
2755 IP_ADDRESS_OFFSET_INVALID;
2756 priv->extract.tc_key_extract[i].key_info.ipv6_dst_offset =
2757 IP_ADDRESS_OFFSET_INVALID;
2760 ret = dpni_set_max_frame_length(dpni_dev, CMD_PRI_LOW, priv->token,
2761 RTE_ETHER_MAX_LEN - RTE_ETHER_CRC_LEN
2764 DPAA2_PMD_ERR("Unable to set mtu. check config");
2768 /*TODO To enable soft parser support DPAA2 driver needs to integrate
2769 * with external entity to receive byte code for software sequence
2770 * and same will be offload to the H/W using MC interface.
2771 * Currently it is assumed that DPAA2 driver has byte code by some
2772 * mean and same if offloaded to H/W.
2774 if (getenv("DPAA2_ENABLE_SOFT_PARSER")) {
2775 WRIOP_SS_INITIALIZER(priv);
2776 ret = dpaa2_eth_load_wriop_soft_parser(priv, DPNI_SS_INGRESS);
2778 DPAA2_PMD_ERR(" Error(%d) in loading softparser\n",
2783 ret = dpaa2_eth_enable_wriop_soft_parser(priv,
2786 DPAA2_PMD_ERR(" Error(%d) in enabling softparser\n",
2791 RTE_LOG(INFO, PMD, "%s: netdev created\n", eth_dev->data->name);
2794 dpaa2_dev_close(eth_dev);
2799 int dpaa2_dev_is_dpaa2(struct rte_eth_dev *dev)
2801 return dev->device->driver == &rte_dpaa2_pmd.driver;
2805 rte_dpaa2_probe(struct rte_dpaa2_driver *dpaa2_drv,
2806 struct rte_dpaa2_device *dpaa2_dev)
2808 struct rte_eth_dev *eth_dev;
2809 struct dpaa2_dev_priv *dev_priv;
2812 if ((DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE) >
2813 RTE_PKTMBUF_HEADROOM) {
2815 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA2 Annotation req(%d)",
2816 RTE_PKTMBUF_HEADROOM,
2817 DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE);
2822 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2823 eth_dev = rte_eth_dev_allocate(dpaa2_dev->device.name);
2826 dev_priv = rte_zmalloc("ethdev private structure",
2827 sizeof(struct dpaa2_dev_priv),
2828 RTE_CACHE_LINE_SIZE);
2829 if (dev_priv == NULL) {
2831 "Unable to allocate memory for private data");
2832 rte_eth_dev_release_port(eth_dev);
2835 eth_dev->data->dev_private = (void *)dev_priv;
2836 /* Store a pointer to eth_dev in dev_private */
2837 dev_priv->eth_dev = eth_dev;
2839 eth_dev = rte_eth_dev_attach_secondary(dpaa2_dev->device.name);
2841 DPAA2_PMD_DEBUG("returning enodev");
2846 eth_dev->device = &dpaa2_dev->device;
2848 dpaa2_dev->eth_dev = eth_dev;
2849 eth_dev->data->rx_mbuf_alloc_failed = 0;
2851 if (dpaa2_drv->drv_flags & RTE_DPAA2_DRV_INTR_LSC)
2852 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;
2854 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2856 /* Invoke PMD device initialization function */
2857 diag = dpaa2_dev_init(eth_dev);
2859 rte_eth_dev_probing_finish(eth_dev);
2863 rte_eth_dev_release_port(eth_dev);
2868 rte_dpaa2_remove(struct rte_dpaa2_device *dpaa2_dev)
2870 struct rte_eth_dev *eth_dev;
2873 eth_dev = dpaa2_dev->eth_dev;
2874 dpaa2_dev_close(eth_dev);
2875 ret = rte_eth_dev_release_port(eth_dev);
2880 static struct rte_dpaa2_driver rte_dpaa2_pmd = {
2881 .drv_flags = RTE_DPAA2_DRV_INTR_LSC | RTE_DPAA2_DRV_IOVA_AS_VA,
2882 .drv_type = DPAA2_ETH,
2883 .probe = rte_dpaa2_probe,
2884 .remove = rte_dpaa2_remove,
2887 RTE_PMD_REGISTER_DPAA2(NET_DPAA2_PMD_DRIVER_NAME, rte_dpaa2_pmd);
2888 RTE_PMD_REGISTER_PARAM_STRING(NET_DPAA2_PMD_DRIVER_NAME,
2889 DRIVER_LOOPBACK_MODE "=<int> "
2890 DRIVER_NO_PREFETCH_MODE "=<int>"
2891 DRIVER_TX_CONF "=<int>"
2892 DRIVER_ERROR_QUEUE "=<int>");
2893 RTE_LOG_REGISTER_DEFAULT(dpaa2_logtype_pmd, NOTICE);