drivers/net/dpaa2/dpaa2_ethdev.c

   1 /* * SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  *   Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
   4  *   Copyright 2016-2020 NXP
   5  *
   6  */
   7
   8 #include <time.h>
   9 #include <net/if.h>
  10
  11 #include <rte_mbuf.h>
  12 #include <ethdev_driver.h>
  13 #include <rte_malloc.h>
  14 #include <rte_memcpy.h>
  15 #include <rte_string_fns.h>
  16 #include <rte_cycles.h>
  17 #include <rte_kvargs.h>
  18 #include <rte_dev.h>
  19 #include <rte_fslmc.h>
  20 #include <rte_flow_driver.h>
  21
  22 #include "dpaa2_pmd_logs.h"
  23 #include <fslmc_vfio.h>
  24 #include <dpaa2_hw_pvt.h>
  25 #include <dpaa2_hw_mempool.h>
  26 #include <dpaa2_hw_dpio.h>
  27 #include <mc/fsl_dpmng.h>
  28 #include "dpaa2_ethdev.h"
  29 #include "dpaa2_sparser.h"
  30 #include <fsl_qbman_debug.h>
  31
  32 #define DRIVER_LOOPBACK_MODE "drv_loopback"
  33 #define DRIVER_NO_PREFETCH_MODE "drv_no_prefetch"
  34 #define CHECK_INTERVAL         100  /* 100ms */
  35 #define MAX_REPEAT_TIME        90   /* 9s (90 * 100ms) in total */
  36
  37 /* Supported Rx offloads */
  38 static uint64_t dev_rx_offloads_sup =
  39                 DEV_RX_OFFLOAD_CHECKSUM |
  40                 DEV_RX_OFFLOAD_SCTP_CKSUM |
  41                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
  42                 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
  43                 DEV_RX_OFFLOAD_VLAN_STRIP |
  44                 DEV_RX_OFFLOAD_VLAN_FILTER |
  45                 DEV_RX_OFFLOAD_JUMBO_FRAME |
  46                 DEV_RX_OFFLOAD_TIMESTAMP;
  47
  48 /* Rx offloads which cannot be disabled */
  49 static uint64_t dev_rx_offloads_nodis =
  50                 DEV_RX_OFFLOAD_RSS_HASH |
  51                 DEV_RX_OFFLOAD_SCATTER;
  52
  53 /* Supported Tx offloads */
  54 static uint64_t dev_tx_offloads_sup =
  55                 DEV_TX_OFFLOAD_VLAN_INSERT |
  56                 DEV_TX_OFFLOAD_IPV4_CKSUM |
  57                 DEV_TX_OFFLOAD_UDP_CKSUM |
  58                 DEV_TX_OFFLOAD_TCP_CKSUM |
  59                 DEV_TX_OFFLOAD_SCTP_CKSUM |
  60                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
  61                 DEV_TX_OFFLOAD_MT_LOCKFREE |
  62                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
  63
  64 /* Tx offloads which cannot be disabled */
  65 static uint64_t dev_tx_offloads_nodis =
  66                 DEV_TX_OFFLOAD_MULTI_SEGS;
  67
  68 /* enable timestamp in mbuf */
  69 bool dpaa2_enable_ts[RTE_MAX_ETHPORTS];
  70 uint64_t dpaa2_timestamp_rx_dynflag;
  71 int dpaa2_timestamp_dynfield_offset = -1;
  72
  73 struct rte_dpaa2_xstats_name_off {
  74         char name[RTE_ETH_XSTATS_NAME_SIZE];
  75         uint8_t page_id; /* dpni statistics page id */
  76         uint8_t stats_id; /* stats id in the given page */
  77 };
  78
  79 static const struct rte_dpaa2_xstats_name_off dpaa2_xstats_strings[] = {
  80         {"ingress_multicast_frames", 0, 2},
  81         {"ingress_multicast_bytes", 0, 3},
  82         {"ingress_broadcast_frames", 0, 4},
  83         {"ingress_broadcast_bytes", 0, 5},
  84         {"egress_multicast_frames", 1, 2},
  85         {"egress_multicast_bytes", 1, 3},
  86         {"egress_broadcast_frames", 1, 4},
  87         {"egress_broadcast_bytes", 1, 5},
  88         {"ingress_filtered_frames", 2, 0},
  89         {"ingress_discarded_frames", 2, 1},
  90         {"ingress_nobuffer_discards", 2, 2},
  91         {"egress_discarded_frames", 2, 3},
  92         {"egress_confirmed_frames", 2, 4},
  93         {"cgr_reject_frames", 4, 0},
  94         {"cgr_reject_bytes", 4, 1},
  95 };
  96
  97 static const enum rte_filter_op dpaa2_supported_filter_ops[] = {
  98         RTE_ETH_FILTER_GET
  99 };
 100
 101 static struct rte_dpaa2_driver rte_dpaa2_pmd;
 102 static int dpaa2_dev_link_update(struct rte_eth_dev *dev,
 103                                  int wait_to_complete);
 104 static int dpaa2_dev_set_link_up(struct rte_eth_dev *dev);
 105 static int dpaa2_dev_set_link_down(struct rte_eth_dev *dev);
 106 static int dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 107
 108 static int
 109 dpaa2_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 110 {
 111         int ret;
 112         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 113         struct fsl_mc_io *dpni = dev->process_private;
 114
 115         PMD_INIT_FUNC_TRACE();
 116
 117         if (dpni == NULL) {
 118                 DPAA2_PMD_ERR("dpni is NULL");
 119                 return -1;
 120         }
 121
 122         if (on)
 123                 ret = dpni_add_vlan_id(dpni, CMD_PRI_LOW, priv->token,
 124                                        vlan_id, 0, 0, 0);
 125         else
 126                 ret = dpni_remove_vlan_id(dpni, CMD_PRI_LOW,
 127                                           priv->token, vlan_id);
 128
 129         if (ret < 0)
 130                 DPAA2_PMD_ERR("ret = %d Unable to add/rem vlan %d hwid =%d",
 131                               ret, vlan_id, priv->hw_id);
 132
 133         return ret;
 134 }
 135
 136 static int
 137 dpaa2_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 138 {
 139         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 140         struct fsl_mc_io *dpni = dev->process_private;
 141         int ret = 0;
 142
 143         PMD_INIT_FUNC_TRACE();
 144
 145         if (mask & ETH_VLAN_FILTER_MASK) {
 146                 /* VLAN Filter not avaialble */
 147                 if (!priv->max_vlan_filters) {
 148                         DPAA2_PMD_INFO("VLAN filter not available");
 149                         return -ENOTSUP;
 150                 }
 151
 152                 if (dev->data->dev_conf.rxmode.offloads &
 153                         DEV_RX_OFFLOAD_VLAN_FILTER)
 154                         ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
 155                                                       priv->token, true);
 156                 else
 157                         ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
 158                                                       priv->token, false);
 159                 if (ret < 0)
 160                         DPAA2_PMD_INFO("Unable to set vlan filter = %d", ret);
 161         }
 162
 163         return ret;
 164 }
 165
 166 static int
 167 dpaa2_vlan_tpid_set(struct rte_eth_dev *dev,
 168                       enum rte_vlan_type vlan_type __rte_unused,
 169                       uint16_t tpid)
 170 {
 171         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 172         struct fsl_mc_io *dpni = dev->process_private;
 173         int ret = -ENOTSUP;
 174
 175         PMD_INIT_FUNC_TRACE();
 176
 177         /* nothing to be done for standard vlan tpids */
 178         if (tpid == 0x8100 || tpid == 0x88A8)
 179                 return 0;
 180
 181         ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
 182                                    priv->token, tpid);
 183         if (ret < 0)
 184                 DPAA2_PMD_INFO("Unable to set vlan tpid = %d", ret);
 185         /* if already configured tpids, remove them first */
 186         if (ret == -EBUSY) {
 187                 struct dpni_custom_tpid_cfg tpid_list = {0};
 188
 189                 ret = dpni_get_custom_tpid(dpni, CMD_PRI_LOW,
 190                                    priv->token, &tpid_list);
 191                 if (ret < 0)
 192                         goto fail;
 193                 ret = dpni_remove_custom_tpid(dpni, CMD_PRI_LOW,
 194                                    priv->token, tpid_list.tpid1);
 195                 if (ret < 0)
 196                         goto fail;
 197                 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
 198                                            priv->token, tpid);
 199         }
 200 fail:
 201         return ret;
 202 }
 203
 204 static int
 205 dpaa2_fw_version_get(struct rte_eth_dev *dev,
 206                      char *fw_version,
 207                      size_t fw_size)
 208 {
 209         int ret;
 210         struct fsl_mc_io *dpni = dev->process_private;
 211         struct mc_soc_version mc_plat_info = {0};
 212         struct mc_version mc_ver_info = {0};
 213
 214         PMD_INIT_FUNC_TRACE();
 215
 216         if (mc_get_soc_version(dpni, CMD_PRI_LOW, &mc_plat_info))
 217                 DPAA2_PMD_WARN("\tmc_get_soc_version failed");
 218
 219         if (mc_get_version(dpni, CMD_PRI_LOW, &mc_ver_info))
 220                 DPAA2_PMD_WARN("\tmc_get_version failed");
 221
 222         ret = snprintf(fw_version, fw_size,
 223                        "%x-%d.%d.%d",
 224                        mc_plat_info.svr,
 225                        mc_ver_info.major,
 226                        mc_ver_info.minor,
 227                        mc_ver_info.revision);
 228
 229         ret += 1; /* add the size of '\0' */
 230         if (fw_size < (uint32_t)ret)
 231                 return ret;
 232         else
 233                 return 0;
 234 }
 235
 236 static int
 237 dpaa2_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
 238 {
 239         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 240
 241         PMD_INIT_FUNC_TRACE();
 242
 243         dev_info->max_mac_addrs = priv->max_mac_filters;
 244         dev_info->max_rx_pktlen = DPAA2_MAX_RX_PKT_LEN;
 245         dev_info->min_rx_bufsize = DPAA2_MIN_RX_BUF_SIZE;
 246         dev_info->max_rx_queues = (uint16_t)priv->nb_rx_queues;
 247         dev_info->max_tx_queues = (uint16_t)priv->nb_tx_queues;
 248         dev_info->rx_offload_capa = dev_rx_offloads_sup |
 249                                         dev_rx_offloads_nodis;
 250         dev_info->tx_offload_capa = dev_tx_offloads_sup |
 251                                         dev_tx_offloads_nodis;
 252         dev_info->speed_capa = ETH_LINK_SPEED_1G |
 253                         ETH_LINK_SPEED_2_5G |
 254                         ETH_LINK_SPEED_10G;
 255
 256         dev_info->max_hash_mac_addrs = 0;
 257         dev_info->max_vfs = 0;
 258         dev_info->max_vmdq_pools = ETH_16_POOLS;
 259         dev_info->flow_type_rss_offloads = DPAA2_RSS_OFFLOAD_ALL;
 260
 261         dev_info->default_rxportconf.burst_size = dpaa2_dqrr_size;
 262         /* same is rx size for best perf */
 263         dev_info->default_txportconf.burst_size = dpaa2_dqrr_size;
 264
 265         dev_info->default_rxportconf.nb_queues = 1;
 266         dev_info->default_txportconf.nb_queues = 1;
 267         dev_info->default_txportconf.ring_size = CONG_ENTER_TX_THRESHOLD;
 268         dev_info->default_rxportconf.ring_size = DPAA2_RX_DEFAULT_NBDESC;
 269
 270         if (dpaa2_svr_family == SVR_LX2160A) {
 271                 dev_info->speed_capa |= ETH_LINK_SPEED_25G |
 272                                 ETH_LINK_SPEED_40G |
 273                                 ETH_LINK_SPEED_50G |
 274                                 ETH_LINK_SPEED_100G;
 275         }
 276
 277         return 0;
 278 }
 279
 280 static int
 281 dpaa2_dev_rx_burst_mode_get(struct rte_eth_dev *dev,
 282                         __rte_unused uint16_t queue_id,
 283                         struct rte_eth_burst_mode *mode)
 284 {
 285         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 286         int ret = -EINVAL;
 287         unsigned int i;
 288         const struct burst_info {
 289                 uint64_t flags;
 290                 const char *output;
 291         } rx_offload_map[] = {
 292                         {DEV_RX_OFFLOAD_CHECKSUM, " Checksum,"},
 293                         {DEV_RX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
 294                         {DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
 295                         {DEV_RX_OFFLOAD_OUTER_UDP_CKSUM, " Outer UDP csum,"},
 296                         {DEV_RX_OFFLOAD_VLAN_STRIP, " VLAN strip,"},
 297                         {DEV_RX_OFFLOAD_VLAN_FILTER, " VLAN filter,"},
 298                         {DEV_RX_OFFLOAD_JUMBO_FRAME, " Jumbo frame,"},
 299                         {DEV_RX_OFFLOAD_TIMESTAMP, " Timestamp,"},
 300                         {DEV_RX_OFFLOAD_RSS_HASH, " RSS,"},
 301                         {DEV_RX_OFFLOAD_SCATTER, " Scattered,"}
 302         };
 303
 304         /* Update Rx offload info */
 305         for (i = 0; i < RTE_DIM(rx_offload_map); i++) {
 306                 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) {
 307                         snprintf(mode->info, sizeof(mode->info), "%s",
 308                                 rx_offload_map[i].output);
 309                         ret = 0;
 310                         break;
 311                 }
 312         }
 313         return ret;
 314 }
 315
 316 static int
 317 dpaa2_dev_tx_burst_mode_get(struct rte_eth_dev *dev,
 318                         __rte_unused uint16_t queue_id,
 319                         struct rte_eth_burst_mode *mode)
 320 {
 321         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 322         int ret = -EINVAL;
 323         unsigned int i;
 324         const struct burst_info {
 325                 uint64_t flags;
 326                 const char *output;
 327         } tx_offload_map[] = {
 328                         {DEV_TX_OFFLOAD_VLAN_INSERT, " VLAN Insert,"},
 329                         {DEV_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"},
 330                         {DEV_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"},
 331                         {DEV_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"},
 332                         {DEV_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
 333                         {DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
 334                         {DEV_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"},
 335                         {DEV_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"},
 336                         {DEV_TX_OFFLOAD_MULTI_SEGS, " Scattered,"}
 337         };
 338
 339         /* Update Tx offload info */
 340         for (i = 0; i < RTE_DIM(tx_offload_map); i++) {
 341                 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) {
 342                         snprintf(mode->info, sizeof(mode->info), "%s",
 343                                 tx_offload_map[i].output);
 344                         ret = 0;
 345                         break;
 346                 }
 347         }
 348         return ret;
 349 }
 350
 351 static int
 352 dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev)
 353 {
 354         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 355         uint16_t dist_idx;
 356         uint32_t vq_id;
 357         uint8_t num_rxqueue_per_tc;
 358         struct dpaa2_queue *mc_q, *mcq;
 359         uint32_t tot_queues;
 360         int i;
 361         struct dpaa2_queue *dpaa2_q;
 362
 363         PMD_INIT_FUNC_TRACE();
 364
 365         num_rxqueue_per_tc = (priv->nb_rx_queues / priv->num_rx_tc);
 366         if (priv->tx_conf_en)
 367                 tot_queues = priv->nb_rx_queues + 2 * priv->nb_tx_queues;
 368         else
 369                 tot_queues = priv->nb_rx_queues + priv->nb_tx_queues;
 370         mc_q = rte_malloc(NULL, sizeof(struct dpaa2_queue) * tot_queues,
 371                           RTE_CACHE_LINE_SIZE);
 372         if (!mc_q) {
 373                 DPAA2_PMD_ERR("Memory allocation failed for rx/tx queues");
 374                 return -1;
 375         }
 376
 377         for (i = 0; i < priv->nb_rx_queues; i++) {
 378                 mc_q->eth_data = dev->data;
 379                 priv->rx_vq[i] = mc_q++;
 380                 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
 381                 dpaa2_q->q_storage = rte_malloc("dq_storage",
 382                                         sizeof(struct queue_storage_info_t),
 383                                         RTE_CACHE_LINE_SIZE);
 384                 if (!dpaa2_q->q_storage)
 385                         goto fail;
 386
 387                 memset(dpaa2_q->q_storage, 0,
 388                        sizeof(struct queue_storage_info_t));
 389                 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
 390                         goto fail;
 391         }
 392
 393         for (i = 0; i < priv->nb_tx_queues; i++) {
 394                 mc_q->eth_data = dev->data;
 395                 mc_q->flow_id = 0xffff;
 396                 priv->tx_vq[i] = mc_q++;
 397                 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
 398                 dpaa2_q->cscn = rte_malloc(NULL,
 399                                            sizeof(struct qbman_result), 16);
 400                 if (!dpaa2_q->cscn)
 401                         goto fail_tx;
 402         }
 403
 404         if (priv->tx_conf_en) {
 405                 /*Setup tx confirmation queues*/
 406                 for (i = 0; i < priv->nb_tx_queues; i++) {
 407                         mc_q->eth_data = dev->data;
 408                         mc_q->tc_index = i;
 409                         mc_q->flow_id = 0;
 410                         priv->tx_conf_vq[i] = mc_q++;
 411                         dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
 412                         dpaa2_q->q_storage =
 413                                 rte_malloc("dq_storage",
 414                                         sizeof(struct queue_storage_info_t),
 415                                         RTE_CACHE_LINE_SIZE);
 416                         if (!dpaa2_q->q_storage)
 417                                 goto fail_tx_conf;
 418
 419                         memset(dpaa2_q->q_storage, 0,
 420                                sizeof(struct queue_storage_info_t));
 421                         if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
 422                                 goto fail_tx_conf;
 423                 }
 424         }
 425
 426         vq_id = 0;
 427         for (dist_idx = 0; dist_idx < priv->nb_rx_queues; dist_idx++) {
 428                 mcq = (struct dpaa2_queue *)priv->rx_vq[vq_id];
 429                 mcq->tc_index = dist_idx / num_rxqueue_per_tc;
 430                 mcq->flow_id = dist_idx % num_rxqueue_per_tc;
 431                 vq_id++;
 432         }
 433
 434         return 0;
 435 fail_tx_conf:
 436         i -= 1;
 437         while (i >= 0) {
 438                 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
 439                 rte_free(dpaa2_q->q_storage);
 440                 priv->tx_conf_vq[i--] = NULL;
 441         }
 442         i = priv->nb_tx_queues;
 443 fail_tx:
 444         i -= 1;
 445         while (i >= 0) {
 446                 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
 447                 rte_free(dpaa2_q->cscn);
 448                 priv->tx_vq[i--] = NULL;
 449         }
 450         i = priv->nb_rx_queues;
 451 fail:
 452         i -= 1;
 453         mc_q = priv->rx_vq[0];
 454         while (i >= 0) {
 455                 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
 456                 dpaa2_free_dq_storage(dpaa2_q->q_storage);
 457                 rte_free(dpaa2_q->q_storage);
 458                 priv->rx_vq[i--] = NULL;
 459         }
 460         rte_free(mc_q);
 461         return -1;
 462 }
 463
 464 static void
 465 dpaa2_free_rx_tx_queues(struct rte_eth_dev *dev)
 466 {
 467         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 468         struct dpaa2_queue *dpaa2_q;
 469         int i;
 470
 471         PMD_INIT_FUNC_TRACE();
 472
 473         /* Queue allocation base */
 474         if (priv->rx_vq[0]) {
 475                 /* cleaning up queue storage */
 476                 for (i = 0; i < priv->nb_rx_queues; i++) {
 477                         dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
 478                         if (dpaa2_q->q_storage)
 479                                 rte_free(dpaa2_q->q_storage);
 480                 }
 481                 /* cleanup tx queue cscn */
 482                 for (i = 0; i < priv->nb_tx_queues; i++) {
 483                         dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
 484                         rte_free(dpaa2_q->cscn);
 485                 }
 486                 if (priv->tx_conf_en) {
 487                         /* cleanup tx conf queue storage */
 488                         for (i = 0; i < priv->nb_tx_queues; i++) {
 489                                 dpaa2_q = (struct dpaa2_queue *)
 490                                                 priv->tx_conf_vq[i];
 491                                 rte_free(dpaa2_q->q_storage);
 492                         }
 493                 }
 494                 /*free memory for all queues (RX+TX) */
 495                 rte_free(priv->rx_vq[0]);
 496                 priv->rx_vq[0] = NULL;
 497         }
 498 }
 499
 500 static int
 501 dpaa2_eth_dev_configure(struct rte_eth_dev *dev)
 502 {
 503         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 504         struct fsl_mc_io *dpni = dev->process_private;
 505         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 506         uint64_t rx_offloads = eth_conf->rxmode.offloads;
 507         uint64_t tx_offloads = eth_conf->txmode.offloads;
 508         int rx_l3_csum_offload = false;
 509         int rx_l4_csum_offload = false;
 510         int tx_l3_csum_offload = false;
 511         int tx_l4_csum_offload = false;
 512         int ret, tc_index;
 513
 514         PMD_INIT_FUNC_TRACE();
 515
 516         /* Rx offloads which are enabled by default */
 517         if (dev_rx_offloads_nodis & ~rx_offloads) {
 518                 DPAA2_PMD_INFO(
 519                 "Some of rx offloads enabled by default - requested 0x%" PRIx64
 520                 " fixed are 0x%" PRIx64,
 521                 rx_offloads, dev_rx_offloads_nodis);
 522         }
 523
 524         /* Tx offloads which are enabled by default */
 525         if (dev_tx_offloads_nodis & ~tx_offloads) {
 526                 DPAA2_PMD_INFO(
 527                 "Some of tx offloads enabled by default - requested 0x%" PRIx64
 528                 " fixed are 0x%" PRIx64,
 529                 tx_offloads, dev_tx_offloads_nodis);
 530         }
 531
 532         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 533                 if (eth_conf->rxmode.max_rx_pkt_len <= DPAA2_MAX_RX_PKT_LEN) {
 534                         ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW,
 535                                 priv->token, eth_conf->rxmode.max_rx_pkt_len
 536                                 - RTE_ETHER_CRC_LEN);
 537                         if (ret) {
 538                                 DPAA2_PMD_ERR(
 539                                         "Unable to set mtu. check config");
 540                                 return ret;
 541                         }
 542                         dev->data->mtu =
 543                                 dev->data->dev_conf.rxmode.max_rx_pkt_len -
 544                                 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN -
 545                                 VLAN_TAG_SIZE;
 546                 } else {
 547                         return -1;
 548                 }
 549         }
 550
 551         if (eth_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) {
 552                 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
 553                         ret = dpaa2_setup_flow_dist(dev,
 554                                         eth_conf->rx_adv_conf.rss_conf.rss_hf,
 555                                         tc_index);
 556                         if (ret) {
 557                                 DPAA2_PMD_ERR(
 558                                         "Unable to set flow distribution on tc%d."
 559                                         "Check queue config", tc_index);
 560                                 return ret;
 561                         }
 562                 }
 563         }
 564
 565         if (rx_offloads & DEV_RX_OFFLOAD_IPV4_CKSUM)
 566                 rx_l3_csum_offload = true;
 567
 568         if ((rx_offloads & DEV_RX_OFFLOAD_UDP_CKSUM) ||
 569                 (rx_offloads & DEV_RX_OFFLOAD_TCP_CKSUM) ||
 570                 (rx_offloads & DEV_RX_OFFLOAD_SCTP_CKSUM))
 571                 rx_l4_csum_offload = true;
 572
 573         ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 574                                DPNI_OFF_RX_L3_CSUM, rx_l3_csum_offload);
 575         if (ret) {
 576                 DPAA2_PMD_ERR("Error to set RX l3 csum:Error = %d", ret);
 577                 return ret;
 578         }
 579
 580         ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 581                                DPNI_OFF_RX_L4_CSUM, rx_l4_csum_offload);
 582         if (ret) {
 583                 DPAA2_PMD_ERR("Error to get RX l4 csum:Error = %d", ret);
 584                 return ret;
 585         }
 586
 587 #if !defined(RTE_LIBRTE_IEEE1588)
 588         if (rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP)
 589 #endif
 590         {
 591                 ret = rte_mbuf_dyn_rx_timestamp_register(
 592                                 &dpaa2_timestamp_dynfield_offset,
 593                                 &dpaa2_timestamp_rx_dynflag);
 594                 if (ret != 0) {
 595                         DPAA2_PMD_ERR("Error to register timestamp field/flag");
 596                         return -rte_errno;
 597                 }
 598                 dpaa2_enable_ts[dev->data->port_id] = true;
 599         }
 600
 601         if (tx_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)
 602                 tx_l3_csum_offload = true;
 603
 604         if ((tx_offloads & DEV_TX_OFFLOAD_UDP_CKSUM) ||
 605                 (tx_offloads & DEV_TX_OFFLOAD_TCP_CKSUM) ||
 606                 (tx_offloads & DEV_TX_OFFLOAD_SCTP_CKSUM))
 607                 tx_l4_csum_offload = true;
 608
 609         ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 610                                DPNI_OFF_TX_L3_CSUM, tx_l3_csum_offload);
 611         if (ret) {
 612                 DPAA2_PMD_ERR("Error to set TX l3 csum:Error = %d", ret);
 613                 return ret;
 614         }
 615
 616         ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 617                                DPNI_OFF_TX_L4_CSUM, tx_l4_csum_offload);
 618         if (ret) {
 619                 DPAA2_PMD_ERR("Error to get TX l4 csum:Error = %d", ret);
 620                 return ret;
 621         }
 622
 623         /* Enabling hash results in FD requires setting DPNI_FLCTYPE_HASH in
 624          * dpni_set_offload API. Setting this FLCTYPE for DPNI sets the FD[SC]
 625          * to 0 for LS2 in the hardware thus disabling data/annotation
 626          * stashing. For LX2 this is fixed in hardware and thus hash result and
 627          * parse results can be received in FD using this option.
 628          */
 629         if (dpaa2_svr_family == SVR_LX2160A) {
 630                 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 631                                        DPNI_FLCTYPE_HASH, true);
 632                 if (ret) {
 633                         DPAA2_PMD_ERR("Error setting FLCTYPE: Err = %d", ret);
 634                         return ret;
 635                 }
 636         }
 637
 638         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 639                 dpaa2_vlan_offload_set(dev, ETH_VLAN_FILTER_MASK);
 640
 641         return 0;
 642 }
 643
 644 /* Function to setup RX flow information. It contains traffic class ID,
 645  * flow ID, destination configuration etc.
 646  */
 647 static int
 648 dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev,
 649                          uint16_t rx_queue_id,
 650                          uint16_t nb_rx_desc,
 651                          unsigned int socket_id __rte_unused,
 652                          const struct rte_eth_rxconf *rx_conf,
 653                          struct rte_mempool *mb_pool)
 654 {
 655         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 656         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
 657         struct dpaa2_queue *dpaa2_q;
 658         struct dpni_queue cfg;
 659         uint8_t options = 0;
 660         uint8_t flow_id;
 661         uint32_t bpid;
 662         int i, ret;
 663
 664         PMD_INIT_FUNC_TRACE();
 665
 666         DPAA2_PMD_DEBUG("dev =%p, queue =%d, pool = %p, conf =%p",
 667                         dev, rx_queue_id, mb_pool, rx_conf);
 668
 669         /* Rx deferred start is not supported */
 670         if (rx_conf->rx_deferred_start) {
 671                 DPAA2_PMD_ERR("%p:Rx deferred start not supported",
 672                                 (void *)dev);
 673                 return -EINVAL;
 674         }
 675
 676         if (!priv->bp_list || priv->bp_list->mp != mb_pool) {
 677                 bpid = mempool_to_bpid(mb_pool);
 678                 ret = dpaa2_attach_bp_list(priv,
 679                                            rte_dpaa2_bpid_info[bpid].bp_list);
 680                 if (ret)
 681                         return ret;
 682         }
 683         dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];
 684         dpaa2_q->mb_pool = mb_pool; /**< mbuf pool to populate RX ring. */
 685         dpaa2_q->bp_array = rte_dpaa2_bpid_info;
 686         dpaa2_q->nb_desc = UINT16_MAX;
 687         dpaa2_q->offloads = rx_conf->offloads;
 688
 689         /*Get the flow id from given VQ id*/
 690         flow_id = dpaa2_q->flow_id;
 691         memset(&cfg, 0, sizeof(struct dpni_queue));
 692
 693         options = options | DPNI_QUEUE_OPT_USER_CTX;
 694         cfg.user_context = (size_t)(dpaa2_q);
 695
 696         /* check if a private cgr available. */
 697         for (i = 0; i < priv->max_cgs; i++) {
 698                 if (!priv->cgid_in_use[i]) {
 699                         priv->cgid_in_use[i] = 1;
 700                         break;
 701                 }
 702         }
 703
 704         if (i < priv->max_cgs) {
 705                 options |= DPNI_QUEUE_OPT_SET_CGID;
 706                 cfg.cgid = i;
 707                 dpaa2_q->cgid = cfg.cgid;
 708         } else {
 709                 dpaa2_q->cgid = 0xff;
 710         }
 711
 712         /*if ls2088 or rev2 device, enable the stashing */
 713
 714         if ((dpaa2_svr_family & 0xffff0000) != SVR_LS2080A) {
 715                 options |= DPNI_QUEUE_OPT_FLC;
 716                 cfg.flc.stash_control = true;
 717                 cfg.flc.value &= 0xFFFFFFFFFFFFFFC0;
 718                 /* 00 00 00 - last 6 bit represent annotation, context stashing,
 719                  * data stashing setting 01 01 00 (0x14)
 720                  * (in following order ->DS AS CS)
 721                  * to enable 1 line data, 1 line annotation.
 722                  * For LX2, this setting should be 01 00 00 (0x10)
 723                  */
 724                 if ((dpaa2_svr_family & 0xffff0000) == SVR_LX2160A)
 725                         cfg.flc.value |= 0x10;
 726                 else
 727                         cfg.flc.value |= 0x14;
 728         }
 729         ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_RX,
 730                              dpaa2_q->tc_index, flow_id, options, &cfg);
 731         if (ret) {
 732                 DPAA2_PMD_ERR("Error in setting the rx flow: = %d", ret);
 733                 return -1;
 734         }
 735
 736         if (!(priv->flags & DPAA2_RX_TAILDROP_OFF)) {
 737                 struct dpni_taildrop taildrop;
 738
 739                 taildrop.enable = 1;
 740                 dpaa2_q->nb_desc = nb_rx_desc;
 741                 /* Private CGR will use tail drop length as nb_rx_desc.
 742                  * for rest cases we can use standard byte based tail drop.
 743                  * There is no HW restriction, but number of CGRs are limited,
 744                  * hence this restriction is placed.
 745                  */
 746                 if (dpaa2_q->cgid != 0xff) {
 747                         /*enabling per rx queue congestion control */
 748                         taildrop.threshold = nb_rx_desc;
 749                         taildrop.units = DPNI_CONGESTION_UNIT_FRAMES;
 750                         taildrop.oal = 0;
 751                         DPAA2_PMD_DEBUG("Enabling CG Tail Drop on queue = %d",
 752                                         rx_queue_id);
 753                         ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
 754                                                 DPNI_CP_CONGESTION_GROUP,
 755                                                 DPNI_QUEUE_RX,
 756                                                 dpaa2_q->tc_index,
 757                                                 dpaa2_q->cgid, &taildrop);
 758                 } else {
 759                         /*enabling per rx queue congestion control */
 760                         taildrop.threshold = CONG_THRESHOLD_RX_BYTES_Q;
 761                         taildrop.units = DPNI_CONGESTION_UNIT_BYTES;
 762                         taildrop.oal = CONG_RX_OAL;
 763                         DPAA2_PMD_DEBUG("Enabling Byte based Drop on queue= %d",
 764                                         rx_queue_id);
 765                         ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
 766                                                 DPNI_CP_QUEUE, DPNI_QUEUE_RX,
 767                                                 dpaa2_q->tc_index, flow_id,
 768                                                 &taildrop);
 769                 }
 770                 if (ret) {
 771                         DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
 772                                       ret);
 773                         return -1;
 774                 }
 775         } else { /* Disable tail Drop */
 776                 struct dpni_taildrop taildrop = {0};
 777                 DPAA2_PMD_INFO("Tail drop is disabled on queue");
 778
 779                 taildrop.enable = 0;
 780                 if (dpaa2_q->cgid != 0xff) {
 781                         ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
 782                                         DPNI_CP_CONGESTION_GROUP, DPNI_QUEUE_RX,
 783                                         dpaa2_q->tc_index,
 784                                         dpaa2_q->cgid, &taildrop);
 785                 } else {
 786                         ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
 787                                         DPNI_CP_QUEUE, DPNI_QUEUE_RX,
 788                                         dpaa2_q->tc_index, flow_id, &taildrop);
 789                 }
 790                 if (ret) {
 791                         DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
 792                                       ret);
 793                         return -1;
 794                 }
 795         }
 796
 797         dev->data->rx_queues[rx_queue_id] = dpaa2_q;
 798         return 0;
 799 }
 800
 801 static int
 802 dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev,
 803                          uint16_t tx_queue_id,
 804                          uint16_t nb_tx_desc,
 805                          unsigned int socket_id __rte_unused,
 806                          const struct rte_eth_txconf *tx_conf)
 807 {
 808         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 809         struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)
 810                 priv->tx_vq[tx_queue_id];
 811         struct dpaa2_queue *dpaa2_tx_conf_q = (struct dpaa2_queue *)
 812                 priv->tx_conf_vq[tx_queue_id];
 813         struct fsl_mc_io *dpni = dev->process_private;
 814         struct dpni_queue tx_conf_cfg;
 815         struct dpni_queue tx_flow_cfg;
 816         uint8_t options = 0, flow_id;
 817         struct dpni_queue_id qid;
 818         uint32_t tc_id;
 819         int ret;
 820
 821         PMD_INIT_FUNC_TRACE();
 822
 823         /* Tx deferred start is not supported */
 824         if (tx_conf->tx_deferred_start) {
 825                 DPAA2_PMD_ERR("%p:Tx deferred start not supported",
 826                                 (void *)dev);
 827                 return -EINVAL;
 828         }
 829
 830         dpaa2_q->nb_desc = UINT16_MAX;
 831         dpaa2_q->offloads = tx_conf->offloads;
 832
 833         /* Return if queue already configured */
 834         if (dpaa2_q->flow_id != 0xffff) {
 835                 dev->data->tx_queues[tx_queue_id] = dpaa2_q;
 836                 return 0;
 837         }
 838
 839         memset(&tx_conf_cfg, 0, sizeof(struct dpni_queue));
 840         memset(&tx_flow_cfg, 0, sizeof(struct dpni_queue));
 841
 842         tc_id = tx_queue_id;
 843         flow_id = 0;
 844
 845         ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_TX,
 846                         tc_id, flow_id, options, &tx_flow_cfg);
 847         if (ret) {
 848                 DPAA2_PMD_ERR("Error in setting the tx flow: "
 849                         "tc_id=%d, flow=%d err=%d",
 850                         tc_id, flow_id, ret);
 851                         return -1;
 852         }
 853
 854         dpaa2_q->flow_id = flow_id;
 855
 856         if (tx_queue_id == 0) {
 857                 /*Set tx-conf and error configuration*/
 858                 if (priv->tx_conf_en)
 859                         ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
 860                                                             priv->token,
 861                                                             DPNI_CONF_AFFINE);
 862                 else
 863                         ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
 864                                                             priv->token,
 865                                                             DPNI_CONF_DISABLE);
 866                 if (ret) {
 867                         DPAA2_PMD_ERR("Error in set tx conf mode settings: "
 868                                       "err=%d", ret);
 869                         return -1;
 870                 }
 871         }
 872         dpaa2_q->tc_index = tc_id;
 873
 874         ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
 875                              DPNI_QUEUE_TX, dpaa2_q->tc_index,
 876                              dpaa2_q->flow_id, &tx_flow_cfg, &qid);
 877         if (ret) {
 878                 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
 879                 return -1;
 880         }
 881         dpaa2_q->fqid = qid.fqid;
 882
 883         if (!(priv->flags & DPAA2_TX_CGR_OFF)) {
 884                 struct dpni_congestion_notification_cfg cong_notif_cfg = {0};
 885
 886                 dpaa2_q->nb_desc = nb_tx_desc;
 887
 888                 cong_notif_cfg.units = DPNI_CONGESTION_UNIT_FRAMES;
 889                 cong_notif_cfg.threshold_entry = nb_tx_desc;
 890                 /* Notify that the queue is not congested when the data in
 891                  * the queue is below this thershold.
 892                  */
 893                 cong_notif_cfg.threshold_exit = nb_tx_desc - 24;
 894                 cong_notif_cfg.message_ctx = 0;
 895                 cong_notif_cfg.message_iova =
 896                                 (size_t)DPAA2_VADDR_TO_IOVA(dpaa2_q->cscn);
 897                 cong_notif_cfg.dest_cfg.dest_type = DPNI_DEST_NONE;
 898                 cong_notif_cfg.notification_mode =
 899                                          DPNI_CONG_OPT_WRITE_MEM_ON_ENTER |
 900                                          DPNI_CONG_OPT_WRITE_MEM_ON_EXIT |
 901                                          DPNI_CONG_OPT_COHERENT_WRITE;
 902                 cong_notif_cfg.cg_point = DPNI_CP_QUEUE;
 903
 904                 ret = dpni_set_congestion_notification(dpni, CMD_PRI_LOW,
 905                                                        priv->token,
 906                                                        DPNI_QUEUE_TX,
 907                                                        tc_id,
 908                                                        &cong_notif_cfg);
 909                 if (ret) {
 910                         DPAA2_PMD_ERR(
 911                            "Error in setting tx congestion notification: "
 912                            "err=%d", ret);
 913                         return -ret;
 914                 }
 915         }
 916         dpaa2_q->cb_eqresp_free = dpaa2_dev_free_eqresp_buf;
 917         dev->data->tx_queues[tx_queue_id] = dpaa2_q;
 918
 919         if (priv->tx_conf_en) {
 920                 dpaa2_q->tx_conf_queue = dpaa2_tx_conf_q;
 921                 options = options | DPNI_QUEUE_OPT_USER_CTX;
 922                 tx_conf_cfg.user_context = (size_t)(dpaa2_q);
 923                 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
 924                              DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
 925                              dpaa2_tx_conf_q->flow_id, options, &tx_conf_cfg);
 926                 if (ret) {
 927                         DPAA2_PMD_ERR("Error in setting the tx conf flow: "
 928                               "tc_index=%d, flow=%d err=%d",
 929                               dpaa2_tx_conf_q->tc_index,
 930                               dpaa2_tx_conf_q->flow_id, ret);
 931                         return -1;
 932                 }
 933
 934                 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
 935                              DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
 936                              dpaa2_tx_conf_q->flow_id, &tx_conf_cfg, &qid);
 937                 if (ret) {
 938                         DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
 939                         return -1;
 940                 }
 941                 dpaa2_tx_conf_q->fqid = qid.fqid;
 942         }
 943         return 0;
 944 }
 945
 946 static void
 947 dpaa2_dev_rx_queue_release(void *q __rte_unused)
 948 {
 949         struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)q;
 950         struct dpaa2_dev_priv *priv = dpaa2_q->eth_data->dev_private;
 951         struct fsl_mc_io *dpni =
 952                 (struct fsl_mc_io *)priv->eth_dev->process_private;
 953         uint8_t options = 0;
 954         int ret;
 955         struct dpni_queue cfg;
 956
 957         memset(&cfg, 0, sizeof(struct dpni_queue));
 958         PMD_INIT_FUNC_TRACE();
 959         if (dpaa2_q->cgid != 0xff) {
 960                 options = DPNI_QUEUE_OPT_CLEAR_CGID;
 961                 cfg.cgid = dpaa2_q->cgid;
 962
 963                 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
 964                                      DPNI_QUEUE_RX,
 965                                      dpaa2_q->tc_index, dpaa2_q->flow_id,
 966                                      options, &cfg);
 967                 if (ret)
 968                         DPAA2_PMD_ERR("Unable to clear CGR from q=%u err=%d",
 969                                         dpaa2_q->fqid, ret);
 970                 priv->cgid_in_use[dpaa2_q->cgid] = 0;
 971                 dpaa2_q->cgid = 0xff;
 972         }
 973 }
 974
 975 static void
 976 dpaa2_dev_tx_queue_release(void *q __rte_unused)
 977 {
 978         PMD_INIT_FUNC_TRACE();
 979 }
 980
 981 static uint32_t
 982 dpaa2_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 983 {
 984         int32_t ret;
 985         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 986         struct dpaa2_queue *dpaa2_q;
 987         struct qbman_swp *swp;
 988         struct qbman_fq_query_np_rslt state;
 989         uint32_t frame_cnt = 0;
 990
 991         if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
 992                 ret = dpaa2_affine_qbman_swp();
 993                 if (ret) {
 994                         DPAA2_PMD_ERR(
 995                                 "Failed to allocate IO portal, tid: %d\n",
 996                                 rte_gettid());
 997                         return -EINVAL;
 998                 }
 999         }
1000         swp = DPAA2_PER_LCORE_PORTAL;
1001
1002         dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];
1003
1004         if (qbman_fq_query_state(swp, dpaa2_q->fqid, &state) == 0) {
1005                 frame_cnt = qbman_fq_state_frame_count(&state);
1006                 DPAA2_PMD_DP_DEBUG("RX frame count for q(%d) is %u",
1007                                 rx_queue_id, frame_cnt);
1008         }
1009         return frame_cnt;
1010 }
1011
1012 static const uint32_t *
1013 dpaa2_supported_ptypes_get(struct rte_eth_dev *dev)
1014 {
1015         static const uint32_t ptypes[] = {
1016                 /*todo -= add more types */
1017                 RTE_PTYPE_L2_ETHER,
1018                 RTE_PTYPE_L3_IPV4,
1019                 RTE_PTYPE_L3_IPV4_EXT,
1020                 RTE_PTYPE_L3_IPV6,
1021                 RTE_PTYPE_L3_IPV6_EXT,
1022                 RTE_PTYPE_L4_TCP,
1023                 RTE_PTYPE_L4_UDP,
1024                 RTE_PTYPE_L4_SCTP,
1025                 RTE_PTYPE_L4_ICMP,
1026                 RTE_PTYPE_UNKNOWN
1027         };
1028
1029         if (dev->rx_pkt_burst == dpaa2_dev_prefetch_rx ||
1030                 dev->rx_pkt_burst == dpaa2_dev_rx ||
1031                 dev->rx_pkt_burst == dpaa2_dev_loopback_rx)
1032                 return ptypes;
1033         return NULL;
1034 }
1035
1036 /**
1037  * Dpaa2 link Interrupt handler
1038  *
1039  * @param param
1040  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1041  *
1042  * @return
1043  *  void
1044  */
1045 static void
1046 dpaa2_interrupt_handler(void *param)
1047 {
1048         struct rte_eth_dev *dev = param;
1049         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1050         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1051         int ret;
1052         int irq_index = DPNI_IRQ_INDEX;
1053         unsigned int status = 0, clear = 0;
1054
1055         PMD_INIT_FUNC_TRACE();
1056
1057         if (dpni == NULL) {
1058                 DPAA2_PMD_ERR("dpni is NULL");
1059                 return;
1060         }
1061
1062         ret = dpni_get_irq_status(dpni, CMD_PRI_LOW, priv->token,
1063                                   irq_index, &status);
1064         if (unlikely(ret)) {
1065                 DPAA2_PMD_ERR("Can't get irq status (err %d)", ret);
1066                 clear = 0xffffffff;
1067                 goto out;
1068         }
1069
1070         if (status & DPNI_IRQ_EVENT_LINK_CHANGED) {
1071                 clear = DPNI_IRQ_EVENT_LINK_CHANGED;
1072                 dpaa2_dev_link_update(dev, 0);
1073                 /* calling all the apps registered for link status event */
1074                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1075         }
1076 out:
1077         ret = dpni_clear_irq_status(dpni, CMD_PRI_LOW, priv->token,
1078                                     irq_index, clear);
1079         if (unlikely(ret))
1080                 DPAA2_PMD_ERR("Can't clear irq status (err %d)", ret);
1081 }
1082
1083 static int
1084 dpaa2_eth_setup_irqs(struct rte_eth_dev *dev, int enable)
1085 {
1086         int err = 0;
1087         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1088         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1089         int irq_index = DPNI_IRQ_INDEX;
1090         unsigned int mask = DPNI_IRQ_EVENT_LINK_CHANGED;
1091
1092         PMD_INIT_FUNC_TRACE();
1093
1094         err = dpni_set_irq_mask(dpni, CMD_PRI_LOW, priv->token,
1095                                 irq_index, mask);
1096         if (err < 0) {
1097                 DPAA2_PMD_ERR("Error: dpni_set_irq_mask():%d (%s)", err,
1098                               strerror(-err));
1099                 return err;
1100         }
1101
1102         err = dpni_set_irq_enable(dpni, CMD_PRI_LOW, priv->token,
1103                                   irq_index, enable);
1104         if (err < 0)
1105                 DPAA2_PMD_ERR("Error: dpni_set_irq_enable():%d (%s)", err,
1106                               strerror(-err));
1107
1108         return err;
1109 }
1110
1111 static int
1112 dpaa2_dev_start(struct rte_eth_dev *dev)
1113 {
1114         struct rte_device *rdev = dev->device;
1115         struct rte_dpaa2_device *dpaa2_dev;
1116         struct rte_eth_dev_data *data = dev->data;
1117         struct dpaa2_dev_priv *priv = data->dev_private;
1118         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1119         struct dpni_queue cfg;
1120         struct dpni_error_cfg   err_cfg;
1121         uint16_t qdid;
1122         struct dpni_queue_id qid;
1123         struct dpaa2_queue *dpaa2_q;
1124         int ret, i;
1125         struct rte_intr_handle *intr_handle;
1126
1127         dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device);
1128         intr_handle = &dpaa2_dev->intr_handle;
1129
1130         PMD_INIT_FUNC_TRACE();
1131
1132         ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1133         if (ret) {
1134                 DPAA2_PMD_ERR("Failure in enabling dpni %d device: err=%d",
1135                               priv->hw_id, ret);
1136                 return ret;
1137         }
1138
1139         /* Power up the phy. Needed to make the link go UP */
1140         dpaa2_dev_set_link_up(dev);
1141
1142         ret = dpni_get_qdid(dpni, CMD_PRI_LOW, priv->token,
1143                             DPNI_QUEUE_TX, &qdid);
1144         if (ret) {
1145                 DPAA2_PMD_ERR("Error in getting qdid: err=%d", ret);
1146                 return ret;
1147         }
1148         priv->qdid = qdid;
1149
1150         for (i = 0; i < data->nb_rx_queues; i++) {
1151                 dpaa2_q = (struct dpaa2_queue *)data->rx_queues[i];
1152                 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
1153                                      DPNI_QUEUE_RX, dpaa2_q->tc_index,
1154                                        dpaa2_q->flow_id, &cfg, &qid);
1155                 if (ret) {
1156                         DPAA2_PMD_ERR("Error in getting flow information: "
1157                                       "err=%d", ret);
1158                         return ret;
1159                 }
1160                 dpaa2_q->fqid = qid.fqid;
1161         }
1162
1163         /*checksum errors, send them to normal path and set it in annotation */
1164         err_cfg.errors = DPNI_ERROR_L3CE | DPNI_ERROR_L4CE;
1165         err_cfg.errors |= DPNI_ERROR_PHE;
1166
1167         err_cfg.error_action = DPNI_ERROR_ACTION_CONTINUE;
1168         err_cfg.set_frame_annotation = true;
1169
1170         ret = dpni_set_errors_behavior(dpni, CMD_PRI_LOW,
1171                                        priv->token, &err_cfg);
1172         if (ret) {
1173                 DPAA2_PMD_ERR("Error to dpni_set_errors_behavior: code = %d",
1174                               ret);
1175                 return ret;
1176         }
1177
1178         /* if the interrupts were configured on this devices*/
1179         if (intr_handle && (intr_handle->fd) &&
1180             (dev->data->dev_conf.intr_conf.lsc != 0)) {
1181                 /* Registering LSC interrupt handler */
1182                 rte_intr_callback_register(intr_handle,
1183                                            dpaa2_interrupt_handler,
1184                                            (void *)dev);
1185
1186                 /* enable vfio intr/eventfd mapping
1187                  * Interrupt index 0 is required, so we can not use
1188                  * rte_intr_enable.
1189                  */
1190                 rte_dpaa2_intr_enable(intr_handle, DPNI_IRQ_INDEX);
1191
1192                 /* enable dpni_irqs */
1193                 dpaa2_eth_setup_irqs(dev, 1);
1194         }
1195
1196         /* Change the tx burst function if ordered queues are used */
1197         if (priv->en_ordered)
1198                 dev->tx_pkt_burst = dpaa2_dev_tx_ordered;
1199
1200         return 0;
1201 }
1202
1203 /**
1204  *  This routine disables all traffic on the adapter by issuing a
1205  *  global reset on the MAC.
1206  */
1207 static int
1208 dpaa2_dev_stop(struct rte_eth_dev *dev)
1209 {
1210         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1211         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1212         int ret;
1213         struct rte_eth_link link;
1214         struct rte_intr_handle *intr_handle = dev->intr_handle;
1215
1216         PMD_INIT_FUNC_TRACE();
1217
1218         /* reset interrupt callback  */
1219         if (intr_handle && (intr_handle->fd) &&
1220             (dev->data->dev_conf.intr_conf.lsc != 0)) {
1221                 /*disable dpni irqs */
1222                 dpaa2_eth_setup_irqs(dev, 0);
1223
1224                 /* disable vfio intr before callback unregister */
1225                 rte_dpaa2_intr_disable(intr_handle, DPNI_IRQ_INDEX);
1226
1227                 /* Unregistering LSC interrupt handler */
1228                 rte_intr_callback_unregister(intr_handle,
1229                                              dpaa2_interrupt_handler,
1230                                              (void *)dev);
1231         }
1232
1233         dpaa2_dev_set_link_down(dev);
1234
1235         ret = dpni_disable(dpni, CMD_PRI_LOW, priv->token);
1236         if (ret) {
1237                 DPAA2_PMD_ERR("Failure (ret %d) in disabling dpni %d dev",
1238                               ret, priv->hw_id);
1239                 return ret;
1240         }
1241
1242         /* clear the recorded link status */
1243         memset(&link, 0, sizeof(link));
1244         rte_eth_linkstatus_set(dev, &link);
1245
1246         return 0;
1247 }
1248
1249 static int
1250 dpaa2_dev_close(struct rte_eth_dev *dev)
1251 {
1252         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1253         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1254         int i, ret;
1255         struct rte_eth_link link;
1256
1257         PMD_INIT_FUNC_TRACE();
1258
1259         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1260                 return 0;
1261
1262         if (!dpni) {
1263                 DPAA2_PMD_WARN("Already closed or not started");
1264                 return -1;
1265         }
1266
1267         dpaa2_flow_clean(dev);
1268         /* Clean the device first */
1269         ret = dpni_reset(dpni, CMD_PRI_LOW, priv->token);
1270         if (ret) {
1271                 DPAA2_PMD_ERR("Failure cleaning dpni device: err=%d", ret);
1272                 return -1;
1273         }
1274
1275         memset(&link, 0, sizeof(link));
1276         rte_eth_linkstatus_set(dev, &link);
1277
1278         /* Free private queues memory */
1279         dpaa2_free_rx_tx_queues(dev);
1280         /* Close the device at underlying layer*/
1281         ret = dpni_close(dpni, CMD_PRI_LOW, priv->token);
1282         if (ret) {
1283                 DPAA2_PMD_ERR("Failure closing dpni device with err code %d",
1284                               ret);
1285         }
1286
1287         /* Free the allocated memory for ethernet private data and dpni*/
1288         priv->hw = NULL;
1289         dev->process_private = NULL;
1290         rte_free(dpni);
1291
1292         for (i = 0; i < MAX_TCS; i++)
1293                 rte_free((void *)(size_t)priv->extract.tc_extract_param[i]);
1294
1295         if (priv->extract.qos_extract_param)
1296                 rte_free((void *)(size_t)priv->extract.qos_extract_param);
1297
1298         DPAA2_PMD_INFO("%s: netdev deleted", dev->data->name);
1299         return 0;
1300 }
1301
1302 static int
1303 dpaa2_dev_promiscuous_enable(
1304                 struct rte_eth_dev *dev)
1305 {
1306         int ret;
1307         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1308         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1309
1310         PMD_INIT_FUNC_TRACE();
1311
1312         if (dpni == NULL) {
1313                 DPAA2_PMD_ERR("dpni is NULL");
1314                 return -ENODEV;
1315         }
1316
1317         ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1318         if (ret < 0)
1319                 DPAA2_PMD_ERR("Unable to enable U promisc mode %d", ret);
1320
1321         ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1322         if (ret < 0)
1323                 DPAA2_PMD_ERR("Unable to enable M promisc mode %d", ret);
1324
1325         return ret;
1326 }
1327
1328 static int
1329 dpaa2_dev_promiscuous_disable(
1330                 struct rte_eth_dev *dev)
1331 {
1332         int ret;
1333         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1334         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1335
1336         PMD_INIT_FUNC_TRACE();
1337
1338         if (dpni == NULL) {
1339                 DPAA2_PMD_ERR("dpni is NULL");
1340                 return -ENODEV;
1341         }
1342
1343         ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1344         if (ret < 0)
1345                 DPAA2_PMD_ERR("Unable to disable U promisc mode %d", ret);
1346
1347         if (dev->data->all_multicast == 0) {
1348                 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW,
1349                                                  priv->token, false);
1350                 if (ret < 0)
1351                         DPAA2_PMD_ERR("Unable to disable M promisc mode %d",
1352                                       ret);
1353         }
1354
1355         return ret;
1356 }
1357
1358 static int
1359 dpaa2_dev_allmulticast_enable(
1360                 struct rte_eth_dev *dev)
1361 {
1362         int ret;
1363         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1364         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1365
1366         PMD_INIT_FUNC_TRACE();
1367
1368         if (dpni == NULL) {
1369                 DPAA2_PMD_ERR("dpni is NULL");
1370                 return -ENODEV;
1371         }
1372
1373         ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1374         if (ret < 0)
1375                 DPAA2_PMD_ERR("Unable to enable multicast mode %d", ret);
1376
1377         return ret;
1378 }
1379
1380 static int
1381 dpaa2_dev_allmulticast_disable(struct rte_eth_dev *dev)
1382 {
1383         int ret;
1384         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1385         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1386
1387         PMD_INIT_FUNC_TRACE();
1388
1389         if (dpni == NULL) {
1390                 DPAA2_PMD_ERR("dpni is NULL");
1391                 return -ENODEV;
1392         }
1393
1394         /* must remain on for all promiscuous */
1395         if (dev->data->promiscuous == 1)
1396                 return 0;
1397
1398         ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1399         if (ret < 0)
1400                 DPAA2_PMD_ERR("Unable to disable multicast mode %d", ret);
1401
1402         return ret;
1403 }
1404
1405 static int
1406 dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1407 {
1408         int ret;
1409         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1410         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1411         uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
1412                                 + VLAN_TAG_SIZE;
1413
1414         PMD_INIT_FUNC_TRACE();
1415
1416         if (dpni == NULL) {
1417                 DPAA2_PMD_ERR("dpni is NULL");
1418                 return -EINVAL;
1419         }
1420
1421         /* check that mtu is within the allowed range */
1422         if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA2_MAX_RX_PKT_LEN)
1423                 return -EINVAL;
1424
1425         if (frame_size > DPAA2_ETH_MAX_LEN)
1426                 dev->data->dev_conf.rxmode.offloads |=
1427                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
1428         else
1429                 dev->data->dev_conf.rxmode.offloads &=
1430                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1431
1432         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1433
1434         /* Set the Max Rx frame length as 'mtu' +
1435          * Maximum Ethernet header length
1436          */
1437         ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, priv->token,
1438                                         frame_size - RTE_ETHER_CRC_LEN);
1439         if (ret) {
1440                 DPAA2_PMD_ERR("Setting the max frame length failed");
1441                 return -1;
1442         }
1443         DPAA2_PMD_INFO("MTU configured for the device: %d", mtu);
1444         return 0;
1445 }
1446
1447 static int
1448 dpaa2_dev_add_mac_addr(struct rte_eth_dev *dev,
1449                        struct rte_ether_addr *addr,
1450                        __rte_unused uint32_t index,
1451                        __rte_unused uint32_t pool)
1452 {
1453         int ret;
1454         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1455         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1456
1457         PMD_INIT_FUNC_TRACE();
1458
1459         if (dpni == NULL) {
1460                 DPAA2_PMD_ERR("dpni is NULL");
1461                 return -1;
1462         }
1463
1464         ret = dpni_add_mac_addr(dpni, CMD_PRI_LOW, priv->token,
1465                                 addr->addr_bytes, 0, 0, 0);
1466         if (ret)
1467                 DPAA2_PMD_ERR(
1468                         "error: Adding the MAC ADDR failed: err = %d", ret);
1469         return 0;
1470 }
1471
1472 static void
1473 dpaa2_dev_remove_mac_addr(struct rte_eth_dev *dev,
1474                           uint32_t index)
1475 {
1476         int ret;
1477         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1478         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1479         struct rte_eth_dev_data *data = dev->data;
1480         struct rte_ether_addr *macaddr;
1481
1482         PMD_INIT_FUNC_TRACE();
1483
1484         macaddr = &data->mac_addrs[index];
1485
1486         if (dpni == NULL) {
1487                 DPAA2_PMD_ERR("dpni is NULL");
1488                 return;
1489         }
1490
1491         ret = dpni_remove_mac_addr(dpni, CMD_PRI_LOW,
1492                                    priv->token, macaddr->addr_bytes);
1493         if (ret)
1494                 DPAA2_PMD_ERR(
1495                         "error: Removing the MAC ADDR failed: err = %d", ret);
1496 }
1497
1498 static int
1499 dpaa2_dev_set_mac_addr(struct rte_eth_dev *dev,
1500                        struct rte_ether_addr *addr)
1501 {
1502         int ret;
1503         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1504         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1505
1506         PMD_INIT_FUNC_TRACE();
1507
1508         if (dpni == NULL) {
1509                 DPAA2_PMD_ERR("dpni is NULL");
1510                 return -EINVAL;
1511         }
1512
1513         ret = dpni_set_primary_mac_addr(dpni, CMD_PRI_LOW,
1514                                         priv->token, addr->addr_bytes);
1515
1516         if (ret)
1517                 DPAA2_PMD_ERR(
1518                         "error: Setting the MAC ADDR failed %d", ret);
1519
1520         return ret;
1521 }
1522
1523 static
1524 int dpaa2_dev_stats_get(struct rte_eth_dev *dev,
1525                          struct rte_eth_stats *stats)
1526 {
1527         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1528         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1529         int32_t  retcode;
1530         uint8_t page0 = 0, page1 = 1, page2 = 2;
1531         union dpni_statistics value;
1532         int i;
1533         struct dpaa2_queue *dpaa2_rxq, *dpaa2_txq;
1534
1535         memset(&value, 0, sizeof(union dpni_statistics));
1536
1537         PMD_INIT_FUNC_TRACE();
1538
1539         if (!dpni) {
1540                 DPAA2_PMD_ERR("dpni is NULL");
1541                 return -EINVAL;
1542         }
1543
1544         if (!stats) {
1545                 DPAA2_PMD_ERR("stats is NULL");
1546                 return -EINVAL;
1547         }
1548
1549         /*Get Counters from page_0*/
1550         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1551                                       page0, 0, &value);
1552         if (retcode)
1553                 goto err;
1554
1555         stats->ipackets = value.page_0.ingress_all_frames;
1556         stats->ibytes = value.page_0.ingress_all_bytes;
1557
1558         /*Get Counters from page_1*/
1559         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1560                                       page1, 0, &value);
1561         if (retcode)
1562                 goto err;
1563
1564         stats->opackets = value.page_1.egress_all_frames;
1565         stats->obytes = value.page_1.egress_all_bytes;
1566
1567         /*Get Counters from page_2*/
1568         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1569                                       page2, 0, &value);
1570         if (retcode)
1571                 goto err;
1572
1573         /* Ingress drop frame count due to configured rules */
1574         stats->ierrors = value.page_2.ingress_filtered_frames;
1575         /* Ingress drop frame count due to error */
1576         stats->ierrors += value.page_2.ingress_discarded_frames;
1577
1578         stats->oerrors = value.page_2.egress_discarded_frames;
1579         stats->imissed = value.page_2.ingress_nobuffer_discards;
1580
1581         /* Fill in per queue stats */
1582         for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) &&
1583                 (i < priv->nb_rx_queues || i < priv->nb_tx_queues); ++i) {
1584                 dpaa2_rxq = (struct dpaa2_queue *)priv->rx_vq[i];
1585                 dpaa2_txq = (struct dpaa2_queue *)priv->tx_vq[i];
1586                 if (dpaa2_rxq)
1587                         stats->q_ipackets[i] = dpaa2_rxq->rx_pkts;
1588                 if (dpaa2_txq)
1589                         stats->q_opackets[i] = dpaa2_txq->tx_pkts;
1590
1591                 /* Byte counting is not implemented */
1592                 stats->q_ibytes[i]   = 0;
1593                 stats->q_obytes[i]   = 0;
1594         }
1595
1596         return 0;
1597
1598 err:
1599         DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1600         return retcode;
1601 };
1602
1603 static int
1604 dpaa2_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1605                      unsigned int n)
1606 {
1607         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1608         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1609         int32_t  retcode;
1610         union dpni_statistics value[5] = {};
1611         unsigned int i = 0, num = RTE_DIM(dpaa2_xstats_strings);
1612
1613         if (n < num)
1614                 return num;
1615
1616         if (xstats == NULL)
1617                 return 0;
1618
1619         /* Get Counters from page_0*/
1620         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1621                                       0, 0, &value[0]);
1622         if (retcode)
1623                 goto err;
1624
1625         /* Get Counters from page_1*/
1626         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1627                                       1, 0, &value[1]);
1628         if (retcode)
1629                 goto err;
1630
1631         /* Get Counters from page_2*/
1632         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1633                                       2, 0, &value[2]);
1634         if (retcode)
1635                 goto err;
1636
1637         for (i = 0; i < priv->max_cgs; i++) {
1638                 if (!priv->cgid_in_use[i]) {
1639                         /* Get Counters from page_4*/
1640                         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW,
1641                                                       priv->token,
1642                                                       4, 0, &value[4]);
1643                         if (retcode)
1644                                 goto err;
1645                         break;
1646                 }
1647         }
1648
1649         for (i = 0; i < num; i++) {
1650                 xstats[i].id = i;
1651                 xstats[i].value = value[dpaa2_xstats_strings[i].page_id].
1652                         raw.counter[dpaa2_xstats_strings[i].stats_id];
1653         }
1654         return i;
1655 err:
1656         DPAA2_PMD_ERR("Error in obtaining extended stats (%d)", retcode);
1657         return retcode;
1658 }
1659
1660 static int
1661 dpaa2_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1662                        struct rte_eth_xstat_name *xstats_names,
1663                        unsigned int limit)
1664 {
1665         unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1666
1667         if (limit < stat_cnt)
1668                 return stat_cnt;
1669
1670         if (xstats_names != NULL)
1671                 for (i = 0; i < stat_cnt; i++)
1672                         strlcpy(xstats_names[i].name,
1673                                 dpaa2_xstats_strings[i].name,
1674                                 sizeof(xstats_names[i].name));
1675
1676         return stat_cnt;
1677 }
1678
1679 static int
1680 dpaa2_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1681                        uint64_t *values, unsigned int n)
1682 {
1683         unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1684         uint64_t values_copy[stat_cnt];
1685
1686         if (!ids) {
1687                 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1688                 struct fsl_mc_io *dpni =
1689                         (struct fsl_mc_io *)dev->process_private;
1690                 int32_t  retcode;
1691                 union dpni_statistics value[5] = {};
1692
1693                 if (n < stat_cnt)
1694                         return stat_cnt;
1695
1696                 if (!values)
1697                         return 0;
1698
1699                 /* Get Counters from page_0*/
1700                 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1701                                               0, 0, &value[0]);
1702                 if (retcode)
1703                         return 0;
1704
1705                 /* Get Counters from page_1*/
1706                 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1707                                               1, 0, &value[1]);
1708                 if (retcode)
1709                         return 0;
1710
1711                 /* Get Counters from page_2*/
1712                 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1713                                               2, 0, &value[2]);
1714                 if (retcode)
1715                         return 0;
1716
1717                 /* Get Counters from page_4*/
1718                 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1719                                               4, 0, &value[4]);
1720                 if (retcode)
1721                         return 0;
1722
1723                 for (i = 0; i < stat_cnt; i++) {
1724                         values[i] = value[dpaa2_xstats_strings[i].page_id].
1725                                 raw.counter[dpaa2_xstats_strings[i].stats_id];
1726                 }
1727                 return stat_cnt;
1728         }
1729
1730         dpaa2_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
1731
1732         for (i = 0; i < n; i++) {
1733                 if (ids[i] >= stat_cnt) {
1734                         DPAA2_PMD_ERR("xstats id value isn't valid");
1735                         return -1;
1736                 }
1737                 values[i] = values_copy[ids[i]];
1738         }
1739         return n;
1740 }
1741
1742 static int
1743 dpaa2_xstats_get_names_by_id(
1744         struct rte_eth_dev *dev,
1745         struct rte_eth_xstat_name *xstats_names,
1746         const uint64_t *ids,
1747         unsigned int limit)
1748 {
1749         unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1750         struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
1751
1752         if (!ids)
1753                 return dpaa2_xstats_get_names(dev, xstats_names, limit);
1754
1755         dpaa2_xstats_get_names(dev, xstats_names_copy, limit);
1756
1757         for (i = 0; i < limit; i++) {
1758                 if (ids[i] >= stat_cnt) {
1759                         DPAA2_PMD_ERR("xstats id value isn't valid");
1760                         return -1;
1761                 }
1762                 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
1763         }
1764         return limit;
1765 }
1766
1767 static int
1768 dpaa2_dev_stats_reset(struct rte_eth_dev *dev)
1769 {
1770         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1771         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1772         int retcode;
1773         int i;
1774         struct dpaa2_queue *dpaa2_q;
1775
1776         PMD_INIT_FUNC_TRACE();
1777
1778         if (dpni == NULL) {
1779                 DPAA2_PMD_ERR("dpni is NULL");
1780                 return -EINVAL;
1781         }
1782
1783         retcode =  dpni_reset_statistics(dpni, CMD_PRI_LOW, priv->token);
1784         if (retcode)
1785                 goto error;
1786
1787         /* Reset the per queue stats in dpaa2_queue structure */
1788         for (i = 0; i < priv->nb_rx_queues; i++) {
1789                 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
1790                 if (dpaa2_q)
1791                         dpaa2_q->rx_pkts = 0;
1792         }
1793
1794         for (i = 0; i < priv->nb_tx_queues; i++) {
1795                 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
1796                 if (dpaa2_q)
1797                         dpaa2_q->tx_pkts = 0;
1798         }
1799
1800         return 0;
1801
1802 error:
1803         DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1804         return retcode;
1805 };
1806
1807 /* return 0 means link status changed, -1 means not changed */
1808 static int
1809 dpaa2_dev_link_update(struct rte_eth_dev *dev,
1810                       int wait_to_complete)
1811 {
1812         int ret;
1813         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1814         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1815         struct rte_eth_link link;
1816         struct dpni_link_state state = {0};
1817         uint8_t count;
1818
1819         if (dpni == NULL) {
1820                 DPAA2_PMD_ERR("dpni is NULL");
1821                 return 0;
1822         }
1823
1824         for (count = 0; count <= MAX_REPEAT_TIME; count++) {
1825                 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token,
1826                                           &state);
1827                 if (ret < 0) {
1828                         DPAA2_PMD_DEBUG("error: dpni_get_link_state %d", ret);
1829                         return -1;
1830                 }
1831                 if (state.up == ETH_LINK_DOWN &&
1832                     wait_to_complete)
1833                         rte_delay_ms(CHECK_INTERVAL);
1834                 else
1835                         break;
1836         }
1837
1838         memset(&link, 0, sizeof(struct rte_eth_link));
1839         link.link_status = state.up;
1840         link.link_speed = state.rate;
1841
1842         if (state.options & DPNI_LINK_OPT_HALF_DUPLEX)
1843                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1844         else
1845                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1846
1847         ret = rte_eth_linkstatus_set(dev, &link);
1848         if (ret == -1)
1849                 DPAA2_PMD_DEBUG("No change in status");
1850         else
1851                 DPAA2_PMD_INFO("Port %d Link is %s\n", dev->data->port_id,
1852                                link.link_status ? "Up" : "Down");
1853
1854         return ret;
1855 }
1856
1857 /**
1858  * Toggle the DPNI to enable, if not already enabled.
1859  * This is not strictly PHY up/down - it is more of logical toggling.
1860  */
1861 static int
1862 dpaa2_dev_set_link_up(struct rte_eth_dev *dev)
1863 {
1864         int ret = -EINVAL;
1865         struct dpaa2_dev_priv *priv;
1866         struct fsl_mc_io *dpni;
1867         int en = 0;
1868         struct dpni_link_state state = {0};
1869
1870         priv = dev->data->dev_private;
1871         dpni = (struct fsl_mc_io *)dev->process_private;
1872
1873         if (dpni == NULL) {
1874                 DPAA2_PMD_ERR("dpni is NULL");
1875                 return ret;
1876         }
1877
1878         /* Check if DPNI is currently enabled */
1879         ret = dpni_is_enabled(dpni, CMD_PRI_LOW, priv->token, &en);
1880         if (ret) {
1881                 /* Unable to obtain dpni status; Not continuing */
1882                 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1883                 return -EINVAL;
1884         }
1885
1886         /* Enable link if not already enabled */
1887         if (!en) {
1888                 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1889                 if (ret) {
1890                         DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1891                         return -EINVAL;
1892                 }
1893         }
1894         ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1895         if (ret < 0) {
1896                 DPAA2_PMD_DEBUG("Unable to get link state (%d)", ret);
1897                 return -1;
1898         }
1899
1900         /* changing tx burst function to start enqueues */
1901         dev->tx_pkt_burst = dpaa2_dev_tx;
1902         dev->data->dev_link.link_status = state.up;
1903         dev->data->dev_link.link_speed = state.rate;
1904
1905         if (state.up)
1906                 DPAA2_PMD_INFO("Port %d Link is Up", dev->data->port_id);
1907         else
1908                 DPAA2_PMD_INFO("Port %d Link is Down", dev->data->port_id);
1909         return ret;
1910 }
1911
1912 /**
1913  * Toggle the DPNI to disable, if not already disabled.
1914  * This is not strictly PHY up/down - it is more of logical toggling.
1915  */
1916 static int
1917 dpaa2_dev_set_link_down(struct rte_eth_dev *dev)
1918 {
1919         int ret = -EINVAL;
1920         struct dpaa2_dev_priv *priv;
1921         struct fsl_mc_io *dpni;
1922         int dpni_enabled = 0;
1923         int retries = 10;
1924
1925         PMD_INIT_FUNC_TRACE();
1926
1927         priv = dev->data->dev_private;
1928         dpni = (struct fsl_mc_io *)dev->process_private;
1929
1930         if (dpni == NULL) {
1931                 DPAA2_PMD_ERR("Device has not yet been configured");
1932                 return ret;
1933         }
1934
1935         /*changing  tx burst function to avoid any more enqueues */
1936         dev->tx_pkt_burst = dummy_dev_tx;
1937
1938         /* Loop while dpni_disable() attempts to drain the egress FQs
1939          * and confirm them back to us.
1940          */
1941         do {
1942                 ret = dpni_disable(dpni, 0, priv->token);
1943                 if (ret) {
1944                         DPAA2_PMD_ERR("dpni disable failed (%d)", ret);
1945                         return ret;
1946                 }
1947                 ret = dpni_is_enabled(dpni, 0, priv->token, &dpni_enabled);
1948                 if (ret) {
1949                         DPAA2_PMD_ERR("dpni enable check failed (%d)", ret);
1950                         return ret;
1951                 }
1952                 if (dpni_enabled)
1953                         /* Allow the MC some slack */
1954                         rte_delay_us(100 * 1000);
1955         } while (dpni_enabled && --retries);
1956
1957         if (!retries) {
1958                 DPAA2_PMD_WARN("Retry count exceeded disabling dpni");
1959                 /* todo- we may have to manually cleanup queues.
1960                  */
1961         } else {
1962                 DPAA2_PMD_INFO("Port %d Link DOWN successful",
1963                                dev->data->port_id);
1964         }
1965
1966         dev->data->dev_link.link_status = 0;
1967
1968         return ret;
1969 }
1970
1971 static int
1972 dpaa2_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1973 {
1974         int ret = -EINVAL;
1975         struct dpaa2_dev_priv *priv;
1976         struct fsl_mc_io *dpni;
1977         struct dpni_link_state state = {0};
1978
1979         PMD_INIT_FUNC_TRACE();
1980
1981         priv = dev->data->dev_private;
1982         dpni = (struct fsl_mc_io *)dev->process_private;
1983
1984         if (dpni == NULL || fc_conf == NULL) {
1985                 DPAA2_PMD_ERR("device not configured");
1986                 return ret;
1987         }
1988
1989         ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1990         if (ret) {
1991                 DPAA2_PMD_ERR("error: dpni_get_link_state %d", ret);
1992                 return ret;
1993         }
1994
1995         memset(fc_conf, 0, sizeof(struct rte_eth_fc_conf));
1996         if (state.options & DPNI_LINK_OPT_PAUSE) {
1997                 /* DPNI_LINK_OPT_PAUSE set
1998                  *  if ASYM_PAUSE not set,
1999                  *      RX Side flow control (handle received Pause frame)
2000                  *      TX side flow control (send Pause frame)
2001                  *  if ASYM_PAUSE set,
2002                  *      RX Side flow control (handle received Pause frame)
2003                  *      No TX side flow control (send Pause frame disabled)
2004                  */
2005                 if (!(state.options & DPNI_LINK_OPT_ASYM_PAUSE))
2006                         fc_conf->mode = RTE_FC_FULL;
2007                 else
2008                         fc_conf->mode = RTE_FC_RX_PAUSE;
2009         } else {
2010                 /* DPNI_LINK_OPT_PAUSE not set
2011                  *  if ASYM_PAUSE set,
2012                  *      TX side flow control (send Pause frame)
2013                  *      No RX side flow control (No action on pause frame rx)
2014                  *  if ASYM_PAUSE not set,
2015                  *      Flow control disabled
2016                  */
2017                 if (state.options & DPNI_LINK_OPT_ASYM_PAUSE)
2018                         fc_conf->mode = RTE_FC_TX_PAUSE;
2019                 else
2020                         fc_conf->mode = RTE_FC_NONE;
2021         }
2022
2023         return ret;
2024 }
2025
2026 static int
2027 dpaa2_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2028 {
2029         int ret = -EINVAL;
2030         struct dpaa2_dev_priv *priv;
2031         struct fsl_mc_io *dpni;
2032         struct dpni_link_state state = {0};
2033         struct dpni_link_cfg cfg = {0};
2034
2035         PMD_INIT_FUNC_TRACE();
2036
2037         priv = dev->data->dev_private;
2038         dpni = (struct fsl_mc_io *)dev->process_private;
2039
2040         if (dpni == NULL) {
2041                 DPAA2_PMD_ERR("dpni is NULL");
2042                 return ret;
2043         }
2044
2045         /* It is necessary to obtain the current state before setting fc_conf
2046          * as MC would return error in case rate, autoneg or duplex values are
2047          * different.
2048          */
2049         ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
2050         if (ret) {
2051                 DPAA2_PMD_ERR("Unable to get link state (err=%d)", ret);
2052                 return -1;
2053         }
2054
2055         /* Disable link before setting configuration */
2056         dpaa2_dev_set_link_down(dev);
2057
2058         /* Based on fc_conf, update cfg */
2059         cfg.rate = state.rate;
2060         cfg.options = state.options;
2061
2062         /* update cfg with fc_conf */
2063         switch (fc_conf->mode) {
2064         case RTE_FC_FULL:
2065                 /* Full flow control;
2066                  * OPT_PAUSE set, ASYM_PAUSE not set
2067                  */
2068                 cfg.options |= DPNI_LINK_OPT_PAUSE;
2069                 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
2070                 break;
2071         case RTE_FC_TX_PAUSE:
2072                 /* Enable RX flow control
2073                  * OPT_PAUSE not set;
2074                  * ASYM_PAUSE set;
2075                  */
2076                 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
2077                 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
2078                 break;
2079         case RTE_FC_RX_PAUSE:
2080                 /* Enable TX Flow control
2081                  * OPT_PAUSE set
2082                  * ASYM_PAUSE set
2083                  */
2084                 cfg.options |= DPNI_LINK_OPT_PAUSE;
2085                 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
2086                 break;
2087         case RTE_FC_NONE:
2088                 /* Disable Flow control
2089                  * OPT_PAUSE not set
2090                  * ASYM_PAUSE not set
2091                  */
2092                 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
2093                 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
2094                 break;
2095         default:
2096                 DPAA2_PMD_ERR("Incorrect Flow control flag (%d)",
2097                               fc_conf->mode);
2098                 return -1;
2099         }
2100
2101         ret = dpni_set_link_cfg(dpni, CMD_PRI_LOW, priv->token, &cfg);
2102         if (ret)
2103                 DPAA2_PMD_ERR("Unable to set Link configuration (err=%d)",
2104                               ret);
2105
2106         /* Enable link */
2107         dpaa2_dev_set_link_up(dev);
2108
2109         return ret;
2110 }
2111
2112 static int
2113 dpaa2_dev_rss_hash_update(struct rte_eth_dev *dev,
2114                           struct rte_eth_rss_conf *rss_conf)
2115 {
2116         struct rte_eth_dev_data *data = dev->data;
2117         struct dpaa2_dev_priv *priv = data->dev_private;
2118         struct rte_eth_conf *eth_conf = &data->dev_conf;
2119         int ret, tc_index;
2120
2121         PMD_INIT_FUNC_TRACE();
2122
2123         if (rss_conf->rss_hf) {
2124                 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
2125                         ret = dpaa2_setup_flow_dist(dev, rss_conf->rss_hf,
2126                                 tc_index);
2127                         if (ret) {
2128                                 DPAA2_PMD_ERR("Unable to set flow dist on tc%d",
2129                                         tc_index);
2130                                 return ret;
2131                         }
2132                 }
2133         } else {
2134                 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
2135                         ret = dpaa2_remove_flow_dist(dev, tc_index);
2136                         if (ret) {
2137                                 DPAA2_PMD_ERR(
2138                                         "Unable to remove flow dist on tc%d",
2139                                         tc_index);
2140                                 return ret;
2141                         }
2142                 }
2143         }
2144         eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf;
2145         return 0;
2146 }
2147
2148 static int
2149 dpaa2_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2150                             struct rte_eth_rss_conf *rss_conf)
2151 {
2152         struct rte_eth_dev_data *data = dev->data;
2153         struct rte_eth_conf *eth_conf = &data->dev_conf;
2154
2155         /* dpaa2 does not support rss_key, so length should be 0*/
2156         rss_conf->rss_key_len = 0;
2157         rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf;
2158         return 0;
2159 }
2160
2161 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev,
2162                 int eth_rx_queue_id,
2163                 struct dpaa2_dpcon_dev *dpcon,
2164                 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
2165 {
2166         struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2167         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2168         struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2169         uint8_t flow_id = dpaa2_ethq->flow_id;
2170         struct dpni_queue cfg;
2171         uint8_t options, priority;
2172         int ret;
2173
2174         if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_PARALLEL)
2175                 dpaa2_ethq->cb = dpaa2_dev_process_parallel_event;
2176         else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC)
2177                 dpaa2_ethq->cb = dpaa2_dev_process_atomic_event;
2178         else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED)
2179                 dpaa2_ethq->cb = dpaa2_dev_process_ordered_event;
2180         else
2181                 return -EINVAL;
2182
2183         priority = (RTE_EVENT_DEV_PRIORITY_LOWEST / queue_conf->ev.priority) *
2184                    (dpcon->num_priorities - 1);
2185
2186         memset(&cfg, 0, sizeof(struct dpni_queue));
2187         options = DPNI_QUEUE_OPT_DEST;
2188         cfg.destination.type = DPNI_DEST_DPCON;
2189         cfg.destination.id = dpcon->dpcon_id;
2190         cfg.destination.priority = priority;
2191
2192         if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) {
2193                 options |= DPNI_QUEUE_OPT_HOLD_ACTIVE;
2194                 cfg.destination.hold_active = 1;
2195         }
2196
2197         if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED &&
2198                         !eth_priv->en_ordered) {
2199                 struct opr_cfg ocfg;
2200
2201                 /* Restoration window size = 256 frames */
2202                 ocfg.oprrws = 3;
2203                 /* Restoration window size = 512 frames for LX2 */
2204                 if (dpaa2_svr_family == SVR_LX2160A)
2205                         ocfg.oprrws = 4;
2206                 /* Auto advance NESN window enabled */
2207                 ocfg.oa = 1;
2208                 /* Late arrival window size disabled */
2209                 ocfg.olws = 0;
2210                 /* ORL resource exhaustaion advance NESN disabled */
2211                 ocfg.oeane = 0;
2212                 /* Loose ordering enabled */
2213                 ocfg.oloe = 1;
2214                 eth_priv->en_loose_ordered = 1;
2215                 /* Strict ordering enabled if explicitly set */
2216                 if (getenv("DPAA2_STRICT_ORDERING_ENABLE")) {
2217                         ocfg.oloe = 0;
2218                         eth_priv->en_loose_ordered = 0;
2219                 }
2220
2221                 ret = dpni_set_opr(dpni, CMD_PRI_LOW, eth_priv->token,
2222                                    dpaa2_ethq->tc_index, flow_id,
2223                                    OPR_OPT_CREATE, &ocfg);
2224                 if (ret) {
2225                         DPAA2_PMD_ERR("Error setting opr: ret: %d\n", ret);
2226                         return ret;
2227                 }
2228
2229                 eth_priv->en_ordered = 1;
2230         }
2231
2232         options |= DPNI_QUEUE_OPT_USER_CTX;
2233         cfg.user_context = (size_t)(dpaa2_ethq);
2234
2235         ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2236                              dpaa2_ethq->tc_index, flow_id, options, &cfg);
2237         if (ret) {
2238                 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2239                 return ret;
2240         }
2241
2242         memcpy(&dpaa2_ethq->ev, &queue_conf->ev, sizeof(struct rte_event));
2243
2244         return 0;
2245 }
2246
2247 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev,
2248                 int eth_rx_queue_id)
2249 {
2250         struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2251         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2252         struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2253         uint8_t flow_id = dpaa2_ethq->flow_id;
2254         struct dpni_queue cfg;
2255         uint8_t options;
2256         int ret;
2257
2258         memset(&cfg, 0, sizeof(struct dpni_queue));
2259         options = DPNI_QUEUE_OPT_DEST;
2260         cfg.destination.type = DPNI_DEST_NONE;
2261
2262         ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2263                              dpaa2_ethq->tc_index, flow_id, options, &cfg);
2264         if (ret)
2265                 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2266
2267         return ret;
2268 }
2269
2270 static inline int
2271 dpaa2_dev_verify_filter_ops(enum rte_filter_op filter_op)
2272 {
2273         unsigned int i;
2274
2275         for (i = 0; i < RTE_DIM(dpaa2_supported_filter_ops); i++) {
2276                 if (dpaa2_supported_filter_ops[i] == filter_op)
2277                         return 0;
2278         }
2279         return -ENOTSUP;
2280 }
2281
2282 static int
2283 dpaa2_dev_flow_ctrl(struct rte_eth_dev *dev,
2284                     enum rte_filter_type filter_type,
2285                                  enum rte_filter_op filter_op,
2286                                  void *arg)
2287 {
2288         int ret = 0;
2289
2290         if (!dev)
2291                 return -ENODEV;
2292
2293         switch (filter_type) {
2294         case RTE_ETH_FILTER_GENERIC:
2295                 if (dpaa2_dev_verify_filter_ops(filter_op) < 0) {
2296                         ret = -ENOTSUP;
2297                         break;
2298                 }
2299                 *(const void **)arg = &dpaa2_flow_ops;
2300                 dpaa2_filter_type |= filter_type;
2301                 break;
2302         default:
2303                 RTE_LOG(ERR, PMD, "Filter type (%d) not supported",
2304                         filter_type);
2305                 ret = -ENOTSUP;
2306                 break;
2307         }
2308         return ret;
2309 }
2310
2311 static void
2312 dpaa2_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2313         struct rte_eth_rxq_info *qinfo)
2314 {
2315         struct dpaa2_queue *rxq;
2316
2317         rxq = (struct dpaa2_queue *)dev->data->rx_queues[queue_id];
2318
2319         qinfo->mp = rxq->mb_pool;
2320         qinfo->scattered_rx = dev->data->scattered_rx;
2321         qinfo->nb_desc = rxq->nb_desc;
2322
2323         qinfo->conf.rx_free_thresh = 1;
2324         qinfo->conf.rx_drop_en = 1;
2325         qinfo->conf.rx_deferred_start = 0;
2326         qinfo->conf.offloads = rxq->offloads;
2327 }
2328
2329 static void
2330 dpaa2_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2331         struct rte_eth_txq_info *qinfo)
2332 {
2333         struct dpaa2_queue *txq;
2334
2335         txq = dev->data->tx_queues[queue_id];
2336
2337         qinfo->nb_desc = txq->nb_desc;
2338         qinfo->conf.tx_thresh.pthresh = 0;
2339         qinfo->conf.tx_thresh.hthresh = 0;
2340         qinfo->conf.tx_thresh.wthresh = 0;
2341
2342         qinfo->conf.tx_free_thresh = 0;
2343         qinfo->conf.tx_rs_thresh = 0;
2344         qinfo->conf.offloads = txq->offloads;
2345         qinfo->conf.tx_deferred_start = 0;
2346 }
2347
2348 static struct eth_dev_ops dpaa2_ethdev_ops = {
2349         .dev_configure    = dpaa2_eth_dev_configure,
2350         .dev_start            = dpaa2_dev_start,
2351         .dev_stop             = dpaa2_dev_stop,
2352         .dev_close            = dpaa2_dev_close,
2353         .promiscuous_enable   = dpaa2_dev_promiscuous_enable,
2354         .promiscuous_disable  = dpaa2_dev_promiscuous_disable,
2355         .allmulticast_enable  = dpaa2_dev_allmulticast_enable,
2356         .allmulticast_disable = dpaa2_dev_allmulticast_disable,
2357         .dev_set_link_up      = dpaa2_dev_set_link_up,
2358         .dev_set_link_down    = dpaa2_dev_set_link_down,
2359         .link_update       = dpaa2_dev_link_update,
2360         .stats_get             = dpaa2_dev_stats_get,
2361         .xstats_get            = dpaa2_dev_xstats_get,
2362         .xstats_get_by_id     = dpaa2_xstats_get_by_id,
2363         .xstats_get_names_by_id = dpaa2_xstats_get_names_by_id,
2364         .xstats_get_names      = dpaa2_xstats_get_names,
2365         .stats_reset       = dpaa2_dev_stats_reset,
2366         .xstats_reset         = dpaa2_dev_stats_reset,
2367         .fw_version_get    = dpaa2_fw_version_get,
2368         .dev_infos_get     = dpaa2_dev_info_get,
2369         .dev_supported_ptypes_get = dpaa2_supported_ptypes_get,
2370         .mtu_set           = dpaa2_dev_mtu_set,
2371         .vlan_filter_set      = dpaa2_vlan_filter_set,
2372         .vlan_offload_set     = dpaa2_vlan_offload_set,
2373         .vlan_tpid_set        = dpaa2_vlan_tpid_set,
2374         .rx_queue_setup    = dpaa2_dev_rx_queue_setup,
2375         .rx_queue_release  = dpaa2_dev_rx_queue_release,
2376         .tx_queue_setup    = dpaa2_dev_tx_queue_setup,
2377         .tx_queue_release  = dpaa2_dev_tx_queue_release,
2378         .rx_burst_mode_get = dpaa2_dev_rx_burst_mode_get,
2379         .tx_burst_mode_get = dpaa2_dev_tx_burst_mode_get,
2380         .flow_ctrl_get        = dpaa2_flow_ctrl_get,
2381         .flow_ctrl_set        = dpaa2_flow_ctrl_set,
2382         .mac_addr_add         = dpaa2_dev_add_mac_addr,
2383         .mac_addr_remove      = dpaa2_dev_remove_mac_addr,
2384         .mac_addr_set         = dpaa2_dev_set_mac_addr,
2385         .rss_hash_update      = dpaa2_dev_rss_hash_update,
2386         .rss_hash_conf_get    = dpaa2_dev_rss_hash_conf_get,
2387         .filter_ctrl          = dpaa2_dev_flow_ctrl,
2388         .rxq_info_get         = dpaa2_rxq_info_get,
2389         .txq_info_get         = dpaa2_txq_info_get,
2390 #if defined(RTE_LIBRTE_IEEE1588)
2391         .timesync_enable      = dpaa2_timesync_enable,
2392         .timesync_disable     = dpaa2_timesync_disable,
2393         .timesync_read_time   = dpaa2_timesync_read_time,
2394         .timesync_write_time  = dpaa2_timesync_write_time,
2395         .timesync_adjust_time = dpaa2_timesync_adjust_time,
2396         .timesync_read_rx_timestamp = dpaa2_timesync_read_rx_timestamp,
2397         .timesync_read_tx_timestamp = dpaa2_timesync_read_tx_timestamp,
2398 #endif
2399 };
2400
2401 /* Populate the mac address from physically available (u-boot/firmware) and/or
2402  * one set by higher layers like MC (restool) etc.
2403  * Returns the table of MAC entries (multiple entries)
2404  */
2405 static int
2406 populate_mac_addr(struct fsl_mc_io *dpni_dev, struct dpaa2_dev_priv *priv,
2407                   struct rte_ether_addr *mac_entry)
2408 {
2409         int ret;
2410         struct rte_ether_addr phy_mac, prime_mac;
2411
2412         memset(&phy_mac, 0, sizeof(struct rte_ether_addr));
2413         memset(&prime_mac, 0, sizeof(struct rte_ether_addr));
2414
2415         /* Get the physical device MAC address */
2416         ret = dpni_get_port_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2417                                      phy_mac.addr_bytes);
2418         if (ret) {
2419                 DPAA2_PMD_ERR("DPNI get physical port MAC failed: %d", ret);
2420                 goto cleanup;
2421         }
2422
2423         ret = dpni_get_primary_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2424                                         prime_mac.addr_bytes);
2425         if (ret) {
2426                 DPAA2_PMD_ERR("DPNI get Prime port MAC failed: %d", ret);
2427                 goto cleanup;
2428         }
2429
2430         /* Now that both MAC have been obtained, do:
2431          *  if not_empty_mac(phy) && phy != Prime, overwrite prime with Phy
2432          *     and return phy
2433          *  If empty_mac(phy), return prime.
2434          *  if both are empty, create random MAC, set as prime and return
2435          */
2436         if (!rte_is_zero_ether_addr(&phy_mac)) {
2437                 /* If the addresses are not same, overwrite prime */
2438                 if (!rte_is_same_ether_addr(&phy_mac, &prime_mac)) {
2439                         ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2440                                                         priv->token,
2441                                                         phy_mac.addr_bytes);
2442                         if (ret) {
2443                                 DPAA2_PMD_ERR("Unable to set MAC Address: %d",
2444                                               ret);
2445                                 goto cleanup;
2446                         }
2447                         memcpy(&prime_mac, &phy_mac,
2448                                 sizeof(struct rte_ether_addr));
2449                 }
2450         } else if (rte_is_zero_ether_addr(&prime_mac)) {
2451                 /* In case phys and prime, both are zero, create random MAC */
2452                 rte_eth_random_addr(prime_mac.addr_bytes);
2453                 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2454                                                 priv->token,
2455                                                 prime_mac.addr_bytes);
2456                 if (ret) {
2457                         DPAA2_PMD_ERR("Unable to set MAC Address: %d", ret);
2458                         goto cleanup;
2459                 }
2460         }
2461
2462         /* prime_mac the final MAC address */
2463         memcpy(mac_entry, &prime_mac, sizeof(struct rte_ether_addr));
2464         return 0;
2465
2466 cleanup:
2467         return -1;
2468 }
2469
2470 static int
2471 check_devargs_handler(__rte_unused const char *key, const char *value,
2472                       __rte_unused void *opaque)
2473 {
2474         if (strcmp(value, "1"))
2475                 return -1;
2476
2477         return 0;
2478 }
2479
2480 static int
2481 dpaa2_get_devargs(struct rte_devargs *devargs, const char *key)
2482 {
2483         struct rte_kvargs *kvlist;
2484
2485         if (!devargs)
2486                 return 0;
2487
2488         kvlist = rte_kvargs_parse(devargs->args, NULL);
2489         if (!kvlist)
2490                 return 0;
2491
2492         if (!rte_kvargs_count(kvlist, key)) {
2493                 rte_kvargs_free(kvlist);
2494                 return 0;
2495         }
2496
2497         if (rte_kvargs_process(kvlist, key,
2498                                check_devargs_handler, NULL) < 0) {
2499                 rte_kvargs_free(kvlist);
2500                 return 0;
2501         }
2502         rte_kvargs_free(kvlist);
2503
2504         return 1;
2505 }
2506
2507 static int
2508 dpaa2_dev_init(struct rte_eth_dev *eth_dev)
2509 {
2510         struct rte_device *dev = eth_dev->device;
2511         struct rte_dpaa2_device *dpaa2_dev;
2512         struct fsl_mc_io *dpni_dev;
2513         struct dpni_attr attr;
2514         struct dpaa2_dev_priv *priv = eth_dev->data->dev_private;
2515         struct dpni_buffer_layout layout;
2516         int ret, hw_id, i;
2517
2518         PMD_INIT_FUNC_TRACE();
2519
2520         dpni_dev = rte_malloc(NULL, sizeof(struct fsl_mc_io), 0);
2521         if (!dpni_dev) {
2522                 DPAA2_PMD_ERR("Memory allocation failed for dpni device");
2523                 return -1;
2524         }
2525         dpni_dev->regs = dpaa2_get_mcp_ptr(MC_PORTAL_INDEX);
2526         eth_dev->process_private = (void *)dpni_dev;
2527
2528         /* For secondary processes, the primary has done all the work */
2529         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2530                 /* In case of secondary, only burst and ops API need to be
2531                  * plugged.
2532                  */
2533                 eth_dev->dev_ops = &dpaa2_ethdev_ops;
2534                 eth_dev->rx_queue_count = dpaa2_dev_rx_queue_count;
2535                 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE))
2536                         eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2537                 else if (dpaa2_get_devargs(dev->devargs,
2538                                         DRIVER_NO_PREFETCH_MODE))
2539                         eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2540                 else
2541                         eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2542                 eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2543                 return 0;
2544         }
2545
2546         dpaa2_dev = container_of(dev, struct rte_dpaa2_device, device);
2547
2548         hw_id = dpaa2_dev->object_id;
2549         ret = dpni_open(dpni_dev, CMD_PRI_LOW, hw_id, &priv->token);
2550         if (ret) {
2551                 DPAA2_PMD_ERR(
2552                              "Failure in opening dpni@%d with err code %d",
2553                              hw_id, ret);
2554                 rte_free(dpni_dev);
2555                 return -1;
2556         }
2557
2558         /* Clean the device first */
2559         ret = dpni_reset(dpni_dev, CMD_PRI_LOW, priv->token);
2560         if (ret) {
2561                 DPAA2_PMD_ERR("Failure cleaning dpni@%d with err code %d",
2562                               hw_id, ret);
2563                 goto init_err;
2564         }
2565
2566         ret = dpni_get_attributes(dpni_dev, CMD_PRI_LOW, priv->token, &attr);
2567         if (ret) {
2568                 DPAA2_PMD_ERR(
2569                              "Failure in get dpni@%d attribute, err code %d",
2570                              hw_id, ret);
2571                 goto init_err;
2572         }
2573
2574         priv->num_rx_tc = attr.num_rx_tcs;
2575         priv->qos_entries = attr.qos_entries;
2576         priv->fs_entries = attr.fs_entries;
2577         priv->dist_queues = attr.num_queues;
2578
2579         /* only if the custom CG is enabled */
2580         if (attr.options & DPNI_OPT_CUSTOM_CG)
2581                 priv->max_cgs = attr.num_cgs;
2582         else
2583                 priv->max_cgs = 0;
2584
2585         for (i = 0; i < priv->max_cgs; i++)
2586                 priv->cgid_in_use[i] = 0;
2587
2588         for (i = 0; i < attr.num_rx_tcs; i++)
2589                 priv->nb_rx_queues += attr.num_queues;
2590
2591         /* Using number of TX queues as number of TX TCs */
2592         priv->nb_tx_queues = attr.num_tx_tcs;
2593
2594         DPAA2_PMD_DEBUG("RX-TC= %d, rx_queues= %d, tx_queues=%d, max_cgs=%d",
2595                         priv->num_rx_tc, priv->nb_rx_queues,
2596                         priv->nb_tx_queues, priv->max_cgs);
2597
2598         priv->hw = dpni_dev;
2599         priv->hw_id = hw_id;
2600         priv->options = attr.options;
2601         priv->max_mac_filters = attr.mac_filter_entries;
2602         priv->max_vlan_filters = attr.vlan_filter_entries;
2603         priv->flags = 0;
2604 #if defined(RTE_LIBRTE_IEEE1588)
2605         priv->tx_conf_en = 1;
2606 #else
2607         priv->tx_conf_en = 0;
2608 #endif
2609
2610         /* Allocate memory for hardware structure for queues */
2611         ret = dpaa2_alloc_rx_tx_queues(eth_dev);
2612         if (ret) {
2613                 DPAA2_PMD_ERR("Queue allocation Failed");
2614                 goto init_err;
2615         }
2616
2617         /* Allocate memory for storing MAC addresses.
2618          * Table of mac_filter_entries size is allocated so that RTE ether lib
2619          * can add MAC entries when rte_eth_dev_mac_addr_add is called.
2620          */
2621         eth_dev->data->mac_addrs = rte_zmalloc("dpni",
2622                 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries, 0);
2623         if (eth_dev->data->mac_addrs == NULL) {
2624                 DPAA2_PMD_ERR(
2625                    "Failed to allocate %d bytes needed to store MAC addresses",
2626                    RTE_ETHER_ADDR_LEN * attr.mac_filter_entries);
2627                 ret = -ENOMEM;
2628                 goto init_err;
2629         }
2630
2631         ret = populate_mac_addr(dpni_dev, priv, &eth_dev->data->mac_addrs[0]);
2632         if (ret) {
2633                 DPAA2_PMD_ERR("Unable to fetch MAC Address for device");
2634                 rte_free(eth_dev->data->mac_addrs);
2635                 eth_dev->data->mac_addrs = NULL;
2636                 goto init_err;
2637         }
2638
2639         /* ... tx buffer layout ... */
2640         memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2641         if (priv->tx_conf_en) {
2642                 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
2643                                  DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2644                 layout.pass_timestamp = true;
2645         } else {
2646                 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2647         }
2648         layout.pass_frame_status = 1;
2649         ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2650                                      DPNI_QUEUE_TX, &layout);
2651         if (ret) {
2652                 DPAA2_PMD_ERR("Error (%d) in setting tx buffer layout", ret);
2653                 goto init_err;
2654         }
2655
2656         /* ... tx-conf and error buffer layout ... */
2657         memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2658         if (priv->tx_conf_en) {
2659                 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
2660                                  DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2661                 layout.pass_timestamp = true;
2662         } else {
2663                 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2664         }
2665         layout.pass_frame_status = 1;
2666         ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2667                                      DPNI_QUEUE_TX_CONFIRM, &layout);
2668         if (ret) {
2669                 DPAA2_PMD_ERR("Error (%d) in setting tx-conf buffer layout",
2670                              ret);
2671                 goto init_err;
2672         }
2673
2674         eth_dev->dev_ops = &dpaa2_ethdev_ops;
2675
2676         if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE)) {
2677                 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2678                 DPAA2_PMD_INFO("Loopback mode");
2679         } else if (dpaa2_get_devargs(dev->devargs, DRIVER_NO_PREFETCH_MODE)) {
2680                 eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2681                 DPAA2_PMD_INFO("No Prefetch mode");
2682         } else {
2683                 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2684         }
2685         eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2686
2687         /*Init fields w.r.t. classficaition*/
2688         memset(&priv->extract.qos_key_extract, 0,
2689                 sizeof(struct dpaa2_key_extract));
2690         priv->extract.qos_extract_param = (size_t)rte_malloc(NULL, 256, 64);
2691         if (!priv->extract.qos_extract_param) {
2692                 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow "
2693                             " classificaiton ", ret);
2694                 goto init_err;
2695         }
2696         priv->extract.qos_key_extract.key_info.ipv4_src_offset =
2697                 IP_ADDRESS_OFFSET_INVALID;
2698         priv->extract.qos_key_extract.key_info.ipv4_dst_offset =
2699                 IP_ADDRESS_OFFSET_INVALID;
2700         priv->extract.qos_key_extract.key_info.ipv6_src_offset =
2701                 IP_ADDRESS_OFFSET_INVALID;
2702         priv->extract.qos_key_extract.key_info.ipv6_dst_offset =
2703                 IP_ADDRESS_OFFSET_INVALID;
2704
2705         for (i = 0; i < MAX_TCS; i++) {
2706                 memset(&priv->extract.tc_key_extract[i], 0,
2707                         sizeof(struct dpaa2_key_extract));
2708                 priv->extract.tc_extract_param[i] =
2709                         (size_t)rte_malloc(NULL, 256, 64);
2710                 if (!priv->extract.tc_extract_param[i]) {
2711                         DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow classificaiton",
2712                                      ret);
2713                         goto init_err;
2714                 }
2715                 priv->extract.tc_key_extract[i].key_info.ipv4_src_offset =
2716                         IP_ADDRESS_OFFSET_INVALID;
2717                 priv->extract.tc_key_extract[i].key_info.ipv4_dst_offset =
2718                         IP_ADDRESS_OFFSET_INVALID;
2719                 priv->extract.tc_key_extract[i].key_info.ipv6_src_offset =
2720                         IP_ADDRESS_OFFSET_INVALID;
2721                 priv->extract.tc_key_extract[i].key_info.ipv6_dst_offset =
2722                         IP_ADDRESS_OFFSET_INVALID;
2723         }
2724
2725         ret = dpni_set_max_frame_length(dpni_dev, CMD_PRI_LOW, priv->token,
2726                                         RTE_ETHER_MAX_LEN - RTE_ETHER_CRC_LEN
2727                                         + VLAN_TAG_SIZE);
2728         if (ret) {
2729                 DPAA2_PMD_ERR("Unable to set mtu. check config");
2730                 goto init_err;
2731         }
2732
2733         /*TODO To enable soft parser support DPAA2 driver needs to integrate
2734          * with external entity to receive byte code for software sequence
2735          * and same will be offload to the H/W using MC interface.
2736          * Currently it is assumed that DPAA2 driver has byte code by some
2737          * mean and same if offloaded to H/W.
2738          */
2739         if (getenv("DPAA2_ENABLE_SOFT_PARSER")) {
2740                 WRIOP_SS_INITIALIZER(priv);
2741                 ret = dpaa2_eth_load_wriop_soft_parser(priv, DPNI_SS_INGRESS);
2742                 if (ret < 0) {
2743                         DPAA2_PMD_ERR(" Error(%d) in loading softparser\n",
2744                                       ret);
2745                         return ret;
2746                 }
2747
2748                 ret = dpaa2_eth_enable_wriop_soft_parser(priv,
2749                                                          DPNI_SS_INGRESS);
2750                 if (ret < 0) {
2751                         DPAA2_PMD_ERR(" Error(%d) in enabling softparser\n",
2752                                       ret);
2753                         return ret;
2754                 }
2755         }
2756         RTE_LOG(INFO, PMD, "%s: netdev created\n", eth_dev->data->name);
2757         return 0;
2758 init_err:
2759         dpaa2_dev_close(eth_dev);
2760
2761         return ret;
2762 }
2763
2764 static int
2765 rte_dpaa2_probe(struct rte_dpaa2_driver *dpaa2_drv,
2766                 struct rte_dpaa2_device *dpaa2_dev)
2767 {
2768         struct rte_eth_dev *eth_dev;
2769         struct dpaa2_dev_priv *dev_priv;
2770         int diag;
2771
2772         if ((DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE) >
2773                 RTE_PKTMBUF_HEADROOM) {
2774                 DPAA2_PMD_ERR(
2775                 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA2 Annotation req(%d)",
2776                 RTE_PKTMBUF_HEADROOM,
2777                 DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE);
2778
2779                 return -1;
2780         }
2781
2782         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2783                 eth_dev = rte_eth_dev_allocate(dpaa2_dev->device.name);
2784                 if (!eth_dev)
2785                         return -ENODEV;
2786                 dev_priv = rte_zmalloc("ethdev private structure",
2787                                        sizeof(struct dpaa2_dev_priv),
2788                                        RTE_CACHE_LINE_SIZE);
2789                 if (dev_priv == NULL) {
2790                         DPAA2_PMD_CRIT(
2791                                 "Unable to allocate memory for private data");
2792                         rte_eth_dev_release_port(eth_dev);
2793                         return -ENOMEM;
2794                 }
2795                 eth_dev->data->dev_private = (void *)dev_priv;
2796                 /* Store a pointer to eth_dev in dev_private */
2797                 dev_priv->eth_dev = eth_dev;
2798                 dev_priv->tx_conf_en = 0;
2799         } else {
2800                 eth_dev = rte_eth_dev_attach_secondary(dpaa2_dev->device.name);
2801                 if (!eth_dev) {
2802                         DPAA2_PMD_DEBUG("returning enodev");
2803                         return -ENODEV;
2804                 }
2805         }
2806
2807         eth_dev->device = &dpaa2_dev->device;
2808
2809         dpaa2_dev->eth_dev = eth_dev;
2810         eth_dev->data->rx_mbuf_alloc_failed = 0;
2811
2812         if (dpaa2_drv->drv_flags & RTE_DPAA2_DRV_INTR_LSC)
2813                 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;
2814
2815         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2816
2817         /* Invoke PMD device initialization function */
2818         diag = dpaa2_dev_init(eth_dev);
2819         if (diag == 0) {
2820                 rte_eth_dev_probing_finish(eth_dev);
2821                 return 0;
2822         }
2823
2824         rte_eth_dev_release_port(eth_dev);
2825         return diag;
2826 }
2827
2828 static int
2829 rte_dpaa2_remove(struct rte_dpaa2_device *dpaa2_dev)
2830 {
2831         struct rte_eth_dev *eth_dev;
2832         int ret;
2833
2834         eth_dev = dpaa2_dev->eth_dev;
2835         dpaa2_dev_close(eth_dev);
2836         ret = rte_eth_dev_release_port(eth_dev);
2837
2838         return ret;
2839 }
2840
2841 static struct rte_dpaa2_driver rte_dpaa2_pmd = {
2842         .drv_flags = RTE_DPAA2_DRV_INTR_LSC | RTE_DPAA2_DRV_IOVA_AS_VA,
2843         .drv_type = DPAA2_ETH,
2844         .probe = rte_dpaa2_probe,
2845         .remove = rte_dpaa2_remove,
2846 };
2847
2848 RTE_PMD_REGISTER_DPAA2(net_dpaa2, rte_dpaa2_pmd);
2849 RTE_PMD_REGISTER_PARAM_STRING(net_dpaa2,
2850                 DRIVER_LOOPBACK_MODE "=<int> "
2851                 DRIVER_NO_PREFETCH_MODE "=<int>");
2852 RTE_LOG_REGISTER(dpaa2_logtype_pmd, pmd.net.dpaa2, NOTICE);