drivers/net/dpaa2/dpaa2_ethdev.c

   1 /* * SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  *   Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
   4  *   Copyright 2016-2020 NXP
   5  *
   6  */
   7
   8 #include <time.h>
   9 #include <net/if.h>
  10
  11 #include <rte_mbuf.h>
  12 #include <rte_ethdev_driver.h>
  13 #include <rte_malloc.h>
  14 #include <rte_memcpy.h>
  15 #include <rte_string_fns.h>
  16 #include <rte_cycles.h>
  17 #include <rte_kvargs.h>
  18 #include <rte_dev.h>
  19 #include <rte_fslmc.h>
  20 #include <rte_flow_driver.h>
  21
  22 #include "dpaa2_pmd_logs.h"
  23 #include <fslmc_vfio.h>
  24 #include <dpaa2_hw_pvt.h>
  25 #include <dpaa2_hw_mempool.h>
  26 #include <dpaa2_hw_dpio.h>
  27 #include <mc/fsl_dpmng.h>
  28 #include "dpaa2_ethdev.h"
  29 #include "dpaa2_sparser.h"
  30 #include <fsl_qbman_debug.h>
  31
  32 #define DRIVER_LOOPBACK_MODE "drv_loopback"
  33 #define DRIVER_NO_PREFETCH_MODE "drv_no_prefetch"
  34
  35 /* Supported Rx offloads */
  36 static uint64_t dev_rx_offloads_sup =
  37                 DEV_RX_OFFLOAD_CHECKSUM |
  38                 DEV_RX_OFFLOAD_SCTP_CKSUM |
  39                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
  40                 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
  41                 DEV_RX_OFFLOAD_VLAN_STRIP |
  42                 DEV_RX_OFFLOAD_VLAN_FILTER |
  43                 DEV_RX_OFFLOAD_JUMBO_FRAME |
  44                 DEV_RX_OFFLOAD_TIMESTAMP;
  45
  46 /* Rx offloads which cannot be disabled */
  47 static uint64_t dev_rx_offloads_nodis =
  48                 DEV_RX_OFFLOAD_RSS_HASH |
  49                 DEV_RX_OFFLOAD_SCATTER;
  50
  51 /* Supported Tx offloads */
  52 static uint64_t dev_tx_offloads_sup =
  53                 DEV_TX_OFFLOAD_VLAN_INSERT |
  54                 DEV_TX_OFFLOAD_IPV4_CKSUM |
  55                 DEV_TX_OFFLOAD_UDP_CKSUM |
  56                 DEV_TX_OFFLOAD_TCP_CKSUM |
  57                 DEV_TX_OFFLOAD_SCTP_CKSUM |
  58                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
  59                 DEV_TX_OFFLOAD_MT_LOCKFREE |
  60                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
  61
  62 /* Tx offloads which cannot be disabled */
  63 static uint64_t dev_tx_offloads_nodis =
  64                 DEV_TX_OFFLOAD_MULTI_SEGS;
  65
  66 /* enable timestamp in mbuf */
  67 bool dpaa2_enable_ts[RTE_MAX_ETHPORTS];
  68
  69 struct rte_dpaa2_xstats_name_off {
  70         char name[RTE_ETH_XSTATS_NAME_SIZE];
  71         uint8_t page_id; /* dpni statistics page id */
  72         uint8_t stats_id; /* stats id in the given page */
  73 };
  74
  75 static const struct rte_dpaa2_xstats_name_off dpaa2_xstats_strings[] = {
  76         {"ingress_multicast_frames", 0, 2},
  77         {"ingress_multicast_bytes", 0, 3},
  78         {"ingress_broadcast_frames", 0, 4},
  79         {"ingress_broadcast_bytes", 0, 5},
  80         {"egress_multicast_frames", 1, 2},
  81         {"egress_multicast_bytes", 1, 3},
  82         {"egress_broadcast_frames", 1, 4},
  83         {"egress_broadcast_bytes", 1, 5},
  84         {"ingress_filtered_frames", 2, 0},
  85         {"ingress_discarded_frames", 2, 1},
  86         {"ingress_nobuffer_discards", 2, 2},
  87         {"egress_discarded_frames", 2, 3},
  88         {"egress_confirmed_frames", 2, 4},
  89         {"cgr_reject_frames", 4, 0},
  90         {"cgr_reject_bytes", 4, 1},
  91 };
  92
  93 static const enum rte_filter_op dpaa2_supported_filter_ops[] = {
  94         RTE_ETH_FILTER_ADD,
  95         RTE_ETH_FILTER_DELETE,
  96         RTE_ETH_FILTER_UPDATE,
  97         RTE_ETH_FILTER_FLUSH,
  98         RTE_ETH_FILTER_GET
  99 };
 100
 101 static struct rte_dpaa2_driver rte_dpaa2_pmd;
 102 static int dpaa2_dev_uninit(struct rte_eth_dev *eth_dev);
 103 static int dpaa2_dev_link_update(struct rte_eth_dev *dev,
 104                                  int wait_to_complete);
 105 static int dpaa2_dev_set_link_up(struct rte_eth_dev *dev);
 106 static int dpaa2_dev_set_link_down(struct rte_eth_dev *dev);
 107 static int dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 108
 109 static int
 110 dpaa2_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 111 {
 112         int ret;
 113         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 114         struct fsl_mc_io *dpni = dev->process_private;
 115
 116         PMD_INIT_FUNC_TRACE();
 117
 118         if (dpni == NULL) {
 119                 DPAA2_PMD_ERR("dpni is NULL");
 120                 return -1;
 121         }
 122
 123         if (on)
 124                 ret = dpni_add_vlan_id(dpni, CMD_PRI_LOW, priv->token,
 125                                        vlan_id, 0, 0, 0);
 126         else
 127                 ret = dpni_remove_vlan_id(dpni, CMD_PRI_LOW,
 128                                           priv->token, vlan_id);
 129
 130         if (ret < 0)
 131                 DPAA2_PMD_ERR("ret = %d Unable to add/rem vlan %d hwid =%d",
 132                               ret, vlan_id, priv->hw_id);
 133
 134         return ret;
 135 }
 136
 137 static int
 138 dpaa2_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 139 {
 140         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 141         struct fsl_mc_io *dpni = dev->process_private;
 142         int ret = 0;
 143
 144         PMD_INIT_FUNC_TRACE();
 145
 146         if (mask & ETH_VLAN_FILTER_MASK) {
 147                 /* VLAN Filter not avaialble */
 148                 if (!priv->max_vlan_filters) {
 149                         DPAA2_PMD_INFO("VLAN filter not available");
 150                         return -ENOTSUP;
 151                 }
 152
 153                 if (dev->data->dev_conf.rxmode.offloads &
 154                         DEV_RX_OFFLOAD_VLAN_FILTER)
 155                         ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
 156                                                       priv->token, true);
 157                 else
 158                         ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
 159                                                       priv->token, false);
 160                 if (ret < 0)
 161                         DPAA2_PMD_INFO("Unable to set vlan filter = %d", ret);
 162         }
 163
 164         return ret;
 165 }
 166
 167 static int
 168 dpaa2_vlan_tpid_set(struct rte_eth_dev *dev,
 169                       enum rte_vlan_type vlan_type __rte_unused,
 170                       uint16_t tpid)
 171 {
 172         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 173         struct fsl_mc_io *dpni = dev->process_private;
 174         int ret = -ENOTSUP;
 175
 176         PMD_INIT_FUNC_TRACE();
 177
 178         /* nothing to be done for standard vlan tpids */
 179         if (tpid == 0x8100 || tpid == 0x88A8)
 180                 return 0;
 181
 182         ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
 183                                    priv->token, tpid);
 184         if (ret < 0)
 185                 DPAA2_PMD_INFO("Unable to set vlan tpid = %d", ret);
 186         /* if already configured tpids, remove them first */
 187         if (ret == -EBUSY) {
 188                 struct dpni_custom_tpid_cfg tpid_list = {0};
 189
 190                 ret = dpni_get_custom_tpid(dpni, CMD_PRI_LOW,
 191                                    priv->token, &tpid_list);
 192                 if (ret < 0)
 193                         goto fail;
 194                 ret = dpni_remove_custom_tpid(dpni, CMD_PRI_LOW,
 195                                    priv->token, tpid_list.tpid1);
 196                 if (ret < 0)
 197                         goto fail;
 198                 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
 199                                            priv->token, tpid);
 200         }
 201 fail:
 202         return ret;
 203 }
 204
 205 static int
 206 dpaa2_fw_version_get(struct rte_eth_dev *dev,
 207                      char *fw_version,
 208                      size_t fw_size)
 209 {
 210         int ret;
 211         struct fsl_mc_io *dpni = dev->process_private;
 212         struct mc_soc_version mc_plat_info = {0};
 213         struct mc_version mc_ver_info = {0};
 214
 215         PMD_INIT_FUNC_TRACE();
 216
 217         if (mc_get_soc_version(dpni, CMD_PRI_LOW, &mc_plat_info))
 218                 DPAA2_PMD_WARN("\tmc_get_soc_version failed");
 219
 220         if (mc_get_version(dpni, CMD_PRI_LOW, &mc_ver_info))
 221                 DPAA2_PMD_WARN("\tmc_get_version failed");
 222
 223         ret = snprintf(fw_version, fw_size,
 224                        "%x-%d.%d.%d",
 225                        mc_plat_info.svr,
 226                        mc_ver_info.major,
 227                        mc_ver_info.minor,
 228                        mc_ver_info.revision);
 229
 230         ret += 1; /* add the size of '\0' */
 231         if (fw_size < (uint32_t)ret)
 232                 return ret;
 233         else
 234                 return 0;
 235 }
 236
 237 static int
 238 dpaa2_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
 239 {
 240         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 241
 242         PMD_INIT_FUNC_TRACE();
 243
 244         dev_info->if_index = priv->hw_id;
 245
 246         dev_info->max_mac_addrs = priv->max_mac_filters;
 247         dev_info->max_rx_pktlen = DPAA2_MAX_RX_PKT_LEN;
 248         dev_info->min_rx_bufsize = DPAA2_MIN_RX_BUF_SIZE;
 249         dev_info->max_rx_queues = (uint16_t)priv->nb_rx_queues;
 250         dev_info->max_tx_queues = (uint16_t)priv->nb_tx_queues;
 251         dev_info->rx_offload_capa = dev_rx_offloads_sup |
 252                                         dev_rx_offloads_nodis;
 253         dev_info->tx_offload_capa = dev_tx_offloads_sup |
 254                                         dev_tx_offloads_nodis;
 255         dev_info->speed_capa = ETH_LINK_SPEED_1G |
 256                         ETH_LINK_SPEED_2_5G |
 257                         ETH_LINK_SPEED_10G;
 258
 259         dev_info->max_hash_mac_addrs = 0;
 260         dev_info->max_vfs = 0;
 261         dev_info->max_vmdq_pools = ETH_16_POOLS;
 262         dev_info->flow_type_rss_offloads = DPAA2_RSS_OFFLOAD_ALL;
 263
 264         dev_info->default_rxportconf.burst_size = dpaa2_dqrr_size;
 265         /* same is rx size for best perf */
 266         dev_info->default_txportconf.burst_size = dpaa2_dqrr_size;
 267
 268         dev_info->default_rxportconf.nb_queues = 1;
 269         dev_info->default_txportconf.nb_queues = 1;
 270         dev_info->default_txportconf.ring_size = CONG_ENTER_TX_THRESHOLD;
 271         dev_info->default_rxportconf.ring_size = DPAA2_RX_DEFAULT_NBDESC;
 272
 273         if (dpaa2_svr_family == SVR_LX2160A) {
 274                 dev_info->speed_capa |= ETH_LINK_SPEED_25G |
 275                                 ETH_LINK_SPEED_40G |
 276                                 ETH_LINK_SPEED_50G |
 277                                 ETH_LINK_SPEED_100G;
 278         }
 279
 280         return 0;
 281 }
 282
 283 static int
 284 dpaa2_dev_rx_burst_mode_get(struct rte_eth_dev *dev,
 285                         __rte_unused uint16_t queue_id,
 286                         struct rte_eth_burst_mode *mode)
 287 {
 288         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 289         int ret = -EINVAL;
 290         unsigned int i;
 291         const struct burst_info {
 292                 uint64_t flags;
 293                 const char *output;
 294         } rx_offload_map[] = {
 295                         {DEV_RX_OFFLOAD_CHECKSUM, " Checksum,"},
 296                         {DEV_RX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
 297                         {DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
 298                         {DEV_RX_OFFLOAD_OUTER_UDP_CKSUM, " Outer UDP csum,"},
 299                         {DEV_RX_OFFLOAD_VLAN_STRIP, " VLAN strip,"},
 300                         {DEV_RX_OFFLOAD_VLAN_FILTER, " VLAN filter,"},
 301                         {DEV_RX_OFFLOAD_JUMBO_FRAME, " Jumbo frame,"},
 302                         {DEV_RX_OFFLOAD_TIMESTAMP, " Timestamp,"},
 303                         {DEV_RX_OFFLOAD_RSS_HASH, " RSS,"},
 304                         {DEV_RX_OFFLOAD_SCATTER, " Scattered,"}
 305         };
 306
 307         /* Update Rx offload info */
 308         for (i = 0; i < RTE_DIM(rx_offload_map); i++) {
 309                 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) {
 310                         snprintf(mode->info, sizeof(mode->info), "%s",
 311                                 rx_offload_map[i].output);
 312                         ret = 0;
 313                         break;
 314                 }
 315         }
 316         return ret;
 317 }
 318
 319 static int
 320 dpaa2_dev_tx_burst_mode_get(struct rte_eth_dev *dev,
 321                         __rte_unused uint16_t queue_id,
 322                         struct rte_eth_burst_mode *mode)
 323 {
 324         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 325         int ret = -EINVAL;
 326         unsigned int i;
 327         const struct burst_info {
 328                 uint64_t flags;
 329                 const char *output;
 330         } tx_offload_map[] = {
 331                         {DEV_TX_OFFLOAD_VLAN_INSERT, " VLAN Insert,"},
 332                         {DEV_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"},
 333                         {DEV_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"},
 334                         {DEV_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"},
 335                         {DEV_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
 336                         {DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
 337                         {DEV_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"},
 338                         {DEV_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"},
 339                         {DEV_TX_OFFLOAD_MULTI_SEGS, " Scattered,"}
 340         };
 341
 342         /* Update Tx offload info */
 343         for (i = 0; i < RTE_DIM(tx_offload_map); i++) {
 344                 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) {
 345                         snprintf(mode->info, sizeof(mode->info), "%s",
 346                                 tx_offload_map[i].output);
 347                         ret = 0;
 348                         break;
 349                 }
 350         }
 351         return ret;
 352 }
 353
 354 static int
 355 dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev)
 356 {
 357         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 358         uint16_t dist_idx;
 359         uint32_t vq_id;
 360         uint8_t num_rxqueue_per_tc;
 361         struct dpaa2_queue *mc_q, *mcq;
 362         uint32_t tot_queues;
 363         int i;
 364         struct dpaa2_queue *dpaa2_q;
 365
 366         PMD_INIT_FUNC_TRACE();
 367
 368         num_rxqueue_per_tc = (priv->nb_rx_queues / priv->num_rx_tc);
 369         if (priv->tx_conf_en)
 370                 tot_queues = priv->nb_rx_queues + 2 * priv->nb_tx_queues;
 371         else
 372                 tot_queues = priv->nb_rx_queues + priv->nb_tx_queues;
 373         mc_q = rte_malloc(NULL, sizeof(struct dpaa2_queue) * tot_queues,
 374                           RTE_CACHE_LINE_SIZE);
 375         if (!mc_q) {
 376                 DPAA2_PMD_ERR("Memory allocation failed for rx/tx queues");
 377                 return -1;
 378         }
 379
 380         for (i = 0; i < priv->nb_rx_queues; i++) {
 381                 mc_q->eth_data = dev->data;
 382                 priv->rx_vq[i] = mc_q++;
 383                 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
 384                 dpaa2_q->q_storage = rte_malloc("dq_storage",
 385                                         sizeof(struct queue_storage_info_t),
 386                                         RTE_CACHE_LINE_SIZE);
 387                 if (!dpaa2_q->q_storage)
 388                         goto fail;
 389
 390                 memset(dpaa2_q->q_storage, 0,
 391                        sizeof(struct queue_storage_info_t));
 392                 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
 393                         goto fail;
 394         }
 395
 396         for (i = 0; i < priv->nb_tx_queues; i++) {
 397                 mc_q->eth_data = dev->data;
 398                 mc_q->flow_id = 0xffff;
 399                 priv->tx_vq[i] = mc_q++;
 400                 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
 401                 dpaa2_q->cscn = rte_malloc(NULL,
 402                                            sizeof(struct qbman_result), 16);
 403                 if (!dpaa2_q->cscn)
 404                         goto fail_tx;
 405         }
 406
 407         if (priv->tx_conf_en) {
 408                 /*Setup tx confirmation queues*/
 409                 for (i = 0; i < priv->nb_tx_queues; i++) {
 410                         mc_q->eth_data = dev->data;
 411                         mc_q->tc_index = i;
 412                         mc_q->flow_id = 0;
 413                         priv->tx_conf_vq[i] = mc_q++;
 414                         dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
 415                         dpaa2_q->q_storage =
 416                                 rte_malloc("dq_storage",
 417                                         sizeof(struct queue_storage_info_t),
 418                                         RTE_CACHE_LINE_SIZE);
 419                         if (!dpaa2_q->q_storage)
 420                                 goto fail_tx_conf;
 421
 422                         memset(dpaa2_q->q_storage, 0,
 423                                sizeof(struct queue_storage_info_t));
 424                         if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
 425                                 goto fail_tx_conf;
 426                 }
 427         }
 428
 429         vq_id = 0;
 430         for (dist_idx = 0; dist_idx < priv->nb_rx_queues; dist_idx++) {
 431                 mcq = (struct dpaa2_queue *)priv->rx_vq[vq_id];
 432                 mcq->tc_index = dist_idx / num_rxqueue_per_tc;
 433                 mcq->flow_id = dist_idx % num_rxqueue_per_tc;
 434                 vq_id++;
 435         }
 436
 437         return 0;
 438 fail_tx_conf:
 439         i -= 1;
 440         while (i >= 0) {
 441                 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
 442                 rte_free(dpaa2_q->q_storage);
 443                 priv->tx_conf_vq[i--] = NULL;
 444         }
 445         i = priv->nb_tx_queues;
 446 fail_tx:
 447         i -= 1;
 448         while (i >= 0) {
 449                 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
 450                 rte_free(dpaa2_q->cscn);
 451                 priv->tx_vq[i--] = NULL;
 452         }
 453         i = priv->nb_rx_queues;
 454 fail:
 455         i -= 1;
 456         mc_q = priv->rx_vq[0];
 457         while (i >= 0) {
 458                 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
 459                 dpaa2_free_dq_storage(dpaa2_q->q_storage);
 460                 rte_free(dpaa2_q->q_storage);
 461                 priv->rx_vq[i--] = NULL;
 462         }
 463         rte_free(mc_q);
 464         return -1;
 465 }
 466
 467 static void
 468 dpaa2_free_rx_tx_queues(struct rte_eth_dev *dev)
 469 {
 470         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 471         struct dpaa2_queue *dpaa2_q;
 472         int i;
 473
 474         PMD_INIT_FUNC_TRACE();
 475
 476         /* Queue allocation base */
 477         if (priv->rx_vq[0]) {
 478                 /* cleaning up queue storage */
 479                 for (i = 0; i < priv->nb_rx_queues; i++) {
 480                         dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
 481                         if (dpaa2_q->q_storage)
 482                                 rte_free(dpaa2_q->q_storage);
 483                 }
 484                 /* cleanup tx queue cscn */
 485                 for (i = 0; i < priv->nb_tx_queues; i++) {
 486                         dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
 487                         rte_free(dpaa2_q->cscn);
 488                 }
 489                 if (priv->tx_conf_en) {
 490                         /* cleanup tx conf queue storage */
 491                         for (i = 0; i < priv->nb_tx_queues; i++) {
 492                                 dpaa2_q = (struct dpaa2_queue *)
 493                                                 priv->tx_conf_vq[i];
 494                                 rte_free(dpaa2_q->q_storage);
 495                         }
 496                 }
 497                 /*free memory for all queues (RX+TX) */
 498                 rte_free(priv->rx_vq[0]);
 499                 priv->rx_vq[0] = NULL;
 500         }
 501 }
 502
 503 static int
 504 dpaa2_eth_dev_configure(struct rte_eth_dev *dev)
 505 {
 506         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 507         struct fsl_mc_io *dpni = dev->process_private;
 508         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 509         uint64_t rx_offloads = eth_conf->rxmode.offloads;
 510         uint64_t tx_offloads = eth_conf->txmode.offloads;
 511         int rx_l3_csum_offload = false;
 512         int rx_l4_csum_offload = false;
 513         int tx_l3_csum_offload = false;
 514         int tx_l4_csum_offload = false;
 515         int ret, tc_index;
 516
 517         PMD_INIT_FUNC_TRACE();
 518
 519         /* Rx offloads which are enabled by default */
 520         if (dev_rx_offloads_nodis & ~rx_offloads) {
 521                 DPAA2_PMD_INFO(
 522                 "Some of rx offloads enabled by default - requested 0x%" PRIx64
 523                 " fixed are 0x%" PRIx64,
 524                 rx_offloads, dev_rx_offloads_nodis);
 525         }
 526
 527         /* Tx offloads which are enabled by default */
 528         if (dev_tx_offloads_nodis & ~tx_offloads) {
 529                 DPAA2_PMD_INFO(
 530                 "Some of tx offloads enabled by default - requested 0x%" PRIx64
 531                 " fixed are 0x%" PRIx64,
 532                 tx_offloads, dev_tx_offloads_nodis);
 533         }
 534
 535         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 536                 if (eth_conf->rxmode.max_rx_pkt_len <= DPAA2_MAX_RX_PKT_LEN) {
 537                         ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW,
 538                                 priv->token, eth_conf->rxmode.max_rx_pkt_len
 539                                 - RTE_ETHER_CRC_LEN);
 540                         if (ret) {
 541                                 DPAA2_PMD_ERR(
 542                                         "Unable to set mtu. check config");
 543                                 return ret;
 544                         }
 545                         dev->data->mtu =
 546                                 dev->data->dev_conf.rxmode.max_rx_pkt_len -
 547                                 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN -
 548                                 VLAN_TAG_SIZE;
 549                 } else {
 550                         return -1;
 551                 }
 552         }
 553
 554         if (eth_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) {
 555                 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
 556                         ret = dpaa2_setup_flow_dist(dev,
 557                                         eth_conf->rx_adv_conf.rss_conf.rss_hf,
 558                                         tc_index);
 559                         if (ret) {
 560                                 DPAA2_PMD_ERR(
 561                                         "Unable to set flow distribution on tc%d."
 562                                         "Check queue config", tc_index);
 563                                 return ret;
 564                         }
 565                 }
 566         }
 567
 568         if (rx_offloads & DEV_RX_OFFLOAD_IPV4_CKSUM)
 569                 rx_l3_csum_offload = true;
 570
 571         if ((rx_offloads & DEV_RX_OFFLOAD_UDP_CKSUM) ||
 572                 (rx_offloads & DEV_RX_OFFLOAD_TCP_CKSUM) ||
 573                 (rx_offloads & DEV_RX_OFFLOAD_SCTP_CKSUM))
 574                 rx_l4_csum_offload = true;
 575
 576         ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 577                                DPNI_OFF_RX_L3_CSUM, rx_l3_csum_offload);
 578         if (ret) {
 579                 DPAA2_PMD_ERR("Error to set RX l3 csum:Error = %d", ret);
 580                 return ret;
 581         }
 582
 583         ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 584                                DPNI_OFF_RX_L4_CSUM, rx_l4_csum_offload);
 585         if (ret) {
 586                 DPAA2_PMD_ERR("Error to get RX l4 csum:Error = %d", ret);
 587                 return ret;
 588         }
 589
 590 #if !defined(RTE_LIBRTE_IEEE1588)
 591         if (rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP)
 592 #endif
 593                 dpaa2_enable_ts[dev->data->port_id] = true;
 594
 595         if (tx_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)
 596                 tx_l3_csum_offload = true;
 597
 598         if ((tx_offloads & DEV_TX_OFFLOAD_UDP_CKSUM) ||
 599                 (tx_offloads & DEV_TX_OFFLOAD_TCP_CKSUM) ||
 600                 (tx_offloads & DEV_TX_OFFLOAD_SCTP_CKSUM))
 601                 tx_l4_csum_offload = true;
 602
 603         ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 604                                DPNI_OFF_TX_L3_CSUM, tx_l3_csum_offload);
 605         if (ret) {
 606                 DPAA2_PMD_ERR("Error to set TX l3 csum:Error = %d", ret);
 607                 return ret;
 608         }
 609
 610         ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 611                                DPNI_OFF_TX_L4_CSUM, tx_l4_csum_offload);
 612         if (ret) {
 613                 DPAA2_PMD_ERR("Error to get TX l4 csum:Error = %d", ret);
 614                 return ret;
 615         }
 616
 617         /* Enabling hash results in FD requires setting DPNI_FLCTYPE_HASH in
 618          * dpni_set_offload API. Setting this FLCTYPE for DPNI sets the FD[SC]
 619          * to 0 for LS2 in the hardware thus disabling data/annotation
 620          * stashing. For LX2 this is fixed in hardware and thus hash result and
 621          * parse results can be received in FD using this option.
 622          */
 623         if (dpaa2_svr_family == SVR_LX2160A) {
 624                 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 625                                        DPNI_FLCTYPE_HASH, true);
 626                 if (ret) {
 627                         DPAA2_PMD_ERR("Error setting FLCTYPE: Err = %d", ret);
 628                         return ret;
 629                 }
 630         }
 631
 632         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 633                 dpaa2_vlan_offload_set(dev, ETH_VLAN_FILTER_MASK);
 634
 635         return 0;
 636 }
 637
 638 /* Function to setup RX flow information. It contains traffic class ID,
 639  * flow ID, destination configuration etc.
 640  */
 641 static int
 642 dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev,
 643                          uint16_t rx_queue_id,
 644                          uint16_t nb_rx_desc,
 645                          unsigned int socket_id __rte_unused,
 646                          const struct rte_eth_rxconf *rx_conf,
 647                          struct rte_mempool *mb_pool)
 648 {
 649         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 650         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
 651         struct dpaa2_queue *dpaa2_q;
 652         struct dpni_queue cfg;
 653         uint8_t options = 0;
 654         uint8_t flow_id;
 655         uint32_t bpid;
 656         int i, ret;
 657
 658         PMD_INIT_FUNC_TRACE();
 659
 660         DPAA2_PMD_DEBUG("dev =%p, queue =%d, pool = %p, conf =%p",
 661                         dev, rx_queue_id, mb_pool, rx_conf);
 662
 663         /* Rx deferred start is not supported */
 664         if (rx_conf->rx_deferred_start) {
 665                 DPAA2_PMD_ERR("%p:Rx deferred start not supported",
 666                                 (void *)dev);
 667                 return -EINVAL;
 668         }
 669
 670         if (!priv->bp_list || priv->bp_list->mp != mb_pool) {
 671                 bpid = mempool_to_bpid(mb_pool);
 672                 ret = dpaa2_attach_bp_list(priv,
 673                                            rte_dpaa2_bpid_info[bpid].bp_list);
 674                 if (ret)
 675                         return ret;
 676         }
 677         dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];
 678         dpaa2_q->mb_pool = mb_pool; /**< mbuf pool to populate RX ring. */
 679         dpaa2_q->bp_array = rte_dpaa2_bpid_info;
 680
 681         /*Get the flow id from given VQ id*/
 682         flow_id = dpaa2_q->flow_id;
 683         memset(&cfg, 0, sizeof(struct dpni_queue));
 684
 685         options = options | DPNI_QUEUE_OPT_USER_CTX;
 686         cfg.user_context = (size_t)(dpaa2_q);
 687
 688         /* check if a private cgr available. */
 689         for (i = 0; i < priv->max_cgs; i++) {
 690                 if (!priv->cgid_in_use[i]) {
 691                         priv->cgid_in_use[i] = 1;
 692                         break;
 693                 }
 694         }
 695
 696         if (i < priv->max_cgs) {
 697                 options |= DPNI_QUEUE_OPT_SET_CGID;
 698                 cfg.cgid = i;
 699                 dpaa2_q->cgid = cfg.cgid;
 700         } else {
 701                 dpaa2_q->cgid = 0xff;
 702         }
 703
 704         /*if ls2088 or rev2 device, enable the stashing */
 705
 706         if ((dpaa2_svr_family & 0xffff0000) != SVR_LS2080A) {
 707                 options |= DPNI_QUEUE_OPT_FLC;
 708                 cfg.flc.stash_control = true;
 709                 cfg.flc.value &= 0xFFFFFFFFFFFFFFC0;
 710                 /* 00 00 00 - last 6 bit represent annotation, context stashing,
 711                  * data stashing setting 01 01 00 (0x14)
 712                  * (in following order ->DS AS CS)
 713                  * to enable 1 line data, 1 line annotation.
 714                  * For LX2, this setting should be 01 00 00 (0x10)
 715                  */
 716                 if ((dpaa2_svr_family & 0xffff0000) == SVR_LX2160A)
 717                         cfg.flc.value |= 0x10;
 718                 else
 719                         cfg.flc.value |= 0x14;
 720         }
 721         ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_RX,
 722                              dpaa2_q->tc_index, flow_id, options, &cfg);
 723         if (ret) {
 724                 DPAA2_PMD_ERR("Error in setting the rx flow: = %d", ret);
 725                 return -1;
 726         }
 727
 728         if (!(priv->flags & DPAA2_RX_TAILDROP_OFF)) {
 729                 struct dpni_taildrop taildrop;
 730
 731                 taildrop.enable = 1;
 732
 733                 /* Private CGR will use tail drop length as nb_rx_desc.
 734                  * for rest cases we can use standard byte based tail drop.
 735                  * There is no HW restriction, but number of CGRs are limited,
 736                  * hence this restriction is placed.
 737                  */
 738                 if (dpaa2_q->cgid != 0xff) {
 739                         /*enabling per rx queue congestion control */
 740                         taildrop.threshold = nb_rx_desc;
 741                         taildrop.units = DPNI_CONGESTION_UNIT_FRAMES;
 742                         taildrop.oal = 0;
 743                         DPAA2_PMD_DEBUG("Enabling CG Tail Drop on queue = %d",
 744                                         rx_queue_id);
 745                         ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
 746                                                 DPNI_CP_CONGESTION_GROUP,
 747                                                 DPNI_QUEUE_RX,
 748                                                 dpaa2_q->tc_index,
 749                                                 dpaa2_q->cgid, &taildrop);
 750                 } else {
 751                         /*enabling per rx queue congestion control */
 752                         taildrop.threshold = CONG_THRESHOLD_RX_BYTES_Q;
 753                         taildrop.units = DPNI_CONGESTION_UNIT_BYTES;
 754                         taildrop.oal = CONG_RX_OAL;
 755                         DPAA2_PMD_DEBUG("Enabling Byte based Drop on queue= %d",
 756                                         rx_queue_id);
 757                         ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
 758                                                 DPNI_CP_QUEUE, DPNI_QUEUE_RX,
 759                                                 dpaa2_q->tc_index, flow_id,
 760                                                 &taildrop);
 761                 }
 762                 if (ret) {
 763                         DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
 764                                       ret);
 765                         return -1;
 766                 }
 767         } else { /* Disable tail Drop */
 768                 struct dpni_taildrop taildrop = {0};
 769                 DPAA2_PMD_INFO("Tail drop is disabled on queue");
 770
 771                 taildrop.enable = 0;
 772                 if (dpaa2_q->cgid != 0xff) {
 773                         ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
 774                                         DPNI_CP_CONGESTION_GROUP, DPNI_QUEUE_RX,
 775                                         dpaa2_q->tc_index,
 776                                         dpaa2_q->cgid, &taildrop);
 777                 } else {
 778                         ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
 779                                         DPNI_CP_QUEUE, DPNI_QUEUE_RX,
 780                                         dpaa2_q->tc_index, flow_id, &taildrop);
 781                 }
 782                 if (ret) {
 783                         DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
 784                                       ret);
 785                         return -1;
 786                 }
 787         }
 788
 789         dev->data->rx_queues[rx_queue_id] = dpaa2_q;
 790         return 0;
 791 }
 792
 793 static int
 794 dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev,
 795                          uint16_t tx_queue_id,
 796                          uint16_t nb_tx_desc,
 797                          unsigned int socket_id __rte_unused,
 798                          const struct rte_eth_txconf *tx_conf)
 799 {
 800         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 801         struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)
 802                 priv->tx_vq[tx_queue_id];
 803         struct dpaa2_queue *dpaa2_tx_conf_q = (struct dpaa2_queue *)
 804                 priv->tx_conf_vq[tx_queue_id];
 805         struct fsl_mc_io *dpni = dev->process_private;
 806         struct dpni_queue tx_conf_cfg;
 807         struct dpni_queue tx_flow_cfg;
 808         uint8_t options = 0, flow_id;
 809         struct dpni_queue_id qid;
 810         uint32_t tc_id;
 811         int ret;
 812
 813         PMD_INIT_FUNC_TRACE();
 814
 815         /* Tx deferred start is not supported */
 816         if (tx_conf->tx_deferred_start) {
 817                 DPAA2_PMD_ERR("%p:Tx deferred start not supported",
 818                                 (void *)dev);
 819                 return -EINVAL;
 820         }
 821
 822         /* Return if queue already configured */
 823         if (dpaa2_q->flow_id != 0xffff) {
 824                 dev->data->tx_queues[tx_queue_id] = dpaa2_q;
 825                 return 0;
 826         }
 827
 828         memset(&tx_conf_cfg, 0, sizeof(struct dpni_queue));
 829         memset(&tx_flow_cfg, 0, sizeof(struct dpni_queue));
 830
 831         tc_id = tx_queue_id;
 832         flow_id = 0;
 833
 834         ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_TX,
 835                         tc_id, flow_id, options, &tx_flow_cfg);
 836         if (ret) {
 837                 DPAA2_PMD_ERR("Error in setting the tx flow: "
 838                         "tc_id=%d, flow=%d err=%d",
 839                         tc_id, flow_id, ret);
 840                         return -1;
 841         }
 842
 843         dpaa2_q->flow_id = flow_id;
 844
 845         if (tx_queue_id == 0) {
 846                 /*Set tx-conf and error configuration*/
 847                 if (priv->tx_conf_en)
 848                         ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
 849                                                             priv->token,
 850                                                             DPNI_CONF_AFFINE);
 851                 else
 852                         ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
 853                                                             priv->token,
 854                                                             DPNI_CONF_DISABLE);
 855                 if (ret) {
 856                         DPAA2_PMD_ERR("Error in set tx conf mode settings: "
 857                                       "err=%d", ret);
 858                         return -1;
 859                 }
 860         }
 861         dpaa2_q->tc_index = tc_id;
 862
 863         ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
 864                              DPNI_QUEUE_TX, dpaa2_q->tc_index,
 865                              dpaa2_q->flow_id, &tx_flow_cfg, &qid);
 866         if (ret) {
 867                 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
 868                 return -1;
 869         }
 870         dpaa2_q->fqid = qid.fqid;
 871
 872         if (!(priv->flags & DPAA2_TX_CGR_OFF)) {
 873                 struct dpni_congestion_notification_cfg cong_notif_cfg = {0};
 874
 875                 cong_notif_cfg.units = DPNI_CONGESTION_UNIT_FRAMES;
 876                 cong_notif_cfg.threshold_entry = nb_tx_desc;
 877                 /* Notify that the queue is not congested when the data in
 878                  * the queue is below this thershold.
 879                  */
 880                 cong_notif_cfg.threshold_exit = nb_tx_desc - 24;
 881                 cong_notif_cfg.message_ctx = 0;
 882                 cong_notif_cfg.message_iova =
 883                                 (size_t)DPAA2_VADDR_TO_IOVA(dpaa2_q->cscn);
 884                 cong_notif_cfg.dest_cfg.dest_type = DPNI_DEST_NONE;
 885                 cong_notif_cfg.notification_mode =
 886                                          DPNI_CONG_OPT_WRITE_MEM_ON_ENTER |
 887                                          DPNI_CONG_OPT_WRITE_MEM_ON_EXIT |
 888                                          DPNI_CONG_OPT_COHERENT_WRITE;
 889                 cong_notif_cfg.cg_point = DPNI_CP_QUEUE;
 890
 891                 ret = dpni_set_congestion_notification(dpni, CMD_PRI_LOW,
 892                                                        priv->token,
 893                                                        DPNI_QUEUE_TX,
 894                                                        tc_id,
 895                                                        &cong_notif_cfg);
 896                 if (ret) {
 897                         DPAA2_PMD_ERR(
 898                            "Error in setting tx congestion notification: "
 899                            "err=%d", ret);
 900                         return -ret;
 901                 }
 902         }
 903         dpaa2_q->cb_eqresp_free = dpaa2_dev_free_eqresp_buf;
 904         dev->data->tx_queues[tx_queue_id] = dpaa2_q;
 905
 906         if (priv->tx_conf_en) {
 907                 dpaa2_q->tx_conf_queue = dpaa2_tx_conf_q;
 908                 options = options | DPNI_QUEUE_OPT_USER_CTX;
 909                 tx_conf_cfg.user_context = (size_t)(dpaa2_q);
 910                 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
 911                              DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
 912                              dpaa2_tx_conf_q->flow_id, options, &tx_conf_cfg);
 913                 if (ret) {
 914                         DPAA2_PMD_ERR("Error in setting the tx conf flow: "
 915                               "tc_index=%d, flow=%d err=%d",
 916                               dpaa2_tx_conf_q->tc_index,
 917                               dpaa2_tx_conf_q->flow_id, ret);
 918                         return -1;
 919                 }
 920
 921                 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
 922                              DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
 923                              dpaa2_tx_conf_q->flow_id, &tx_conf_cfg, &qid);
 924                 if (ret) {
 925                         DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
 926                         return -1;
 927                 }
 928                 dpaa2_tx_conf_q->fqid = qid.fqid;
 929         }
 930         return 0;
 931 }
 932
 933 static void
 934 dpaa2_dev_rx_queue_release(void *q __rte_unused)
 935 {
 936         struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)q;
 937         struct dpaa2_dev_priv *priv = dpaa2_q->eth_data->dev_private;
 938         struct fsl_mc_io *dpni =
 939                 (struct fsl_mc_io *)priv->eth_dev->process_private;
 940         uint8_t options = 0;
 941         int ret;
 942         struct dpni_queue cfg;
 943
 944         memset(&cfg, 0, sizeof(struct dpni_queue));
 945         PMD_INIT_FUNC_TRACE();
 946         if (dpaa2_q->cgid != 0xff) {
 947                 options = DPNI_QUEUE_OPT_CLEAR_CGID;
 948                 cfg.cgid = dpaa2_q->cgid;
 949
 950                 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
 951                                      DPNI_QUEUE_RX,
 952                                      dpaa2_q->tc_index, dpaa2_q->flow_id,
 953                                      options, &cfg);
 954                 if (ret)
 955                         DPAA2_PMD_ERR("Unable to clear CGR from q=%u err=%d",
 956                                         dpaa2_q->fqid, ret);
 957                 priv->cgid_in_use[dpaa2_q->cgid] = 0;
 958                 dpaa2_q->cgid = 0xff;
 959         }
 960 }
 961
 962 static void
 963 dpaa2_dev_tx_queue_release(void *q __rte_unused)
 964 {
 965         PMD_INIT_FUNC_TRACE();
 966 }
 967
 968 static uint32_t
 969 dpaa2_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 970 {
 971         int32_t ret;
 972         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 973         struct dpaa2_queue *dpaa2_q;
 974         struct qbman_swp *swp;
 975         struct qbman_fq_query_np_rslt state;
 976         uint32_t frame_cnt = 0;
 977
 978         if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
 979                 ret = dpaa2_affine_qbman_swp();
 980                 if (ret) {
 981                         DPAA2_PMD_ERR(
 982                                 "Failed to allocate IO portal, tid: %d\n",
 983                                 rte_gettid());
 984                         return -EINVAL;
 985                 }
 986         }
 987         swp = DPAA2_PER_LCORE_PORTAL;
 988
 989         dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];
 990
 991         if (qbman_fq_query_state(swp, dpaa2_q->fqid, &state) == 0) {
 992                 frame_cnt = qbman_fq_state_frame_count(&state);
 993                 DPAA2_PMD_DP_DEBUG("RX frame count for q(%d) is %u",
 994                                 rx_queue_id, frame_cnt);
 995         }
 996         return frame_cnt;
 997 }
 998
 999 static const uint32_t *
1000 dpaa2_supported_ptypes_get(struct rte_eth_dev *dev)
1001 {
1002         static const uint32_t ptypes[] = {
1003                 /*todo -= add more types */
1004                 RTE_PTYPE_L2_ETHER,
1005                 RTE_PTYPE_L3_IPV4,
1006                 RTE_PTYPE_L3_IPV4_EXT,
1007                 RTE_PTYPE_L3_IPV6,
1008                 RTE_PTYPE_L3_IPV6_EXT,
1009                 RTE_PTYPE_L4_TCP,
1010                 RTE_PTYPE_L4_UDP,
1011                 RTE_PTYPE_L4_SCTP,
1012                 RTE_PTYPE_L4_ICMP,
1013                 RTE_PTYPE_UNKNOWN
1014         };
1015
1016         if (dev->rx_pkt_burst == dpaa2_dev_prefetch_rx ||
1017                 dev->rx_pkt_burst == dpaa2_dev_rx ||
1018                 dev->rx_pkt_burst == dpaa2_dev_loopback_rx)
1019                 return ptypes;
1020         return NULL;
1021 }
1022
1023 /**
1024  * Dpaa2 link Interrupt handler
1025  *
1026  * @param param
1027  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1028  *
1029  * @return
1030  *  void
1031  */
1032 static void
1033 dpaa2_interrupt_handler(void *param)
1034 {
1035         struct rte_eth_dev *dev = param;
1036         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1037         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1038         int ret;
1039         int irq_index = DPNI_IRQ_INDEX;
1040         unsigned int status = 0, clear = 0;
1041
1042         PMD_INIT_FUNC_TRACE();
1043
1044         if (dpni == NULL) {
1045                 DPAA2_PMD_ERR("dpni is NULL");
1046                 return;
1047         }
1048
1049         ret = dpni_get_irq_status(dpni, CMD_PRI_LOW, priv->token,
1050                                   irq_index, &status);
1051         if (unlikely(ret)) {
1052                 DPAA2_PMD_ERR("Can't get irq status (err %d)", ret);
1053                 clear = 0xffffffff;
1054                 goto out;
1055         }
1056
1057         if (status & DPNI_IRQ_EVENT_LINK_CHANGED) {
1058                 clear = DPNI_IRQ_EVENT_LINK_CHANGED;
1059                 dpaa2_dev_link_update(dev, 0);
1060                 /* calling all the apps registered for link status event */
1061                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
1062                                               NULL);
1063         }
1064 out:
1065         ret = dpni_clear_irq_status(dpni, CMD_PRI_LOW, priv->token,
1066                                     irq_index, clear);
1067         if (unlikely(ret))
1068                 DPAA2_PMD_ERR("Can't clear irq status (err %d)", ret);
1069 }
1070
1071 static int
1072 dpaa2_eth_setup_irqs(struct rte_eth_dev *dev, int enable)
1073 {
1074         int err = 0;
1075         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1076         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1077         int irq_index = DPNI_IRQ_INDEX;
1078         unsigned int mask = DPNI_IRQ_EVENT_LINK_CHANGED;
1079
1080         PMD_INIT_FUNC_TRACE();
1081
1082         err = dpni_set_irq_mask(dpni, CMD_PRI_LOW, priv->token,
1083                                 irq_index, mask);
1084         if (err < 0) {
1085                 DPAA2_PMD_ERR("Error: dpni_set_irq_mask():%d (%s)", err,
1086                               strerror(-err));
1087                 return err;
1088         }
1089
1090         err = dpni_set_irq_enable(dpni, CMD_PRI_LOW, priv->token,
1091                                   irq_index, enable);
1092         if (err < 0)
1093                 DPAA2_PMD_ERR("Error: dpni_set_irq_enable():%d (%s)", err,
1094                               strerror(-err));
1095
1096         return err;
1097 }
1098
1099 static int
1100 dpaa2_dev_start(struct rte_eth_dev *dev)
1101 {
1102         struct rte_device *rdev = dev->device;
1103         struct rte_dpaa2_device *dpaa2_dev;
1104         struct rte_eth_dev_data *data = dev->data;
1105         struct dpaa2_dev_priv *priv = data->dev_private;
1106         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1107         struct dpni_queue cfg;
1108         struct dpni_error_cfg   err_cfg;
1109         uint16_t qdid;
1110         struct dpni_queue_id qid;
1111         struct dpaa2_queue *dpaa2_q;
1112         int ret, i;
1113         struct rte_intr_handle *intr_handle;
1114
1115         dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device);
1116         intr_handle = &dpaa2_dev->intr_handle;
1117
1118         PMD_INIT_FUNC_TRACE();
1119
1120         ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1121         if (ret) {
1122                 DPAA2_PMD_ERR("Failure in enabling dpni %d device: err=%d",
1123                               priv->hw_id, ret);
1124                 return ret;
1125         }
1126
1127         /* Power up the phy. Needed to make the link go UP */
1128         dpaa2_dev_set_link_up(dev);
1129
1130         ret = dpni_get_qdid(dpni, CMD_PRI_LOW, priv->token,
1131                             DPNI_QUEUE_TX, &qdid);
1132         if (ret) {
1133                 DPAA2_PMD_ERR("Error in getting qdid: err=%d", ret);
1134                 return ret;
1135         }
1136         priv->qdid = qdid;
1137
1138         for (i = 0; i < data->nb_rx_queues; i++) {
1139                 dpaa2_q = (struct dpaa2_queue *)data->rx_queues[i];
1140                 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
1141                                      DPNI_QUEUE_RX, dpaa2_q->tc_index,
1142                                        dpaa2_q->flow_id, &cfg, &qid);
1143                 if (ret) {
1144                         DPAA2_PMD_ERR("Error in getting flow information: "
1145                                       "err=%d", ret);
1146                         return ret;
1147                 }
1148                 dpaa2_q->fqid = qid.fqid;
1149         }
1150
1151         /*checksum errors, send them to normal path and set it in annotation */
1152         err_cfg.errors = DPNI_ERROR_L3CE | DPNI_ERROR_L4CE;
1153         err_cfg.errors |= DPNI_ERROR_PHE;
1154
1155         err_cfg.error_action = DPNI_ERROR_ACTION_CONTINUE;
1156         err_cfg.set_frame_annotation = true;
1157
1158         ret = dpni_set_errors_behavior(dpni, CMD_PRI_LOW,
1159                                        priv->token, &err_cfg);
1160         if (ret) {
1161                 DPAA2_PMD_ERR("Error to dpni_set_errors_behavior: code = %d",
1162                               ret);
1163                 return ret;
1164         }
1165
1166         /* if the interrupts were configured on this devices*/
1167         if (intr_handle && (intr_handle->fd) &&
1168             (dev->data->dev_conf.intr_conf.lsc != 0)) {
1169                 /* Registering LSC interrupt handler */
1170                 rte_intr_callback_register(intr_handle,
1171                                            dpaa2_interrupt_handler,
1172                                            (void *)dev);
1173
1174                 /* enable vfio intr/eventfd mapping
1175                  * Interrupt index 0 is required, so we can not use
1176                  * rte_intr_enable.
1177                  */
1178                 rte_dpaa2_intr_enable(intr_handle, DPNI_IRQ_INDEX);
1179
1180                 /* enable dpni_irqs */
1181                 dpaa2_eth_setup_irqs(dev, 1);
1182         }
1183
1184         /* Change the tx burst function if ordered queues are used */
1185         if (priv->en_ordered)
1186                 dev->tx_pkt_burst = dpaa2_dev_tx_ordered;
1187
1188         return 0;
1189 }
1190
1191 /**
1192  *  This routine disables all traffic on the adapter by issuing a
1193  *  global reset on the MAC.
1194  */
1195 static void
1196 dpaa2_dev_stop(struct rte_eth_dev *dev)
1197 {
1198         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1199         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1200         int ret;
1201         struct rte_eth_link link;
1202         struct rte_intr_handle *intr_handle = dev->intr_handle;
1203
1204         PMD_INIT_FUNC_TRACE();
1205
1206         /* reset interrupt callback  */
1207         if (intr_handle && (intr_handle->fd) &&
1208             (dev->data->dev_conf.intr_conf.lsc != 0)) {
1209                 /*disable dpni irqs */
1210                 dpaa2_eth_setup_irqs(dev, 0);
1211
1212                 /* disable vfio intr before callback unregister */
1213                 rte_dpaa2_intr_disable(intr_handle, DPNI_IRQ_INDEX);
1214
1215                 /* Unregistering LSC interrupt handler */
1216                 rte_intr_callback_unregister(intr_handle,
1217                                              dpaa2_interrupt_handler,
1218                                              (void *)dev);
1219         }
1220
1221         dpaa2_dev_set_link_down(dev);
1222
1223         ret = dpni_disable(dpni, CMD_PRI_LOW, priv->token);
1224         if (ret) {
1225                 DPAA2_PMD_ERR("Failure (ret %d) in disabling dpni %d dev",
1226                               ret, priv->hw_id);
1227                 return;
1228         }
1229
1230         /* clear the recorded link status */
1231         memset(&link, 0, sizeof(link));
1232         rte_eth_linkstatus_set(dev, &link);
1233 }
1234
1235 static void
1236 dpaa2_dev_close(struct rte_eth_dev *dev)
1237 {
1238         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1239         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1240         int ret;
1241         struct rte_eth_link link;
1242
1243         PMD_INIT_FUNC_TRACE();
1244
1245         dpaa2_flow_clean(dev);
1246
1247         /* Clean the device first */
1248         ret = dpni_reset(dpni, CMD_PRI_LOW, priv->token);
1249         if (ret) {
1250                 DPAA2_PMD_ERR("Failure cleaning dpni device: err=%d", ret);
1251                 return;
1252         }
1253
1254         memset(&link, 0, sizeof(link));
1255         rte_eth_linkstatus_set(dev, &link);
1256 }
1257
1258 static int
1259 dpaa2_dev_promiscuous_enable(
1260                 struct rte_eth_dev *dev)
1261 {
1262         int ret;
1263         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1264         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1265
1266         PMD_INIT_FUNC_TRACE();
1267
1268         if (dpni == NULL) {
1269                 DPAA2_PMD_ERR("dpni is NULL");
1270                 return -ENODEV;
1271         }
1272
1273         ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1274         if (ret < 0)
1275                 DPAA2_PMD_ERR("Unable to enable U promisc mode %d", ret);
1276
1277         ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1278         if (ret < 0)
1279                 DPAA2_PMD_ERR("Unable to enable M promisc mode %d", ret);
1280
1281         return ret;
1282 }
1283
1284 static int
1285 dpaa2_dev_promiscuous_disable(
1286                 struct rte_eth_dev *dev)
1287 {
1288         int ret;
1289         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1290         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1291
1292         PMD_INIT_FUNC_TRACE();
1293
1294         if (dpni == NULL) {
1295                 DPAA2_PMD_ERR("dpni is NULL");
1296                 return -ENODEV;
1297         }
1298
1299         ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1300         if (ret < 0)
1301                 DPAA2_PMD_ERR("Unable to disable U promisc mode %d", ret);
1302
1303         if (dev->data->all_multicast == 0) {
1304                 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW,
1305                                                  priv->token, false);
1306                 if (ret < 0)
1307                         DPAA2_PMD_ERR("Unable to disable M promisc mode %d",
1308                                       ret);
1309         }
1310
1311         return ret;
1312 }
1313
1314 static int
1315 dpaa2_dev_allmulticast_enable(
1316                 struct rte_eth_dev *dev)
1317 {
1318         int ret;
1319         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1320         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1321
1322         PMD_INIT_FUNC_TRACE();
1323
1324         if (dpni == NULL) {
1325                 DPAA2_PMD_ERR("dpni is NULL");
1326                 return -ENODEV;
1327         }
1328
1329         ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1330         if (ret < 0)
1331                 DPAA2_PMD_ERR("Unable to enable multicast mode %d", ret);
1332
1333         return ret;
1334 }
1335
1336 static int
1337 dpaa2_dev_allmulticast_disable(struct rte_eth_dev *dev)
1338 {
1339         int ret;
1340         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1341         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1342
1343         PMD_INIT_FUNC_TRACE();
1344
1345         if (dpni == NULL) {
1346                 DPAA2_PMD_ERR("dpni is NULL");
1347                 return -ENODEV;
1348         }
1349
1350         /* must remain on for all promiscuous */
1351         if (dev->data->promiscuous == 1)
1352                 return 0;
1353
1354         ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1355         if (ret < 0)
1356                 DPAA2_PMD_ERR("Unable to disable multicast mode %d", ret);
1357
1358         return ret;
1359 }
1360
1361 static int
1362 dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1363 {
1364         int ret;
1365         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1366         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1367         uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
1368                                 + VLAN_TAG_SIZE;
1369
1370         PMD_INIT_FUNC_TRACE();
1371
1372         if (dpni == NULL) {
1373                 DPAA2_PMD_ERR("dpni is NULL");
1374                 return -EINVAL;
1375         }
1376
1377         /* check that mtu is within the allowed range */
1378         if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA2_MAX_RX_PKT_LEN)
1379                 return -EINVAL;
1380
1381         if (frame_size > RTE_ETHER_MAX_LEN)
1382                 dev->data->dev_conf.rxmode.offloads |=
1383                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
1384         else
1385                 dev->data->dev_conf.rxmode.offloads &=
1386                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1387
1388         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1389
1390         /* Set the Max Rx frame length as 'mtu' +
1391          * Maximum Ethernet header length
1392          */
1393         ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, priv->token,
1394                                         frame_size - RTE_ETHER_CRC_LEN);
1395         if (ret) {
1396                 DPAA2_PMD_ERR("Setting the max frame length failed");
1397                 return -1;
1398         }
1399         DPAA2_PMD_INFO("MTU configured for the device: %d", mtu);
1400         return 0;
1401 }
1402
1403 static int
1404 dpaa2_dev_add_mac_addr(struct rte_eth_dev *dev,
1405                        struct rte_ether_addr *addr,
1406                        __rte_unused uint32_t index,
1407                        __rte_unused uint32_t pool)
1408 {
1409         int ret;
1410         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1411         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1412
1413         PMD_INIT_FUNC_TRACE();
1414
1415         if (dpni == NULL) {
1416                 DPAA2_PMD_ERR("dpni is NULL");
1417                 return -1;
1418         }
1419
1420         ret = dpni_add_mac_addr(dpni, CMD_PRI_LOW, priv->token,
1421                                 addr->addr_bytes, 0, 0, 0);
1422         if (ret)
1423                 DPAA2_PMD_ERR(
1424                         "error: Adding the MAC ADDR failed: err = %d", ret);
1425         return 0;
1426 }
1427
1428 static void
1429 dpaa2_dev_remove_mac_addr(struct rte_eth_dev *dev,
1430                           uint32_t index)
1431 {
1432         int ret;
1433         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1434         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1435         struct rte_eth_dev_data *data = dev->data;
1436         struct rte_ether_addr *macaddr;
1437
1438         PMD_INIT_FUNC_TRACE();
1439
1440         macaddr = &data->mac_addrs[index];
1441
1442         if (dpni == NULL) {
1443                 DPAA2_PMD_ERR("dpni is NULL");
1444                 return;
1445         }
1446
1447         ret = dpni_remove_mac_addr(dpni, CMD_PRI_LOW,
1448                                    priv->token, macaddr->addr_bytes);
1449         if (ret)
1450                 DPAA2_PMD_ERR(
1451                         "error: Removing the MAC ADDR failed: err = %d", ret);
1452 }
1453
1454 static int
1455 dpaa2_dev_set_mac_addr(struct rte_eth_dev *dev,
1456                        struct rte_ether_addr *addr)
1457 {
1458         int ret;
1459         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1460         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1461
1462         PMD_INIT_FUNC_TRACE();
1463
1464         if (dpni == NULL) {
1465                 DPAA2_PMD_ERR("dpni is NULL");
1466                 return -EINVAL;
1467         }
1468
1469         ret = dpni_set_primary_mac_addr(dpni, CMD_PRI_LOW,
1470                                         priv->token, addr->addr_bytes);
1471
1472         if (ret)
1473                 DPAA2_PMD_ERR(
1474                         "error: Setting the MAC ADDR failed %d", ret);
1475
1476         return ret;
1477 }
1478
1479 static
1480 int dpaa2_dev_stats_get(struct rte_eth_dev *dev,
1481                          struct rte_eth_stats *stats)
1482 {
1483         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1484         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1485         int32_t  retcode;
1486         uint8_t page0 = 0, page1 = 1, page2 = 2;
1487         union dpni_statistics value;
1488         int i;
1489         struct dpaa2_queue *dpaa2_rxq, *dpaa2_txq;
1490
1491         memset(&value, 0, sizeof(union dpni_statistics));
1492
1493         PMD_INIT_FUNC_TRACE();
1494
1495         if (!dpni) {
1496                 DPAA2_PMD_ERR("dpni is NULL");
1497                 return -EINVAL;
1498         }
1499
1500         if (!stats) {
1501                 DPAA2_PMD_ERR("stats is NULL");
1502                 return -EINVAL;
1503         }
1504
1505         /*Get Counters from page_0*/
1506         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1507                                       page0, 0, &value);
1508         if (retcode)
1509                 goto err;
1510
1511         stats->ipackets = value.page_0.ingress_all_frames;
1512         stats->ibytes = value.page_0.ingress_all_bytes;
1513
1514         /*Get Counters from page_1*/
1515         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1516                                       page1, 0, &value);
1517         if (retcode)
1518                 goto err;
1519
1520         stats->opackets = value.page_1.egress_all_frames;
1521         stats->obytes = value.page_1.egress_all_bytes;
1522
1523         /*Get Counters from page_2*/
1524         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1525                                       page2, 0, &value);
1526         if (retcode)
1527                 goto err;
1528
1529         /* Ingress drop frame count due to configured rules */
1530         stats->ierrors = value.page_2.ingress_filtered_frames;
1531         /* Ingress drop frame count due to error */
1532         stats->ierrors += value.page_2.ingress_discarded_frames;
1533
1534         stats->oerrors = value.page_2.egress_discarded_frames;
1535         stats->imissed = value.page_2.ingress_nobuffer_discards;
1536
1537         /* Fill in per queue stats */
1538         for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) &&
1539                 (i < priv->nb_rx_queues || i < priv->nb_tx_queues); ++i) {
1540                 dpaa2_rxq = (struct dpaa2_queue *)priv->rx_vq[i];
1541                 dpaa2_txq = (struct dpaa2_queue *)priv->tx_vq[i];
1542                 if (dpaa2_rxq)
1543                         stats->q_ipackets[i] = dpaa2_rxq->rx_pkts;
1544                 if (dpaa2_txq)
1545                         stats->q_opackets[i] = dpaa2_txq->tx_pkts;
1546
1547                 /* Byte counting is not implemented */
1548                 stats->q_ibytes[i]   = 0;
1549                 stats->q_obytes[i]   = 0;
1550         }
1551
1552         return 0;
1553
1554 err:
1555         DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1556         return retcode;
1557 };
1558
1559 static int
1560 dpaa2_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1561                      unsigned int n)
1562 {
1563         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1564         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1565         int32_t  retcode;
1566         union dpni_statistics value[5] = {};
1567         unsigned int i = 0, num = RTE_DIM(dpaa2_xstats_strings);
1568
1569         if (n < num)
1570                 return num;
1571
1572         if (xstats == NULL)
1573                 return 0;
1574
1575         /* Get Counters from page_0*/
1576         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1577                                       0, 0, &value[0]);
1578         if (retcode)
1579                 goto err;
1580
1581         /* Get Counters from page_1*/
1582         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1583                                       1, 0, &value[1]);
1584         if (retcode)
1585                 goto err;
1586
1587         /* Get Counters from page_2*/
1588         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1589                                       2, 0, &value[2]);
1590         if (retcode)
1591                 goto err;
1592
1593         for (i = 0; i < priv->max_cgs; i++) {
1594                 if (!priv->cgid_in_use[i]) {
1595                         /* Get Counters from page_4*/
1596                         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW,
1597                                                       priv->token,
1598                                                       4, 0, &value[4]);
1599                         if (retcode)
1600                                 goto err;
1601                         break;
1602                 }
1603         }
1604
1605         for (i = 0; i < num; i++) {
1606                 xstats[i].id = i;
1607                 xstats[i].value = value[dpaa2_xstats_strings[i].page_id].
1608                         raw.counter[dpaa2_xstats_strings[i].stats_id];
1609         }
1610         return i;
1611 err:
1612         DPAA2_PMD_ERR("Error in obtaining extended stats (%d)", retcode);
1613         return retcode;
1614 }
1615
1616 static int
1617 dpaa2_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1618                        struct rte_eth_xstat_name *xstats_names,
1619                        unsigned int limit)
1620 {
1621         unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1622
1623         if (limit < stat_cnt)
1624                 return stat_cnt;
1625
1626         if (xstats_names != NULL)
1627                 for (i = 0; i < stat_cnt; i++)
1628                         strlcpy(xstats_names[i].name,
1629                                 dpaa2_xstats_strings[i].name,
1630                                 sizeof(xstats_names[i].name));
1631
1632         return stat_cnt;
1633 }
1634
1635 static int
1636 dpaa2_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1637                        uint64_t *values, unsigned int n)
1638 {
1639         unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1640         uint64_t values_copy[stat_cnt];
1641
1642         if (!ids) {
1643                 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1644                 struct fsl_mc_io *dpni =
1645                         (struct fsl_mc_io *)dev->process_private;
1646                 int32_t  retcode;
1647                 union dpni_statistics value[5] = {};
1648
1649                 if (n < stat_cnt)
1650                         return stat_cnt;
1651
1652                 if (!values)
1653                         return 0;
1654
1655                 /* Get Counters from page_0*/
1656                 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1657                                               0, 0, &value[0]);
1658                 if (retcode)
1659                         return 0;
1660
1661                 /* Get Counters from page_1*/
1662                 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1663                                               1, 0, &value[1]);
1664                 if (retcode)
1665                         return 0;
1666
1667                 /* Get Counters from page_2*/
1668                 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1669                                               2, 0, &value[2]);
1670                 if (retcode)
1671                         return 0;
1672
1673                 /* Get Counters from page_4*/
1674                 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1675                                               4, 0, &value[4]);
1676                 if (retcode)
1677                         return 0;
1678
1679                 for (i = 0; i < stat_cnt; i++) {
1680                         values[i] = value[dpaa2_xstats_strings[i].page_id].
1681                                 raw.counter[dpaa2_xstats_strings[i].stats_id];
1682                 }
1683                 return stat_cnt;
1684         }
1685
1686         dpaa2_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
1687
1688         for (i = 0; i < n; i++) {
1689                 if (ids[i] >= stat_cnt) {
1690                         DPAA2_PMD_ERR("xstats id value isn't valid");
1691                         return -1;
1692                 }
1693                 values[i] = values_copy[ids[i]];
1694         }
1695         return n;
1696 }
1697
1698 static int
1699 dpaa2_xstats_get_names_by_id(
1700         struct rte_eth_dev *dev,
1701         struct rte_eth_xstat_name *xstats_names,
1702         const uint64_t *ids,
1703         unsigned int limit)
1704 {
1705         unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1706         struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
1707
1708         if (!ids)
1709                 return dpaa2_xstats_get_names(dev, xstats_names, limit);
1710
1711         dpaa2_xstats_get_names(dev, xstats_names_copy, limit);
1712
1713         for (i = 0; i < limit; i++) {
1714                 if (ids[i] >= stat_cnt) {
1715                         DPAA2_PMD_ERR("xstats id value isn't valid");
1716                         return -1;
1717                 }
1718                 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
1719         }
1720         return limit;
1721 }
1722
1723 static int
1724 dpaa2_dev_stats_reset(struct rte_eth_dev *dev)
1725 {
1726         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1727         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1728         int retcode;
1729         int i;
1730         struct dpaa2_queue *dpaa2_q;
1731
1732         PMD_INIT_FUNC_TRACE();
1733
1734         if (dpni == NULL) {
1735                 DPAA2_PMD_ERR("dpni is NULL");
1736                 return -EINVAL;
1737         }
1738
1739         retcode =  dpni_reset_statistics(dpni, CMD_PRI_LOW, priv->token);
1740         if (retcode)
1741                 goto error;
1742
1743         /* Reset the per queue stats in dpaa2_queue structure */
1744         for (i = 0; i < priv->nb_rx_queues; i++) {
1745                 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
1746                 if (dpaa2_q)
1747                         dpaa2_q->rx_pkts = 0;
1748         }
1749
1750         for (i = 0; i < priv->nb_tx_queues; i++) {
1751                 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
1752                 if (dpaa2_q)
1753                         dpaa2_q->tx_pkts = 0;
1754         }
1755
1756         return 0;
1757
1758 error:
1759         DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1760         return retcode;
1761 };
1762
1763 /* return 0 means link status changed, -1 means not changed */
1764 static int
1765 dpaa2_dev_link_update(struct rte_eth_dev *dev,
1766                         int wait_to_complete __rte_unused)
1767 {
1768         int ret;
1769         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1770         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1771         struct rte_eth_link link;
1772         struct dpni_link_state state = {0};
1773
1774         if (dpni == NULL) {
1775                 DPAA2_PMD_ERR("dpni is NULL");
1776                 return 0;
1777         }
1778
1779         ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1780         if (ret < 0) {
1781                 DPAA2_PMD_DEBUG("error: dpni_get_link_state %d", ret);
1782                 return -1;
1783         }
1784
1785         memset(&link, 0, sizeof(struct rte_eth_link));
1786         link.link_status = state.up;
1787         link.link_speed = state.rate;
1788
1789         if (state.options & DPNI_LINK_OPT_HALF_DUPLEX)
1790                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1791         else
1792                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1793
1794         ret = rte_eth_linkstatus_set(dev, &link);
1795         if (ret == -1)
1796                 DPAA2_PMD_DEBUG("No change in status");
1797         else
1798                 DPAA2_PMD_INFO("Port %d Link is %s\n", dev->data->port_id,
1799                                link.link_status ? "Up" : "Down");
1800
1801         return ret;
1802 }
1803
1804 /**
1805  * Toggle the DPNI to enable, if not already enabled.
1806  * This is not strictly PHY up/down - it is more of logical toggling.
1807  */
1808 static int
1809 dpaa2_dev_set_link_up(struct rte_eth_dev *dev)
1810 {
1811         int ret = -EINVAL;
1812         struct dpaa2_dev_priv *priv;
1813         struct fsl_mc_io *dpni;
1814         int en = 0;
1815         struct dpni_link_state state = {0};
1816
1817         priv = dev->data->dev_private;
1818         dpni = (struct fsl_mc_io *)dev->process_private;
1819
1820         if (dpni == NULL) {
1821                 DPAA2_PMD_ERR("dpni is NULL");
1822                 return ret;
1823         }
1824
1825         /* Check if DPNI is currently enabled */
1826         ret = dpni_is_enabled(dpni, CMD_PRI_LOW, priv->token, &en);
1827         if (ret) {
1828                 /* Unable to obtain dpni status; Not continuing */
1829                 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1830                 return -EINVAL;
1831         }
1832
1833         /* Enable link if not already enabled */
1834         if (!en) {
1835                 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1836                 if (ret) {
1837                         DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1838                         return -EINVAL;
1839                 }
1840         }
1841         ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1842         if (ret < 0) {
1843                 DPAA2_PMD_DEBUG("Unable to get link state (%d)", ret);
1844                 return -1;
1845         }
1846
1847         /* changing tx burst function to start enqueues */
1848         dev->tx_pkt_burst = dpaa2_dev_tx;
1849         dev->data->dev_link.link_status = state.up;
1850         dev->data->dev_link.link_speed = state.rate;
1851
1852         if (state.up)
1853                 DPAA2_PMD_INFO("Port %d Link is Up", dev->data->port_id);
1854         else
1855                 DPAA2_PMD_INFO("Port %d Link is Down", dev->data->port_id);
1856         return ret;
1857 }
1858
1859 /**
1860  * Toggle the DPNI to disable, if not already disabled.
1861  * This is not strictly PHY up/down - it is more of logical toggling.
1862  */
1863 static int
1864 dpaa2_dev_set_link_down(struct rte_eth_dev *dev)
1865 {
1866         int ret = -EINVAL;
1867         struct dpaa2_dev_priv *priv;
1868         struct fsl_mc_io *dpni;
1869         int dpni_enabled = 0;
1870         int retries = 10;
1871
1872         PMD_INIT_FUNC_TRACE();
1873
1874         priv = dev->data->dev_private;
1875         dpni = (struct fsl_mc_io *)dev->process_private;
1876
1877         if (dpni == NULL) {
1878                 DPAA2_PMD_ERR("Device has not yet been configured");
1879                 return ret;
1880         }
1881
1882         /*changing  tx burst function to avoid any more enqueues */
1883         dev->tx_pkt_burst = dummy_dev_tx;
1884
1885         /* Loop while dpni_disable() attempts to drain the egress FQs
1886          * and confirm them back to us.
1887          */
1888         do {
1889                 ret = dpni_disable(dpni, 0, priv->token);
1890                 if (ret) {
1891                         DPAA2_PMD_ERR("dpni disable failed (%d)", ret);
1892                         return ret;
1893                 }
1894                 ret = dpni_is_enabled(dpni, 0, priv->token, &dpni_enabled);
1895                 if (ret) {
1896                         DPAA2_PMD_ERR("dpni enable check failed (%d)", ret);
1897                         return ret;
1898                 }
1899                 if (dpni_enabled)
1900                         /* Allow the MC some slack */
1901                         rte_delay_us(100 * 1000);
1902         } while (dpni_enabled && --retries);
1903
1904         if (!retries) {
1905                 DPAA2_PMD_WARN("Retry count exceeded disabling dpni");
1906                 /* todo- we may have to manually cleanup queues.
1907                  */
1908         } else {
1909                 DPAA2_PMD_INFO("Port %d Link DOWN successful",
1910                                dev->data->port_id);
1911         }
1912
1913         dev->data->dev_link.link_status = 0;
1914
1915         return ret;
1916 }
1917
1918 static int
1919 dpaa2_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1920 {
1921         int ret = -EINVAL;
1922         struct dpaa2_dev_priv *priv;
1923         struct fsl_mc_io *dpni;
1924         struct dpni_link_state state = {0};
1925
1926         PMD_INIT_FUNC_TRACE();
1927
1928         priv = dev->data->dev_private;
1929         dpni = (struct fsl_mc_io *)dev->process_private;
1930
1931         if (dpni == NULL || fc_conf == NULL) {
1932                 DPAA2_PMD_ERR("device not configured");
1933                 return ret;
1934         }
1935
1936         ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1937         if (ret) {
1938                 DPAA2_PMD_ERR("error: dpni_get_link_state %d", ret);
1939                 return ret;
1940         }
1941
1942         memset(fc_conf, 0, sizeof(struct rte_eth_fc_conf));
1943         if (state.options & DPNI_LINK_OPT_PAUSE) {
1944                 /* DPNI_LINK_OPT_PAUSE set
1945                  *  if ASYM_PAUSE not set,
1946                  *      RX Side flow control (handle received Pause frame)
1947                  *      TX side flow control (send Pause frame)
1948                  *  if ASYM_PAUSE set,
1949                  *      RX Side flow control (handle received Pause frame)
1950                  *      No TX side flow control (send Pause frame disabled)
1951                  */
1952                 if (!(state.options & DPNI_LINK_OPT_ASYM_PAUSE))
1953                         fc_conf->mode = RTE_FC_FULL;
1954                 else
1955                         fc_conf->mode = RTE_FC_RX_PAUSE;
1956         } else {
1957                 /* DPNI_LINK_OPT_PAUSE not set
1958                  *  if ASYM_PAUSE set,
1959                  *      TX side flow control (send Pause frame)
1960                  *      No RX side flow control (No action on pause frame rx)
1961                  *  if ASYM_PAUSE not set,
1962                  *      Flow control disabled
1963                  */
1964                 if (state.options & DPNI_LINK_OPT_ASYM_PAUSE)
1965                         fc_conf->mode = RTE_FC_TX_PAUSE;
1966                 else
1967                         fc_conf->mode = RTE_FC_NONE;
1968         }
1969
1970         return ret;
1971 }
1972
1973 static int
1974 dpaa2_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1975 {
1976         int ret = -EINVAL;
1977         struct dpaa2_dev_priv *priv;
1978         struct fsl_mc_io *dpni;
1979         struct dpni_link_state state = {0};
1980         struct dpni_link_cfg cfg = {0};
1981
1982         PMD_INIT_FUNC_TRACE();
1983
1984         priv = dev->data->dev_private;
1985         dpni = (struct fsl_mc_io *)dev->process_private;
1986
1987         if (dpni == NULL) {
1988                 DPAA2_PMD_ERR("dpni is NULL");
1989                 return ret;
1990         }
1991
1992         /* It is necessary to obtain the current state before setting fc_conf
1993          * as MC would return error in case rate, autoneg or duplex values are
1994          * different.
1995          */
1996         ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1997         if (ret) {
1998                 DPAA2_PMD_ERR("Unable to get link state (err=%d)", ret);
1999                 return -1;
2000         }
2001
2002         /* Disable link before setting configuration */
2003         dpaa2_dev_set_link_down(dev);
2004
2005         /* Based on fc_conf, update cfg */
2006         cfg.rate = state.rate;
2007         cfg.options = state.options;
2008
2009         /* update cfg with fc_conf */
2010         switch (fc_conf->mode) {
2011         case RTE_FC_FULL:
2012                 /* Full flow control;
2013                  * OPT_PAUSE set, ASYM_PAUSE not set
2014                  */
2015                 cfg.options |= DPNI_LINK_OPT_PAUSE;
2016                 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
2017                 break;
2018         case RTE_FC_TX_PAUSE:
2019                 /* Enable RX flow control
2020                  * OPT_PAUSE not set;
2021                  * ASYM_PAUSE set;
2022                  */
2023                 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
2024                 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
2025                 break;
2026         case RTE_FC_RX_PAUSE:
2027                 /* Enable TX Flow control
2028                  * OPT_PAUSE set
2029                  * ASYM_PAUSE set
2030                  */
2031                 cfg.options |= DPNI_LINK_OPT_PAUSE;
2032                 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
2033                 break;
2034         case RTE_FC_NONE:
2035                 /* Disable Flow control
2036                  * OPT_PAUSE not set
2037                  * ASYM_PAUSE not set
2038                  */
2039                 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
2040                 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
2041                 break;
2042         default:
2043                 DPAA2_PMD_ERR("Incorrect Flow control flag (%d)",
2044                               fc_conf->mode);
2045                 return -1;
2046         }
2047
2048         ret = dpni_set_link_cfg(dpni, CMD_PRI_LOW, priv->token, &cfg);
2049         if (ret)
2050                 DPAA2_PMD_ERR("Unable to set Link configuration (err=%d)",
2051                               ret);
2052
2053         /* Enable link */
2054         dpaa2_dev_set_link_up(dev);
2055
2056         return ret;
2057 }
2058
2059 static int
2060 dpaa2_dev_rss_hash_update(struct rte_eth_dev *dev,
2061                           struct rte_eth_rss_conf *rss_conf)
2062 {
2063         struct rte_eth_dev_data *data = dev->data;
2064         struct dpaa2_dev_priv *priv = data->dev_private;
2065         struct rte_eth_conf *eth_conf = &data->dev_conf;
2066         int ret, tc_index;
2067
2068         PMD_INIT_FUNC_TRACE();
2069
2070         if (rss_conf->rss_hf) {
2071                 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
2072                         ret = dpaa2_setup_flow_dist(dev, rss_conf->rss_hf,
2073                                 tc_index);
2074                         if (ret) {
2075                                 DPAA2_PMD_ERR("Unable to set flow dist on tc%d",
2076                                         tc_index);
2077                                 return ret;
2078                         }
2079                 }
2080         } else {
2081                 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
2082                         ret = dpaa2_remove_flow_dist(dev, tc_index);
2083                         if (ret) {
2084                                 DPAA2_PMD_ERR(
2085                                         "Unable to remove flow dist on tc%d",
2086                                         tc_index);
2087                                 return ret;
2088                         }
2089                 }
2090         }
2091         eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf;
2092         return 0;
2093 }
2094
2095 static int
2096 dpaa2_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2097                             struct rte_eth_rss_conf *rss_conf)
2098 {
2099         struct rte_eth_dev_data *data = dev->data;
2100         struct rte_eth_conf *eth_conf = &data->dev_conf;
2101
2102         /* dpaa2 does not support rss_key, so length should be 0*/
2103         rss_conf->rss_key_len = 0;
2104         rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf;
2105         return 0;
2106 }
2107
2108 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev,
2109                 int eth_rx_queue_id,
2110                 struct dpaa2_dpcon_dev *dpcon,
2111                 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
2112 {
2113         struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2114         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2115         struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2116         uint8_t flow_id = dpaa2_ethq->flow_id;
2117         struct dpni_queue cfg;
2118         uint8_t options, priority;
2119         int ret;
2120
2121         if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_PARALLEL)
2122                 dpaa2_ethq->cb = dpaa2_dev_process_parallel_event;
2123         else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC)
2124                 dpaa2_ethq->cb = dpaa2_dev_process_atomic_event;
2125         else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED)
2126                 dpaa2_ethq->cb = dpaa2_dev_process_ordered_event;
2127         else
2128                 return -EINVAL;
2129
2130         priority = (RTE_EVENT_DEV_PRIORITY_LOWEST / queue_conf->ev.priority) *
2131                    (dpcon->num_priorities - 1);
2132
2133         memset(&cfg, 0, sizeof(struct dpni_queue));
2134         options = DPNI_QUEUE_OPT_DEST;
2135         cfg.destination.type = DPNI_DEST_DPCON;
2136         cfg.destination.id = dpcon->dpcon_id;
2137         cfg.destination.priority = priority;
2138
2139         if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) {
2140                 options |= DPNI_QUEUE_OPT_HOLD_ACTIVE;
2141                 cfg.destination.hold_active = 1;
2142         }
2143
2144         if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED &&
2145                         !eth_priv->en_ordered) {
2146                 struct opr_cfg ocfg;
2147
2148                 /* Restoration window size = 256 frames */
2149                 ocfg.oprrws = 3;
2150                 /* Restoration window size = 512 frames for LX2 */
2151                 if (dpaa2_svr_family == SVR_LX2160A)
2152                         ocfg.oprrws = 4;
2153                 /* Auto advance NESN window enabled */
2154                 ocfg.oa = 1;
2155                 /* Late arrival window size disabled */
2156                 ocfg.olws = 0;
2157                 /* ORL resource exhaustaion advance NESN disabled */
2158                 ocfg.oeane = 0;
2159                 /* Loose ordering enabled */
2160                 ocfg.oloe = 1;
2161                 eth_priv->en_loose_ordered = 1;
2162                 /* Strict ordering enabled if explicitly set */
2163                 if (getenv("DPAA2_STRICT_ORDERING_ENABLE")) {
2164                         ocfg.oloe = 0;
2165                         eth_priv->en_loose_ordered = 0;
2166                 }
2167
2168                 ret = dpni_set_opr(dpni, CMD_PRI_LOW, eth_priv->token,
2169                                    dpaa2_ethq->tc_index, flow_id,
2170                                    OPR_OPT_CREATE, &ocfg);
2171                 if (ret) {
2172                         DPAA2_PMD_ERR("Error setting opr: ret: %d\n", ret);
2173                         return ret;
2174                 }
2175
2176                 eth_priv->en_ordered = 1;
2177         }
2178
2179         options |= DPNI_QUEUE_OPT_USER_CTX;
2180         cfg.user_context = (size_t)(dpaa2_ethq);
2181
2182         ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2183                              dpaa2_ethq->tc_index, flow_id, options, &cfg);
2184         if (ret) {
2185                 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2186                 return ret;
2187         }
2188
2189         memcpy(&dpaa2_ethq->ev, &queue_conf->ev, sizeof(struct rte_event));
2190
2191         return 0;
2192 }
2193
2194 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev,
2195                 int eth_rx_queue_id)
2196 {
2197         struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2198         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2199         struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2200         uint8_t flow_id = dpaa2_ethq->flow_id;
2201         struct dpni_queue cfg;
2202         uint8_t options;
2203         int ret;
2204
2205         memset(&cfg, 0, sizeof(struct dpni_queue));
2206         options = DPNI_QUEUE_OPT_DEST;
2207         cfg.destination.type = DPNI_DEST_NONE;
2208
2209         ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2210                              dpaa2_ethq->tc_index, flow_id, options, &cfg);
2211         if (ret)
2212                 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2213
2214         return ret;
2215 }
2216
2217 static inline int
2218 dpaa2_dev_verify_filter_ops(enum rte_filter_op filter_op)
2219 {
2220         unsigned int i;
2221
2222         for (i = 0; i < RTE_DIM(dpaa2_supported_filter_ops); i++) {
2223                 if (dpaa2_supported_filter_ops[i] == filter_op)
2224                         return 0;
2225         }
2226         return -ENOTSUP;
2227 }
2228
2229 static int
2230 dpaa2_dev_flow_ctrl(struct rte_eth_dev *dev,
2231                     enum rte_filter_type filter_type,
2232                                  enum rte_filter_op filter_op,
2233                                  void *arg)
2234 {
2235         int ret = 0;
2236
2237         if (!dev)
2238                 return -ENODEV;
2239
2240         switch (filter_type) {
2241         case RTE_ETH_FILTER_GENERIC:
2242                 if (dpaa2_dev_verify_filter_ops(filter_op) < 0) {
2243                         ret = -ENOTSUP;
2244                         break;
2245                 }
2246                 *(const void **)arg = &dpaa2_flow_ops;
2247                 dpaa2_filter_type |= filter_type;
2248                 break;
2249         default:
2250                 RTE_LOG(ERR, PMD, "Filter type (%d) not supported",
2251                         filter_type);
2252                 ret = -ENOTSUP;
2253                 break;
2254         }
2255         return ret;
2256 }
2257
2258 static struct eth_dev_ops dpaa2_ethdev_ops = {
2259         .dev_configure    = dpaa2_eth_dev_configure,
2260         .dev_start            = dpaa2_dev_start,
2261         .dev_stop             = dpaa2_dev_stop,
2262         .dev_close            = dpaa2_dev_close,
2263         .promiscuous_enable   = dpaa2_dev_promiscuous_enable,
2264         .promiscuous_disable  = dpaa2_dev_promiscuous_disable,
2265         .allmulticast_enable  = dpaa2_dev_allmulticast_enable,
2266         .allmulticast_disable = dpaa2_dev_allmulticast_disable,
2267         .dev_set_link_up      = dpaa2_dev_set_link_up,
2268         .dev_set_link_down    = dpaa2_dev_set_link_down,
2269         .link_update       = dpaa2_dev_link_update,
2270         .stats_get             = dpaa2_dev_stats_get,
2271         .xstats_get            = dpaa2_dev_xstats_get,
2272         .xstats_get_by_id     = dpaa2_xstats_get_by_id,
2273         .xstats_get_names_by_id = dpaa2_xstats_get_names_by_id,
2274         .xstats_get_names      = dpaa2_xstats_get_names,
2275         .stats_reset       = dpaa2_dev_stats_reset,
2276         .xstats_reset         = dpaa2_dev_stats_reset,
2277         .fw_version_get    = dpaa2_fw_version_get,
2278         .dev_infos_get     = dpaa2_dev_info_get,
2279         .dev_supported_ptypes_get = dpaa2_supported_ptypes_get,
2280         .mtu_set           = dpaa2_dev_mtu_set,
2281         .vlan_filter_set      = dpaa2_vlan_filter_set,
2282         .vlan_offload_set     = dpaa2_vlan_offload_set,
2283         .vlan_tpid_set        = dpaa2_vlan_tpid_set,
2284         .rx_queue_setup    = dpaa2_dev_rx_queue_setup,
2285         .rx_queue_release  = dpaa2_dev_rx_queue_release,
2286         .tx_queue_setup    = dpaa2_dev_tx_queue_setup,
2287         .tx_queue_release  = dpaa2_dev_tx_queue_release,
2288         .rx_burst_mode_get = dpaa2_dev_rx_burst_mode_get,
2289         .tx_burst_mode_get = dpaa2_dev_tx_burst_mode_get,
2290         .rx_queue_count       = dpaa2_dev_rx_queue_count,
2291         .flow_ctrl_get        = dpaa2_flow_ctrl_get,
2292         .flow_ctrl_set        = dpaa2_flow_ctrl_set,
2293         .mac_addr_add         = dpaa2_dev_add_mac_addr,
2294         .mac_addr_remove      = dpaa2_dev_remove_mac_addr,
2295         .mac_addr_set         = dpaa2_dev_set_mac_addr,
2296         .rss_hash_update      = dpaa2_dev_rss_hash_update,
2297         .rss_hash_conf_get    = dpaa2_dev_rss_hash_conf_get,
2298         .filter_ctrl          = dpaa2_dev_flow_ctrl,
2299 #if defined(RTE_LIBRTE_IEEE1588)
2300         .timesync_enable      = dpaa2_timesync_enable,
2301         .timesync_disable     = dpaa2_timesync_disable,
2302         .timesync_read_time   = dpaa2_timesync_read_time,
2303         .timesync_write_time  = dpaa2_timesync_write_time,
2304         .timesync_adjust_time = dpaa2_timesync_adjust_time,
2305         .timesync_read_rx_timestamp = dpaa2_timesync_read_rx_timestamp,
2306         .timesync_read_tx_timestamp = dpaa2_timesync_read_tx_timestamp,
2307 #endif
2308 };
2309
2310 /* Populate the mac address from physically available (u-boot/firmware) and/or
2311  * one set by higher layers like MC (restool) etc.
2312  * Returns the table of MAC entries (multiple entries)
2313  */
2314 static int
2315 populate_mac_addr(struct fsl_mc_io *dpni_dev, struct dpaa2_dev_priv *priv,
2316                   struct rte_ether_addr *mac_entry)
2317 {
2318         int ret;
2319         struct rte_ether_addr phy_mac, prime_mac;
2320
2321         memset(&phy_mac, 0, sizeof(struct rte_ether_addr));
2322         memset(&prime_mac, 0, sizeof(struct rte_ether_addr));
2323
2324         /* Get the physical device MAC address */
2325         ret = dpni_get_port_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2326                                      phy_mac.addr_bytes);
2327         if (ret) {
2328                 DPAA2_PMD_ERR("DPNI get physical port MAC failed: %d", ret);
2329                 goto cleanup;
2330         }
2331
2332         ret = dpni_get_primary_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2333                                         prime_mac.addr_bytes);
2334         if (ret) {
2335                 DPAA2_PMD_ERR("DPNI get Prime port MAC failed: %d", ret);
2336                 goto cleanup;
2337         }
2338
2339         /* Now that both MAC have been obtained, do:
2340          *  if not_empty_mac(phy) && phy != Prime, overwrite prime with Phy
2341          *     and return phy
2342          *  If empty_mac(phy), return prime.
2343          *  if both are empty, create random MAC, set as prime and return
2344          */
2345         if (!rte_is_zero_ether_addr(&phy_mac)) {
2346                 /* If the addresses are not same, overwrite prime */
2347                 if (!rte_is_same_ether_addr(&phy_mac, &prime_mac)) {
2348                         ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2349                                                         priv->token,
2350                                                         phy_mac.addr_bytes);
2351                         if (ret) {
2352                                 DPAA2_PMD_ERR("Unable to set MAC Address: %d",
2353                                               ret);
2354                                 goto cleanup;
2355                         }
2356                         memcpy(&prime_mac, &phy_mac,
2357                                 sizeof(struct rte_ether_addr));
2358                 }
2359         } else if (rte_is_zero_ether_addr(&prime_mac)) {
2360                 /* In case phys and prime, both are zero, create random MAC */
2361                 rte_eth_random_addr(prime_mac.addr_bytes);
2362                 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2363                                                 priv->token,
2364                                                 prime_mac.addr_bytes);
2365                 if (ret) {
2366                         DPAA2_PMD_ERR("Unable to set MAC Address: %d", ret);
2367                         goto cleanup;
2368                 }
2369         }
2370
2371         /* prime_mac the final MAC address */
2372         memcpy(mac_entry, &prime_mac, sizeof(struct rte_ether_addr));
2373         return 0;
2374
2375 cleanup:
2376         return -1;
2377 }
2378
2379 static int
2380 check_devargs_handler(__rte_unused const char *key, const char *value,
2381                       __rte_unused void *opaque)
2382 {
2383         if (strcmp(value, "1"))
2384                 return -1;
2385
2386         return 0;
2387 }
2388
2389 static int
2390 dpaa2_get_devargs(struct rte_devargs *devargs, const char *key)
2391 {
2392         struct rte_kvargs *kvlist;
2393
2394         if (!devargs)
2395                 return 0;
2396
2397         kvlist = rte_kvargs_parse(devargs->args, NULL);
2398         if (!kvlist)
2399                 return 0;
2400
2401         if (!rte_kvargs_count(kvlist, key)) {
2402                 rte_kvargs_free(kvlist);
2403                 return 0;
2404         }
2405
2406         if (rte_kvargs_process(kvlist, key,
2407                                check_devargs_handler, NULL) < 0) {
2408                 rte_kvargs_free(kvlist);
2409                 return 0;
2410         }
2411         rte_kvargs_free(kvlist);
2412
2413         return 1;
2414 }
2415
2416 static int
2417 dpaa2_dev_init(struct rte_eth_dev *eth_dev)
2418 {
2419         struct rte_device *dev = eth_dev->device;
2420         struct rte_dpaa2_device *dpaa2_dev;
2421         struct fsl_mc_io *dpni_dev;
2422         struct dpni_attr attr;
2423         struct dpaa2_dev_priv *priv = eth_dev->data->dev_private;
2424         struct dpni_buffer_layout layout;
2425         int ret, hw_id, i;
2426
2427         PMD_INIT_FUNC_TRACE();
2428
2429         dpni_dev = rte_malloc(NULL, sizeof(struct fsl_mc_io), 0);
2430         if (!dpni_dev) {
2431                 DPAA2_PMD_ERR("Memory allocation failed for dpni device");
2432                 return -1;
2433         }
2434         dpni_dev->regs = dpaa2_get_mcp_ptr(MC_PORTAL_INDEX);
2435         eth_dev->process_private = (void *)dpni_dev;
2436
2437         /* For secondary processes, the primary has done all the work */
2438         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2439                 /* In case of secondary, only burst and ops API need to be
2440                  * plugged.
2441                  */
2442                 eth_dev->dev_ops = &dpaa2_ethdev_ops;
2443                 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE))
2444                         eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2445                 else if (dpaa2_get_devargs(dev->devargs,
2446                                         DRIVER_NO_PREFETCH_MODE))
2447                         eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2448                 else
2449                         eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2450                 eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2451                 return 0;
2452         }
2453
2454         dpaa2_dev = container_of(dev, struct rte_dpaa2_device, device);
2455
2456         hw_id = dpaa2_dev->object_id;
2457         ret = dpni_open(dpni_dev, CMD_PRI_LOW, hw_id, &priv->token);
2458         if (ret) {
2459                 DPAA2_PMD_ERR(
2460                              "Failure in opening dpni@%d with err code %d",
2461                              hw_id, ret);
2462                 rte_free(dpni_dev);
2463                 return -1;
2464         }
2465
2466         /* Clean the device first */
2467         ret = dpni_reset(dpni_dev, CMD_PRI_LOW, priv->token);
2468         if (ret) {
2469                 DPAA2_PMD_ERR("Failure cleaning dpni@%d with err code %d",
2470                               hw_id, ret);
2471                 goto init_err;
2472         }
2473
2474         ret = dpni_get_attributes(dpni_dev, CMD_PRI_LOW, priv->token, &attr);
2475         if (ret) {
2476                 DPAA2_PMD_ERR(
2477                              "Failure in get dpni@%d attribute, err code %d",
2478                              hw_id, ret);
2479                 goto init_err;
2480         }
2481
2482         priv->num_rx_tc = attr.num_rx_tcs;
2483         priv->qos_entries = attr.qos_entries;
2484         priv->fs_entries = attr.fs_entries;
2485         priv->dist_queues = attr.num_queues;
2486
2487         /* only if the custom CG is enabled */
2488         if (attr.options & DPNI_OPT_CUSTOM_CG)
2489                 priv->max_cgs = attr.num_cgs;
2490         else
2491                 priv->max_cgs = 0;
2492
2493         for (i = 0; i < priv->max_cgs; i++)
2494                 priv->cgid_in_use[i] = 0;
2495
2496         for (i = 0; i < attr.num_rx_tcs; i++)
2497                 priv->nb_rx_queues += attr.num_queues;
2498
2499         /* Using number of TX queues as number of TX TCs */
2500         priv->nb_tx_queues = attr.num_tx_tcs;
2501
2502         DPAA2_PMD_DEBUG("RX-TC= %d, rx_queues= %d, tx_queues=%d, max_cgs=%d",
2503                         priv->num_rx_tc, priv->nb_rx_queues,
2504                         priv->nb_tx_queues, priv->max_cgs);
2505
2506         priv->hw = dpni_dev;
2507         priv->hw_id = hw_id;
2508         priv->options = attr.options;
2509         priv->max_mac_filters = attr.mac_filter_entries;
2510         priv->max_vlan_filters = attr.vlan_filter_entries;
2511         priv->flags = 0;
2512 #if defined(RTE_LIBRTE_IEEE1588)
2513         priv->tx_conf_en = 1;
2514 #else
2515         priv->tx_conf_en = 0;
2516 #endif
2517
2518         /* Allocate memory for hardware structure for queues */
2519         ret = dpaa2_alloc_rx_tx_queues(eth_dev);
2520         if (ret) {
2521                 DPAA2_PMD_ERR("Queue allocation Failed");
2522                 goto init_err;
2523         }
2524
2525         /* Allocate memory for storing MAC addresses.
2526          * Table of mac_filter_entries size is allocated so that RTE ether lib
2527          * can add MAC entries when rte_eth_dev_mac_addr_add is called.
2528          */
2529         eth_dev->data->mac_addrs = rte_zmalloc("dpni",
2530                 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries, 0);
2531         if (eth_dev->data->mac_addrs == NULL) {
2532                 DPAA2_PMD_ERR(
2533                    "Failed to allocate %d bytes needed to store MAC addresses",
2534                    RTE_ETHER_ADDR_LEN * attr.mac_filter_entries);
2535                 ret = -ENOMEM;
2536                 goto init_err;
2537         }
2538
2539         ret = populate_mac_addr(dpni_dev, priv, &eth_dev->data->mac_addrs[0]);
2540         if (ret) {
2541                 DPAA2_PMD_ERR("Unable to fetch MAC Address for device");
2542                 rte_free(eth_dev->data->mac_addrs);
2543                 eth_dev->data->mac_addrs = NULL;
2544                 goto init_err;
2545         }
2546
2547         /* ... tx buffer layout ... */
2548         memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2549         if (priv->tx_conf_en) {
2550                 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
2551                                  DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2552                 layout.pass_timestamp = true;
2553         } else {
2554                 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2555         }
2556         layout.pass_frame_status = 1;
2557         ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2558                                      DPNI_QUEUE_TX, &layout);
2559         if (ret) {
2560                 DPAA2_PMD_ERR("Error (%d) in setting tx buffer layout", ret);
2561                 goto init_err;
2562         }
2563
2564         /* ... tx-conf and error buffer layout ... */
2565         memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2566         if (priv->tx_conf_en) {
2567                 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
2568                                  DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2569                 layout.pass_timestamp = true;
2570         } else {
2571                 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2572         }
2573         layout.pass_frame_status = 1;
2574         ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2575                                      DPNI_QUEUE_TX_CONFIRM, &layout);
2576         if (ret) {
2577                 DPAA2_PMD_ERR("Error (%d) in setting tx-conf buffer layout",
2578                              ret);
2579                 goto init_err;
2580         }
2581
2582         eth_dev->dev_ops = &dpaa2_ethdev_ops;
2583
2584         if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE)) {
2585                 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2586                 DPAA2_PMD_INFO("Loopback mode");
2587         } else if (dpaa2_get_devargs(dev->devargs, DRIVER_NO_PREFETCH_MODE)) {
2588                 eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2589                 DPAA2_PMD_INFO("No Prefetch mode");
2590         } else {
2591                 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2592         }
2593         eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2594
2595         /*Init fields w.r.t. classficaition*/
2596         memset(&priv->extract.qos_key_extract, 0,
2597                 sizeof(struct dpaa2_key_extract));
2598         priv->extract.qos_extract_param = (size_t)rte_malloc(NULL, 256, 64);
2599         if (!priv->extract.qos_extract_param) {
2600                 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow "
2601                             " classificaiton ", ret);
2602                 goto init_err;
2603         }
2604         priv->extract.qos_key_extract.key_info.ipv4_src_offset =
2605                 IP_ADDRESS_OFFSET_INVALID;
2606         priv->extract.qos_key_extract.key_info.ipv4_dst_offset =
2607                 IP_ADDRESS_OFFSET_INVALID;
2608         priv->extract.qos_key_extract.key_info.ipv6_src_offset =
2609                 IP_ADDRESS_OFFSET_INVALID;
2610         priv->extract.qos_key_extract.key_info.ipv6_dst_offset =
2611                 IP_ADDRESS_OFFSET_INVALID;
2612
2613         for (i = 0; i < MAX_TCS; i++) {
2614                 memset(&priv->extract.tc_key_extract[i], 0,
2615                         sizeof(struct dpaa2_key_extract));
2616                 priv->extract.tc_extract_param[i] =
2617                         (size_t)rte_malloc(NULL, 256, 64);
2618                 if (!priv->extract.tc_extract_param[i]) {
2619                         DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow classificaiton",
2620                                      ret);
2621                         goto init_err;
2622                 }
2623                 priv->extract.tc_key_extract[i].key_info.ipv4_src_offset =
2624                         IP_ADDRESS_OFFSET_INVALID;
2625                 priv->extract.tc_key_extract[i].key_info.ipv4_dst_offset =
2626                         IP_ADDRESS_OFFSET_INVALID;
2627                 priv->extract.tc_key_extract[i].key_info.ipv6_src_offset =
2628                         IP_ADDRESS_OFFSET_INVALID;
2629                 priv->extract.tc_key_extract[i].key_info.ipv6_dst_offset =
2630                         IP_ADDRESS_OFFSET_INVALID;
2631         }
2632
2633         ret = dpni_set_max_frame_length(dpni_dev, CMD_PRI_LOW, priv->token,
2634                                         RTE_ETHER_MAX_LEN - RTE_ETHER_CRC_LEN
2635                                         + VLAN_TAG_SIZE);
2636         if (ret) {
2637                 DPAA2_PMD_ERR("Unable to set mtu. check config");
2638                 goto init_err;
2639         }
2640
2641         /*TODO To enable soft parser support DPAA2 driver needs to integrate
2642          * with external entity to receive byte code for software sequence
2643          * and same will be offload to the H/W using MC interface.
2644          * Currently it is assumed that DPAA2 driver has byte code by some
2645          * mean and same if offloaded to H/W.
2646          */
2647         if (getenv("DPAA2_ENABLE_SOFT_PARSER")) {
2648                 WRIOP_SS_INITIALIZER(priv);
2649                 ret = dpaa2_eth_load_wriop_soft_parser(priv, DPNI_SS_INGRESS);
2650                 if (ret < 0) {
2651                         DPAA2_PMD_ERR(" Error(%d) in loading softparser\n",
2652                                       ret);
2653                         return ret;
2654                 }
2655
2656                 ret = dpaa2_eth_enable_wriop_soft_parser(priv,
2657                                                          DPNI_SS_INGRESS);
2658                 if (ret < 0) {
2659                         DPAA2_PMD_ERR(" Error(%d) in enabling softparser\n",
2660                                       ret);
2661                         return ret;
2662                 }
2663         }
2664         RTE_LOG(INFO, PMD, "%s: netdev created\n", eth_dev->data->name);
2665         return 0;
2666 init_err:
2667         dpaa2_dev_uninit(eth_dev);
2668         return ret;
2669 }
2670
2671 static int
2672 dpaa2_dev_uninit(struct rte_eth_dev *eth_dev)
2673 {
2674         struct dpaa2_dev_priv *priv = eth_dev->data->dev_private;
2675         struct fsl_mc_io *dpni = (struct fsl_mc_io *)eth_dev->process_private;
2676         int i, ret;
2677
2678         PMD_INIT_FUNC_TRACE();
2679
2680         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2681                 return 0;
2682
2683         if (!dpni) {
2684                 DPAA2_PMD_WARN("Already closed or not started");
2685                 return -1;
2686         }
2687
2688         dpaa2_dev_close(eth_dev);
2689
2690         dpaa2_free_rx_tx_queues(eth_dev);
2691
2692         /* Close the device at underlying layer*/
2693         ret = dpni_close(dpni, CMD_PRI_LOW, priv->token);
2694         if (ret) {
2695                 DPAA2_PMD_ERR(
2696                              "Failure closing dpni device with err code %d",
2697                              ret);
2698         }
2699
2700         /* Free the allocated memory for ethernet private data and dpni*/
2701         priv->hw = NULL;
2702         eth_dev->process_private = NULL;
2703         rte_free(dpni);
2704
2705         for (i = 0; i < MAX_TCS; i++)
2706                 rte_free((void *)(size_t)priv->extract.tc_extract_param[i]);
2707
2708         if (priv->extract.qos_extract_param)
2709                 rte_free((void *)(size_t)priv->extract.qos_extract_param);
2710
2711         eth_dev->dev_ops = NULL;
2712         eth_dev->rx_pkt_burst = NULL;
2713         eth_dev->tx_pkt_burst = NULL;
2714
2715         DPAA2_PMD_INFO("%s: netdev deleted", eth_dev->data->name);
2716         return 0;
2717 }
2718
2719 static int
2720 rte_dpaa2_probe(struct rte_dpaa2_driver *dpaa2_drv,
2721                 struct rte_dpaa2_device *dpaa2_dev)
2722 {
2723         struct rte_eth_dev *eth_dev;
2724         struct dpaa2_dev_priv *dev_priv;
2725         int diag;
2726
2727         if ((DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE) >
2728                 RTE_PKTMBUF_HEADROOM) {
2729                 DPAA2_PMD_ERR(
2730                 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA2 Annotation req(%d)",
2731                 RTE_PKTMBUF_HEADROOM,
2732                 DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE);
2733
2734                 return -1;
2735         }
2736
2737         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2738                 eth_dev = rte_eth_dev_allocate(dpaa2_dev->device.name);
2739                 if (!eth_dev)
2740                         return -ENODEV;
2741                 dev_priv = rte_zmalloc("ethdev private structure",
2742                                        sizeof(struct dpaa2_dev_priv),
2743                                        RTE_CACHE_LINE_SIZE);
2744                 if (dev_priv == NULL) {
2745                         DPAA2_PMD_CRIT(
2746                                 "Unable to allocate memory for private data");
2747                         rte_eth_dev_release_port(eth_dev);
2748                         return -ENOMEM;
2749                 }
2750                 eth_dev->data->dev_private = (void *)dev_priv;
2751                 /* Store a pointer to eth_dev in dev_private */
2752                 dev_priv->eth_dev = eth_dev;
2753                 dev_priv->tx_conf_en = 0;
2754         } else {
2755                 eth_dev = rte_eth_dev_attach_secondary(dpaa2_dev->device.name);
2756                 if (!eth_dev) {
2757                         DPAA2_PMD_DEBUG("returning enodev");
2758                         return -ENODEV;
2759                 }
2760         }
2761
2762         eth_dev->device = &dpaa2_dev->device;
2763
2764         dpaa2_dev->eth_dev = eth_dev;
2765         eth_dev->data->rx_mbuf_alloc_failed = 0;
2766
2767         if (dpaa2_drv->drv_flags & RTE_DPAA2_DRV_INTR_LSC)
2768                 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;
2769
2770         /* Invoke PMD device initialization function */
2771         diag = dpaa2_dev_init(eth_dev);
2772         if (diag == 0) {
2773                 rte_eth_dev_probing_finish(eth_dev);
2774                 return 0;
2775         }
2776
2777         rte_eth_dev_release_port(eth_dev);
2778         return diag;
2779 }
2780
2781 static int
2782 rte_dpaa2_remove(struct rte_dpaa2_device *dpaa2_dev)
2783 {
2784         struct rte_eth_dev *eth_dev;
2785
2786         eth_dev = dpaa2_dev->eth_dev;
2787         dpaa2_dev_uninit(eth_dev);
2788
2789         rte_eth_dev_release_port(eth_dev);
2790
2791         return 0;
2792 }
2793
2794 static struct rte_dpaa2_driver rte_dpaa2_pmd = {
2795         .drv_flags = RTE_DPAA2_DRV_INTR_LSC | RTE_DPAA2_DRV_IOVA_AS_VA,
2796         .drv_type = DPAA2_ETH,
2797         .probe = rte_dpaa2_probe,
2798         .remove = rte_dpaa2_remove,
2799 };
2800
2801 RTE_PMD_REGISTER_DPAA2(net_dpaa2, rte_dpaa2_pmd);
2802 RTE_PMD_REGISTER_PARAM_STRING(net_dpaa2,
2803                 DRIVER_LOOPBACK_MODE "=<int> "
2804                 DRIVER_NO_PREFETCH_MODE "=<int>");
2805 RTE_LOG_REGISTER(dpaa2_logtype_pmd, pmd.net.dpaa2, NOTICE);