1 /* * SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
4 * Copyright 2016-2020 NXP
12 #include <rte_ethdev_driver.h>
13 #include <rte_malloc.h>
14 #include <rte_memcpy.h>
15 #include <rte_string_fns.h>
16 #include <rte_cycles.h>
17 #include <rte_kvargs.h>
19 #include <rte_fslmc.h>
20 #include <rte_flow_driver.h>
22 #include "dpaa2_pmd_logs.h"
23 #include <fslmc_vfio.h>
24 #include <dpaa2_hw_pvt.h>
25 #include <dpaa2_hw_mempool.h>
26 #include <dpaa2_hw_dpio.h>
27 #include <mc/fsl_dpmng.h>
28 #include "dpaa2_ethdev.h"
29 #include "dpaa2_sparser.h"
30 #include <fsl_qbman_debug.h>
32 #define DRIVER_LOOPBACK_MODE "drv_loopback"
33 #define DRIVER_NO_PREFETCH_MODE "drv_no_prefetch"
35 /* Supported Rx offloads */
36 static uint64_t dev_rx_offloads_sup =
37 DEV_RX_OFFLOAD_CHECKSUM |
38 DEV_RX_OFFLOAD_SCTP_CKSUM |
39 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
40 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
41 DEV_RX_OFFLOAD_VLAN_STRIP |
42 DEV_RX_OFFLOAD_VLAN_FILTER |
43 DEV_RX_OFFLOAD_JUMBO_FRAME |
44 DEV_RX_OFFLOAD_TIMESTAMP;
46 /* Rx offloads which cannot be disabled */
47 static uint64_t dev_rx_offloads_nodis =
48 DEV_RX_OFFLOAD_RSS_HASH |
49 DEV_RX_OFFLOAD_SCATTER;
51 /* Supported Tx offloads */
52 static uint64_t dev_tx_offloads_sup =
53 DEV_TX_OFFLOAD_VLAN_INSERT |
54 DEV_TX_OFFLOAD_IPV4_CKSUM |
55 DEV_TX_OFFLOAD_UDP_CKSUM |
56 DEV_TX_OFFLOAD_TCP_CKSUM |
57 DEV_TX_OFFLOAD_SCTP_CKSUM |
58 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
59 DEV_TX_OFFLOAD_MT_LOCKFREE |
60 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
62 /* Tx offloads which cannot be disabled */
63 static uint64_t dev_tx_offloads_nodis =
64 DEV_TX_OFFLOAD_MULTI_SEGS;
66 /* enable timestamp in mbuf */
67 bool dpaa2_enable_ts[RTE_MAX_ETHPORTS];
69 struct rte_dpaa2_xstats_name_off {
70 char name[RTE_ETH_XSTATS_NAME_SIZE];
71 uint8_t page_id; /* dpni statistics page id */
72 uint8_t stats_id; /* stats id in the given page */
75 static const struct rte_dpaa2_xstats_name_off dpaa2_xstats_strings[] = {
76 {"ingress_multicast_frames", 0, 2},
77 {"ingress_multicast_bytes", 0, 3},
78 {"ingress_broadcast_frames", 0, 4},
79 {"ingress_broadcast_bytes", 0, 5},
80 {"egress_multicast_frames", 1, 2},
81 {"egress_multicast_bytes", 1, 3},
82 {"egress_broadcast_frames", 1, 4},
83 {"egress_broadcast_bytes", 1, 5},
84 {"ingress_filtered_frames", 2, 0},
85 {"ingress_discarded_frames", 2, 1},
86 {"ingress_nobuffer_discards", 2, 2},
87 {"egress_discarded_frames", 2, 3},
88 {"egress_confirmed_frames", 2, 4},
89 {"cgr_reject_frames", 4, 0},
90 {"cgr_reject_bytes", 4, 1},
93 static const enum rte_filter_op dpaa2_supported_filter_ops[] = {
95 RTE_ETH_FILTER_DELETE,
96 RTE_ETH_FILTER_UPDATE,
101 static struct rte_dpaa2_driver rte_dpaa2_pmd;
102 static int dpaa2_dev_link_update(struct rte_eth_dev *dev,
103 int wait_to_complete);
104 static int dpaa2_dev_set_link_up(struct rte_eth_dev *dev);
105 static int dpaa2_dev_set_link_down(struct rte_eth_dev *dev);
106 static int dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
109 dpaa2_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
112 struct dpaa2_dev_priv *priv = dev->data->dev_private;
113 struct fsl_mc_io *dpni = dev->process_private;
115 PMD_INIT_FUNC_TRACE();
118 DPAA2_PMD_ERR("dpni is NULL");
123 ret = dpni_add_vlan_id(dpni, CMD_PRI_LOW, priv->token,
126 ret = dpni_remove_vlan_id(dpni, CMD_PRI_LOW,
127 priv->token, vlan_id);
130 DPAA2_PMD_ERR("ret = %d Unable to add/rem vlan %d hwid =%d",
131 ret, vlan_id, priv->hw_id);
137 dpaa2_vlan_offload_set(struct rte_eth_dev *dev, int mask)
139 struct dpaa2_dev_priv *priv = dev->data->dev_private;
140 struct fsl_mc_io *dpni = dev->process_private;
143 PMD_INIT_FUNC_TRACE();
145 if (mask & ETH_VLAN_FILTER_MASK) {
146 /* VLAN Filter not avaialble */
147 if (!priv->max_vlan_filters) {
148 DPAA2_PMD_INFO("VLAN filter not available");
152 if (dev->data->dev_conf.rxmode.offloads &
153 DEV_RX_OFFLOAD_VLAN_FILTER)
154 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
157 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
160 DPAA2_PMD_INFO("Unable to set vlan filter = %d", ret);
167 dpaa2_vlan_tpid_set(struct rte_eth_dev *dev,
168 enum rte_vlan_type vlan_type __rte_unused,
171 struct dpaa2_dev_priv *priv = dev->data->dev_private;
172 struct fsl_mc_io *dpni = dev->process_private;
175 PMD_INIT_FUNC_TRACE();
177 /* nothing to be done for standard vlan tpids */
178 if (tpid == 0x8100 || tpid == 0x88A8)
181 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
184 DPAA2_PMD_INFO("Unable to set vlan tpid = %d", ret);
185 /* if already configured tpids, remove them first */
187 struct dpni_custom_tpid_cfg tpid_list = {0};
189 ret = dpni_get_custom_tpid(dpni, CMD_PRI_LOW,
190 priv->token, &tpid_list);
193 ret = dpni_remove_custom_tpid(dpni, CMD_PRI_LOW,
194 priv->token, tpid_list.tpid1);
197 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
205 dpaa2_fw_version_get(struct rte_eth_dev *dev,
210 struct fsl_mc_io *dpni = dev->process_private;
211 struct mc_soc_version mc_plat_info = {0};
212 struct mc_version mc_ver_info = {0};
214 PMD_INIT_FUNC_TRACE();
216 if (mc_get_soc_version(dpni, CMD_PRI_LOW, &mc_plat_info))
217 DPAA2_PMD_WARN("\tmc_get_soc_version failed");
219 if (mc_get_version(dpni, CMD_PRI_LOW, &mc_ver_info))
220 DPAA2_PMD_WARN("\tmc_get_version failed");
222 ret = snprintf(fw_version, fw_size,
227 mc_ver_info.revision);
229 ret += 1; /* add the size of '\0' */
230 if (fw_size < (uint32_t)ret)
237 dpaa2_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
239 struct dpaa2_dev_priv *priv = dev->data->dev_private;
241 PMD_INIT_FUNC_TRACE();
243 dev_info->max_mac_addrs = priv->max_mac_filters;
244 dev_info->max_rx_pktlen = DPAA2_MAX_RX_PKT_LEN;
245 dev_info->min_rx_bufsize = DPAA2_MIN_RX_BUF_SIZE;
246 dev_info->max_rx_queues = (uint16_t)priv->nb_rx_queues;
247 dev_info->max_tx_queues = (uint16_t)priv->nb_tx_queues;
248 dev_info->rx_offload_capa = dev_rx_offloads_sup |
249 dev_rx_offloads_nodis;
250 dev_info->tx_offload_capa = dev_tx_offloads_sup |
251 dev_tx_offloads_nodis;
252 dev_info->speed_capa = ETH_LINK_SPEED_1G |
253 ETH_LINK_SPEED_2_5G |
256 dev_info->max_hash_mac_addrs = 0;
257 dev_info->max_vfs = 0;
258 dev_info->max_vmdq_pools = ETH_16_POOLS;
259 dev_info->flow_type_rss_offloads = DPAA2_RSS_OFFLOAD_ALL;
261 dev_info->default_rxportconf.burst_size = dpaa2_dqrr_size;
262 /* same is rx size for best perf */
263 dev_info->default_txportconf.burst_size = dpaa2_dqrr_size;
265 dev_info->default_rxportconf.nb_queues = 1;
266 dev_info->default_txportconf.nb_queues = 1;
267 dev_info->default_txportconf.ring_size = CONG_ENTER_TX_THRESHOLD;
268 dev_info->default_rxportconf.ring_size = DPAA2_RX_DEFAULT_NBDESC;
270 if (dpaa2_svr_family == SVR_LX2160A) {
271 dev_info->speed_capa |= ETH_LINK_SPEED_25G |
281 dpaa2_dev_rx_burst_mode_get(struct rte_eth_dev *dev,
282 __rte_unused uint16_t queue_id,
283 struct rte_eth_burst_mode *mode)
285 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
288 const struct burst_info {
291 } rx_offload_map[] = {
292 {DEV_RX_OFFLOAD_CHECKSUM, " Checksum,"},
293 {DEV_RX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
294 {DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
295 {DEV_RX_OFFLOAD_OUTER_UDP_CKSUM, " Outer UDP csum,"},
296 {DEV_RX_OFFLOAD_VLAN_STRIP, " VLAN strip,"},
297 {DEV_RX_OFFLOAD_VLAN_FILTER, " VLAN filter,"},
298 {DEV_RX_OFFLOAD_JUMBO_FRAME, " Jumbo frame,"},
299 {DEV_RX_OFFLOAD_TIMESTAMP, " Timestamp,"},
300 {DEV_RX_OFFLOAD_RSS_HASH, " RSS,"},
301 {DEV_RX_OFFLOAD_SCATTER, " Scattered,"}
304 /* Update Rx offload info */
305 for (i = 0; i < RTE_DIM(rx_offload_map); i++) {
306 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) {
307 snprintf(mode->info, sizeof(mode->info), "%s",
308 rx_offload_map[i].output);
317 dpaa2_dev_tx_burst_mode_get(struct rte_eth_dev *dev,
318 __rte_unused uint16_t queue_id,
319 struct rte_eth_burst_mode *mode)
321 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
324 const struct burst_info {
327 } tx_offload_map[] = {
328 {DEV_TX_OFFLOAD_VLAN_INSERT, " VLAN Insert,"},
329 {DEV_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"},
330 {DEV_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"},
331 {DEV_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"},
332 {DEV_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
333 {DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
334 {DEV_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"},
335 {DEV_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"},
336 {DEV_TX_OFFLOAD_MULTI_SEGS, " Scattered,"}
339 /* Update Tx offload info */
340 for (i = 0; i < RTE_DIM(tx_offload_map); i++) {
341 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) {
342 snprintf(mode->info, sizeof(mode->info), "%s",
343 tx_offload_map[i].output);
352 dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev)
354 struct dpaa2_dev_priv *priv = dev->data->dev_private;
357 uint8_t num_rxqueue_per_tc;
358 struct dpaa2_queue *mc_q, *mcq;
361 struct dpaa2_queue *dpaa2_q;
363 PMD_INIT_FUNC_TRACE();
365 num_rxqueue_per_tc = (priv->nb_rx_queues / priv->num_rx_tc);
366 if (priv->tx_conf_en)
367 tot_queues = priv->nb_rx_queues + 2 * priv->nb_tx_queues;
369 tot_queues = priv->nb_rx_queues + priv->nb_tx_queues;
370 mc_q = rte_malloc(NULL, sizeof(struct dpaa2_queue) * tot_queues,
371 RTE_CACHE_LINE_SIZE);
373 DPAA2_PMD_ERR("Memory allocation failed for rx/tx queues");
377 for (i = 0; i < priv->nb_rx_queues; i++) {
378 mc_q->eth_data = dev->data;
379 priv->rx_vq[i] = mc_q++;
380 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
381 dpaa2_q->q_storage = rte_malloc("dq_storage",
382 sizeof(struct queue_storage_info_t),
383 RTE_CACHE_LINE_SIZE);
384 if (!dpaa2_q->q_storage)
387 memset(dpaa2_q->q_storage, 0,
388 sizeof(struct queue_storage_info_t));
389 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
393 for (i = 0; i < priv->nb_tx_queues; i++) {
394 mc_q->eth_data = dev->data;
395 mc_q->flow_id = 0xffff;
396 priv->tx_vq[i] = mc_q++;
397 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
398 dpaa2_q->cscn = rte_malloc(NULL,
399 sizeof(struct qbman_result), 16);
404 if (priv->tx_conf_en) {
405 /*Setup tx confirmation queues*/
406 for (i = 0; i < priv->nb_tx_queues; i++) {
407 mc_q->eth_data = dev->data;
410 priv->tx_conf_vq[i] = mc_q++;
411 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
413 rte_malloc("dq_storage",
414 sizeof(struct queue_storage_info_t),
415 RTE_CACHE_LINE_SIZE);
416 if (!dpaa2_q->q_storage)
419 memset(dpaa2_q->q_storage, 0,
420 sizeof(struct queue_storage_info_t));
421 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
427 for (dist_idx = 0; dist_idx < priv->nb_rx_queues; dist_idx++) {
428 mcq = (struct dpaa2_queue *)priv->rx_vq[vq_id];
429 mcq->tc_index = dist_idx / num_rxqueue_per_tc;
430 mcq->flow_id = dist_idx % num_rxqueue_per_tc;
438 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
439 rte_free(dpaa2_q->q_storage);
440 priv->tx_conf_vq[i--] = NULL;
442 i = priv->nb_tx_queues;
446 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
447 rte_free(dpaa2_q->cscn);
448 priv->tx_vq[i--] = NULL;
450 i = priv->nb_rx_queues;
453 mc_q = priv->rx_vq[0];
455 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
456 dpaa2_free_dq_storage(dpaa2_q->q_storage);
457 rte_free(dpaa2_q->q_storage);
458 priv->rx_vq[i--] = NULL;
465 dpaa2_free_rx_tx_queues(struct rte_eth_dev *dev)
467 struct dpaa2_dev_priv *priv = dev->data->dev_private;
468 struct dpaa2_queue *dpaa2_q;
471 PMD_INIT_FUNC_TRACE();
473 /* Queue allocation base */
474 if (priv->rx_vq[0]) {
475 /* cleaning up queue storage */
476 for (i = 0; i < priv->nb_rx_queues; i++) {
477 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
478 if (dpaa2_q->q_storage)
479 rte_free(dpaa2_q->q_storage);
481 /* cleanup tx queue cscn */
482 for (i = 0; i < priv->nb_tx_queues; i++) {
483 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
484 rte_free(dpaa2_q->cscn);
486 if (priv->tx_conf_en) {
487 /* cleanup tx conf queue storage */
488 for (i = 0; i < priv->nb_tx_queues; i++) {
489 dpaa2_q = (struct dpaa2_queue *)
491 rte_free(dpaa2_q->q_storage);
494 /*free memory for all queues (RX+TX) */
495 rte_free(priv->rx_vq[0]);
496 priv->rx_vq[0] = NULL;
501 dpaa2_eth_dev_configure(struct rte_eth_dev *dev)
503 struct dpaa2_dev_priv *priv = dev->data->dev_private;
504 struct fsl_mc_io *dpni = dev->process_private;
505 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
506 uint64_t rx_offloads = eth_conf->rxmode.offloads;
507 uint64_t tx_offloads = eth_conf->txmode.offloads;
508 int rx_l3_csum_offload = false;
509 int rx_l4_csum_offload = false;
510 int tx_l3_csum_offload = false;
511 int tx_l4_csum_offload = false;
514 PMD_INIT_FUNC_TRACE();
516 /* Rx offloads which are enabled by default */
517 if (dev_rx_offloads_nodis & ~rx_offloads) {
519 "Some of rx offloads enabled by default - requested 0x%" PRIx64
520 " fixed are 0x%" PRIx64,
521 rx_offloads, dev_rx_offloads_nodis);
524 /* Tx offloads which are enabled by default */
525 if (dev_tx_offloads_nodis & ~tx_offloads) {
527 "Some of tx offloads enabled by default - requested 0x%" PRIx64
528 " fixed are 0x%" PRIx64,
529 tx_offloads, dev_tx_offloads_nodis);
532 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
533 if (eth_conf->rxmode.max_rx_pkt_len <= DPAA2_MAX_RX_PKT_LEN) {
534 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW,
535 priv->token, eth_conf->rxmode.max_rx_pkt_len
536 - RTE_ETHER_CRC_LEN);
539 "Unable to set mtu. check config");
543 dev->data->dev_conf.rxmode.max_rx_pkt_len -
544 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN -
551 if (eth_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) {
552 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
553 ret = dpaa2_setup_flow_dist(dev,
554 eth_conf->rx_adv_conf.rss_conf.rss_hf,
558 "Unable to set flow distribution on tc%d."
559 "Check queue config", tc_index);
565 if (rx_offloads & DEV_RX_OFFLOAD_IPV4_CKSUM)
566 rx_l3_csum_offload = true;
568 if ((rx_offloads & DEV_RX_OFFLOAD_UDP_CKSUM) ||
569 (rx_offloads & DEV_RX_OFFLOAD_TCP_CKSUM) ||
570 (rx_offloads & DEV_RX_OFFLOAD_SCTP_CKSUM))
571 rx_l4_csum_offload = true;
573 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
574 DPNI_OFF_RX_L3_CSUM, rx_l3_csum_offload);
576 DPAA2_PMD_ERR("Error to set RX l3 csum:Error = %d", ret);
580 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
581 DPNI_OFF_RX_L4_CSUM, rx_l4_csum_offload);
583 DPAA2_PMD_ERR("Error to get RX l4 csum:Error = %d", ret);
587 #if !defined(RTE_LIBRTE_IEEE1588)
588 if (rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP)
590 dpaa2_enable_ts[dev->data->port_id] = true;
592 if (tx_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)
593 tx_l3_csum_offload = true;
595 if ((tx_offloads & DEV_TX_OFFLOAD_UDP_CKSUM) ||
596 (tx_offloads & DEV_TX_OFFLOAD_TCP_CKSUM) ||
597 (tx_offloads & DEV_TX_OFFLOAD_SCTP_CKSUM))
598 tx_l4_csum_offload = true;
600 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
601 DPNI_OFF_TX_L3_CSUM, tx_l3_csum_offload);
603 DPAA2_PMD_ERR("Error to set TX l3 csum:Error = %d", ret);
607 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
608 DPNI_OFF_TX_L4_CSUM, tx_l4_csum_offload);
610 DPAA2_PMD_ERR("Error to get TX l4 csum:Error = %d", ret);
614 /* Enabling hash results in FD requires setting DPNI_FLCTYPE_HASH in
615 * dpni_set_offload API. Setting this FLCTYPE for DPNI sets the FD[SC]
616 * to 0 for LS2 in the hardware thus disabling data/annotation
617 * stashing. For LX2 this is fixed in hardware and thus hash result and
618 * parse results can be received in FD using this option.
620 if (dpaa2_svr_family == SVR_LX2160A) {
621 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
622 DPNI_FLCTYPE_HASH, true);
624 DPAA2_PMD_ERR("Error setting FLCTYPE: Err = %d", ret);
629 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
630 dpaa2_vlan_offload_set(dev, ETH_VLAN_FILTER_MASK);
635 /* Function to setup RX flow information. It contains traffic class ID,
636 * flow ID, destination configuration etc.
639 dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev,
640 uint16_t rx_queue_id,
642 unsigned int socket_id __rte_unused,
643 const struct rte_eth_rxconf *rx_conf,
644 struct rte_mempool *mb_pool)
646 struct dpaa2_dev_priv *priv = dev->data->dev_private;
647 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
648 struct dpaa2_queue *dpaa2_q;
649 struct dpni_queue cfg;
655 PMD_INIT_FUNC_TRACE();
657 DPAA2_PMD_DEBUG("dev =%p, queue =%d, pool = %p, conf =%p",
658 dev, rx_queue_id, mb_pool, rx_conf);
660 /* Rx deferred start is not supported */
661 if (rx_conf->rx_deferred_start) {
662 DPAA2_PMD_ERR("%p:Rx deferred start not supported",
667 if (!priv->bp_list || priv->bp_list->mp != mb_pool) {
668 bpid = mempool_to_bpid(mb_pool);
669 ret = dpaa2_attach_bp_list(priv,
670 rte_dpaa2_bpid_info[bpid].bp_list);
674 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];
675 dpaa2_q->mb_pool = mb_pool; /**< mbuf pool to populate RX ring. */
676 dpaa2_q->bp_array = rte_dpaa2_bpid_info;
677 dpaa2_q->nb_desc = UINT16_MAX;
678 dpaa2_q->offloads = rx_conf->offloads;
680 /*Get the flow id from given VQ id*/
681 flow_id = dpaa2_q->flow_id;
682 memset(&cfg, 0, sizeof(struct dpni_queue));
684 options = options | DPNI_QUEUE_OPT_USER_CTX;
685 cfg.user_context = (size_t)(dpaa2_q);
687 /* check if a private cgr available. */
688 for (i = 0; i < priv->max_cgs; i++) {
689 if (!priv->cgid_in_use[i]) {
690 priv->cgid_in_use[i] = 1;
695 if (i < priv->max_cgs) {
696 options |= DPNI_QUEUE_OPT_SET_CGID;
698 dpaa2_q->cgid = cfg.cgid;
700 dpaa2_q->cgid = 0xff;
703 /*if ls2088 or rev2 device, enable the stashing */
705 if ((dpaa2_svr_family & 0xffff0000) != SVR_LS2080A) {
706 options |= DPNI_QUEUE_OPT_FLC;
707 cfg.flc.stash_control = true;
708 cfg.flc.value &= 0xFFFFFFFFFFFFFFC0;
709 /* 00 00 00 - last 6 bit represent annotation, context stashing,
710 * data stashing setting 01 01 00 (0x14)
711 * (in following order ->DS AS CS)
712 * to enable 1 line data, 1 line annotation.
713 * For LX2, this setting should be 01 00 00 (0x10)
715 if ((dpaa2_svr_family & 0xffff0000) == SVR_LX2160A)
716 cfg.flc.value |= 0x10;
718 cfg.flc.value |= 0x14;
720 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_RX,
721 dpaa2_q->tc_index, flow_id, options, &cfg);
723 DPAA2_PMD_ERR("Error in setting the rx flow: = %d", ret);
727 if (!(priv->flags & DPAA2_RX_TAILDROP_OFF)) {
728 struct dpni_taildrop taildrop;
731 dpaa2_q->nb_desc = nb_rx_desc;
732 /* Private CGR will use tail drop length as nb_rx_desc.
733 * for rest cases we can use standard byte based tail drop.
734 * There is no HW restriction, but number of CGRs are limited,
735 * hence this restriction is placed.
737 if (dpaa2_q->cgid != 0xff) {
738 /*enabling per rx queue congestion control */
739 taildrop.threshold = nb_rx_desc;
740 taildrop.units = DPNI_CONGESTION_UNIT_FRAMES;
742 DPAA2_PMD_DEBUG("Enabling CG Tail Drop on queue = %d",
744 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
745 DPNI_CP_CONGESTION_GROUP,
748 dpaa2_q->cgid, &taildrop);
750 /*enabling per rx queue congestion control */
751 taildrop.threshold = CONG_THRESHOLD_RX_BYTES_Q;
752 taildrop.units = DPNI_CONGESTION_UNIT_BYTES;
753 taildrop.oal = CONG_RX_OAL;
754 DPAA2_PMD_DEBUG("Enabling Byte based Drop on queue= %d",
756 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
757 DPNI_CP_QUEUE, DPNI_QUEUE_RX,
758 dpaa2_q->tc_index, flow_id,
762 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
766 } else { /* Disable tail Drop */
767 struct dpni_taildrop taildrop = {0};
768 DPAA2_PMD_INFO("Tail drop is disabled on queue");
771 if (dpaa2_q->cgid != 0xff) {
772 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
773 DPNI_CP_CONGESTION_GROUP, DPNI_QUEUE_RX,
775 dpaa2_q->cgid, &taildrop);
777 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
778 DPNI_CP_QUEUE, DPNI_QUEUE_RX,
779 dpaa2_q->tc_index, flow_id, &taildrop);
782 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
788 dev->data->rx_queues[rx_queue_id] = dpaa2_q;
793 dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev,
794 uint16_t tx_queue_id,
796 unsigned int socket_id __rte_unused,
797 const struct rte_eth_txconf *tx_conf)
799 struct dpaa2_dev_priv *priv = dev->data->dev_private;
800 struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)
801 priv->tx_vq[tx_queue_id];
802 struct dpaa2_queue *dpaa2_tx_conf_q = (struct dpaa2_queue *)
803 priv->tx_conf_vq[tx_queue_id];
804 struct fsl_mc_io *dpni = dev->process_private;
805 struct dpni_queue tx_conf_cfg;
806 struct dpni_queue tx_flow_cfg;
807 uint8_t options = 0, flow_id;
808 struct dpni_queue_id qid;
812 PMD_INIT_FUNC_TRACE();
814 /* Tx deferred start is not supported */
815 if (tx_conf->tx_deferred_start) {
816 DPAA2_PMD_ERR("%p:Tx deferred start not supported",
821 dpaa2_q->nb_desc = UINT16_MAX;
822 dpaa2_q->offloads = tx_conf->offloads;
824 /* Return if queue already configured */
825 if (dpaa2_q->flow_id != 0xffff) {
826 dev->data->tx_queues[tx_queue_id] = dpaa2_q;
830 memset(&tx_conf_cfg, 0, sizeof(struct dpni_queue));
831 memset(&tx_flow_cfg, 0, sizeof(struct dpni_queue));
836 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_TX,
837 tc_id, flow_id, options, &tx_flow_cfg);
839 DPAA2_PMD_ERR("Error in setting the tx flow: "
840 "tc_id=%d, flow=%d err=%d",
841 tc_id, flow_id, ret);
845 dpaa2_q->flow_id = flow_id;
847 if (tx_queue_id == 0) {
848 /*Set tx-conf and error configuration*/
849 if (priv->tx_conf_en)
850 ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
854 ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
858 DPAA2_PMD_ERR("Error in set tx conf mode settings: "
863 dpaa2_q->tc_index = tc_id;
865 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
866 DPNI_QUEUE_TX, dpaa2_q->tc_index,
867 dpaa2_q->flow_id, &tx_flow_cfg, &qid);
869 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
872 dpaa2_q->fqid = qid.fqid;
874 if (!(priv->flags & DPAA2_TX_CGR_OFF)) {
875 struct dpni_congestion_notification_cfg cong_notif_cfg = {0};
877 dpaa2_q->nb_desc = nb_tx_desc;
879 cong_notif_cfg.units = DPNI_CONGESTION_UNIT_FRAMES;
880 cong_notif_cfg.threshold_entry = nb_tx_desc;
881 /* Notify that the queue is not congested when the data in
882 * the queue is below this thershold.
884 cong_notif_cfg.threshold_exit = nb_tx_desc - 24;
885 cong_notif_cfg.message_ctx = 0;
886 cong_notif_cfg.message_iova =
887 (size_t)DPAA2_VADDR_TO_IOVA(dpaa2_q->cscn);
888 cong_notif_cfg.dest_cfg.dest_type = DPNI_DEST_NONE;
889 cong_notif_cfg.notification_mode =
890 DPNI_CONG_OPT_WRITE_MEM_ON_ENTER |
891 DPNI_CONG_OPT_WRITE_MEM_ON_EXIT |
892 DPNI_CONG_OPT_COHERENT_WRITE;
893 cong_notif_cfg.cg_point = DPNI_CP_QUEUE;
895 ret = dpni_set_congestion_notification(dpni, CMD_PRI_LOW,
902 "Error in setting tx congestion notification: "
907 dpaa2_q->cb_eqresp_free = dpaa2_dev_free_eqresp_buf;
908 dev->data->tx_queues[tx_queue_id] = dpaa2_q;
910 if (priv->tx_conf_en) {
911 dpaa2_q->tx_conf_queue = dpaa2_tx_conf_q;
912 options = options | DPNI_QUEUE_OPT_USER_CTX;
913 tx_conf_cfg.user_context = (size_t)(dpaa2_q);
914 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
915 DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
916 dpaa2_tx_conf_q->flow_id, options, &tx_conf_cfg);
918 DPAA2_PMD_ERR("Error in setting the tx conf flow: "
919 "tc_index=%d, flow=%d err=%d",
920 dpaa2_tx_conf_q->tc_index,
921 dpaa2_tx_conf_q->flow_id, ret);
925 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
926 DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
927 dpaa2_tx_conf_q->flow_id, &tx_conf_cfg, &qid);
929 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
932 dpaa2_tx_conf_q->fqid = qid.fqid;
938 dpaa2_dev_rx_queue_release(void *q __rte_unused)
940 struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)q;
941 struct dpaa2_dev_priv *priv = dpaa2_q->eth_data->dev_private;
942 struct fsl_mc_io *dpni =
943 (struct fsl_mc_io *)priv->eth_dev->process_private;
946 struct dpni_queue cfg;
948 memset(&cfg, 0, sizeof(struct dpni_queue));
949 PMD_INIT_FUNC_TRACE();
950 if (dpaa2_q->cgid != 0xff) {
951 options = DPNI_QUEUE_OPT_CLEAR_CGID;
952 cfg.cgid = dpaa2_q->cgid;
954 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
956 dpaa2_q->tc_index, dpaa2_q->flow_id,
959 DPAA2_PMD_ERR("Unable to clear CGR from q=%u err=%d",
961 priv->cgid_in_use[dpaa2_q->cgid] = 0;
962 dpaa2_q->cgid = 0xff;
967 dpaa2_dev_tx_queue_release(void *q __rte_unused)
969 PMD_INIT_FUNC_TRACE();
973 dpaa2_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
976 struct dpaa2_dev_priv *priv = dev->data->dev_private;
977 struct dpaa2_queue *dpaa2_q;
978 struct qbman_swp *swp;
979 struct qbman_fq_query_np_rslt state;
980 uint32_t frame_cnt = 0;
982 if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
983 ret = dpaa2_affine_qbman_swp();
986 "Failed to allocate IO portal, tid: %d\n",
991 swp = DPAA2_PER_LCORE_PORTAL;
993 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];
995 if (qbman_fq_query_state(swp, dpaa2_q->fqid, &state) == 0) {
996 frame_cnt = qbman_fq_state_frame_count(&state);
997 DPAA2_PMD_DP_DEBUG("RX frame count for q(%d) is %u",
998 rx_queue_id, frame_cnt);
1003 static const uint32_t *
1004 dpaa2_supported_ptypes_get(struct rte_eth_dev *dev)
1006 static const uint32_t ptypes[] = {
1007 /*todo -= add more types */
1010 RTE_PTYPE_L3_IPV4_EXT,
1012 RTE_PTYPE_L3_IPV6_EXT,
1020 if (dev->rx_pkt_burst == dpaa2_dev_prefetch_rx ||
1021 dev->rx_pkt_burst == dpaa2_dev_rx ||
1022 dev->rx_pkt_burst == dpaa2_dev_loopback_rx)
1028 * Dpaa2 link Interrupt handler
1031 * The address of parameter (struct rte_eth_dev *) regsitered before.
1037 dpaa2_interrupt_handler(void *param)
1039 struct rte_eth_dev *dev = param;
1040 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1041 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1043 int irq_index = DPNI_IRQ_INDEX;
1044 unsigned int status = 0, clear = 0;
1046 PMD_INIT_FUNC_TRACE();
1049 DPAA2_PMD_ERR("dpni is NULL");
1053 ret = dpni_get_irq_status(dpni, CMD_PRI_LOW, priv->token,
1054 irq_index, &status);
1055 if (unlikely(ret)) {
1056 DPAA2_PMD_ERR("Can't get irq status (err %d)", ret);
1061 if (status & DPNI_IRQ_EVENT_LINK_CHANGED) {
1062 clear = DPNI_IRQ_EVENT_LINK_CHANGED;
1063 dpaa2_dev_link_update(dev, 0);
1064 /* calling all the apps registered for link status event */
1065 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1068 ret = dpni_clear_irq_status(dpni, CMD_PRI_LOW, priv->token,
1071 DPAA2_PMD_ERR("Can't clear irq status (err %d)", ret);
1075 dpaa2_eth_setup_irqs(struct rte_eth_dev *dev, int enable)
1078 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1079 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1080 int irq_index = DPNI_IRQ_INDEX;
1081 unsigned int mask = DPNI_IRQ_EVENT_LINK_CHANGED;
1083 PMD_INIT_FUNC_TRACE();
1085 err = dpni_set_irq_mask(dpni, CMD_PRI_LOW, priv->token,
1088 DPAA2_PMD_ERR("Error: dpni_set_irq_mask():%d (%s)", err,
1093 err = dpni_set_irq_enable(dpni, CMD_PRI_LOW, priv->token,
1096 DPAA2_PMD_ERR("Error: dpni_set_irq_enable():%d (%s)", err,
1103 dpaa2_dev_start(struct rte_eth_dev *dev)
1105 struct rte_device *rdev = dev->device;
1106 struct rte_dpaa2_device *dpaa2_dev;
1107 struct rte_eth_dev_data *data = dev->data;
1108 struct dpaa2_dev_priv *priv = data->dev_private;
1109 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1110 struct dpni_queue cfg;
1111 struct dpni_error_cfg err_cfg;
1113 struct dpni_queue_id qid;
1114 struct dpaa2_queue *dpaa2_q;
1116 struct rte_intr_handle *intr_handle;
1118 dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device);
1119 intr_handle = &dpaa2_dev->intr_handle;
1121 PMD_INIT_FUNC_TRACE();
1123 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1125 DPAA2_PMD_ERR("Failure in enabling dpni %d device: err=%d",
1130 /* Power up the phy. Needed to make the link go UP */
1131 dpaa2_dev_set_link_up(dev);
1133 ret = dpni_get_qdid(dpni, CMD_PRI_LOW, priv->token,
1134 DPNI_QUEUE_TX, &qdid);
1136 DPAA2_PMD_ERR("Error in getting qdid: err=%d", ret);
1141 for (i = 0; i < data->nb_rx_queues; i++) {
1142 dpaa2_q = (struct dpaa2_queue *)data->rx_queues[i];
1143 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
1144 DPNI_QUEUE_RX, dpaa2_q->tc_index,
1145 dpaa2_q->flow_id, &cfg, &qid);
1147 DPAA2_PMD_ERR("Error in getting flow information: "
1151 dpaa2_q->fqid = qid.fqid;
1154 /*checksum errors, send them to normal path and set it in annotation */
1155 err_cfg.errors = DPNI_ERROR_L3CE | DPNI_ERROR_L4CE;
1156 err_cfg.errors |= DPNI_ERROR_PHE;
1158 err_cfg.error_action = DPNI_ERROR_ACTION_CONTINUE;
1159 err_cfg.set_frame_annotation = true;
1161 ret = dpni_set_errors_behavior(dpni, CMD_PRI_LOW,
1162 priv->token, &err_cfg);
1164 DPAA2_PMD_ERR("Error to dpni_set_errors_behavior: code = %d",
1169 /* if the interrupts were configured on this devices*/
1170 if (intr_handle && (intr_handle->fd) &&
1171 (dev->data->dev_conf.intr_conf.lsc != 0)) {
1172 /* Registering LSC interrupt handler */
1173 rte_intr_callback_register(intr_handle,
1174 dpaa2_interrupt_handler,
1177 /* enable vfio intr/eventfd mapping
1178 * Interrupt index 0 is required, so we can not use
1181 rte_dpaa2_intr_enable(intr_handle, DPNI_IRQ_INDEX);
1183 /* enable dpni_irqs */
1184 dpaa2_eth_setup_irqs(dev, 1);
1187 /* Change the tx burst function if ordered queues are used */
1188 if (priv->en_ordered)
1189 dev->tx_pkt_burst = dpaa2_dev_tx_ordered;
1195 * This routine disables all traffic on the adapter by issuing a
1196 * global reset on the MAC.
1199 dpaa2_dev_stop(struct rte_eth_dev *dev)
1201 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1202 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1204 struct rte_eth_link link;
1205 struct rte_intr_handle *intr_handle = dev->intr_handle;
1207 PMD_INIT_FUNC_TRACE();
1209 /* reset interrupt callback */
1210 if (intr_handle && (intr_handle->fd) &&
1211 (dev->data->dev_conf.intr_conf.lsc != 0)) {
1212 /*disable dpni irqs */
1213 dpaa2_eth_setup_irqs(dev, 0);
1215 /* disable vfio intr before callback unregister */
1216 rte_dpaa2_intr_disable(intr_handle, DPNI_IRQ_INDEX);
1218 /* Unregistering LSC interrupt handler */
1219 rte_intr_callback_unregister(intr_handle,
1220 dpaa2_interrupt_handler,
1224 dpaa2_dev_set_link_down(dev);
1226 ret = dpni_disable(dpni, CMD_PRI_LOW, priv->token);
1228 DPAA2_PMD_ERR("Failure (ret %d) in disabling dpni %d dev",
1233 /* clear the recorded link status */
1234 memset(&link, 0, sizeof(link));
1235 rte_eth_linkstatus_set(dev, &link);
1239 dpaa2_dev_close(struct rte_eth_dev *dev)
1241 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1242 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1244 struct rte_eth_link link;
1246 PMD_INIT_FUNC_TRACE();
1248 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1252 DPAA2_PMD_WARN("Already closed or not started");
1256 dpaa2_flow_clean(dev);
1257 /* Clean the device first */
1258 ret = dpni_reset(dpni, CMD_PRI_LOW, priv->token);
1260 DPAA2_PMD_ERR("Failure cleaning dpni device: err=%d", ret);
1264 memset(&link, 0, sizeof(link));
1265 rte_eth_linkstatus_set(dev, &link);
1267 /* Free private queues memory */
1268 dpaa2_free_rx_tx_queues(dev);
1269 /* Close the device at underlying layer*/
1270 ret = dpni_close(dpni, CMD_PRI_LOW, priv->token);
1272 DPAA2_PMD_ERR("Failure closing dpni device with err code %d",
1276 /* Free the allocated memory for ethernet private data and dpni*/
1278 dev->process_private = NULL;
1281 for (i = 0; i < MAX_TCS; i++)
1282 rte_free((void *)(size_t)priv->extract.tc_extract_param[i]);
1284 if (priv->extract.qos_extract_param)
1285 rte_free((void *)(size_t)priv->extract.qos_extract_param);
1287 dev->dev_ops = NULL;
1288 dev->rx_pkt_burst = NULL;
1289 dev->tx_pkt_burst = NULL;
1291 DPAA2_PMD_INFO("%s: netdev deleted", dev->data->name);
1296 dpaa2_dev_promiscuous_enable(
1297 struct rte_eth_dev *dev)
1300 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1301 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1303 PMD_INIT_FUNC_TRACE();
1306 DPAA2_PMD_ERR("dpni is NULL");
1310 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1312 DPAA2_PMD_ERR("Unable to enable U promisc mode %d", ret);
1314 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1316 DPAA2_PMD_ERR("Unable to enable M promisc mode %d", ret);
1322 dpaa2_dev_promiscuous_disable(
1323 struct rte_eth_dev *dev)
1326 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1327 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1329 PMD_INIT_FUNC_TRACE();
1332 DPAA2_PMD_ERR("dpni is NULL");
1336 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1338 DPAA2_PMD_ERR("Unable to disable U promisc mode %d", ret);
1340 if (dev->data->all_multicast == 0) {
1341 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW,
1342 priv->token, false);
1344 DPAA2_PMD_ERR("Unable to disable M promisc mode %d",
1352 dpaa2_dev_allmulticast_enable(
1353 struct rte_eth_dev *dev)
1356 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1357 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1359 PMD_INIT_FUNC_TRACE();
1362 DPAA2_PMD_ERR("dpni is NULL");
1366 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1368 DPAA2_PMD_ERR("Unable to enable multicast mode %d", ret);
1374 dpaa2_dev_allmulticast_disable(struct rte_eth_dev *dev)
1377 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1378 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1380 PMD_INIT_FUNC_TRACE();
1383 DPAA2_PMD_ERR("dpni is NULL");
1387 /* must remain on for all promiscuous */
1388 if (dev->data->promiscuous == 1)
1391 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1393 DPAA2_PMD_ERR("Unable to disable multicast mode %d", ret);
1399 dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1402 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1403 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1404 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
1407 PMD_INIT_FUNC_TRACE();
1410 DPAA2_PMD_ERR("dpni is NULL");
1414 /* check that mtu is within the allowed range */
1415 if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA2_MAX_RX_PKT_LEN)
1418 if (frame_size > RTE_ETHER_MAX_LEN)
1419 dev->data->dev_conf.rxmode.offloads |=
1420 DEV_RX_OFFLOAD_JUMBO_FRAME;
1422 dev->data->dev_conf.rxmode.offloads &=
1423 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1425 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1427 /* Set the Max Rx frame length as 'mtu' +
1428 * Maximum Ethernet header length
1430 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, priv->token,
1431 frame_size - RTE_ETHER_CRC_LEN);
1433 DPAA2_PMD_ERR("Setting the max frame length failed");
1436 DPAA2_PMD_INFO("MTU configured for the device: %d", mtu);
1441 dpaa2_dev_add_mac_addr(struct rte_eth_dev *dev,
1442 struct rte_ether_addr *addr,
1443 __rte_unused uint32_t index,
1444 __rte_unused uint32_t pool)
1447 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1448 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1450 PMD_INIT_FUNC_TRACE();
1453 DPAA2_PMD_ERR("dpni is NULL");
1457 ret = dpni_add_mac_addr(dpni, CMD_PRI_LOW, priv->token,
1458 addr->addr_bytes, 0, 0, 0);
1461 "error: Adding the MAC ADDR failed: err = %d", ret);
1466 dpaa2_dev_remove_mac_addr(struct rte_eth_dev *dev,
1470 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1471 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1472 struct rte_eth_dev_data *data = dev->data;
1473 struct rte_ether_addr *macaddr;
1475 PMD_INIT_FUNC_TRACE();
1477 macaddr = &data->mac_addrs[index];
1480 DPAA2_PMD_ERR("dpni is NULL");
1484 ret = dpni_remove_mac_addr(dpni, CMD_PRI_LOW,
1485 priv->token, macaddr->addr_bytes);
1488 "error: Removing the MAC ADDR failed: err = %d", ret);
1492 dpaa2_dev_set_mac_addr(struct rte_eth_dev *dev,
1493 struct rte_ether_addr *addr)
1496 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1497 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1499 PMD_INIT_FUNC_TRACE();
1502 DPAA2_PMD_ERR("dpni is NULL");
1506 ret = dpni_set_primary_mac_addr(dpni, CMD_PRI_LOW,
1507 priv->token, addr->addr_bytes);
1511 "error: Setting the MAC ADDR failed %d", ret);
1517 int dpaa2_dev_stats_get(struct rte_eth_dev *dev,
1518 struct rte_eth_stats *stats)
1520 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1521 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1523 uint8_t page0 = 0, page1 = 1, page2 = 2;
1524 union dpni_statistics value;
1526 struct dpaa2_queue *dpaa2_rxq, *dpaa2_txq;
1528 memset(&value, 0, sizeof(union dpni_statistics));
1530 PMD_INIT_FUNC_TRACE();
1533 DPAA2_PMD_ERR("dpni is NULL");
1538 DPAA2_PMD_ERR("stats is NULL");
1542 /*Get Counters from page_0*/
1543 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1548 stats->ipackets = value.page_0.ingress_all_frames;
1549 stats->ibytes = value.page_0.ingress_all_bytes;
1551 /*Get Counters from page_1*/
1552 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1557 stats->opackets = value.page_1.egress_all_frames;
1558 stats->obytes = value.page_1.egress_all_bytes;
1560 /*Get Counters from page_2*/
1561 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1566 /* Ingress drop frame count due to configured rules */
1567 stats->ierrors = value.page_2.ingress_filtered_frames;
1568 /* Ingress drop frame count due to error */
1569 stats->ierrors += value.page_2.ingress_discarded_frames;
1571 stats->oerrors = value.page_2.egress_discarded_frames;
1572 stats->imissed = value.page_2.ingress_nobuffer_discards;
1574 /* Fill in per queue stats */
1575 for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) &&
1576 (i < priv->nb_rx_queues || i < priv->nb_tx_queues); ++i) {
1577 dpaa2_rxq = (struct dpaa2_queue *)priv->rx_vq[i];
1578 dpaa2_txq = (struct dpaa2_queue *)priv->tx_vq[i];
1580 stats->q_ipackets[i] = dpaa2_rxq->rx_pkts;
1582 stats->q_opackets[i] = dpaa2_txq->tx_pkts;
1584 /* Byte counting is not implemented */
1585 stats->q_ibytes[i] = 0;
1586 stats->q_obytes[i] = 0;
1592 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1597 dpaa2_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1600 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1601 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1603 union dpni_statistics value[5] = {};
1604 unsigned int i = 0, num = RTE_DIM(dpaa2_xstats_strings);
1612 /* Get Counters from page_0*/
1613 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1618 /* Get Counters from page_1*/
1619 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1624 /* Get Counters from page_2*/
1625 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1630 for (i = 0; i < priv->max_cgs; i++) {
1631 if (!priv->cgid_in_use[i]) {
1632 /* Get Counters from page_4*/
1633 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW,
1642 for (i = 0; i < num; i++) {
1644 xstats[i].value = value[dpaa2_xstats_strings[i].page_id].
1645 raw.counter[dpaa2_xstats_strings[i].stats_id];
1649 DPAA2_PMD_ERR("Error in obtaining extended stats (%d)", retcode);
1654 dpaa2_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1655 struct rte_eth_xstat_name *xstats_names,
1658 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1660 if (limit < stat_cnt)
1663 if (xstats_names != NULL)
1664 for (i = 0; i < stat_cnt; i++)
1665 strlcpy(xstats_names[i].name,
1666 dpaa2_xstats_strings[i].name,
1667 sizeof(xstats_names[i].name));
1673 dpaa2_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1674 uint64_t *values, unsigned int n)
1676 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1677 uint64_t values_copy[stat_cnt];
1680 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1681 struct fsl_mc_io *dpni =
1682 (struct fsl_mc_io *)dev->process_private;
1684 union dpni_statistics value[5] = {};
1692 /* Get Counters from page_0*/
1693 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1698 /* Get Counters from page_1*/
1699 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1704 /* Get Counters from page_2*/
1705 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1710 /* Get Counters from page_4*/
1711 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1716 for (i = 0; i < stat_cnt; i++) {
1717 values[i] = value[dpaa2_xstats_strings[i].page_id].
1718 raw.counter[dpaa2_xstats_strings[i].stats_id];
1723 dpaa2_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
1725 for (i = 0; i < n; i++) {
1726 if (ids[i] >= stat_cnt) {
1727 DPAA2_PMD_ERR("xstats id value isn't valid");
1730 values[i] = values_copy[ids[i]];
1736 dpaa2_xstats_get_names_by_id(
1737 struct rte_eth_dev *dev,
1738 struct rte_eth_xstat_name *xstats_names,
1739 const uint64_t *ids,
1742 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1743 struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
1746 return dpaa2_xstats_get_names(dev, xstats_names, limit);
1748 dpaa2_xstats_get_names(dev, xstats_names_copy, limit);
1750 for (i = 0; i < limit; i++) {
1751 if (ids[i] >= stat_cnt) {
1752 DPAA2_PMD_ERR("xstats id value isn't valid");
1755 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
1761 dpaa2_dev_stats_reset(struct rte_eth_dev *dev)
1763 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1764 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1767 struct dpaa2_queue *dpaa2_q;
1769 PMD_INIT_FUNC_TRACE();
1772 DPAA2_PMD_ERR("dpni is NULL");
1776 retcode = dpni_reset_statistics(dpni, CMD_PRI_LOW, priv->token);
1780 /* Reset the per queue stats in dpaa2_queue structure */
1781 for (i = 0; i < priv->nb_rx_queues; i++) {
1782 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
1784 dpaa2_q->rx_pkts = 0;
1787 for (i = 0; i < priv->nb_tx_queues; i++) {
1788 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
1790 dpaa2_q->tx_pkts = 0;
1796 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1800 /* return 0 means link status changed, -1 means not changed */
1802 dpaa2_dev_link_update(struct rte_eth_dev *dev,
1803 int wait_to_complete __rte_unused)
1806 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1807 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1808 struct rte_eth_link link;
1809 struct dpni_link_state state = {0};
1812 DPAA2_PMD_ERR("dpni is NULL");
1816 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1818 DPAA2_PMD_DEBUG("error: dpni_get_link_state %d", ret);
1822 memset(&link, 0, sizeof(struct rte_eth_link));
1823 link.link_status = state.up;
1824 link.link_speed = state.rate;
1826 if (state.options & DPNI_LINK_OPT_HALF_DUPLEX)
1827 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1829 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1831 ret = rte_eth_linkstatus_set(dev, &link);
1833 DPAA2_PMD_DEBUG("No change in status");
1835 DPAA2_PMD_INFO("Port %d Link is %s\n", dev->data->port_id,
1836 link.link_status ? "Up" : "Down");
1842 * Toggle the DPNI to enable, if not already enabled.
1843 * This is not strictly PHY up/down - it is more of logical toggling.
1846 dpaa2_dev_set_link_up(struct rte_eth_dev *dev)
1849 struct dpaa2_dev_priv *priv;
1850 struct fsl_mc_io *dpni;
1852 struct dpni_link_state state = {0};
1854 priv = dev->data->dev_private;
1855 dpni = (struct fsl_mc_io *)dev->process_private;
1858 DPAA2_PMD_ERR("dpni is NULL");
1862 /* Check if DPNI is currently enabled */
1863 ret = dpni_is_enabled(dpni, CMD_PRI_LOW, priv->token, &en);
1865 /* Unable to obtain dpni status; Not continuing */
1866 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1870 /* Enable link if not already enabled */
1872 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1874 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1878 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1880 DPAA2_PMD_DEBUG("Unable to get link state (%d)", ret);
1884 /* changing tx burst function to start enqueues */
1885 dev->tx_pkt_burst = dpaa2_dev_tx;
1886 dev->data->dev_link.link_status = state.up;
1887 dev->data->dev_link.link_speed = state.rate;
1890 DPAA2_PMD_INFO("Port %d Link is Up", dev->data->port_id);
1892 DPAA2_PMD_INFO("Port %d Link is Down", dev->data->port_id);
1897 * Toggle the DPNI to disable, if not already disabled.
1898 * This is not strictly PHY up/down - it is more of logical toggling.
1901 dpaa2_dev_set_link_down(struct rte_eth_dev *dev)
1904 struct dpaa2_dev_priv *priv;
1905 struct fsl_mc_io *dpni;
1906 int dpni_enabled = 0;
1909 PMD_INIT_FUNC_TRACE();
1911 priv = dev->data->dev_private;
1912 dpni = (struct fsl_mc_io *)dev->process_private;
1915 DPAA2_PMD_ERR("Device has not yet been configured");
1919 /*changing tx burst function to avoid any more enqueues */
1920 dev->tx_pkt_burst = dummy_dev_tx;
1922 /* Loop while dpni_disable() attempts to drain the egress FQs
1923 * and confirm them back to us.
1926 ret = dpni_disable(dpni, 0, priv->token);
1928 DPAA2_PMD_ERR("dpni disable failed (%d)", ret);
1931 ret = dpni_is_enabled(dpni, 0, priv->token, &dpni_enabled);
1933 DPAA2_PMD_ERR("dpni enable check failed (%d)", ret);
1937 /* Allow the MC some slack */
1938 rte_delay_us(100 * 1000);
1939 } while (dpni_enabled && --retries);
1942 DPAA2_PMD_WARN("Retry count exceeded disabling dpni");
1943 /* todo- we may have to manually cleanup queues.
1946 DPAA2_PMD_INFO("Port %d Link DOWN successful",
1947 dev->data->port_id);
1950 dev->data->dev_link.link_status = 0;
1956 dpaa2_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1959 struct dpaa2_dev_priv *priv;
1960 struct fsl_mc_io *dpni;
1961 struct dpni_link_state state = {0};
1963 PMD_INIT_FUNC_TRACE();
1965 priv = dev->data->dev_private;
1966 dpni = (struct fsl_mc_io *)dev->process_private;
1968 if (dpni == NULL || fc_conf == NULL) {
1969 DPAA2_PMD_ERR("device not configured");
1973 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1975 DPAA2_PMD_ERR("error: dpni_get_link_state %d", ret);
1979 memset(fc_conf, 0, sizeof(struct rte_eth_fc_conf));
1980 if (state.options & DPNI_LINK_OPT_PAUSE) {
1981 /* DPNI_LINK_OPT_PAUSE set
1982 * if ASYM_PAUSE not set,
1983 * RX Side flow control (handle received Pause frame)
1984 * TX side flow control (send Pause frame)
1985 * if ASYM_PAUSE set,
1986 * RX Side flow control (handle received Pause frame)
1987 * No TX side flow control (send Pause frame disabled)
1989 if (!(state.options & DPNI_LINK_OPT_ASYM_PAUSE))
1990 fc_conf->mode = RTE_FC_FULL;
1992 fc_conf->mode = RTE_FC_RX_PAUSE;
1994 /* DPNI_LINK_OPT_PAUSE not set
1995 * if ASYM_PAUSE set,
1996 * TX side flow control (send Pause frame)
1997 * No RX side flow control (No action on pause frame rx)
1998 * if ASYM_PAUSE not set,
1999 * Flow control disabled
2001 if (state.options & DPNI_LINK_OPT_ASYM_PAUSE)
2002 fc_conf->mode = RTE_FC_TX_PAUSE;
2004 fc_conf->mode = RTE_FC_NONE;
2011 dpaa2_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2014 struct dpaa2_dev_priv *priv;
2015 struct fsl_mc_io *dpni;
2016 struct dpni_link_state state = {0};
2017 struct dpni_link_cfg cfg = {0};
2019 PMD_INIT_FUNC_TRACE();
2021 priv = dev->data->dev_private;
2022 dpni = (struct fsl_mc_io *)dev->process_private;
2025 DPAA2_PMD_ERR("dpni is NULL");
2029 /* It is necessary to obtain the current state before setting fc_conf
2030 * as MC would return error in case rate, autoneg or duplex values are
2033 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
2035 DPAA2_PMD_ERR("Unable to get link state (err=%d)", ret);
2039 /* Disable link before setting configuration */
2040 dpaa2_dev_set_link_down(dev);
2042 /* Based on fc_conf, update cfg */
2043 cfg.rate = state.rate;
2044 cfg.options = state.options;
2046 /* update cfg with fc_conf */
2047 switch (fc_conf->mode) {
2049 /* Full flow control;
2050 * OPT_PAUSE set, ASYM_PAUSE not set
2052 cfg.options |= DPNI_LINK_OPT_PAUSE;
2053 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
2055 case RTE_FC_TX_PAUSE:
2056 /* Enable RX flow control
2057 * OPT_PAUSE not set;
2060 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
2061 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
2063 case RTE_FC_RX_PAUSE:
2064 /* Enable TX Flow control
2068 cfg.options |= DPNI_LINK_OPT_PAUSE;
2069 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
2072 /* Disable Flow control
2074 * ASYM_PAUSE not set
2076 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
2077 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
2080 DPAA2_PMD_ERR("Incorrect Flow control flag (%d)",
2085 ret = dpni_set_link_cfg(dpni, CMD_PRI_LOW, priv->token, &cfg);
2087 DPAA2_PMD_ERR("Unable to set Link configuration (err=%d)",
2091 dpaa2_dev_set_link_up(dev);
2097 dpaa2_dev_rss_hash_update(struct rte_eth_dev *dev,
2098 struct rte_eth_rss_conf *rss_conf)
2100 struct rte_eth_dev_data *data = dev->data;
2101 struct dpaa2_dev_priv *priv = data->dev_private;
2102 struct rte_eth_conf *eth_conf = &data->dev_conf;
2105 PMD_INIT_FUNC_TRACE();
2107 if (rss_conf->rss_hf) {
2108 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
2109 ret = dpaa2_setup_flow_dist(dev, rss_conf->rss_hf,
2112 DPAA2_PMD_ERR("Unable to set flow dist on tc%d",
2118 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
2119 ret = dpaa2_remove_flow_dist(dev, tc_index);
2122 "Unable to remove flow dist on tc%d",
2128 eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf;
2133 dpaa2_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2134 struct rte_eth_rss_conf *rss_conf)
2136 struct rte_eth_dev_data *data = dev->data;
2137 struct rte_eth_conf *eth_conf = &data->dev_conf;
2139 /* dpaa2 does not support rss_key, so length should be 0*/
2140 rss_conf->rss_key_len = 0;
2141 rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf;
2145 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev,
2146 int eth_rx_queue_id,
2147 struct dpaa2_dpcon_dev *dpcon,
2148 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
2150 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2151 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2152 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2153 uint8_t flow_id = dpaa2_ethq->flow_id;
2154 struct dpni_queue cfg;
2155 uint8_t options, priority;
2158 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_PARALLEL)
2159 dpaa2_ethq->cb = dpaa2_dev_process_parallel_event;
2160 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC)
2161 dpaa2_ethq->cb = dpaa2_dev_process_atomic_event;
2162 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED)
2163 dpaa2_ethq->cb = dpaa2_dev_process_ordered_event;
2167 priority = (RTE_EVENT_DEV_PRIORITY_LOWEST / queue_conf->ev.priority) *
2168 (dpcon->num_priorities - 1);
2170 memset(&cfg, 0, sizeof(struct dpni_queue));
2171 options = DPNI_QUEUE_OPT_DEST;
2172 cfg.destination.type = DPNI_DEST_DPCON;
2173 cfg.destination.id = dpcon->dpcon_id;
2174 cfg.destination.priority = priority;
2176 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) {
2177 options |= DPNI_QUEUE_OPT_HOLD_ACTIVE;
2178 cfg.destination.hold_active = 1;
2181 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED &&
2182 !eth_priv->en_ordered) {
2183 struct opr_cfg ocfg;
2185 /* Restoration window size = 256 frames */
2187 /* Restoration window size = 512 frames for LX2 */
2188 if (dpaa2_svr_family == SVR_LX2160A)
2190 /* Auto advance NESN window enabled */
2192 /* Late arrival window size disabled */
2194 /* ORL resource exhaustaion advance NESN disabled */
2196 /* Loose ordering enabled */
2198 eth_priv->en_loose_ordered = 1;
2199 /* Strict ordering enabled if explicitly set */
2200 if (getenv("DPAA2_STRICT_ORDERING_ENABLE")) {
2202 eth_priv->en_loose_ordered = 0;
2205 ret = dpni_set_opr(dpni, CMD_PRI_LOW, eth_priv->token,
2206 dpaa2_ethq->tc_index, flow_id,
2207 OPR_OPT_CREATE, &ocfg);
2209 DPAA2_PMD_ERR("Error setting opr: ret: %d\n", ret);
2213 eth_priv->en_ordered = 1;
2216 options |= DPNI_QUEUE_OPT_USER_CTX;
2217 cfg.user_context = (size_t)(dpaa2_ethq);
2219 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2220 dpaa2_ethq->tc_index, flow_id, options, &cfg);
2222 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2226 memcpy(&dpaa2_ethq->ev, &queue_conf->ev, sizeof(struct rte_event));
2231 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev,
2232 int eth_rx_queue_id)
2234 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2235 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2236 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2237 uint8_t flow_id = dpaa2_ethq->flow_id;
2238 struct dpni_queue cfg;
2242 memset(&cfg, 0, sizeof(struct dpni_queue));
2243 options = DPNI_QUEUE_OPT_DEST;
2244 cfg.destination.type = DPNI_DEST_NONE;
2246 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2247 dpaa2_ethq->tc_index, flow_id, options, &cfg);
2249 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2255 dpaa2_dev_verify_filter_ops(enum rte_filter_op filter_op)
2259 for (i = 0; i < RTE_DIM(dpaa2_supported_filter_ops); i++) {
2260 if (dpaa2_supported_filter_ops[i] == filter_op)
2267 dpaa2_dev_flow_ctrl(struct rte_eth_dev *dev,
2268 enum rte_filter_type filter_type,
2269 enum rte_filter_op filter_op,
2277 switch (filter_type) {
2278 case RTE_ETH_FILTER_GENERIC:
2279 if (dpaa2_dev_verify_filter_ops(filter_op) < 0) {
2283 *(const void **)arg = &dpaa2_flow_ops;
2284 dpaa2_filter_type |= filter_type;
2287 RTE_LOG(ERR, PMD, "Filter type (%d) not supported",
2296 dpaa2_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2297 struct rte_eth_rxq_info *qinfo)
2299 struct dpaa2_queue *rxq;
2301 rxq = (struct dpaa2_queue *)dev->data->rx_queues[queue_id];
2303 qinfo->mp = rxq->mb_pool;
2304 qinfo->scattered_rx = dev->data->scattered_rx;
2305 qinfo->nb_desc = rxq->nb_desc;
2307 qinfo->conf.rx_free_thresh = 1;
2308 qinfo->conf.rx_drop_en = 1;
2309 qinfo->conf.rx_deferred_start = 0;
2310 qinfo->conf.offloads = rxq->offloads;
2314 dpaa2_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2315 struct rte_eth_txq_info *qinfo)
2317 struct dpaa2_queue *txq;
2319 txq = dev->data->tx_queues[queue_id];
2321 qinfo->nb_desc = txq->nb_desc;
2322 qinfo->conf.tx_thresh.pthresh = 0;
2323 qinfo->conf.tx_thresh.hthresh = 0;
2324 qinfo->conf.tx_thresh.wthresh = 0;
2326 qinfo->conf.tx_free_thresh = 0;
2327 qinfo->conf.tx_rs_thresh = 0;
2328 qinfo->conf.offloads = txq->offloads;
2329 qinfo->conf.tx_deferred_start = 0;
2332 static struct eth_dev_ops dpaa2_ethdev_ops = {
2333 .dev_configure = dpaa2_eth_dev_configure,
2334 .dev_start = dpaa2_dev_start,
2335 .dev_stop = dpaa2_dev_stop,
2336 .dev_close = dpaa2_dev_close,
2337 .promiscuous_enable = dpaa2_dev_promiscuous_enable,
2338 .promiscuous_disable = dpaa2_dev_promiscuous_disable,
2339 .allmulticast_enable = dpaa2_dev_allmulticast_enable,
2340 .allmulticast_disable = dpaa2_dev_allmulticast_disable,
2341 .dev_set_link_up = dpaa2_dev_set_link_up,
2342 .dev_set_link_down = dpaa2_dev_set_link_down,
2343 .link_update = dpaa2_dev_link_update,
2344 .stats_get = dpaa2_dev_stats_get,
2345 .xstats_get = dpaa2_dev_xstats_get,
2346 .xstats_get_by_id = dpaa2_xstats_get_by_id,
2347 .xstats_get_names_by_id = dpaa2_xstats_get_names_by_id,
2348 .xstats_get_names = dpaa2_xstats_get_names,
2349 .stats_reset = dpaa2_dev_stats_reset,
2350 .xstats_reset = dpaa2_dev_stats_reset,
2351 .fw_version_get = dpaa2_fw_version_get,
2352 .dev_infos_get = dpaa2_dev_info_get,
2353 .dev_supported_ptypes_get = dpaa2_supported_ptypes_get,
2354 .mtu_set = dpaa2_dev_mtu_set,
2355 .vlan_filter_set = dpaa2_vlan_filter_set,
2356 .vlan_offload_set = dpaa2_vlan_offload_set,
2357 .vlan_tpid_set = dpaa2_vlan_tpid_set,
2358 .rx_queue_setup = dpaa2_dev_rx_queue_setup,
2359 .rx_queue_release = dpaa2_dev_rx_queue_release,
2360 .tx_queue_setup = dpaa2_dev_tx_queue_setup,
2361 .tx_queue_release = dpaa2_dev_tx_queue_release,
2362 .rx_burst_mode_get = dpaa2_dev_rx_burst_mode_get,
2363 .tx_burst_mode_get = dpaa2_dev_tx_burst_mode_get,
2364 .flow_ctrl_get = dpaa2_flow_ctrl_get,
2365 .flow_ctrl_set = dpaa2_flow_ctrl_set,
2366 .mac_addr_add = dpaa2_dev_add_mac_addr,
2367 .mac_addr_remove = dpaa2_dev_remove_mac_addr,
2368 .mac_addr_set = dpaa2_dev_set_mac_addr,
2369 .rss_hash_update = dpaa2_dev_rss_hash_update,
2370 .rss_hash_conf_get = dpaa2_dev_rss_hash_conf_get,
2371 .filter_ctrl = dpaa2_dev_flow_ctrl,
2372 .rxq_info_get = dpaa2_rxq_info_get,
2373 .txq_info_get = dpaa2_txq_info_get,
2374 #if defined(RTE_LIBRTE_IEEE1588)
2375 .timesync_enable = dpaa2_timesync_enable,
2376 .timesync_disable = dpaa2_timesync_disable,
2377 .timesync_read_time = dpaa2_timesync_read_time,
2378 .timesync_write_time = dpaa2_timesync_write_time,
2379 .timesync_adjust_time = dpaa2_timesync_adjust_time,
2380 .timesync_read_rx_timestamp = dpaa2_timesync_read_rx_timestamp,
2381 .timesync_read_tx_timestamp = dpaa2_timesync_read_tx_timestamp,
2385 /* Populate the mac address from physically available (u-boot/firmware) and/or
2386 * one set by higher layers like MC (restool) etc.
2387 * Returns the table of MAC entries (multiple entries)
2390 populate_mac_addr(struct fsl_mc_io *dpni_dev, struct dpaa2_dev_priv *priv,
2391 struct rte_ether_addr *mac_entry)
2394 struct rte_ether_addr phy_mac, prime_mac;
2396 memset(&phy_mac, 0, sizeof(struct rte_ether_addr));
2397 memset(&prime_mac, 0, sizeof(struct rte_ether_addr));
2399 /* Get the physical device MAC address */
2400 ret = dpni_get_port_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2401 phy_mac.addr_bytes);
2403 DPAA2_PMD_ERR("DPNI get physical port MAC failed: %d", ret);
2407 ret = dpni_get_primary_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2408 prime_mac.addr_bytes);
2410 DPAA2_PMD_ERR("DPNI get Prime port MAC failed: %d", ret);
2414 /* Now that both MAC have been obtained, do:
2415 * if not_empty_mac(phy) && phy != Prime, overwrite prime with Phy
2417 * If empty_mac(phy), return prime.
2418 * if both are empty, create random MAC, set as prime and return
2420 if (!rte_is_zero_ether_addr(&phy_mac)) {
2421 /* If the addresses are not same, overwrite prime */
2422 if (!rte_is_same_ether_addr(&phy_mac, &prime_mac)) {
2423 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2425 phy_mac.addr_bytes);
2427 DPAA2_PMD_ERR("Unable to set MAC Address: %d",
2431 memcpy(&prime_mac, &phy_mac,
2432 sizeof(struct rte_ether_addr));
2434 } else if (rte_is_zero_ether_addr(&prime_mac)) {
2435 /* In case phys and prime, both are zero, create random MAC */
2436 rte_eth_random_addr(prime_mac.addr_bytes);
2437 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2439 prime_mac.addr_bytes);
2441 DPAA2_PMD_ERR("Unable to set MAC Address: %d", ret);
2446 /* prime_mac the final MAC address */
2447 memcpy(mac_entry, &prime_mac, sizeof(struct rte_ether_addr));
2455 check_devargs_handler(__rte_unused const char *key, const char *value,
2456 __rte_unused void *opaque)
2458 if (strcmp(value, "1"))
2465 dpaa2_get_devargs(struct rte_devargs *devargs, const char *key)
2467 struct rte_kvargs *kvlist;
2472 kvlist = rte_kvargs_parse(devargs->args, NULL);
2476 if (!rte_kvargs_count(kvlist, key)) {
2477 rte_kvargs_free(kvlist);
2481 if (rte_kvargs_process(kvlist, key,
2482 check_devargs_handler, NULL) < 0) {
2483 rte_kvargs_free(kvlist);
2486 rte_kvargs_free(kvlist);
2492 dpaa2_dev_init(struct rte_eth_dev *eth_dev)
2494 struct rte_device *dev = eth_dev->device;
2495 struct rte_dpaa2_device *dpaa2_dev;
2496 struct fsl_mc_io *dpni_dev;
2497 struct dpni_attr attr;
2498 struct dpaa2_dev_priv *priv = eth_dev->data->dev_private;
2499 struct dpni_buffer_layout layout;
2502 PMD_INIT_FUNC_TRACE();
2504 dpni_dev = rte_malloc(NULL, sizeof(struct fsl_mc_io), 0);
2506 DPAA2_PMD_ERR("Memory allocation failed for dpni device");
2509 dpni_dev->regs = dpaa2_get_mcp_ptr(MC_PORTAL_INDEX);
2510 eth_dev->process_private = (void *)dpni_dev;
2512 /* For secondary processes, the primary has done all the work */
2513 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2514 /* In case of secondary, only burst and ops API need to be
2517 eth_dev->dev_ops = &dpaa2_ethdev_ops;
2518 eth_dev->rx_queue_count = dpaa2_dev_rx_queue_count;
2519 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE))
2520 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2521 else if (dpaa2_get_devargs(dev->devargs,
2522 DRIVER_NO_PREFETCH_MODE))
2523 eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2525 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2526 eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2530 dpaa2_dev = container_of(dev, struct rte_dpaa2_device, device);
2532 hw_id = dpaa2_dev->object_id;
2533 ret = dpni_open(dpni_dev, CMD_PRI_LOW, hw_id, &priv->token);
2536 "Failure in opening dpni@%d with err code %d",
2542 /* Clean the device first */
2543 ret = dpni_reset(dpni_dev, CMD_PRI_LOW, priv->token);
2545 DPAA2_PMD_ERR("Failure cleaning dpni@%d with err code %d",
2550 ret = dpni_get_attributes(dpni_dev, CMD_PRI_LOW, priv->token, &attr);
2553 "Failure in get dpni@%d attribute, err code %d",
2558 priv->num_rx_tc = attr.num_rx_tcs;
2559 priv->qos_entries = attr.qos_entries;
2560 priv->fs_entries = attr.fs_entries;
2561 priv->dist_queues = attr.num_queues;
2563 /* only if the custom CG is enabled */
2564 if (attr.options & DPNI_OPT_CUSTOM_CG)
2565 priv->max_cgs = attr.num_cgs;
2569 for (i = 0; i < priv->max_cgs; i++)
2570 priv->cgid_in_use[i] = 0;
2572 for (i = 0; i < attr.num_rx_tcs; i++)
2573 priv->nb_rx_queues += attr.num_queues;
2575 /* Using number of TX queues as number of TX TCs */
2576 priv->nb_tx_queues = attr.num_tx_tcs;
2578 DPAA2_PMD_DEBUG("RX-TC= %d, rx_queues= %d, tx_queues=%d, max_cgs=%d",
2579 priv->num_rx_tc, priv->nb_rx_queues,
2580 priv->nb_tx_queues, priv->max_cgs);
2582 priv->hw = dpni_dev;
2583 priv->hw_id = hw_id;
2584 priv->options = attr.options;
2585 priv->max_mac_filters = attr.mac_filter_entries;
2586 priv->max_vlan_filters = attr.vlan_filter_entries;
2588 #if defined(RTE_LIBRTE_IEEE1588)
2589 priv->tx_conf_en = 1;
2591 priv->tx_conf_en = 0;
2594 /* Allocate memory for hardware structure for queues */
2595 ret = dpaa2_alloc_rx_tx_queues(eth_dev);
2597 DPAA2_PMD_ERR("Queue allocation Failed");
2601 /* Allocate memory for storing MAC addresses.
2602 * Table of mac_filter_entries size is allocated so that RTE ether lib
2603 * can add MAC entries when rte_eth_dev_mac_addr_add is called.
2605 eth_dev->data->mac_addrs = rte_zmalloc("dpni",
2606 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries, 0);
2607 if (eth_dev->data->mac_addrs == NULL) {
2609 "Failed to allocate %d bytes needed to store MAC addresses",
2610 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries);
2615 ret = populate_mac_addr(dpni_dev, priv, ð_dev->data->mac_addrs[0]);
2617 DPAA2_PMD_ERR("Unable to fetch MAC Address for device");
2618 rte_free(eth_dev->data->mac_addrs);
2619 eth_dev->data->mac_addrs = NULL;
2623 /* ... tx buffer layout ... */
2624 memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2625 if (priv->tx_conf_en) {
2626 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
2627 DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2628 layout.pass_timestamp = true;
2630 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2632 layout.pass_frame_status = 1;
2633 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2634 DPNI_QUEUE_TX, &layout);
2636 DPAA2_PMD_ERR("Error (%d) in setting tx buffer layout", ret);
2640 /* ... tx-conf and error buffer layout ... */
2641 memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2642 if (priv->tx_conf_en) {
2643 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
2644 DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2645 layout.pass_timestamp = true;
2647 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2649 layout.pass_frame_status = 1;
2650 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2651 DPNI_QUEUE_TX_CONFIRM, &layout);
2653 DPAA2_PMD_ERR("Error (%d) in setting tx-conf buffer layout",
2658 eth_dev->dev_ops = &dpaa2_ethdev_ops;
2660 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE)) {
2661 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2662 DPAA2_PMD_INFO("Loopback mode");
2663 } else if (dpaa2_get_devargs(dev->devargs, DRIVER_NO_PREFETCH_MODE)) {
2664 eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2665 DPAA2_PMD_INFO("No Prefetch mode");
2667 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2669 eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2671 /*Init fields w.r.t. classficaition*/
2672 memset(&priv->extract.qos_key_extract, 0,
2673 sizeof(struct dpaa2_key_extract));
2674 priv->extract.qos_extract_param = (size_t)rte_malloc(NULL, 256, 64);
2675 if (!priv->extract.qos_extract_param) {
2676 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow "
2677 " classificaiton ", ret);
2680 priv->extract.qos_key_extract.key_info.ipv4_src_offset =
2681 IP_ADDRESS_OFFSET_INVALID;
2682 priv->extract.qos_key_extract.key_info.ipv4_dst_offset =
2683 IP_ADDRESS_OFFSET_INVALID;
2684 priv->extract.qos_key_extract.key_info.ipv6_src_offset =
2685 IP_ADDRESS_OFFSET_INVALID;
2686 priv->extract.qos_key_extract.key_info.ipv6_dst_offset =
2687 IP_ADDRESS_OFFSET_INVALID;
2689 for (i = 0; i < MAX_TCS; i++) {
2690 memset(&priv->extract.tc_key_extract[i], 0,
2691 sizeof(struct dpaa2_key_extract));
2692 priv->extract.tc_extract_param[i] =
2693 (size_t)rte_malloc(NULL, 256, 64);
2694 if (!priv->extract.tc_extract_param[i]) {
2695 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow classificaiton",
2699 priv->extract.tc_key_extract[i].key_info.ipv4_src_offset =
2700 IP_ADDRESS_OFFSET_INVALID;
2701 priv->extract.tc_key_extract[i].key_info.ipv4_dst_offset =
2702 IP_ADDRESS_OFFSET_INVALID;
2703 priv->extract.tc_key_extract[i].key_info.ipv6_src_offset =
2704 IP_ADDRESS_OFFSET_INVALID;
2705 priv->extract.tc_key_extract[i].key_info.ipv6_dst_offset =
2706 IP_ADDRESS_OFFSET_INVALID;
2709 ret = dpni_set_max_frame_length(dpni_dev, CMD_PRI_LOW, priv->token,
2710 RTE_ETHER_MAX_LEN - RTE_ETHER_CRC_LEN
2713 DPAA2_PMD_ERR("Unable to set mtu. check config");
2717 /*TODO To enable soft parser support DPAA2 driver needs to integrate
2718 * with external entity to receive byte code for software sequence
2719 * and same will be offload to the H/W using MC interface.
2720 * Currently it is assumed that DPAA2 driver has byte code by some
2721 * mean and same if offloaded to H/W.
2723 if (getenv("DPAA2_ENABLE_SOFT_PARSER")) {
2724 WRIOP_SS_INITIALIZER(priv);
2725 ret = dpaa2_eth_load_wriop_soft_parser(priv, DPNI_SS_INGRESS);
2727 DPAA2_PMD_ERR(" Error(%d) in loading softparser\n",
2732 ret = dpaa2_eth_enable_wriop_soft_parser(priv,
2735 DPAA2_PMD_ERR(" Error(%d) in enabling softparser\n",
2740 RTE_LOG(INFO, PMD, "%s: netdev created\n", eth_dev->data->name);
2743 dpaa2_dev_close(eth_dev);
2749 rte_dpaa2_probe(struct rte_dpaa2_driver *dpaa2_drv,
2750 struct rte_dpaa2_device *dpaa2_dev)
2752 struct rte_eth_dev *eth_dev;
2753 struct dpaa2_dev_priv *dev_priv;
2756 if ((DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE) >
2757 RTE_PKTMBUF_HEADROOM) {
2759 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA2 Annotation req(%d)",
2760 RTE_PKTMBUF_HEADROOM,
2761 DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE);
2766 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2767 eth_dev = rte_eth_dev_allocate(dpaa2_dev->device.name);
2770 dev_priv = rte_zmalloc("ethdev private structure",
2771 sizeof(struct dpaa2_dev_priv),
2772 RTE_CACHE_LINE_SIZE);
2773 if (dev_priv == NULL) {
2775 "Unable to allocate memory for private data");
2776 rte_eth_dev_release_port(eth_dev);
2779 eth_dev->data->dev_private = (void *)dev_priv;
2780 /* Store a pointer to eth_dev in dev_private */
2781 dev_priv->eth_dev = eth_dev;
2782 dev_priv->tx_conf_en = 0;
2784 eth_dev = rte_eth_dev_attach_secondary(dpaa2_dev->device.name);
2786 DPAA2_PMD_DEBUG("returning enodev");
2791 eth_dev->device = &dpaa2_dev->device;
2793 dpaa2_dev->eth_dev = eth_dev;
2794 eth_dev->data->rx_mbuf_alloc_failed = 0;
2796 if (dpaa2_drv->drv_flags & RTE_DPAA2_DRV_INTR_LSC)
2797 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;
2799 /* Invoke PMD device initialization function */
2800 diag = dpaa2_dev_init(eth_dev);
2802 rte_eth_dev_probing_finish(eth_dev);
2806 rte_eth_dev_release_port(eth_dev);
2811 rte_dpaa2_remove(struct rte_dpaa2_device *dpaa2_dev)
2813 struct rte_eth_dev *eth_dev;
2816 eth_dev = dpaa2_dev->eth_dev;
2817 dpaa2_dev_close(eth_dev);
2818 ret = rte_eth_dev_release_port(eth_dev);
2823 static struct rte_dpaa2_driver rte_dpaa2_pmd = {
2824 .drv_flags = RTE_DPAA2_DRV_INTR_LSC | RTE_DPAA2_DRV_IOVA_AS_VA,
2825 .drv_type = DPAA2_ETH,
2826 .probe = rte_dpaa2_probe,
2827 .remove = rte_dpaa2_remove,
2830 RTE_PMD_REGISTER_DPAA2(net_dpaa2, rte_dpaa2_pmd);
2831 RTE_PMD_REGISTER_PARAM_STRING(net_dpaa2,
2832 DRIVER_LOOPBACK_MODE "=<int> "
2833 DRIVER_NO_PREFETCH_MODE "=<int>");
2834 RTE_LOG_REGISTER(dpaa2_logtype_pmd, pmd.net.dpaa2, NOTICE);