drivers/net/dpaa2/dpaa2_ethdev.c

   1 /* * SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  *   Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
   4  *   Copyright 2016-2021 NXP
   5  *
   6  */
   7
   8 #include <time.h>
   9 #include <net/if.h>
  10
  11 #include <rte_mbuf.h>
  12 #include <ethdev_driver.h>
  13 #include <rte_malloc.h>
  14 #include <rte_memcpy.h>
  15 #include <rte_string_fns.h>
  16 #include <rte_cycles.h>
  17 #include <rte_kvargs.h>
  18 #include <rte_dev.h>
  19 #include <rte_fslmc.h>
  20 #include <rte_flow_driver.h>
  21
  22 #include "dpaa2_pmd_logs.h"
  23 #include <fslmc_vfio.h>
  24 #include <dpaa2_hw_pvt.h>
  25 #include <dpaa2_hw_mempool.h>
  26 #include <dpaa2_hw_dpio.h>
  27 #include <mc/fsl_dpmng.h>
  28 #include "dpaa2_ethdev.h"
  29 #include "dpaa2_sparser.h"
  30 #include <fsl_qbman_debug.h>
  31
  32 #define DRIVER_LOOPBACK_MODE "drv_loopback"
  33 #define DRIVER_NO_PREFETCH_MODE "drv_no_prefetch"
  34 #define DRIVER_TX_CONF "drv_tx_conf"
  35 #define DRIVER_ERROR_QUEUE  "drv_err_queue"
  36 #define CHECK_INTERVAL         100  /* 100ms */
  37 #define MAX_REPEAT_TIME        90   /* 9s (90 * 100ms) in total */
  38
  39 /* Supported Rx offloads */
  40 static uint64_t dev_rx_offloads_sup =
  41                 DEV_RX_OFFLOAD_CHECKSUM |
  42                 DEV_RX_OFFLOAD_SCTP_CKSUM |
  43                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
  44                 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
  45                 DEV_RX_OFFLOAD_VLAN_STRIP |
  46                 DEV_RX_OFFLOAD_VLAN_FILTER |
  47                 DEV_RX_OFFLOAD_JUMBO_FRAME |
  48                 DEV_RX_OFFLOAD_TIMESTAMP;
  49
  50 /* Rx offloads which cannot be disabled */
  51 static uint64_t dev_rx_offloads_nodis =
  52                 DEV_RX_OFFLOAD_RSS_HASH |
  53                 DEV_RX_OFFLOAD_SCATTER;
  54
  55 /* Supported Tx offloads */
  56 static uint64_t dev_tx_offloads_sup =
  57                 DEV_TX_OFFLOAD_VLAN_INSERT |
  58                 DEV_TX_OFFLOAD_IPV4_CKSUM |
  59                 DEV_TX_OFFLOAD_UDP_CKSUM |
  60                 DEV_TX_OFFLOAD_TCP_CKSUM |
  61                 DEV_TX_OFFLOAD_SCTP_CKSUM |
  62                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
  63                 DEV_TX_OFFLOAD_MT_LOCKFREE |
  64                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
  65
  66 /* Tx offloads which cannot be disabled */
  67 static uint64_t dev_tx_offloads_nodis =
  68                 DEV_TX_OFFLOAD_MULTI_SEGS;
  69
  70 /* enable timestamp in mbuf */
  71 bool dpaa2_enable_ts[RTE_MAX_ETHPORTS];
  72 uint64_t dpaa2_timestamp_rx_dynflag;
  73 int dpaa2_timestamp_dynfield_offset = -1;
  74
  75 /* Enable error queue */
  76 bool dpaa2_enable_err_queue;
  77
  78 struct rte_dpaa2_xstats_name_off {
  79         char name[RTE_ETH_XSTATS_NAME_SIZE];
  80         uint8_t page_id; /* dpni statistics page id */
  81         uint8_t stats_id; /* stats id in the given page */
  82 };
  83
  84 static const struct rte_dpaa2_xstats_name_off dpaa2_xstats_strings[] = {
  85         {"ingress_multicast_frames", 0, 2},
  86         {"ingress_multicast_bytes", 0, 3},
  87         {"ingress_broadcast_frames", 0, 4},
  88         {"ingress_broadcast_bytes", 0, 5},
  89         {"egress_multicast_frames", 1, 2},
  90         {"egress_multicast_bytes", 1, 3},
  91         {"egress_broadcast_frames", 1, 4},
  92         {"egress_broadcast_bytes", 1, 5},
  93         {"ingress_filtered_frames", 2, 0},
  94         {"ingress_discarded_frames", 2, 1},
  95         {"ingress_nobuffer_discards", 2, 2},
  96         {"egress_discarded_frames", 2, 3},
  97         {"egress_confirmed_frames", 2, 4},
  98         {"cgr_reject_frames", 4, 0},
  99         {"cgr_reject_bytes", 4, 1},
 100 };
 101
 102 static struct rte_dpaa2_driver rte_dpaa2_pmd;
 103 static int dpaa2_dev_link_update(struct rte_eth_dev *dev,
 104                                  int wait_to_complete);
 105 static int dpaa2_dev_set_link_up(struct rte_eth_dev *dev);
 106 static int dpaa2_dev_set_link_down(struct rte_eth_dev *dev);
 107 static int dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 108
 109 static int
 110 dpaa2_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 111 {
 112         int ret;
 113         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 114         struct fsl_mc_io *dpni = dev->process_private;
 115
 116         PMD_INIT_FUNC_TRACE();
 117
 118         if (dpni == NULL) {
 119                 DPAA2_PMD_ERR("dpni is NULL");
 120                 return -1;
 121         }
 122
 123         if (on)
 124                 ret = dpni_add_vlan_id(dpni, CMD_PRI_LOW, priv->token,
 125                                        vlan_id, 0, 0, 0);
 126         else
 127                 ret = dpni_remove_vlan_id(dpni, CMD_PRI_LOW,
 128                                           priv->token, vlan_id);
 129
 130         if (ret < 0)
 131                 DPAA2_PMD_ERR("ret = %d Unable to add/rem vlan %d hwid =%d",
 132                               ret, vlan_id, priv->hw_id);
 133
 134         return ret;
 135 }
 136
 137 static int
 138 dpaa2_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 139 {
 140         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 141         struct fsl_mc_io *dpni = dev->process_private;
 142         int ret = 0;
 143
 144         PMD_INIT_FUNC_TRACE();
 145
 146         if (mask & ETH_VLAN_FILTER_MASK) {
 147                 /* VLAN Filter not avaialble */
 148                 if (!priv->max_vlan_filters) {
 149                         DPAA2_PMD_INFO("VLAN filter not available");
 150                         return -ENOTSUP;
 151                 }
 152
 153                 if (dev->data->dev_conf.rxmode.offloads &
 154                         DEV_RX_OFFLOAD_VLAN_FILTER)
 155                         ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
 156                                                       priv->token, true);
 157                 else
 158                         ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
 159                                                       priv->token, false);
 160                 if (ret < 0)
 161                         DPAA2_PMD_INFO("Unable to set vlan filter = %d", ret);
 162         }
 163
 164         return ret;
 165 }
 166
 167 static int
 168 dpaa2_vlan_tpid_set(struct rte_eth_dev *dev,
 169                       enum rte_vlan_type vlan_type __rte_unused,
 170                       uint16_t tpid)
 171 {
 172         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 173         struct fsl_mc_io *dpni = dev->process_private;
 174         int ret = -ENOTSUP;
 175
 176         PMD_INIT_FUNC_TRACE();
 177
 178         /* nothing to be done for standard vlan tpids */
 179         if (tpid == 0x8100 || tpid == 0x88A8)
 180                 return 0;
 181
 182         ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
 183                                    priv->token, tpid);
 184         if (ret < 0)
 185                 DPAA2_PMD_INFO("Unable to set vlan tpid = %d", ret);
 186         /* if already configured tpids, remove them first */
 187         if (ret == -EBUSY) {
 188                 struct dpni_custom_tpid_cfg tpid_list = {0};
 189
 190                 ret = dpni_get_custom_tpid(dpni, CMD_PRI_LOW,
 191                                    priv->token, &tpid_list);
 192                 if (ret < 0)
 193                         goto fail;
 194                 ret = dpni_remove_custom_tpid(dpni, CMD_PRI_LOW,
 195                                    priv->token, tpid_list.tpid1);
 196                 if (ret < 0)
 197                         goto fail;
 198                 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
 199                                            priv->token, tpid);
 200         }
 201 fail:
 202         return ret;
 203 }
 204
 205 static int
 206 dpaa2_fw_version_get(struct rte_eth_dev *dev,
 207                      char *fw_version,
 208                      size_t fw_size)
 209 {
 210         int ret;
 211         struct fsl_mc_io *dpni = dev->process_private;
 212         struct mc_soc_version mc_plat_info = {0};
 213         struct mc_version mc_ver_info = {0};
 214
 215         PMD_INIT_FUNC_TRACE();
 216
 217         if (mc_get_soc_version(dpni, CMD_PRI_LOW, &mc_plat_info))
 218                 DPAA2_PMD_WARN("\tmc_get_soc_version failed");
 219
 220         if (mc_get_version(dpni, CMD_PRI_LOW, &mc_ver_info))
 221                 DPAA2_PMD_WARN("\tmc_get_version failed");
 222
 223         ret = snprintf(fw_version, fw_size,
 224                        "%x-%d.%d.%d",
 225                        mc_plat_info.svr,
 226                        mc_ver_info.major,
 227                        mc_ver_info.minor,
 228                        mc_ver_info.revision);
 229         if (ret < 0)
 230                 return -EINVAL;
 231
 232         ret += 1; /* add the size of '\0' */
 233         if (fw_size < (size_t)ret)
 234                 return ret;
 235         else
 236                 return 0;
 237 }
 238
 239 static int
 240 dpaa2_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
 241 {
 242         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 243
 244         PMD_INIT_FUNC_TRACE();
 245
 246         dev_info->max_mac_addrs = priv->max_mac_filters;
 247         dev_info->max_rx_pktlen = DPAA2_MAX_RX_PKT_LEN;
 248         dev_info->min_rx_bufsize = DPAA2_MIN_RX_BUF_SIZE;
 249         dev_info->max_rx_queues = (uint16_t)priv->nb_rx_queues;
 250         dev_info->max_tx_queues = (uint16_t)priv->nb_tx_queues;
 251         dev_info->rx_offload_capa = dev_rx_offloads_sup |
 252                                         dev_rx_offloads_nodis;
 253         dev_info->tx_offload_capa = dev_tx_offloads_sup |
 254                                         dev_tx_offloads_nodis;
 255         dev_info->speed_capa = ETH_LINK_SPEED_1G |
 256                         ETH_LINK_SPEED_2_5G |
 257                         ETH_LINK_SPEED_10G;
 258
 259         dev_info->max_hash_mac_addrs = 0;
 260         dev_info->max_vfs = 0;
 261         dev_info->max_vmdq_pools = ETH_16_POOLS;
 262         dev_info->flow_type_rss_offloads = DPAA2_RSS_OFFLOAD_ALL;
 263
 264         dev_info->default_rxportconf.burst_size = dpaa2_dqrr_size;
 265         /* same is rx size for best perf */
 266         dev_info->default_txportconf.burst_size = dpaa2_dqrr_size;
 267
 268         dev_info->default_rxportconf.nb_queues = 1;
 269         dev_info->default_txportconf.nb_queues = 1;
 270         dev_info->default_txportconf.ring_size = CONG_ENTER_TX_THRESHOLD;
 271         dev_info->default_rxportconf.ring_size = DPAA2_RX_DEFAULT_NBDESC;
 272
 273         if (dpaa2_svr_family == SVR_LX2160A) {
 274                 dev_info->speed_capa |= ETH_LINK_SPEED_25G |
 275                                 ETH_LINK_SPEED_40G |
 276                                 ETH_LINK_SPEED_50G |
 277                                 ETH_LINK_SPEED_100G;
 278         }
 279
 280         return 0;
 281 }
 282
 283 static int
 284 dpaa2_dev_rx_burst_mode_get(struct rte_eth_dev *dev,
 285                         __rte_unused uint16_t queue_id,
 286                         struct rte_eth_burst_mode *mode)
 287 {
 288         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 289         int ret = -EINVAL;
 290         unsigned int i;
 291         const struct burst_info {
 292                 uint64_t flags;
 293                 const char *output;
 294         } rx_offload_map[] = {
 295                         {DEV_RX_OFFLOAD_CHECKSUM, " Checksum,"},
 296                         {DEV_RX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
 297                         {DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
 298                         {DEV_RX_OFFLOAD_OUTER_UDP_CKSUM, " Outer UDP csum,"},
 299                         {DEV_RX_OFFLOAD_VLAN_STRIP, " VLAN strip,"},
 300                         {DEV_RX_OFFLOAD_VLAN_FILTER, " VLAN filter,"},
 301                         {DEV_RX_OFFLOAD_JUMBO_FRAME, " Jumbo frame,"},
 302                         {DEV_RX_OFFLOAD_TIMESTAMP, " Timestamp,"},
 303                         {DEV_RX_OFFLOAD_RSS_HASH, " RSS,"},
 304                         {DEV_RX_OFFLOAD_SCATTER, " Scattered,"}
 305         };
 306
 307         /* Update Rx offload info */
 308         for (i = 0; i < RTE_DIM(rx_offload_map); i++) {
 309                 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) {
 310                         snprintf(mode->info, sizeof(mode->info), "%s",
 311                                 rx_offload_map[i].output);
 312                         ret = 0;
 313                         break;
 314                 }
 315         }
 316         return ret;
 317 }
 318
 319 static int
 320 dpaa2_dev_tx_burst_mode_get(struct rte_eth_dev *dev,
 321                         __rte_unused uint16_t queue_id,
 322                         struct rte_eth_burst_mode *mode)
 323 {
 324         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 325         int ret = -EINVAL;
 326         unsigned int i;
 327         const struct burst_info {
 328                 uint64_t flags;
 329                 const char *output;
 330         } tx_offload_map[] = {
 331                         {DEV_TX_OFFLOAD_VLAN_INSERT, " VLAN Insert,"},
 332                         {DEV_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"},
 333                         {DEV_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"},
 334                         {DEV_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"},
 335                         {DEV_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
 336                         {DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
 337                         {DEV_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"},
 338                         {DEV_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"},
 339                         {DEV_TX_OFFLOAD_MULTI_SEGS, " Scattered,"}
 340         };
 341
 342         /* Update Tx offload info */
 343         for (i = 0; i < RTE_DIM(tx_offload_map); i++) {
 344                 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) {
 345                         snprintf(mode->info, sizeof(mode->info), "%s",
 346                                 tx_offload_map[i].output);
 347                         ret = 0;
 348                         break;
 349                 }
 350         }
 351         return ret;
 352 }
 353
 354 static int
 355 dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev)
 356 {
 357         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 358         uint16_t dist_idx;
 359         uint32_t vq_id;
 360         uint8_t num_rxqueue_per_tc;
 361         struct dpaa2_queue *mc_q, *mcq;
 362         uint32_t tot_queues;
 363         int i;
 364         struct dpaa2_queue *dpaa2_q;
 365
 366         PMD_INIT_FUNC_TRACE();
 367
 368         num_rxqueue_per_tc = (priv->nb_rx_queues / priv->num_rx_tc);
 369         if (priv->flags & DPAA2_TX_CONF_ENABLE)
 370                 tot_queues = priv->nb_rx_queues + 2 * priv->nb_tx_queues;
 371         else
 372                 tot_queues = priv->nb_rx_queues + priv->nb_tx_queues;
 373         mc_q = rte_malloc(NULL, sizeof(struct dpaa2_queue) * tot_queues,
 374                           RTE_CACHE_LINE_SIZE);
 375         if (!mc_q) {
 376                 DPAA2_PMD_ERR("Memory allocation failed for rx/tx queues");
 377                 return -1;
 378         }
 379
 380         for (i = 0; i < priv->nb_rx_queues; i++) {
 381                 mc_q->eth_data = dev->data;
 382                 priv->rx_vq[i] = mc_q++;
 383                 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
 384                 dpaa2_q->q_storage = rte_malloc("dq_storage",
 385                                         sizeof(struct queue_storage_info_t),
 386                                         RTE_CACHE_LINE_SIZE);
 387                 if (!dpaa2_q->q_storage)
 388                         goto fail;
 389
 390                 memset(dpaa2_q->q_storage, 0,
 391                        sizeof(struct queue_storage_info_t));
 392                 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
 393                         goto fail;
 394         }
 395
 396         if (dpaa2_enable_err_queue) {
 397                 priv->rx_err_vq = rte_zmalloc("dpni_rx_err",
 398                         sizeof(struct dpaa2_queue), 0);
 399
 400                 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq;
 401                 dpaa2_q->q_storage = rte_malloc("err_dq_storage",
 402                                         sizeof(struct queue_storage_info_t) *
 403                                         RTE_MAX_LCORE,
 404                                         RTE_CACHE_LINE_SIZE);
 405                 if (!dpaa2_q->q_storage)
 406                         goto fail;
 407
 408                 memset(dpaa2_q->q_storage, 0,
 409                        sizeof(struct queue_storage_info_t));
 410                 for (i = 0; i < RTE_MAX_LCORE; i++)
 411                         if (dpaa2_alloc_dq_storage(&dpaa2_q->q_storage[i]))
 412                                 goto fail;
 413         }
 414
 415         for (i = 0; i < priv->nb_tx_queues; i++) {
 416                 mc_q->eth_data = dev->data;
 417                 mc_q->flow_id = 0xffff;
 418                 priv->tx_vq[i] = mc_q++;
 419                 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
 420                 dpaa2_q->cscn = rte_malloc(NULL,
 421                                            sizeof(struct qbman_result), 16);
 422                 if (!dpaa2_q->cscn)
 423                         goto fail_tx;
 424         }
 425
 426         if (priv->flags & DPAA2_TX_CONF_ENABLE) {
 427                 /*Setup tx confirmation queues*/
 428                 for (i = 0; i < priv->nb_tx_queues; i++) {
 429                         mc_q->eth_data = dev->data;
 430                         mc_q->tc_index = i;
 431                         mc_q->flow_id = 0;
 432                         priv->tx_conf_vq[i] = mc_q++;
 433                         dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
 434                         dpaa2_q->q_storage =
 435                                 rte_malloc("dq_storage",
 436                                         sizeof(struct queue_storage_info_t),
 437                                         RTE_CACHE_LINE_SIZE);
 438                         if (!dpaa2_q->q_storage)
 439                                 goto fail_tx_conf;
 440
 441                         memset(dpaa2_q->q_storage, 0,
 442                                sizeof(struct queue_storage_info_t));
 443                         if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
 444                                 goto fail_tx_conf;
 445                 }
 446         }
 447
 448         vq_id = 0;
 449         for (dist_idx = 0; dist_idx < priv->nb_rx_queues; dist_idx++) {
 450                 mcq = (struct dpaa2_queue *)priv->rx_vq[vq_id];
 451                 mcq->tc_index = dist_idx / num_rxqueue_per_tc;
 452                 mcq->flow_id = dist_idx % num_rxqueue_per_tc;
 453                 vq_id++;
 454         }
 455
 456         return 0;
 457 fail_tx_conf:
 458         i -= 1;
 459         while (i >= 0) {
 460                 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
 461                 rte_free(dpaa2_q->q_storage);
 462                 priv->tx_conf_vq[i--] = NULL;
 463         }
 464         i = priv->nb_tx_queues;
 465 fail_tx:
 466         i -= 1;
 467         while (i >= 0) {
 468                 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
 469                 rte_free(dpaa2_q->cscn);
 470                 priv->tx_vq[i--] = NULL;
 471         }
 472         i = priv->nb_rx_queues;
 473 fail:
 474         i -= 1;
 475         mc_q = priv->rx_vq[0];
 476         while (i >= 0) {
 477                 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
 478                 dpaa2_free_dq_storage(dpaa2_q->q_storage);
 479                 rte_free(dpaa2_q->q_storage);
 480                 priv->rx_vq[i--] = NULL;
 481         }
 482
 483         if (dpaa2_enable_err_queue) {
 484                 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq;
 485                 if (dpaa2_q->q_storage)
 486                         dpaa2_free_dq_storage(dpaa2_q->q_storage);
 487                 rte_free(dpaa2_q->q_storage);
 488         }
 489
 490         rte_free(mc_q);
 491         return -1;
 492 }
 493
 494 static void
 495 dpaa2_free_rx_tx_queues(struct rte_eth_dev *dev)
 496 {
 497         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 498         struct dpaa2_queue *dpaa2_q;
 499         int i;
 500
 501         PMD_INIT_FUNC_TRACE();
 502
 503         /* Queue allocation base */
 504         if (priv->rx_vq[0]) {
 505                 /* cleaning up queue storage */
 506                 for (i = 0; i < priv->nb_rx_queues; i++) {
 507                         dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
 508                         if (dpaa2_q->q_storage)
 509                                 rte_free(dpaa2_q->q_storage);
 510                 }
 511                 /* cleanup tx queue cscn */
 512                 for (i = 0; i < priv->nb_tx_queues; i++) {
 513                         dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
 514                         rte_free(dpaa2_q->cscn);
 515                 }
 516                 if (priv->flags & DPAA2_TX_CONF_ENABLE) {
 517                         /* cleanup tx conf queue storage */
 518                         for (i = 0; i < priv->nb_tx_queues; i++) {
 519                                 dpaa2_q = (struct dpaa2_queue *)
 520                                                 priv->tx_conf_vq[i];
 521                                 rte_free(dpaa2_q->q_storage);
 522                         }
 523                 }
 524                 /*free memory for all queues (RX+TX) */
 525                 rte_free(priv->rx_vq[0]);
 526                 priv->rx_vq[0] = NULL;
 527         }
 528 }
 529
 530 static int
 531 dpaa2_eth_dev_configure(struct rte_eth_dev *dev)
 532 {
 533         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 534         struct fsl_mc_io *dpni = dev->process_private;
 535         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 536         uint64_t rx_offloads = eth_conf->rxmode.offloads;
 537         uint64_t tx_offloads = eth_conf->txmode.offloads;
 538         int rx_l3_csum_offload = false;
 539         int rx_l4_csum_offload = false;
 540         int tx_l3_csum_offload = false;
 541         int tx_l4_csum_offload = false;
 542         int ret, tc_index;
 543
 544         PMD_INIT_FUNC_TRACE();
 545
 546         /* Rx offloads which are enabled by default */
 547         if (dev_rx_offloads_nodis & ~rx_offloads) {
 548                 DPAA2_PMD_INFO(
 549                 "Some of rx offloads enabled by default - requested 0x%" PRIx64
 550                 " fixed are 0x%" PRIx64,
 551                 rx_offloads, dev_rx_offloads_nodis);
 552         }
 553
 554         /* Tx offloads which are enabled by default */
 555         if (dev_tx_offloads_nodis & ~tx_offloads) {
 556                 DPAA2_PMD_INFO(
 557                 "Some of tx offloads enabled by default - requested 0x%" PRIx64
 558                 " fixed are 0x%" PRIx64,
 559                 tx_offloads, dev_tx_offloads_nodis);
 560         }
 561
 562         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 563                 if (eth_conf->rxmode.max_rx_pkt_len <= DPAA2_MAX_RX_PKT_LEN) {
 564                         ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW,
 565                                 priv->token, eth_conf->rxmode.max_rx_pkt_len
 566                                 - RTE_ETHER_CRC_LEN);
 567                         if (ret) {
 568                                 DPAA2_PMD_ERR(
 569                                         "Unable to set mtu. check config");
 570                                 return ret;
 571                         }
 572                         dev->data->mtu =
 573                                 dev->data->dev_conf.rxmode.max_rx_pkt_len -
 574                                 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN -
 575                                 VLAN_TAG_SIZE;
 576                                 DPAA2_PMD_INFO("MTU configured for the device: %d",
 577                                                 dev->data->mtu);
 578                 } else {
 579                         return -1;
 580                 }
 581         }
 582
 583         if (eth_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) {
 584                 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
 585                         ret = dpaa2_setup_flow_dist(dev,
 586                                         eth_conf->rx_adv_conf.rss_conf.rss_hf,
 587                                         tc_index);
 588                         if (ret) {
 589                                 DPAA2_PMD_ERR(
 590                                         "Unable to set flow distribution on tc%d."
 591                                         "Check queue config", tc_index);
 592                                 return ret;
 593                         }
 594                 }
 595         }
 596
 597         if (rx_offloads & DEV_RX_OFFLOAD_IPV4_CKSUM)
 598                 rx_l3_csum_offload = true;
 599
 600         if ((rx_offloads & DEV_RX_OFFLOAD_UDP_CKSUM) ||
 601                 (rx_offloads & DEV_RX_OFFLOAD_TCP_CKSUM) ||
 602                 (rx_offloads & DEV_RX_OFFLOAD_SCTP_CKSUM))
 603                 rx_l4_csum_offload = true;
 604
 605         ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 606                                DPNI_OFF_RX_L3_CSUM, rx_l3_csum_offload);
 607         if (ret) {
 608                 DPAA2_PMD_ERR("Error to set RX l3 csum:Error = %d", ret);
 609                 return ret;
 610         }
 611
 612         ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 613                                DPNI_OFF_RX_L4_CSUM, rx_l4_csum_offload);
 614         if (ret) {
 615                 DPAA2_PMD_ERR("Error to get RX l4 csum:Error = %d", ret);
 616                 return ret;
 617         }
 618
 619 #if !defined(RTE_LIBRTE_IEEE1588)
 620         if (rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP)
 621 #endif
 622         {
 623                 ret = rte_mbuf_dyn_rx_timestamp_register(
 624                                 &dpaa2_timestamp_dynfield_offset,
 625                                 &dpaa2_timestamp_rx_dynflag);
 626                 if (ret != 0) {
 627                         DPAA2_PMD_ERR("Error to register timestamp field/flag");
 628                         return -rte_errno;
 629                 }
 630                 dpaa2_enable_ts[dev->data->port_id] = true;
 631         }
 632
 633         if (tx_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)
 634                 tx_l3_csum_offload = true;
 635
 636         if ((tx_offloads & DEV_TX_OFFLOAD_UDP_CKSUM) ||
 637                 (tx_offloads & DEV_TX_OFFLOAD_TCP_CKSUM) ||
 638                 (tx_offloads & DEV_TX_OFFLOAD_SCTP_CKSUM))
 639                 tx_l4_csum_offload = true;
 640
 641         ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 642                                DPNI_OFF_TX_L3_CSUM, tx_l3_csum_offload);
 643         if (ret) {
 644                 DPAA2_PMD_ERR("Error to set TX l3 csum:Error = %d", ret);
 645                 return ret;
 646         }
 647
 648         ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 649                                DPNI_OFF_TX_L4_CSUM, tx_l4_csum_offload);
 650         if (ret) {
 651                 DPAA2_PMD_ERR("Error to get TX l4 csum:Error = %d", ret);
 652                 return ret;
 653         }
 654
 655         /* Enabling hash results in FD requires setting DPNI_FLCTYPE_HASH in
 656          * dpni_set_offload API. Setting this FLCTYPE for DPNI sets the FD[SC]
 657          * to 0 for LS2 in the hardware thus disabling data/annotation
 658          * stashing. For LX2 this is fixed in hardware and thus hash result and
 659          * parse results can be received in FD using this option.
 660          */
 661         if (dpaa2_svr_family == SVR_LX2160A) {
 662                 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 663                                        DPNI_FLCTYPE_HASH, true);
 664                 if (ret) {
 665                         DPAA2_PMD_ERR("Error setting FLCTYPE: Err = %d", ret);
 666                         return ret;
 667                 }
 668         }
 669
 670         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 671                 dpaa2_vlan_offload_set(dev, ETH_VLAN_FILTER_MASK);
 672
 673         dpaa2_tm_init(dev);
 674
 675         return 0;
 676 }
 677
 678 /* Function to setup RX flow information. It contains traffic class ID,
 679  * flow ID, destination configuration etc.
 680  */
 681 static int
 682 dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev,
 683                          uint16_t rx_queue_id,
 684                          uint16_t nb_rx_desc,
 685                          unsigned int socket_id __rte_unused,
 686                          const struct rte_eth_rxconf *rx_conf,
 687                          struct rte_mempool *mb_pool)
 688 {
 689         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 690         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
 691         struct dpaa2_queue *dpaa2_q;
 692         struct dpni_queue cfg;
 693         uint8_t options = 0;
 694         uint8_t flow_id;
 695         uint32_t bpid;
 696         int i, ret;
 697
 698         PMD_INIT_FUNC_TRACE();
 699
 700         DPAA2_PMD_DEBUG("dev =%p, queue =%d, pool = %p, conf =%p",
 701                         dev, rx_queue_id, mb_pool, rx_conf);
 702
 703         /* Rx deferred start is not supported */
 704         if (rx_conf->rx_deferred_start) {
 705                 DPAA2_PMD_ERR("%p:Rx deferred start not supported",
 706                                 (void *)dev);
 707                 return -EINVAL;
 708         }
 709
 710         if (!priv->bp_list || priv->bp_list->mp != mb_pool) {
 711                 bpid = mempool_to_bpid(mb_pool);
 712                 ret = dpaa2_attach_bp_list(priv,
 713                                            rte_dpaa2_bpid_info[bpid].bp_list);
 714                 if (ret)
 715                         return ret;
 716         }
 717         dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];
 718         dpaa2_q->mb_pool = mb_pool; /**< mbuf pool to populate RX ring. */
 719         dpaa2_q->bp_array = rte_dpaa2_bpid_info;
 720         dpaa2_q->nb_desc = UINT16_MAX;
 721         dpaa2_q->offloads = rx_conf->offloads;
 722
 723         /*Get the flow id from given VQ id*/
 724         flow_id = dpaa2_q->flow_id;
 725         memset(&cfg, 0, sizeof(struct dpni_queue));
 726
 727         options = options | DPNI_QUEUE_OPT_USER_CTX;
 728         cfg.user_context = (size_t)(dpaa2_q);
 729
 730         /* check if a private cgr available. */
 731         for (i = 0; i < priv->max_cgs; i++) {
 732                 if (!priv->cgid_in_use[i]) {
 733                         priv->cgid_in_use[i] = 1;
 734                         break;
 735                 }
 736         }
 737
 738         if (i < priv->max_cgs) {
 739                 options |= DPNI_QUEUE_OPT_SET_CGID;
 740                 cfg.cgid = i;
 741                 dpaa2_q->cgid = cfg.cgid;
 742         } else {
 743                 dpaa2_q->cgid = 0xff;
 744         }
 745
 746         /*if ls2088 or rev2 device, enable the stashing */
 747
 748         if ((dpaa2_svr_family & 0xffff0000) != SVR_LS2080A) {
 749                 options |= DPNI_QUEUE_OPT_FLC;
 750                 cfg.flc.stash_control = true;
 751                 cfg.flc.value &= 0xFFFFFFFFFFFFFFC0;
 752                 /* 00 00 00 - last 6 bit represent annotation, context stashing,
 753                  * data stashing setting 01 01 00 (0x14)
 754                  * (in following order ->DS AS CS)
 755                  * to enable 1 line data, 1 line annotation.
 756                  * For LX2, this setting should be 01 00 00 (0x10)
 757                  */
 758                 if ((dpaa2_svr_family & 0xffff0000) == SVR_LX2160A)
 759                         cfg.flc.value |= 0x10;
 760                 else
 761                         cfg.flc.value |= 0x14;
 762         }
 763         ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_RX,
 764                              dpaa2_q->tc_index, flow_id, options, &cfg);
 765         if (ret) {
 766                 DPAA2_PMD_ERR("Error in setting the rx flow: = %d", ret);
 767                 return -1;
 768         }
 769
 770         if (!(priv->flags & DPAA2_RX_TAILDROP_OFF)) {
 771                 struct dpni_taildrop taildrop;
 772
 773                 taildrop.enable = 1;
 774                 dpaa2_q->nb_desc = nb_rx_desc;
 775                 /* Private CGR will use tail drop length as nb_rx_desc.
 776                  * for rest cases we can use standard byte based tail drop.
 777                  * There is no HW restriction, but number of CGRs are limited,
 778                  * hence this restriction is placed.
 779                  */
 780                 if (dpaa2_q->cgid != 0xff) {
 781                         /*enabling per rx queue congestion control */
 782                         taildrop.threshold = nb_rx_desc;
 783                         taildrop.units = DPNI_CONGESTION_UNIT_FRAMES;
 784                         taildrop.oal = 0;
 785                         DPAA2_PMD_DEBUG("Enabling CG Tail Drop on queue = %d",
 786                                         rx_queue_id);
 787                         ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
 788                                                 DPNI_CP_CONGESTION_GROUP,
 789                                                 DPNI_QUEUE_RX,
 790                                                 dpaa2_q->tc_index,
 791                                                 dpaa2_q->cgid, &taildrop);
 792                 } else {
 793                         /*enabling per rx queue congestion control */
 794                         taildrop.threshold = CONG_THRESHOLD_RX_BYTES_Q;
 795                         taildrop.units = DPNI_CONGESTION_UNIT_BYTES;
 796                         taildrop.oal = CONG_RX_OAL;
 797                         DPAA2_PMD_DEBUG("Enabling Byte based Drop on queue= %d",
 798                                         rx_queue_id);
 799                         ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
 800                                                 DPNI_CP_QUEUE, DPNI_QUEUE_RX,
 801                                                 dpaa2_q->tc_index, flow_id,
 802                                                 &taildrop);
 803                 }
 804                 if (ret) {
 805                         DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
 806                                       ret);
 807                         return -1;
 808                 }
 809         } else { /* Disable tail Drop */
 810                 struct dpni_taildrop taildrop = {0};
 811                 DPAA2_PMD_INFO("Tail drop is disabled on queue");
 812
 813                 taildrop.enable = 0;
 814                 if (dpaa2_q->cgid != 0xff) {
 815                         ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
 816                                         DPNI_CP_CONGESTION_GROUP, DPNI_QUEUE_RX,
 817                                         dpaa2_q->tc_index,
 818                                         dpaa2_q->cgid, &taildrop);
 819                 } else {
 820                         ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
 821                                         DPNI_CP_QUEUE, DPNI_QUEUE_RX,
 822                                         dpaa2_q->tc_index, flow_id, &taildrop);
 823                 }
 824                 if (ret) {
 825                         DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
 826                                       ret);
 827                         return -1;
 828                 }
 829         }
 830
 831         dev->data->rx_queues[rx_queue_id] = dpaa2_q;
 832         return 0;
 833 }
 834
 835 static int
 836 dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev,
 837                          uint16_t tx_queue_id,
 838                          uint16_t nb_tx_desc,
 839                          unsigned int socket_id __rte_unused,
 840                          const struct rte_eth_txconf *tx_conf)
 841 {
 842         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 843         struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)
 844                 priv->tx_vq[tx_queue_id];
 845         struct dpaa2_queue *dpaa2_tx_conf_q = (struct dpaa2_queue *)
 846                 priv->tx_conf_vq[tx_queue_id];
 847         struct fsl_mc_io *dpni = dev->process_private;
 848         struct dpni_queue tx_conf_cfg;
 849         struct dpni_queue tx_flow_cfg;
 850         uint8_t options = 0, flow_id;
 851         struct dpni_queue_id qid;
 852         uint32_t tc_id;
 853         int ret;
 854
 855         PMD_INIT_FUNC_TRACE();
 856
 857         /* Tx deferred start is not supported */
 858         if (tx_conf->tx_deferred_start) {
 859                 DPAA2_PMD_ERR("%p:Tx deferred start not supported",
 860                                 (void *)dev);
 861                 return -EINVAL;
 862         }
 863
 864         dpaa2_q->nb_desc = UINT16_MAX;
 865         dpaa2_q->offloads = tx_conf->offloads;
 866
 867         /* Return if queue already configured */
 868         if (dpaa2_q->flow_id != 0xffff) {
 869                 dev->data->tx_queues[tx_queue_id] = dpaa2_q;
 870                 return 0;
 871         }
 872
 873         memset(&tx_conf_cfg, 0, sizeof(struct dpni_queue));
 874         memset(&tx_flow_cfg, 0, sizeof(struct dpni_queue));
 875
 876         tc_id = tx_queue_id;
 877         flow_id = 0;
 878
 879         ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_TX,
 880                         tc_id, flow_id, options, &tx_flow_cfg);
 881         if (ret) {
 882                 DPAA2_PMD_ERR("Error in setting the tx flow: "
 883                         "tc_id=%d, flow=%d err=%d",
 884                         tc_id, flow_id, ret);
 885                         return -1;
 886         }
 887
 888         dpaa2_q->flow_id = flow_id;
 889
 890         if (tx_queue_id == 0) {
 891                 /*Set tx-conf and error configuration*/
 892                 if (priv->flags & DPAA2_TX_CONF_ENABLE)
 893                         ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
 894                                                             priv->token,
 895                                                             DPNI_CONF_AFFINE);
 896                 else
 897                         ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
 898                                                             priv->token,
 899                                                             DPNI_CONF_DISABLE);
 900                 if (ret) {
 901                         DPAA2_PMD_ERR("Error in set tx conf mode settings: "
 902                                       "err=%d", ret);
 903                         return -1;
 904                 }
 905         }
 906         dpaa2_q->tc_index = tc_id;
 907
 908         ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
 909                              DPNI_QUEUE_TX, dpaa2_q->tc_index,
 910                              dpaa2_q->flow_id, &tx_flow_cfg, &qid);
 911         if (ret) {
 912                 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
 913                 return -1;
 914         }
 915         dpaa2_q->fqid = qid.fqid;
 916
 917         if (!(priv->flags & DPAA2_TX_CGR_OFF)) {
 918                 struct dpni_congestion_notification_cfg cong_notif_cfg = {0};
 919
 920                 dpaa2_q->nb_desc = nb_tx_desc;
 921
 922                 cong_notif_cfg.units = DPNI_CONGESTION_UNIT_FRAMES;
 923                 cong_notif_cfg.threshold_entry = nb_tx_desc;
 924                 /* Notify that the queue is not congested when the data in
 925                  * the queue is below this thershold.(90% of value)
 926                  */
 927                 cong_notif_cfg.threshold_exit = (nb_tx_desc * 9) / 10;
 928                 cong_notif_cfg.message_ctx = 0;
 929                 cong_notif_cfg.message_iova =
 930                                 (size_t)DPAA2_VADDR_TO_IOVA(dpaa2_q->cscn);
 931                 cong_notif_cfg.dest_cfg.dest_type = DPNI_DEST_NONE;
 932                 cong_notif_cfg.notification_mode =
 933                                          DPNI_CONG_OPT_WRITE_MEM_ON_ENTER |
 934                                          DPNI_CONG_OPT_WRITE_MEM_ON_EXIT |
 935                                          DPNI_CONG_OPT_COHERENT_WRITE;
 936                 cong_notif_cfg.cg_point = DPNI_CP_QUEUE;
 937
 938                 ret = dpni_set_congestion_notification(dpni, CMD_PRI_LOW,
 939                                                        priv->token,
 940                                                        DPNI_QUEUE_TX,
 941                                                        tc_id,
 942                                                        &cong_notif_cfg);
 943                 if (ret) {
 944                         DPAA2_PMD_ERR(
 945                            "Error in setting tx congestion notification: "
 946                            "err=%d", ret);
 947                         return -ret;
 948                 }
 949         }
 950         dpaa2_q->cb_eqresp_free = dpaa2_dev_free_eqresp_buf;
 951         dev->data->tx_queues[tx_queue_id] = dpaa2_q;
 952
 953         if (priv->flags & DPAA2_TX_CONF_ENABLE) {
 954                 dpaa2_q->tx_conf_queue = dpaa2_tx_conf_q;
 955                 options = options | DPNI_QUEUE_OPT_USER_CTX;
 956                 tx_conf_cfg.user_context = (size_t)(dpaa2_q);
 957                 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
 958                              DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
 959                              dpaa2_tx_conf_q->flow_id, options, &tx_conf_cfg);
 960                 if (ret) {
 961                         DPAA2_PMD_ERR("Error in setting the tx conf flow: "
 962                               "tc_index=%d, flow=%d err=%d",
 963                               dpaa2_tx_conf_q->tc_index,
 964                               dpaa2_tx_conf_q->flow_id, ret);
 965                         return -1;
 966                 }
 967
 968                 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
 969                              DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
 970                              dpaa2_tx_conf_q->flow_id, &tx_conf_cfg, &qid);
 971                 if (ret) {
 972                         DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
 973                         return -1;
 974                 }
 975                 dpaa2_tx_conf_q->fqid = qid.fqid;
 976         }
 977         return 0;
 978 }
 979
 980 static void
 981 dpaa2_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 982 {
 983         struct dpaa2_queue *dpaa2_q = dev->data->rx_queues[rx_queue_id];
 984         struct dpaa2_dev_priv *priv = dpaa2_q->eth_data->dev_private;
 985         struct fsl_mc_io *dpni =
 986                 (struct fsl_mc_io *)priv->eth_dev->process_private;
 987         uint8_t options = 0;
 988         int ret;
 989         struct dpni_queue cfg;
 990
 991         memset(&cfg, 0, sizeof(struct dpni_queue));
 992         PMD_INIT_FUNC_TRACE();
 993         if (dpaa2_q->cgid != 0xff) {
 994                 options = DPNI_QUEUE_OPT_CLEAR_CGID;
 995                 cfg.cgid = dpaa2_q->cgid;
 996
 997                 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
 998                                      DPNI_QUEUE_RX,
 999                                      dpaa2_q->tc_index, dpaa2_q->flow_id,
1000                                      options, &cfg);
1001                 if (ret)
1002                         DPAA2_PMD_ERR("Unable to clear CGR from q=%u err=%d",
1003                                         dpaa2_q->fqid, ret);
1004                 priv->cgid_in_use[dpaa2_q->cgid] = 0;
1005                 dpaa2_q->cgid = 0xff;
1006         }
1007 }
1008
1009 static uint32_t
1010 dpaa2_dev_rx_queue_count(void *rx_queue)
1011 {
1012         int32_t ret;
1013         struct dpaa2_queue *dpaa2_q;
1014         struct qbman_swp *swp;
1015         struct qbman_fq_query_np_rslt state;
1016         uint32_t frame_cnt = 0;
1017
1018         if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
1019                 ret = dpaa2_affine_qbman_swp();
1020                 if (ret) {
1021                         DPAA2_PMD_ERR(
1022                                 "Failed to allocate IO portal, tid: %d\n",
1023                                 rte_gettid());
1024                         return -EINVAL;
1025                 }
1026         }
1027         swp = DPAA2_PER_LCORE_PORTAL;
1028
1029         dpaa2_q = rx_queue;
1030
1031         if (qbman_fq_query_state(swp, dpaa2_q->fqid, &state) == 0) {
1032                 frame_cnt = qbman_fq_state_frame_count(&state);
1033                 DPAA2_PMD_DP_DEBUG("RX frame count for q(%p) is %u",
1034                                 rx_queue, frame_cnt);
1035         }
1036         return frame_cnt;
1037 }
1038
1039 static const uint32_t *
1040 dpaa2_supported_ptypes_get(struct rte_eth_dev *dev)
1041 {
1042         static const uint32_t ptypes[] = {
1043                 /*todo -= add more types */
1044                 RTE_PTYPE_L2_ETHER,
1045                 RTE_PTYPE_L3_IPV4,
1046                 RTE_PTYPE_L3_IPV4_EXT,
1047                 RTE_PTYPE_L3_IPV6,
1048                 RTE_PTYPE_L3_IPV6_EXT,
1049                 RTE_PTYPE_L4_TCP,
1050                 RTE_PTYPE_L4_UDP,
1051                 RTE_PTYPE_L4_SCTP,
1052                 RTE_PTYPE_L4_ICMP,
1053                 RTE_PTYPE_UNKNOWN
1054         };
1055
1056         if (dev->rx_pkt_burst == dpaa2_dev_prefetch_rx ||
1057                 dev->rx_pkt_burst == dpaa2_dev_rx ||
1058                 dev->rx_pkt_burst == dpaa2_dev_loopback_rx)
1059                 return ptypes;
1060         return NULL;
1061 }
1062
1063 /**
1064  * Dpaa2 link Interrupt handler
1065  *
1066  * @param param
1067  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1068  *
1069  * @return
1070  *  void
1071  */
1072 static void
1073 dpaa2_interrupt_handler(void *param)
1074 {
1075         struct rte_eth_dev *dev = param;
1076         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1077         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1078         int ret;
1079         int irq_index = DPNI_IRQ_INDEX;
1080         unsigned int status = 0, clear = 0;
1081
1082         PMD_INIT_FUNC_TRACE();
1083
1084         if (dpni == NULL) {
1085                 DPAA2_PMD_ERR("dpni is NULL");
1086                 return;
1087         }
1088
1089         ret = dpni_get_irq_status(dpni, CMD_PRI_LOW, priv->token,
1090                                   irq_index, &status);
1091         if (unlikely(ret)) {
1092                 DPAA2_PMD_ERR("Can't get irq status (err %d)", ret);
1093                 clear = 0xffffffff;
1094                 goto out;
1095         }
1096
1097         if (status & DPNI_IRQ_EVENT_LINK_CHANGED) {
1098                 clear = DPNI_IRQ_EVENT_LINK_CHANGED;
1099                 dpaa2_dev_link_update(dev, 0);
1100                 /* calling all the apps registered for link status event */
1101                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1102         }
1103 out:
1104         ret = dpni_clear_irq_status(dpni, CMD_PRI_LOW, priv->token,
1105                                     irq_index, clear);
1106         if (unlikely(ret))
1107                 DPAA2_PMD_ERR("Can't clear irq status (err %d)", ret);
1108 }
1109
1110 static int
1111 dpaa2_eth_setup_irqs(struct rte_eth_dev *dev, int enable)
1112 {
1113         int err = 0;
1114         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1115         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1116         int irq_index = DPNI_IRQ_INDEX;
1117         unsigned int mask = DPNI_IRQ_EVENT_LINK_CHANGED;
1118
1119         PMD_INIT_FUNC_TRACE();
1120
1121         err = dpni_set_irq_mask(dpni, CMD_PRI_LOW, priv->token,
1122                                 irq_index, mask);
1123         if (err < 0) {
1124                 DPAA2_PMD_ERR("Error: dpni_set_irq_mask():%d (%s)", err,
1125                               strerror(-err));
1126                 return err;
1127         }
1128
1129         err = dpni_set_irq_enable(dpni, CMD_PRI_LOW, priv->token,
1130                                   irq_index, enable);
1131         if (err < 0)
1132                 DPAA2_PMD_ERR("Error: dpni_set_irq_enable():%d (%s)", err,
1133                               strerror(-err));
1134
1135         return err;
1136 }
1137
1138 static int
1139 dpaa2_dev_start(struct rte_eth_dev *dev)
1140 {
1141         struct rte_device *rdev = dev->device;
1142         struct rte_dpaa2_device *dpaa2_dev;
1143         struct rte_eth_dev_data *data = dev->data;
1144         struct dpaa2_dev_priv *priv = data->dev_private;
1145         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1146         struct dpni_queue cfg;
1147         struct dpni_error_cfg   err_cfg;
1148         uint16_t qdid;
1149         struct dpni_queue_id qid;
1150         struct dpaa2_queue *dpaa2_q;
1151         int ret, i;
1152         struct rte_intr_handle *intr_handle;
1153
1154         dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device);
1155         intr_handle = &dpaa2_dev->intr_handle;
1156
1157         PMD_INIT_FUNC_TRACE();
1158
1159         ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1160         if (ret) {
1161                 DPAA2_PMD_ERR("Failure in enabling dpni %d device: err=%d",
1162                               priv->hw_id, ret);
1163                 return ret;
1164         }
1165
1166         /* Power up the phy. Needed to make the link go UP */
1167         dpaa2_dev_set_link_up(dev);
1168
1169         ret = dpni_get_qdid(dpni, CMD_PRI_LOW, priv->token,
1170                             DPNI_QUEUE_TX, &qdid);
1171         if (ret) {
1172                 DPAA2_PMD_ERR("Error in getting qdid: err=%d", ret);
1173                 return ret;
1174         }
1175         priv->qdid = qdid;
1176
1177         for (i = 0; i < data->nb_rx_queues; i++) {
1178                 dpaa2_q = (struct dpaa2_queue *)data->rx_queues[i];
1179                 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
1180                                      DPNI_QUEUE_RX, dpaa2_q->tc_index,
1181                                        dpaa2_q->flow_id, &cfg, &qid);
1182                 if (ret) {
1183                         DPAA2_PMD_ERR("Error in getting flow information: "
1184                                       "err=%d", ret);
1185                         return ret;
1186                 }
1187                 dpaa2_q->fqid = qid.fqid;
1188         }
1189
1190         if (dpaa2_enable_err_queue) {
1191                 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
1192                                      DPNI_QUEUE_RX_ERR, 0, 0, &cfg, &qid);
1193                 if (ret) {
1194                         DPAA2_PMD_ERR("Error getting rx err flow information: err=%d",
1195                                                 ret);
1196                         return ret;
1197                 }
1198                 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq;
1199                 dpaa2_q->fqid = qid.fqid;
1200                 dpaa2_q->eth_data = dev->data;
1201
1202                 err_cfg.errors =  DPNI_ERROR_DISC;
1203                 err_cfg.error_action = DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE;
1204         } else {
1205                 /* checksum errors, send them to normal path
1206                  * and set it in annotation
1207                  */
1208                 err_cfg.errors = DPNI_ERROR_L3CE | DPNI_ERROR_L4CE;
1209
1210                 /* if packet with parse error are not to be dropped */
1211                 err_cfg.errors |= DPNI_ERROR_PHE;
1212
1213                 err_cfg.error_action = DPNI_ERROR_ACTION_CONTINUE;
1214         }
1215         err_cfg.set_frame_annotation = true;
1216
1217         ret = dpni_set_errors_behavior(dpni, CMD_PRI_LOW,
1218                                        priv->token, &err_cfg);
1219         if (ret) {
1220                 DPAA2_PMD_ERR("Error to dpni_set_errors_behavior: code = %d",
1221                               ret);
1222                 return ret;
1223         }
1224
1225         /* if the interrupts were configured on this devices*/
1226         if (intr_handle && (intr_handle->fd) &&
1227             (dev->data->dev_conf.intr_conf.lsc != 0)) {
1228                 /* Registering LSC interrupt handler */
1229                 rte_intr_callback_register(intr_handle,
1230                                            dpaa2_interrupt_handler,
1231                                            (void *)dev);
1232
1233                 /* enable vfio intr/eventfd mapping
1234                  * Interrupt index 0 is required, so we can not use
1235                  * rte_intr_enable.
1236                  */
1237                 rte_dpaa2_intr_enable(intr_handle, DPNI_IRQ_INDEX);
1238
1239                 /* enable dpni_irqs */
1240                 dpaa2_eth_setup_irqs(dev, 1);
1241         }
1242
1243         /* Change the tx burst function if ordered queues are used */
1244         if (priv->en_ordered)
1245                 dev->tx_pkt_burst = dpaa2_dev_tx_ordered;
1246
1247         return 0;
1248 }
1249
1250 /**
1251  *  This routine disables all traffic on the adapter by issuing a
1252  *  global reset on the MAC.
1253  */
1254 static int
1255 dpaa2_dev_stop(struct rte_eth_dev *dev)
1256 {
1257         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1258         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1259         int ret;
1260         struct rte_eth_link link;
1261         struct rte_intr_handle *intr_handle = dev->intr_handle;
1262
1263         PMD_INIT_FUNC_TRACE();
1264
1265         /* reset interrupt callback  */
1266         if (intr_handle && (intr_handle->fd) &&
1267             (dev->data->dev_conf.intr_conf.lsc != 0)) {
1268                 /*disable dpni irqs */
1269                 dpaa2_eth_setup_irqs(dev, 0);
1270
1271                 /* disable vfio intr before callback unregister */
1272                 rte_dpaa2_intr_disable(intr_handle, DPNI_IRQ_INDEX);
1273
1274                 /* Unregistering LSC interrupt handler */
1275                 rte_intr_callback_unregister(intr_handle,
1276                                              dpaa2_interrupt_handler,
1277                                              (void *)dev);
1278         }
1279
1280         dpaa2_dev_set_link_down(dev);
1281
1282         ret = dpni_disable(dpni, CMD_PRI_LOW, priv->token);
1283         if (ret) {
1284                 DPAA2_PMD_ERR("Failure (ret %d) in disabling dpni %d dev",
1285                               ret, priv->hw_id);
1286                 return ret;
1287         }
1288
1289         /* clear the recorded link status */
1290         memset(&link, 0, sizeof(link));
1291         rte_eth_linkstatus_set(dev, &link);
1292
1293         return 0;
1294 }
1295
1296 static int
1297 dpaa2_dev_close(struct rte_eth_dev *dev)
1298 {
1299         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1300         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1301         int i, ret;
1302         struct rte_eth_link link;
1303
1304         PMD_INIT_FUNC_TRACE();
1305
1306         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1307                 return 0;
1308
1309         if (!dpni) {
1310                 DPAA2_PMD_WARN("Already closed or not started");
1311                 return -1;
1312         }
1313
1314         dpaa2_tm_deinit(dev);
1315         dpaa2_flow_clean(dev);
1316         /* Clean the device first */
1317         ret = dpni_reset(dpni, CMD_PRI_LOW, priv->token);
1318         if (ret) {
1319                 DPAA2_PMD_ERR("Failure cleaning dpni device: err=%d", ret);
1320                 return -1;
1321         }
1322
1323         memset(&link, 0, sizeof(link));
1324         rte_eth_linkstatus_set(dev, &link);
1325
1326         /* Free private queues memory */
1327         dpaa2_free_rx_tx_queues(dev);
1328         /* Close the device at underlying layer*/
1329         ret = dpni_close(dpni, CMD_PRI_LOW, priv->token);
1330         if (ret) {
1331                 DPAA2_PMD_ERR("Failure closing dpni device with err code %d",
1332                               ret);
1333         }
1334
1335         /* Free the allocated memory for ethernet private data and dpni*/
1336         priv->hw = NULL;
1337         dev->process_private = NULL;
1338         rte_free(dpni);
1339
1340         for (i = 0; i < MAX_TCS; i++)
1341                 rte_free((void *)(size_t)priv->extract.tc_extract_param[i]);
1342
1343         if (priv->extract.qos_extract_param)
1344                 rte_free((void *)(size_t)priv->extract.qos_extract_param);
1345
1346         DPAA2_PMD_INFO("%s: netdev deleted", dev->data->name);
1347         return 0;
1348 }
1349
1350 static int
1351 dpaa2_dev_promiscuous_enable(
1352                 struct rte_eth_dev *dev)
1353 {
1354         int ret;
1355         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1356         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1357
1358         PMD_INIT_FUNC_TRACE();
1359
1360         if (dpni == NULL) {
1361                 DPAA2_PMD_ERR("dpni is NULL");
1362                 return -ENODEV;
1363         }
1364
1365         ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1366         if (ret < 0)
1367                 DPAA2_PMD_ERR("Unable to enable U promisc mode %d", ret);
1368
1369         ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1370         if (ret < 0)
1371                 DPAA2_PMD_ERR("Unable to enable M promisc mode %d", ret);
1372
1373         return ret;
1374 }
1375
1376 static int
1377 dpaa2_dev_promiscuous_disable(
1378                 struct rte_eth_dev *dev)
1379 {
1380         int ret;
1381         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1382         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1383
1384         PMD_INIT_FUNC_TRACE();
1385
1386         if (dpni == NULL) {
1387                 DPAA2_PMD_ERR("dpni is NULL");
1388                 return -ENODEV;
1389         }
1390
1391         ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1392         if (ret < 0)
1393                 DPAA2_PMD_ERR("Unable to disable U promisc mode %d", ret);
1394
1395         if (dev->data->all_multicast == 0) {
1396                 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW,
1397                                                  priv->token, false);
1398                 if (ret < 0)
1399                         DPAA2_PMD_ERR("Unable to disable M promisc mode %d",
1400                                       ret);
1401         }
1402
1403         return ret;
1404 }
1405
1406 static int
1407 dpaa2_dev_allmulticast_enable(
1408                 struct rte_eth_dev *dev)
1409 {
1410         int ret;
1411         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1412         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1413
1414         PMD_INIT_FUNC_TRACE();
1415
1416         if (dpni == NULL) {
1417                 DPAA2_PMD_ERR("dpni is NULL");
1418                 return -ENODEV;
1419         }
1420
1421         ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1422         if (ret < 0)
1423                 DPAA2_PMD_ERR("Unable to enable multicast mode %d", ret);
1424
1425         return ret;
1426 }
1427
1428 static int
1429 dpaa2_dev_allmulticast_disable(struct rte_eth_dev *dev)
1430 {
1431         int ret;
1432         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1433         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1434
1435         PMD_INIT_FUNC_TRACE();
1436
1437         if (dpni == NULL) {
1438                 DPAA2_PMD_ERR("dpni is NULL");
1439                 return -ENODEV;
1440         }
1441
1442         /* must remain on for all promiscuous */
1443         if (dev->data->promiscuous == 1)
1444                 return 0;
1445
1446         ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1447         if (ret < 0)
1448                 DPAA2_PMD_ERR("Unable to disable multicast mode %d", ret);
1449
1450         return ret;
1451 }
1452
1453 static int
1454 dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1455 {
1456         int ret;
1457         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1458         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1459         uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
1460                                 + VLAN_TAG_SIZE;
1461
1462         PMD_INIT_FUNC_TRACE();
1463
1464         if (dpni == NULL) {
1465                 DPAA2_PMD_ERR("dpni is NULL");
1466                 return -EINVAL;
1467         }
1468
1469         /* check that mtu is within the allowed range */
1470         if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA2_MAX_RX_PKT_LEN)
1471                 return -EINVAL;
1472
1473         if (frame_size > DPAA2_ETH_MAX_LEN)
1474                 dev->data->dev_conf.rxmode.offloads |=
1475                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
1476         else
1477                 dev->data->dev_conf.rxmode.offloads &=
1478                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1479
1480         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1481
1482         /* Set the Max Rx frame length as 'mtu' +
1483          * Maximum Ethernet header length
1484          */
1485         ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, priv->token,
1486                                         frame_size - RTE_ETHER_CRC_LEN);
1487         if (ret) {
1488                 DPAA2_PMD_ERR("Setting the max frame length failed");
1489                 return -1;
1490         }
1491         DPAA2_PMD_INFO("MTU configured for the device: %d", mtu);
1492         return 0;
1493 }
1494
1495 static int
1496 dpaa2_dev_add_mac_addr(struct rte_eth_dev *dev,
1497                        struct rte_ether_addr *addr,
1498                        __rte_unused uint32_t index,
1499                        __rte_unused uint32_t pool)
1500 {
1501         int ret;
1502         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1503         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1504
1505         PMD_INIT_FUNC_TRACE();
1506
1507         if (dpni == NULL) {
1508                 DPAA2_PMD_ERR("dpni is NULL");
1509                 return -1;
1510         }
1511
1512         ret = dpni_add_mac_addr(dpni, CMD_PRI_LOW, priv->token,
1513                                 addr->addr_bytes, 0, 0, 0);
1514         if (ret)
1515                 DPAA2_PMD_ERR(
1516                         "error: Adding the MAC ADDR failed: err = %d", ret);
1517         return 0;
1518 }
1519
1520 static void
1521 dpaa2_dev_remove_mac_addr(struct rte_eth_dev *dev,
1522                           uint32_t index)
1523 {
1524         int ret;
1525         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1526         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1527         struct rte_eth_dev_data *data = dev->data;
1528         struct rte_ether_addr *macaddr;
1529
1530         PMD_INIT_FUNC_TRACE();
1531
1532         macaddr = &data->mac_addrs[index];
1533
1534         if (dpni == NULL) {
1535                 DPAA2_PMD_ERR("dpni is NULL");
1536                 return;
1537         }
1538
1539         ret = dpni_remove_mac_addr(dpni, CMD_PRI_LOW,
1540                                    priv->token, macaddr->addr_bytes);
1541         if (ret)
1542                 DPAA2_PMD_ERR(
1543                         "error: Removing the MAC ADDR failed: err = %d", ret);
1544 }
1545
1546 static int
1547 dpaa2_dev_set_mac_addr(struct rte_eth_dev *dev,
1548                        struct rte_ether_addr *addr)
1549 {
1550         int ret;
1551         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1552         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1553
1554         PMD_INIT_FUNC_TRACE();
1555
1556         if (dpni == NULL) {
1557                 DPAA2_PMD_ERR("dpni is NULL");
1558                 return -EINVAL;
1559         }
1560
1561         ret = dpni_set_primary_mac_addr(dpni, CMD_PRI_LOW,
1562                                         priv->token, addr->addr_bytes);
1563
1564         if (ret)
1565                 DPAA2_PMD_ERR(
1566                         "error: Setting the MAC ADDR failed %d", ret);
1567
1568         return ret;
1569 }
1570
1571 static
1572 int dpaa2_dev_stats_get(struct rte_eth_dev *dev,
1573                          struct rte_eth_stats *stats)
1574 {
1575         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1576         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1577         int32_t  retcode;
1578         uint8_t page0 = 0, page1 = 1, page2 = 2;
1579         union dpni_statistics value;
1580         int i;
1581         struct dpaa2_queue *dpaa2_rxq, *dpaa2_txq;
1582
1583         memset(&value, 0, sizeof(union dpni_statistics));
1584
1585         PMD_INIT_FUNC_TRACE();
1586
1587         if (!dpni) {
1588                 DPAA2_PMD_ERR("dpni is NULL");
1589                 return -EINVAL;
1590         }
1591
1592         if (!stats) {
1593                 DPAA2_PMD_ERR("stats is NULL");
1594                 return -EINVAL;
1595         }
1596
1597         /*Get Counters from page_0*/
1598         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1599                                       page0, 0, &value);
1600         if (retcode)
1601                 goto err;
1602
1603         stats->ipackets = value.page_0.ingress_all_frames;
1604         stats->ibytes = value.page_0.ingress_all_bytes;
1605
1606         /*Get Counters from page_1*/
1607         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1608                                       page1, 0, &value);
1609         if (retcode)
1610                 goto err;
1611
1612         stats->opackets = value.page_1.egress_all_frames;
1613         stats->obytes = value.page_1.egress_all_bytes;
1614
1615         /*Get Counters from page_2*/
1616         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1617                                       page2, 0, &value);
1618         if (retcode)
1619                 goto err;
1620
1621         /* Ingress drop frame count due to configured rules */
1622         stats->ierrors = value.page_2.ingress_filtered_frames;
1623         /* Ingress drop frame count due to error */
1624         stats->ierrors += value.page_2.ingress_discarded_frames;
1625
1626         stats->oerrors = value.page_2.egress_discarded_frames;
1627         stats->imissed = value.page_2.ingress_nobuffer_discards;
1628
1629         /* Fill in per queue stats */
1630         for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) &&
1631                 (i < priv->nb_rx_queues || i < priv->nb_tx_queues); ++i) {
1632                 dpaa2_rxq = (struct dpaa2_queue *)priv->rx_vq[i];
1633                 dpaa2_txq = (struct dpaa2_queue *)priv->tx_vq[i];
1634                 if (dpaa2_rxq)
1635                         stats->q_ipackets[i] = dpaa2_rxq->rx_pkts;
1636                 if (dpaa2_txq)
1637                         stats->q_opackets[i] = dpaa2_txq->tx_pkts;
1638
1639                 /* Byte counting is not implemented */
1640                 stats->q_ibytes[i]   = 0;
1641                 stats->q_obytes[i]   = 0;
1642         }
1643
1644         return 0;
1645
1646 err:
1647         DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1648         return retcode;
1649 };
1650
1651 static int
1652 dpaa2_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1653                      unsigned int n)
1654 {
1655         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1656         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1657         int32_t  retcode;
1658         union dpni_statistics value[5] = {};
1659         unsigned int i = 0, num = RTE_DIM(dpaa2_xstats_strings);
1660
1661         if (n < num)
1662                 return num;
1663
1664         if (xstats == NULL)
1665                 return 0;
1666
1667         /* Get Counters from page_0*/
1668         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1669                                       0, 0, &value[0]);
1670         if (retcode)
1671                 goto err;
1672
1673         /* Get Counters from page_1*/
1674         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1675                                       1, 0, &value[1]);
1676         if (retcode)
1677                 goto err;
1678
1679         /* Get Counters from page_2*/
1680         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1681                                       2, 0, &value[2]);
1682         if (retcode)
1683                 goto err;
1684
1685         for (i = 0; i < priv->max_cgs; i++) {
1686                 if (!priv->cgid_in_use[i]) {
1687                         /* Get Counters from page_4*/
1688                         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW,
1689                                                       priv->token,
1690                                                       4, 0, &value[4]);
1691                         if (retcode)
1692                                 goto err;
1693                         break;
1694                 }
1695         }
1696
1697         for (i = 0; i < num; i++) {
1698                 xstats[i].id = i;
1699                 xstats[i].value = value[dpaa2_xstats_strings[i].page_id].
1700                         raw.counter[dpaa2_xstats_strings[i].stats_id];
1701         }
1702         return i;
1703 err:
1704         DPAA2_PMD_ERR("Error in obtaining extended stats (%d)", retcode);
1705         return retcode;
1706 }
1707
1708 static int
1709 dpaa2_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1710                        struct rte_eth_xstat_name *xstats_names,
1711                        unsigned int limit)
1712 {
1713         unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1714
1715         if (limit < stat_cnt)
1716                 return stat_cnt;
1717
1718         if (xstats_names != NULL)
1719                 for (i = 0; i < stat_cnt; i++)
1720                         strlcpy(xstats_names[i].name,
1721                                 dpaa2_xstats_strings[i].name,
1722                                 sizeof(xstats_names[i].name));
1723
1724         return stat_cnt;
1725 }
1726
1727 static int
1728 dpaa2_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1729                        uint64_t *values, unsigned int n)
1730 {
1731         unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1732         uint64_t values_copy[stat_cnt];
1733
1734         if (!ids) {
1735                 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1736                 struct fsl_mc_io *dpni =
1737                         (struct fsl_mc_io *)dev->process_private;
1738                 int32_t  retcode;
1739                 union dpni_statistics value[5] = {};
1740
1741                 if (n < stat_cnt)
1742                         return stat_cnt;
1743
1744                 if (!values)
1745                         return 0;
1746
1747                 /* Get Counters from page_0*/
1748                 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1749                                               0, 0, &value[0]);
1750                 if (retcode)
1751                         return 0;
1752
1753                 /* Get Counters from page_1*/
1754                 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1755                                               1, 0, &value[1]);
1756                 if (retcode)
1757                         return 0;
1758
1759                 /* Get Counters from page_2*/
1760                 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1761                                               2, 0, &value[2]);
1762                 if (retcode)
1763                         return 0;
1764
1765                 /* Get Counters from page_4*/
1766                 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1767                                               4, 0, &value[4]);
1768                 if (retcode)
1769                         return 0;
1770
1771                 for (i = 0; i < stat_cnt; i++) {
1772                         values[i] = value[dpaa2_xstats_strings[i].page_id].
1773                                 raw.counter[dpaa2_xstats_strings[i].stats_id];
1774                 }
1775                 return stat_cnt;
1776         }
1777
1778         dpaa2_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
1779
1780         for (i = 0; i < n; i++) {
1781                 if (ids[i] >= stat_cnt) {
1782                         DPAA2_PMD_ERR("xstats id value isn't valid");
1783                         return -1;
1784                 }
1785                 values[i] = values_copy[ids[i]];
1786         }
1787         return n;
1788 }
1789
1790 static int
1791 dpaa2_xstats_get_names_by_id(
1792         struct rte_eth_dev *dev,
1793         const uint64_t *ids,
1794         struct rte_eth_xstat_name *xstats_names,
1795         unsigned int limit)
1796 {
1797         unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1798         struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
1799
1800         if (!ids)
1801                 return dpaa2_xstats_get_names(dev, xstats_names, limit);
1802
1803         dpaa2_xstats_get_names(dev, xstats_names_copy, limit);
1804
1805         for (i = 0; i < limit; i++) {
1806                 if (ids[i] >= stat_cnt) {
1807                         DPAA2_PMD_ERR("xstats id value isn't valid");
1808                         return -1;
1809                 }
1810                 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
1811         }
1812         return limit;
1813 }
1814
1815 static int
1816 dpaa2_dev_stats_reset(struct rte_eth_dev *dev)
1817 {
1818         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1819         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1820         int retcode;
1821         int i;
1822         struct dpaa2_queue *dpaa2_q;
1823
1824         PMD_INIT_FUNC_TRACE();
1825
1826         if (dpni == NULL) {
1827                 DPAA2_PMD_ERR("dpni is NULL");
1828                 return -EINVAL;
1829         }
1830
1831         retcode =  dpni_reset_statistics(dpni, CMD_PRI_LOW, priv->token);
1832         if (retcode)
1833                 goto error;
1834
1835         /* Reset the per queue stats in dpaa2_queue structure */
1836         for (i = 0; i < priv->nb_rx_queues; i++) {
1837                 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
1838                 if (dpaa2_q)
1839                         dpaa2_q->rx_pkts = 0;
1840         }
1841
1842         for (i = 0; i < priv->nb_tx_queues; i++) {
1843                 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
1844                 if (dpaa2_q)
1845                         dpaa2_q->tx_pkts = 0;
1846         }
1847
1848         return 0;
1849
1850 error:
1851         DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1852         return retcode;
1853 };
1854
1855 /* return 0 means link status changed, -1 means not changed */
1856 static int
1857 dpaa2_dev_link_update(struct rte_eth_dev *dev,
1858                       int wait_to_complete)
1859 {
1860         int ret;
1861         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1862         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1863         struct rte_eth_link link;
1864         struct dpni_link_state state = {0};
1865         uint8_t count;
1866
1867         if (dpni == NULL) {
1868                 DPAA2_PMD_ERR("dpni is NULL");
1869                 return 0;
1870         }
1871
1872         for (count = 0; count <= MAX_REPEAT_TIME; count++) {
1873                 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token,
1874                                           &state);
1875                 if (ret < 0) {
1876                         DPAA2_PMD_DEBUG("error: dpni_get_link_state %d", ret);
1877                         return -1;
1878                 }
1879                 if (state.up == ETH_LINK_DOWN &&
1880                     wait_to_complete)
1881                         rte_delay_ms(CHECK_INTERVAL);
1882                 else
1883                         break;
1884         }
1885
1886         memset(&link, 0, sizeof(struct rte_eth_link));
1887         link.link_status = state.up;
1888         link.link_speed = state.rate;
1889
1890         if (state.options & DPNI_LINK_OPT_HALF_DUPLEX)
1891                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1892         else
1893                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1894
1895         ret = rte_eth_linkstatus_set(dev, &link);
1896         if (ret == -1)
1897                 DPAA2_PMD_DEBUG("No change in status");
1898         else
1899                 DPAA2_PMD_INFO("Port %d Link is %s\n", dev->data->port_id,
1900                                link.link_status ? "Up" : "Down");
1901
1902         return ret;
1903 }
1904
1905 /**
1906  * Toggle the DPNI to enable, if not already enabled.
1907  * This is not strictly PHY up/down - it is more of logical toggling.
1908  */
1909 static int
1910 dpaa2_dev_set_link_up(struct rte_eth_dev *dev)
1911 {
1912         int ret = -EINVAL;
1913         struct dpaa2_dev_priv *priv;
1914         struct fsl_mc_io *dpni;
1915         int en = 0;
1916         struct dpni_link_state state = {0};
1917
1918         priv = dev->data->dev_private;
1919         dpni = (struct fsl_mc_io *)dev->process_private;
1920
1921         if (dpni == NULL) {
1922                 DPAA2_PMD_ERR("dpni is NULL");
1923                 return ret;
1924         }
1925
1926         /* Check if DPNI is currently enabled */
1927         ret = dpni_is_enabled(dpni, CMD_PRI_LOW, priv->token, &en);
1928         if (ret) {
1929                 /* Unable to obtain dpni status; Not continuing */
1930                 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1931                 return -EINVAL;
1932         }
1933
1934         /* Enable link if not already enabled */
1935         if (!en) {
1936                 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1937                 if (ret) {
1938                         DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1939                         return -EINVAL;
1940                 }
1941         }
1942         ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1943         if (ret < 0) {
1944                 DPAA2_PMD_DEBUG("Unable to get link state (%d)", ret);
1945                 return -1;
1946         }
1947
1948         /* changing tx burst function to start enqueues */
1949         dev->tx_pkt_burst = dpaa2_dev_tx;
1950         dev->data->dev_link.link_status = state.up;
1951         dev->data->dev_link.link_speed = state.rate;
1952
1953         if (state.up)
1954                 DPAA2_PMD_INFO("Port %d Link is Up", dev->data->port_id);
1955         else
1956                 DPAA2_PMD_INFO("Port %d Link is Down", dev->data->port_id);
1957         return ret;
1958 }
1959
1960 /**
1961  * Toggle the DPNI to disable, if not already disabled.
1962  * This is not strictly PHY up/down - it is more of logical toggling.
1963  */
1964 static int
1965 dpaa2_dev_set_link_down(struct rte_eth_dev *dev)
1966 {
1967         int ret = -EINVAL;
1968         struct dpaa2_dev_priv *priv;
1969         struct fsl_mc_io *dpni;
1970         int dpni_enabled = 0;
1971         int retries = 10;
1972
1973         PMD_INIT_FUNC_TRACE();
1974
1975         priv = dev->data->dev_private;
1976         dpni = (struct fsl_mc_io *)dev->process_private;
1977
1978         if (dpni == NULL) {
1979                 DPAA2_PMD_ERR("Device has not yet been configured");
1980                 return ret;
1981         }
1982
1983         /*changing  tx burst function to avoid any more enqueues */
1984         dev->tx_pkt_burst = dummy_dev_tx;
1985
1986         /* Loop while dpni_disable() attempts to drain the egress FQs
1987          * and confirm them back to us.
1988          */
1989         do {
1990                 ret = dpni_disable(dpni, 0, priv->token);
1991                 if (ret) {
1992                         DPAA2_PMD_ERR("dpni disable failed (%d)", ret);
1993                         return ret;
1994                 }
1995                 ret = dpni_is_enabled(dpni, 0, priv->token, &dpni_enabled);
1996                 if (ret) {
1997                         DPAA2_PMD_ERR("dpni enable check failed (%d)", ret);
1998                         return ret;
1999                 }
2000                 if (dpni_enabled)
2001                         /* Allow the MC some slack */
2002                         rte_delay_us(100 * 1000);
2003         } while (dpni_enabled && --retries);
2004
2005         if (!retries) {
2006                 DPAA2_PMD_WARN("Retry count exceeded disabling dpni");
2007                 /* todo- we may have to manually cleanup queues.
2008                  */
2009         } else {
2010                 DPAA2_PMD_INFO("Port %d Link DOWN successful",
2011                                dev->data->port_id);
2012         }
2013
2014         dev->data->dev_link.link_status = 0;
2015
2016         return ret;
2017 }
2018
2019 static int
2020 dpaa2_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2021 {
2022         int ret = -EINVAL;
2023         struct dpaa2_dev_priv *priv;
2024         struct fsl_mc_io *dpni;
2025         struct dpni_link_state state = {0};
2026
2027         PMD_INIT_FUNC_TRACE();
2028
2029         priv = dev->data->dev_private;
2030         dpni = (struct fsl_mc_io *)dev->process_private;
2031
2032         if (dpni == NULL || fc_conf == NULL) {
2033                 DPAA2_PMD_ERR("device not configured");
2034                 return ret;
2035         }
2036
2037         ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
2038         if (ret) {
2039                 DPAA2_PMD_ERR("error: dpni_get_link_state %d", ret);
2040                 return ret;
2041         }
2042
2043         memset(fc_conf, 0, sizeof(struct rte_eth_fc_conf));
2044         if (state.options & DPNI_LINK_OPT_PAUSE) {
2045                 /* DPNI_LINK_OPT_PAUSE set
2046                  *  if ASYM_PAUSE not set,
2047                  *      RX Side flow control (handle received Pause frame)
2048                  *      TX side flow control (send Pause frame)
2049                  *  if ASYM_PAUSE set,
2050                  *      RX Side flow control (handle received Pause frame)
2051                  *      No TX side flow control (send Pause frame disabled)
2052                  */
2053                 if (!(state.options & DPNI_LINK_OPT_ASYM_PAUSE))
2054                         fc_conf->mode = RTE_FC_FULL;
2055                 else
2056                         fc_conf->mode = RTE_FC_RX_PAUSE;
2057         } else {
2058                 /* DPNI_LINK_OPT_PAUSE not set
2059                  *  if ASYM_PAUSE set,
2060                  *      TX side flow control (send Pause frame)
2061                  *      No RX side flow control (No action on pause frame rx)
2062                  *  if ASYM_PAUSE not set,
2063                  *      Flow control disabled
2064                  */
2065                 if (state.options & DPNI_LINK_OPT_ASYM_PAUSE)
2066                         fc_conf->mode = RTE_FC_TX_PAUSE;
2067                 else
2068                         fc_conf->mode = RTE_FC_NONE;
2069         }
2070
2071         return ret;
2072 }
2073
2074 static int
2075 dpaa2_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2076 {
2077         int ret = -EINVAL;
2078         struct dpaa2_dev_priv *priv;
2079         struct fsl_mc_io *dpni;
2080         struct dpni_link_state state = {0};
2081         struct dpni_link_cfg cfg = {0};
2082
2083         PMD_INIT_FUNC_TRACE();
2084
2085         priv = dev->data->dev_private;
2086         dpni = (struct fsl_mc_io *)dev->process_private;
2087
2088         if (dpni == NULL) {
2089                 DPAA2_PMD_ERR("dpni is NULL");
2090                 return ret;
2091         }
2092
2093         /* It is necessary to obtain the current state before setting fc_conf
2094          * as MC would return error in case rate, autoneg or duplex values are
2095          * different.
2096          */
2097         ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
2098         if (ret) {
2099                 DPAA2_PMD_ERR("Unable to get link state (err=%d)", ret);
2100                 return -1;
2101         }
2102
2103         /* Disable link before setting configuration */
2104         dpaa2_dev_set_link_down(dev);
2105
2106         /* Based on fc_conf, update cfg */
2107         cfg.rate = state.rate;
2108         cfg.options = state.options;
2109
2110         /* update cfg with fc_conf */
2111         switch (fc_conf->mode) {
2112         case RTE_FC_FULL:
2113                 /* Full flow control;
2114                  * OPT_PAUSE set, ASYM_PAUSE not set
2115                  */
2116                 cfg.options |= DPNI_LINK_OPT_PAUSE;
2117                 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
2118                 break;
2119         case RTE_FC_TX_PAUSE:
2120                 /* Enable RX flow control
2121                  * OPT_PAUSE not set;
2122                  * ASYM_PAUSE set;
2123                  */
2124                 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
2125                 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
2126                 break;
2127         case RTE_FC_RX_PAUSE:
2128                 /* Enable TX Flow control
2129                  * OPT_PAUSE set
2130                  * ASYM_PAUSE set
2131                  */
2132                 cfg.options |= DPNI_LINK_OPT_PAUSE;
2133                 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
2134                 break;
2135         case RTE_FC_NONE:
2136                 /* Disable Flow control
2137                  * OPT_PAUSE not set
2138                  * ASYM_PAUSE not set
2139                  */
2140                 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
2141                 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
2142                 break;
2143         default:
2144                 DPAA2_PMD_ERR("Incorrect Flow control flag (%d)",
2145                               fc_conf->mode);
2146                 return -1;
2147         }
2148
2149         ret = dpni_set_link_cfg(dpni, CMD_PRI_LOW, priv->token, &cfg);
2150         if (ret)
2151                 DPAA2_PMD_ERR("Unable to set Link configuration (err=%d)",
2152                               ret);
2153
2154         /* Enable link */
2155         dpaa2_dev_set_link_up(dev);
2156
2157         return ret;
2158 }
2159
2160 static int
2161 dpaa2_dev_rss_hash_update(struct rte_eth_dev *dev,
2162                           struct rte_eth_rss_conf *rss_conf)
2163 {
2164         struct rte_eth_dev_data *data = dev->data;
2165         struct dpaa2_dev_priv *priv = data->dev_private;
2166         struct rte_eth_conf *eth_conf = &data->dev_conf;
2167         int ret, tc_index;
2168
2169         PMD_INIT_FUNC_TRACE();
2170
2171         if (rss_conf->rss_hf) {
2172                 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
2173                         ret = dpaa2_setup_flow_dist(dev, rss_conf->rss_hf,
2174                                 tc_index);
2175                         if (ret) {
2176                                 DPAA2_PMD_ERR("Unable to set flow dist on tc%d",
2177                                         tc_index);
2178                                 return ret;
2179                         }
2180                 }
2181         } else {
2182                 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
2183                         ret = dpaa2_remove_flow_dist(dev, tc_index);
2184                         if (ret) {
2185                                 DPAA2_PMD_ERR(
2186                                         "Unable to remove flow dist on tc%d",
2187                                         tc_index);
2188                                 return ret;
2189                         }
2190                 }
2191         }
2192         eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf;
2193         return 0;
2194 }
2195
2196 static int
2197 dpaa2_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2198                             struct rte_eth_rss_conf *rss_conf)
2199 {
2200         struct rte_eth_dev_data *data = dev->data;
2201         struct rte_eth_conf *eth_conf = &data->dev_conf;
2202
2203         /* dpaa2 does not support rss_key, so length should be 0*/
2204         rss_conf->rss_key_len = 0;
2205         rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf;
2206         return 0;
2207 }
2208
2209 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev,
2210                 int eth_rx_queue_id,
2211                 struct dpaa2_dpcon_dev *dpcon,
2212                 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
2213 {
2214         struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2215         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2216         struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2217         uint8_t flow_id = dpaa2_ethq->flow_id;
2218         struct dpni_queue cfg;
2219         uint8_t options, priority;
2220         int ret;
2221
2222         if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_PARALLEL)
2223                 dpaa2_ethq->cb = dpaa2_dev_process_parallel_event;
2224         else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC)
2225                 dpaa2_ethq->cb = dpaa2_dev_process_atomic_event;
2226         else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED)
2227                 dpaa2_ethq->cb = dpaa2_dev_process_ordered_event;
2228         else
2229                 return -EINVAL;
2230
2231         priority = (RTE_EVENT_DEV_PRIORITY_LOWEST / queue_conf->ev.priority) *
2232                    (dpcon->num_priorities - 1);
2233
2234         memset(&cfg, 0, sizeof(struct dpni_queue));
2235         options = DPNI_QUEUE_OPT_DEST;
2236         cfg.destination.type = DPNI_DEST_DPCON;
2237         cfg.destination.id = dpcon->dpcon_id;
2238         cfg.destination.priority = priority;
2239
2240         if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) {
2241                 options |= DPNI_QUEUE_OPT_HOLD_ACTIVE;
2242                 cfg.destination.hold_active = 1;
2243         }
2244
2245         if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED &&
2246                         !eth_priv->en_ordered) {
2247                 struct opr_cfg ocfg;
2248
2249                 /* Restoration window size = 256 frames */
2250                 ocfg.oprrws = 3;
2251                 /* Restoration window size = 512 frames for LX2 */
2252                 if (dpaa2_svr_family == SVR_LX2160A)
2253                         ocfg.oprrws = 4;
2254                 /* Auto advance NESN window enabled */
2255                 ocfg.oa = 1;
2256                 /* Late arrival window size disabled */
2257                 ocfg.olws = 0;
2258                 /* ORL resource exhaustaion advance NESN disabled */
2259                 ocfg.oeane = 0;
2260                 /* Loose ordering enabled */
2261                 ocfg.oloe = 1;
2262                 eth_priv->en_loose_ordered = 1;
2263                 /* Strict ordering enabled if explicitly set */
2264                 if (getenv("DPAA2_STRICT_ORDERING_ENABLE")) {
2265                         ocfg.oloe = 0;
2266                         eth_priv->en_loose_ordered = 0;
2267                 }
2268
2269                 ret = dpni_set_opr(dpni, CMD_PRI_LOW, eth_priv->token,
2270                                    dpaa2_ethq->tc_index, flow_id,
2271                                    OPR_OPT_CREATE, &ocfg, 0);
2272                 if (ret) {
2273                         DPAA2_PMD_ERR("Error setting opr: ret: %d\n", ret);
2274                         return ret;
2275                 }
2276
2277                 eth_priv->en_ordered = 1;
2278         }
2279
2280         options |= DPNI_QUEUE_OPT_USER_CTX;
2281         cfg.user_context = (size_t)(dpaa2_ethq);
2282
2283         ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2284                              dpaa2_ethq->tc_index, flow_id, options, &cfg);
2285         if (ret) {
2286                 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2287                 return ret;
2288         }
2289
2290         memcpy(&dpaa2_ethq->ev, &queue_conf->ev, sizeof(struct rte_event));
2291
2292         return 0;
2293 }
2294
2295 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev,
2296                 int eth_rx_queue_id)
2297 {
2298         struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2299         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2300         struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2301         uint8_t flow_id = dpaa2_ethq->flow_id;
2302         struct dpni_queue cfg;
2303         uint8_t options;
2304         int ret;
2305
2306         memset(&cfg, 0, sizeof(struct dpni_queue));
2307         options = DPNI_QUEUE_OPT_DEST;
2308         cfg.destination.type = DPNI_DEST_NONE;
2309
2310         ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2311                              dpaa2_ethq->tc_index, flow_id, options, &cfg);
2312         if (ret)
2313                 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2314
2315         return ret;
2316 }
2317
2318 static int
2319 dpaa2_dev_flow_ops_get(struct rte_eth_dev *dev,
2320                        const struct rte_flow_ops **ops)
2321 {
2322         if (!dev)
2323                 return -ENODEV;
2324
2325         *ops = &dpaa2_flow_ops;
2326         return 0;
2327 }
2328
2329 static void
2330 dpaa2_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2331         struct rte_eth_rxq_info *qinfo)
2332 {
2333         struct dpaa2_queue *rxq;
2334         struct dpaa2_dev_priv *priv = dev->data->dev_private;
2335         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2336         uint16_t max_frame_length;
2337
2338         rxq = (struct dpaa2_queue *)dev->data->rx_queues[queue_id];
2339
2340         qinfo->mp = rxq->mb_pool;
2341         qinfo->scattered_rx = dev->data->scattered_rx;
2342         qinfo->nb_desc = rxq->nb_desc;
2343         if (dpni_get_max_frame_length(dpni, CMD_PRI_LOW, priv->token,
2344                                 &max_frame_length) == 0)
2345                 qinfo->rx_buf_size = max_frame_length;
2346
2347         qinfo->conf.rx_free_thresh = 1;
2348         qinfo->conf.rx_drop_en = 1;
2349         qinfo->conf.rx_deferred_start = 0;
2350         qinfo->conf.offloads = rxq->offloads;
2351 }
2352
2353 static void
2354 dpaa2_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2355         struct rte_eth_txq_info *qinfo)
2356 {
2357         struct dpaa2_queue *txq;
2358
2359         txq = dev->data->tx_queues[queue_id];
2360
2361         qinfo->nb_desc = txq->nb_desc;
2362         qinfo->conf.tx_thresh.pthresh = 0;
2363         qinfo->conf.tx_thresh.hthresh = 0;
2364         qinfo->conf.tx_thresh.wthresh = 0;
2365
2366         qinfo->conf.tx_free_thresh = 0;
2367         qinfo->conf.tx_rs_thresh = 0;
2368         qinfo->conf.offloads = txq->offloads;
2369         qinfo->conf.tx_deferred_start = 0;
2370 }
2371
2372 static int
2373 dpaa2_tm_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops)
2374 {
2375         *(const void **)ops = &dpaa2_tm_ops;
2376
2377         return 0;
2378 }
2379
2380 void
2381 rte_pmd_dpaa2_thread_init(void)
2382 {
2383         int ret;
2384
2385         if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
2386                 ret = dpaa2_affine_qbman_swp();
2387                 if (ret) {
2388                         DPAA2_PMD_ERR(
2389                                 "Failed to allocate IO portal, tid: %d\n",
2390                                 rte_gettid());
2391                         return;
2392                 }
2393         }
2394 }
2395
2396 static struct eth_dev_ops dpaa2_ethdev_ops = {
2397         .dev_configure    = dpaa2_eth_dev_configure,
2398         .dev_start            = dpaa2_dev_start,
2399         .dev_stop             = dpaa2_dev_stop,
2400         .dev_close            = dpaa2_dev_close,
2401         .promiscuous_enable   = dpaa2_dev_promiscuous_enable,
2402         .promiscuous_disable  = dpaa2_dev_promiscuous_disable,
2403         .allmulticast_enable  = dpaa2_dev_allmulticast_enable,
2404         .allmulticast_disable = dpaa2_dev_allmulticast_disable,
2405         .dev_set_link_up      = dpaa2_dev_set_link_up,
2406         .dev_set_link_down    = dpaa2_dev_set_link_down,
2407         .link_update       = dpaa2_dev_link_update,
2408         .stats_get             = dpaa2_dev_stats_get,
2409         .xstats_get            = dpaa2_dev_xstats_get,
2410         .xstats_get_by_id     = dpaa2_xstats_get_by_id,
2411         .xstats_get_names_by_id = dpaa2_xstats_get_names_by_id,
2412         .xstats_get_names      = dpaa2_xstats_get_names,
2413         .stats_reset       = dpaa2_dev_stats_reset,
2414         .xstats_reset         = dpaa2_dev_stats_reset,
2415         .fw_version_get    = dpaa2_fw_version_get,
2416         .dev_infos_get     = dpaa2_dev_info_get,
2417         .dev_supported_ptypes_get = dpaa2_supported_ptypes_get,
2418         .mtu_set           = dpaa2_dev_mtu_set,
2419         .vlan_filter_set      = dpaa2_vlan_filter_set,
2420         .vlan_offload_set     = dpaa2_vlan_offload_set,
2421         .vlan_tpid_set        = dpaa2_vlan_tpid_set,
2422         .rx_queue_setup    = dpaa2_dev_rx_queue_setup,
2423         .rx_queue_release  = dpaa2_dev_rx_queue_release,
2424         .tx_queue_setup    = dpaa2_dev_tx_queue_setup,
2425         .rx_burst_mode_get = dpaa2_dev_rx_burst_mode_get,
2426         .tx_burst_mode_get = dpaa2_dev_tx_burst_mode_get,
2427         .flow_ctrl_get        = dpaa2_flow_ctrl_get,
2428         .flow_ctrl_set        = dpaa2_flow_ctrl_set,
2429         .mac_addr_add         = dpaa2_dev_add_mac_addr,
2430         .mac_addr_remove      = dpaa2_dev_remove_mac_addr,
2431         .mac_addr_set         = dpaa2_dev_set_mac_addr,
2432         .rss_hash_update      = dpaa2_dev_rss_hash_update,
2433         .rss_hash_conf_get    = dpaa2_dev_rss_hash_conf_get,
2434         .flow_ops_get         = dpaa2_dev_flow_ops_get,
2435         .rxq_info_get         = dpaa2_rxq_info_get,
2436         .txq_info_get         = dpaa2_txq_info_get,
2437         .tm_ops_get           = dpaa2_tm_ops_get,
2438 #if defined(RTE_LIBRTE_IEEE1588)
2439         .timesync_enable      = dpaa2_timesync_enable,
2440         .timesync_disable     = dpaa2_timesync_disable,
2441         .timesync_read_time   = dpaa2_timesync_read_time,
2442         .timesync_write_time  = dpaa2_timesync_write_time,
2443         .timesync_adjust_time = dpaa2_timesync_adjust_time,
2444         .timesync_read_rx_timestamp = dpaa2_timesync_read_rx_timestamp,
2445         .timesync_read_tx_timestamp = dpaa2_timesync_read_tx_timestamp,
2446 #endif
2447 };
2448
2449 /* Populate the mac address from physically available (u-boot/firmware) and/or
2450  * one set by higher layers like MC (restool) etc.
2451  * Returns the table of MAC entries (multiple entries)
2452  */
2453 static int
2454 populate_mac_addr(struct fsl_mc_io *dpni_dev, struct dpaa2_dev_priv *priv,
2455                   struct rte_ether_addr *mac_entry)
2456 {
2457         int ret;
2458         struct rte_ether_addr phy_mac, prime_mac;
2459
2460         memset(&phy_mac, 0, sizeof(struct rte_ether_addr));
2461         memset(&prime_mac, 0, sizeof(struct rte_ether_addr));
2462
2463         /* Get the physical device MAC address */
2464         ret = dpni_get_port_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2465                                      phy_mac.addr_bytes);
2466         if (ret) {
2467                 DPAA2_PMD_ERR("DPNI get physical port MAC failed: %d", ret);
2468                 goto cleanup;
2469         }
2470
2471         ret = dpni_get_primary_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2472                                         prime_mac.addr_bytes);
2473         if (ret) {
2474                 DPAA2_PMD_ERR("DPNI get Prime port MAC failed: %d", ret);
2475                 goto cleanup;
2476         }
2477
2478         /* Now that both MAC have been obtained, do:
2479          *  if not_empty_mac(phy) && phy != Prime, overwrite prime with Phy
2480          *     and return phy
2481          *  If empty_mac(phy), return prime.
2482          *  if both are empty, create random MAC, set as prime and return
2483          */
2484         if (!rte_is_zero_ether_addr(&phy_mac)) {
2485                 /* If the addresses are not same, overwrite prime */
2486                 if (!rte_is_same_ether_addr(&phy_mac, &prime_mac)) {
2487                         ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2488                                                         priv->token,
2489                                                         phy_mac.addr_bytes);
2490                         if (ret) {
2491                                 DPAA2_PMD_ERR("Unable to set MAC Address: %d",
2492                                               ret);
2493                                 goto cleanup;
2494                         }
2495                         memcpy(&prime_mac, &phy_mac,
2496                                 sizeof(struct rte_ether_addr));
2497                 }
2498         } else if (rte_is_zero_ether_addr(&prime_mac)) {
2499                 /* In case phys and prime, both are zero, create random MAC */
2500                 rte_eth_random_addr(prime_mac.addr_bytes);
2501                 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2502                                                 priv->token,
2503                                                 prime_mac.addr_bytes);
2504                 if (ret) {
2505                         DPAA2_PMD_ERR("Unable to set MAC Address: %d", ret);
2506                         goto cleanup;
2507                 }
2508         }
2509
2510         /* prime_mac the final MAC address */
2511         memcpy(mac_entry, &prime_mac, sizeof(struct rte_ether_addr));
2512         return 0;
2513
2514 cleanup:
2515         return -1;
2516 }
2517
2518 static int
2519 check_devargs_handler(__rte_unused const char *key, const char *value,
2520                       __rte_unused void *opaque)
2521 {
2522         if (strcmp(value, "1"))
2523                 return -1;
2524
2525         return 0;
2526 }
2527
2528 static int
2529 dpaa2_get_devargs(struct rte_devargs *devargs, const char *key)
2530 {
2531         struct rte_kvargs *kvlist;
2532
2533         if (!devargs)
2534                 return 0;
2535
2536         kvlist = rte_kvargs_parse(devargs->args, NULL);
2537         if (!kvlist)
2538                 return 0;
2539
2540         if (!rte_kvargs_count(kvlist, key)) {
2541                 rte_kvargs_free(kvlist);
2542                 return 0;
2543         }
2544
2545         if (rte_kvargs_process(kvlist, key,
2546                                check_devargs_handler, NULL) < 0) {
2547                 rte_kvargs_free(kvlist);
2548                 return 0;
2549         }
2550         rte_kvargs_free(kvlist);
2551
2552         return 1;
2553 }
2554
2555 static int
2556 dpaa2_dev_init(struct rte_eth_dev *eth_dev)
2557 {
2558         struct rte_device *dev = eth_dev->device;
2559         struct rte_dpaa2_device *dpaa2_dev;
2560         struct fsl_mc_io *dpni_dev;
2561         struct dpni_attr attr;
2562         struct dpaa2_dev_priv *priv = eth_dev->data->dev_private;
2563         struct dpni_buffer_layout layout;
2564         int ret, hw_id, i;
2565
2566         PMD_INIT_FUNC_TRACE();
2567
2568         dpni_dev = rte_malloc(NULL, sizeof(struct fsl_mc_io), 0);
2569         if (!dpni_dev) {
2570                 DPAA2_PMD_ERR("Memory allocation failed for dpni device");
2571                 return -1;
2572         }
2573         dpni_dev->regs = dpaa2_get_mcp_ptr(MC_PORTAL_INDEX);
2574         eth_dev->process_private = (void *)dpni_dev;
2575
2576         /* For secondary processes, the primary has done all the work */
2577         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2578                 /* In case of secondary, only burst and ops API need to be
2579                  * plugged.
2580                  */
2581                 eth_dev->dev_ops = &dpaa2_ethdev_ops;
2582                 eth_dev->rx_queue_count = dpaa2_dev_rx_queue_count;
2583                 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE))
2584                         eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2585                 else if (dpaa2_get_devargs(dev->devargs,
2586                                         DRIVER_NO_PREFETCH_MODE))
2587                         eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2588                 else
2589                         eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2590                 eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2591                 return 0;
2592         }
2593
2594         dpaa2_dev = container_of(dev, struct rte_dpaa2_device, device);
2595
2596         hw_id = dpaa2_dev->object_id;
2597         ret = dpni_open(dpni_dev, CMD_PRI_LOW, hw_id, &priv->token);
2598         if (ret) {
2599                 DPAA2_PMD_ERR(
2600                              "Failure in opening dpni@%d with err code %d",
2601                              hw_id, ret);
2602                 rte_free(dpni_dev);
2603                 return -1;
2604         }
2605
2606         /* Clean the device first */
2607         ret = dpni_reset(dpni_dev, CMD_PRI_LOW, priv->token);
2608         if (ret) {
2609                 DPAA2_PMD_ERR("Failure cleaning dpni@%d with err code %d",
2610                               hw_id, ret);
2611                 goto init_err;
2612         }
2613
2614         ret = dpni_get_attributes(dpni_dev, CMD_PRI_LOW, priv->token, &attr);
2615         if (ret) {
2616                 DPAA2_PMD_ERR(
2617                              "Failure in get dpni@%d attribute, err code %d",
2618                              hw_id, ret);
2619                 goto init_err;
2620         }
2621
2622         priv->num_rx_tc = attr.num_rx_tcs;
2623         priv->qos_entries = attr.qos_entries;
2624         priv->fs_entries = attr.fs_entries;
2625         priv->dist_queues = attr.num_queues;
2626
2627         /* only if the custom CG is enabled */
2628         if (attr.options & DPNI_OPT_CUSTOM_CG)
2629                 priv->max_cgs = attr.num_cgs;
2630         else
2631                 priv->max_cgs = 0;
2632
2633         for (i = 0; i < priv->max_cgs; i++)
2634                 priv->cgid_in_use[i] = 0;
2635
2636         for (i = 0; i < attr.num_rx_tcs; i++)
2637                 priv->nb_rx_queues += attr.num_queues;
2638
2639         /* Using number of TX queues as number of TX TCs */
2640         priv->nb_tx_queues = attr.num_tx_tcs;
2641
2642         DPAA2_PMD_DEBUG("RX-TC= %d, rx_queues= %d, tx_queues=%d, max_cgs=%d",
2643                         priv->num_rx_tc, priv->nb_rx_queues,
2644                         priv->nb_tx_queues, priv->max_cgs);
2645
2646         priv->hw = dpni_dev;
2647         priv->hw_id = hw_id;
2648         priv->options = attr.options;
2649         priv->max_mac_filters = attr.mac_filter_entries;
2650         priv->max_vlan_filters = attr.vlan_filter_entries;
2651         priv->flags = 0;
2652 #if defined(RTE_LIBRTE_IEEE1588)
2653         printf("DPDK IEEE1588 is enabled\n");
2654         priv->flags |= DPAA2_TX_CONF_ENABLE;
2655 #endif
2656         /* Used with ``fslmc:dpni.1,drv_tx_conf=1`` */
2657         if (dpaa2_get_devargs(dev->devargs, DRIVER_TX_CONF)) {
2658                 priv->flags |= DPAA2_TX_CONF_ENABLE;
2659                 DPAA2_PMD_INFO("TX_CONF Enabled");
2660         }
2661
2662         if (dpaa2_get_devargs(dev->devargs, DRIVER_ERROR_QUEUE)) {
2663                 dpaa2_enable_err_queue = 1;
2664                 DPAA2_PMD_INFO("Enable error queue");
2665         }
2666
2667         /* Allocate memory for hardware structure for queues */
2668         ret = dpaa2_alloc_rx_tx_queues(eth_dev);
2669         if (ret) {
2670                 DPAA2_PMD_ERR("Queue allocation Failed");
2671                 goto init_err;
2672         }
2673
2674         /* Allocate memory for storing MAC addresses.
2675          * Table of mac_filter_entries size is allocated so that RTE ether lib
2676          * can add MAC entries when rte_eth_dev_mac_addr_add is called.
2677          */
2678         eth_dev->data->mac_addrs = rte_zmalloc("dpni",
2679                 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries, 0);
2680         if (eth_dev->data->mac_addrs == NULL) {
2681                 DPAA2_PMD_ERR(
2682                    "Failed to allocate %d bytes needed to store MAC addresses",
2683                    RTE_ETHER_ADDR_LEN * attr.mac_filter_entries);
2684                 ret = -ENOMEM;
2685                 goto init_err;
2686         }
2687
2688         ret = populate_mac_addr(dpni_dev, priv, &eth_dev->data->mac_addrs[0]);
2689         if (ret) {
2690                 DPAA2_PMD_ERR("Unable to fetch MAC Address for device");
2691                 rte_free(eth_dev->data->mac_addrs);
2692                 eth_dev->data->mac_addrs = NULL;
2693                 goto init_err;
2694         }
2695
2696         /* ... tx buffer layout ... */
2697         memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2698         if (priv->flags & DPAA2_TX_CONF_ENABLE) {
2699                 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
2700                                  DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2701                 layout.pass_timestamp = true;
2702         } else {
2703                 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2704         }
2705         layout.pass_frame_status = 1;
2706         ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2707                                      DPNI_QUEUE_TX, &layout);
2708         if (ret) {
2709                 DPAA2_PMD_ERR("Error (%d) in setting tx buffer layout", ret);
2710                 goto init_err;
2711         }
2712
2713         /* ... tx-conf and error buffer layout ... */
2714         memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2715         if (priv->flags & DPAA2_TX_CONF_ENABLE) {
2716                 layout.options = DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2717                 layout.pass_timestamp = true;
2718         }
2719         layout.options |= DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2720         layout.pass_frame_status = 1;
2721         ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2722                                      DPNI_QUEUE_TX_CONFIRM, &layout);
2723         if (ret) {
2724                 DPAA2_PMD_ERR("Error (%d) in setting tx-conf buffer layout",
2725                              ret);
2726                 goto init_err;
2727         }
2728
2729         eth_dev->dev_ops = &dpaa2_ethdev_ops;
2730
2731         if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE)) {
2732                 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2733                 DPAA2_PMD_INFO("Loopback mode");
2734         } else if (dpaa2_get_devargs(dev->devargs, DRIVER_NO_PREFETCH_MODE)) {
2735                 eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2736                 DPAA2_PMD_INFO("No Prefetch mode");
2737         } else {
2738                 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2739         }
2740         eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2741
2742         /*Init fields w.r.t. classficaition*/
2743         memset(&priv->extract.qos_key_extract, 0,
2744                 sizeof(struct dpaa2_key_extract));
2745         priv->extract.qos_extract_param = (size_t)rte_malloc(NULL, 256, 64);
2746         if (!priv->extract.qos_extract_param) {
2747                 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow "
2748                             " classificaiton ", ret);
2749                 goto init_err;
2750         }
2751         priv->extract.qos_key_extract.key_info.ipv4_src_offset =
2752                 IP_ADDRESS_OFFSET_INVALID;
2753         priv->extract.qos_key_extract.key_info.ipv4_dst_offset =
2754                 IP_ADDRESS_OFFSET_INVALID;
2755         priv->extract.qos_key_extract.key_info.ipv6_src_offset =
2756                 IP_ADDRESS_OFFSET_INVALID;
2757         priv->extract.qos_key_extract.key_info.ipv6_dst_offset =
2758                 IP_ADDRESS_OFFSET_INVALID;
2759
2760         for (i = 0; i < MAX_TCS; i++) {
2761                 memset(&priv->extract.tc_key_extract[i], 0,
2762                         sizeof(struct dpaa2_key_extract));
2763                 priv->extract.tc_extract_param[i] =
2764                         (size_t)rte_malloc(NULL, 256, 64);
2765                 if (!priv->extract.tc_extract_param[i]) {
2766                         DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow classificaiton",
2767                                      ret);
2768                         goto init_err;
2769                 }
2770                 priv->extract.tc_key_extract[i].key_info.ipv4_src_offset =
2771                         IP_ADDRESS_OFFSET_INVALID;
2772                 priv->extract.tc_key_extract[i].key_info.ipv4_dst_offset =
2773                         IP_ADDRESS_OFFSET_INVALID;
2774                 priv->extract.tc_key_extract[i].key_info.ipv6_src_offset =
2775                         IP_ADDRESS_OFFSET_INVALID;
2776                 priv->extract.tc_key_extract[i].key_info.ipv6_dst_offset =
2777                         IP_ADDRESS_OFFSET_INVALID;
2778         }
2779
2780         ret = dpni_set_max_frame_length(dpni_dev, CMD_PRI_LOW, priv->token,
2781                                         RTE_ETHER_MAX_LEN - RTE_ETHER_CRC_LEN
2782                                         + VLAN_TAG_SIZE);
2783         if (ret) {
2784                 DPAA2_PMD_ERR("Unable to set mtu. check config");
2785                 goto init_err;
2786         }
2787
2788         /*TODO To enable soft parser support DPAA2 driver needs to integrate
2789          * with external entity to receive byte code for software sequence
2790          * and same will be offload to the H/W using MC interface.
2791          * Currently it is assumed that DPAA2 driver has byte code by some
2792          * mean and same if offloaded to H/W.
2793          */
2794         if (getenv("DPAA2_ENABLE_SOFT_PARSER")) {
2795                 WRIOP_SS_INITIALIZER(priv);
2796                 ret = dpaa2_eth_load_wriop_soft_parser(priv, DPNI_SS_INGRESS);
2797                 if (ret < 0) {
2798                         DPAA2_PMD_ERR(" Error(%d) in loading softparser\n",
2799                                       ret);
2800                         return ret;
2801                 }
2802
2803                 ret = dpaa2_eth_enable_wriop_soft_parser(priv,
2804                                                          DPNI_SS_INGRESS);
2805                 if (ret < 0) {
2806                         DPAA2_PMD_ERR(" Error(%d) in enabling softparser\n",
2807                                       ret);
2808                         return ret;
2809                 }
2810         }
2811         RTE_LOG(INFO, PMD, "%s: netdev created\n", eth_dev->data->name);
2812         return 0;
2813 init_err:
2814         dpaa2_dev_close(eth_dev);
2815
2816         return ret;
2817 }
2818
2819 int dpaa2_dev_is_dpaa2(struct rte_eth_dev *dev)
2820 {
2821         return dev->device->driver == &rte_dpaa2_pmd.driver;
2822 }
2823
2824 static int
2825 rte_dpaa2_probe(struct rte_dpaa2_driver *dpaa2_drv,
2826                 struct rte_dpaa2_device *dpaa2_dev)
2827 {
2828         struct rte_eth_dev *eth_dev;
2829         struct dpaa2_dev_priv *dev_priv;
2830         int diag;
2831
2832         if ((DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE) >
2833                 RTE_PKTMBUF_HEADROOM) {
2834                 DPAA2_PMD_ERR(
2835                 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA2 Annotation req(%d)",
2836                 RTE_PKTMBUF_HEADROOM,
2837                 DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE);
2838
2839                 return -1;
2840         }
2841
2842         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2843                 eth_dev = rte_eth_dev_allocate(dpaa2_dev->device.name);
2844                 if (!eth_dev)
2845                         return -ENODEV;
2846                 dev_priv = rte_zmalloc("ethdev private structure",
2847                                        sizeof(struct dpaa2_dev_priv),
2848                                        RTE_CACHE_LINE_SIZE);
2849                 if (dev_priv == NULL) {
2850                         DPAA2_PMD_CRIT(
2851                                 "Unable to allocate memory for private data");
2852                         rte_eth_dev_release_port(eth_dev);
2853                         return -ENOMEM;
2854                 }
2855                 eth_dev->data->dev_private = (void *)dev_priv;
2856                 /* Store a pointer to eth_dev in dev_private */
2857                 dev_priv->eth_dev = eth_dev;
2858         } else {
2859                 eth_dev = rte_eth_dev_attach_secondary(dpaa2_dev->device.name);
2860                 if (!eth_dev) {
2861                         DPAA2_PMD_DEBUG("returning enodev");
2862                         return -ENODEV;
2863                 }
2864         }
2865
2866         eth_dev->device = &dpaa2_dev->device;
2867
2868         dpaa2_dev->eth_dev = eth_dev;
2869         eth_dev->data->rx_mbuf_alloc_failed = 0;
2870
2871         if (dpaa2_drv->drv_flags & RTE_DPAA2_DRV_INTR_LSC)
2872                 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;
2873
2874         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2875
2876         /* Invoke PMD device initialization function */
2877         diag = dpaa2_dev_init(eth_dev);
2878         if (diag == 0) {
2879                 rte_eth_dev_probing_finish(eth_dev);
2880                 return 0;
2881         }
2882
2883         rte_eth_dev_release_port(eth_dev);
2884         return diag;
2885 }
2886
2887 static int
2888 rte_dpaa2_remove(struct rte_dpaa2_device *dpaa2_dev)
2889 {
2890         struct rte_eth_dev *eth_dev;
2891         int ret;
2892
2893         eth_dev = dpaa2_dev->eth_dev;
2894         dpaa2_dev_close(eth_dev);
2895         ret = rte_eth_dev_release_port(eth_dev);
2896
2897         return ret;
2898 }
2899
2900 static struct rte_dpaa2_driver rte_dpaa2_pmd = {
2901         .drv_flags = RTE_DPAA2_DRV_INTR_LSC | RTE_DPAA2_DRV_IOVA_AS_VA,
2902         .drv_type = DPAA2_ETH,
2903         .probe = rte_dpaa2_probe,
2904         .remove = rte_dpaa2_remove,
2905 };
2906
2907 RTE_PMD_REGISTER_DPAA2(NET_DPAA2_PMD_DRIVER_NAME, rte_dpaa2_pmd);
2908 RTE_PMD_REGISTER_PARAM_STRING(NET_DPAA2_PMD_DRIVER_NAME,
2909                 DRIVER_LOOPBACK_MODE "=<int> "
2910                 DRIVER_NO_PREFETCH_MODE "=<int>"
2911                 DRIVER_TX_CONF "=<int>"
2912                 DRIVER_ERROR_QUEUE "=<int>");
2913 RTE_LOG_REGISTER_DEFAULT(dpaa2_logtype_pmd, NOTICE);