drivers/net/dpaa2/dpaa2_ethdev.c

   1 /* * SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  *   Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
   4  *   Copyright 2016-2021 NXP
   5  *
   6  */
   7
   8 #include <time.h>
   9 #include <net/if.h>
  10
  11 #include <rte_mbuf.h>
  12 #include <ethdev_driver.h>
  13 #include <rte_malloc.h>
  14 #include <rte_memcpy.h>
  15 #include <rte_string_fns.h>
  16 #include <rte_cycles.h>
  17 #include <rte_kvargs.h>
  18 #include <rte_dev.h>
  19 #include <rte_fslmc.h>
  20 #include <rte_flow_driver.h>
  21
  22 #include "dpaa2_pmd_logs.h"
  23 #include <fslmc_vfio.h>
  24 #include <dpaa2_hw_pvt.h>
  25 #include <dpaa2_hw_mempool.h>
  26 #include <dpaa2_hw_dpio.h>
  27 #include <mc/fsl_dpmng.h>
  28 #include "dpaa2_ethdev.h"
  29 #include "dpaa2_sparser.h"
  30 #include <fsl_qbman_debug.h>
  31
  32 #define DRIVER_LOOPBACK_MODE "drv_loopback"
  33 #define DRIVER_NO_PREFETCH_MODE "drv_no_prefetch"
  34 #define DRIVER_TX_CONF "drv_tx_conf"
  35 #define DRIVER_ERROR_QUEUE  "drv_err_queue"
  36 #define CHECK_INTERVAL         100  /* 100ms */
  37 #define MAX_REPEAT_TIME        90   /* 9s (90 * 100ms) in total */
  38
  39 /* Supported Rx offloads */
  40 static uint64_t dev_rx_offloads_sup =
  41                 DEV_RX_OFFLOAD_CHECKSUM |
  42                 DEV_RX_OFFLOAD_SCTP_CKSUM |
  43                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
  44                 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
  45                 DEV_RX_OFFLOAD_VLAN_STRIP |
  46                 DEV_RX_OFFLOAD_VLAN_FILTER |
  47                 DEV_RX_OFFLOAD_JUMBO_FRAME |
  48                 DEV_RX_OFFLOAD_TIMESTAMP;
  49
  50 /* Rx offloads which cannot be disabled */
  51 static uint64_t dev_rx_offloads_nodis =
  52                 DEV_RX_OFFLOAD_RSS_HASH |
  53                 DEV_RX_OFFLOAD_SCATTER;
  54
  55 /* Supported Tx offloads */
  56 static uint64_t dev_tx_offloads_sup =
  57                 DEV_TX_OFFLOAD_VLAN_INSERT |
  58                 DEV_TX_OFFLOAD_IPV4_CKSUM |
  59                 DEV_TX_OFFLOAD_UDP_CKSUM |
  60                 DEV_TX_OFFLOAD_TCP_CKSUM |
  61                 DEV_TX_OFFLOAD_SCTP_CKSUM |
  62                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
  63                 DEV_TX_OFFLOAD_MT_LOCKFREE |
  64                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
  65
  66 /* Tx offloads which cannot be disabled */
  67 static uint64_t dev_tx_offloads_nodis =
  68                 DEV_TX_OFFLOAD_MULTI_SEGS;
  69
  70 /* enable timestamp in mbuf */
  71 bool dpaa2_enable_ts[RTE_MAX_ETHPORTS];
  72 uint64_t dpaa2_timestamp_rx_dynflag;
  73 int dpaa2_timestamp_dynfield_offset = -1;
  74
  75 /* Enable error queue */
  76 bool dpaa2_enable_err_queue;
  77
  78 struct rte_dpaa2_xstats_name_off {
  79         char name[RTE_ETH_XSTATS_NAME_SIZE];
  80         uint8_t page_id; /* dpni statistics page id */
  81         uint8_t stats_id; /* stats id in the given page */
  82 };
  83
  84 static const struct rte_dpaa2_xstats_name_off dpaa2_xstats_strings[] = {
  85         {"ingress_multicast_frames", 0, 2},
  86         {"ingress_multicast_bytes", 0, 3},
  87         {"ingress_broadcast_frames", 0, 4},
  88         {"ingress_broadcast_bytes", 0, 5},
  89         {"egress_multicast_frames", 1, 2},
  90         {"egress_multicast_bytes", 1, 3},
  91         {"egress_broadcast_frames", 1, 4},
  92         {"egress_broadcast_bytes", 1, 5},
  93         {"ingress_filtered_frames", 2, 0},
  94         {"ingress_discarded_frames", 2, 1},
  95         {"ingress_nobuffer_discards", 2, 2},
  96         {"egress_discarded_frames", 2, 3},
  97         {"egress_confirmed_frames", 2, 4},
  98         {"cgr_reject_frames", 4, 0},
  99         {"cgr_reject_bytes", 4, 1},
 100 };
 101
 102 static struct rte_dpaa2_driver rte_dpaa2_pmd;
 103 static int dpaa2_dev_link_update(struct rte_eth_dev *dev,
 104                                  int wait_to_complete);
 105 static int dpaa2_dev_set_link_up(struct rte_eth_dev *dev);
 106 static int dpaa2_dev_set_link_down(struct rte_eth_dev *dev);
 107 static int dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 108
 109 static int
 110 dpaa2_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 111 {
 112         int ret;
 113         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 114         struct fsl_mc_io *dpni = dev->process_private;
 115
 116         PMD_INIT_FUNC_TRACE();
 117
 118         if (dpni == NULL) {
 119                 DPAA2_PMD_ERR("dpni is NULL");
 120                 return -1;
 121         }
 122
 123         if (on)
 124                 ret = dpni_add_vlan_id(dpni, CMD_PRI_LOW, priv->token,
 125                                        vlan_id, 0, 0, 0);
 126         else
 127                 ret = dpni_remove_vlan_id(dpni, CMD_PRI_LOW,
 128                                           priv->token, vlan_id);
 129
 130         if (ret < 0)
 131                 DPAA2_PMD_ERR("ret = %d Unable to add/rem vlan %d hwid =%d",
 132                               ret, vlan_id, priv->hw_id);
 133
 134         return ret;
 135 }
 136
 137 static int
 138 dpaa2_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 139 {
 140         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 141         struct fsl_mc_io *dpni = dev->process_private;
 142         int ret = 0;
 143
 144         PMD_INIT_FUNC_TRACE();
 145
 146         if (mask & ETH_VLAN_FILTER_MASK) {
 147                 /* VLAN Filter not avaialble */
 148                 if (!priv->max_vlan_filters) {
 149                         DPAA2_PMD_INFO("VLAN filter not available");
 150                         return -ENOTSUP;
 151                 }
 152
 153                 if (dev->data->dev_conf.rxmode.offloads &
 154                         DEV_RX_OFFLOAD_VLAN_FILTER)
 155                         ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
 156                                                       priv->token, true);
 157                 else
 158                         ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
 159                                                       priv->token, false);
 160                 if (ret < 0)
 161                         DPAA2_PMD_INFO("Unable to set vlan filter = %d", ret);
 162         }
 163
 164         return ret;
 165 }
 166
 167 static int
 168 dpaa2_vlan_tpid_set(struct rte_eth_dev *dev,
 169                       enum rte_vlan_type vlan_type __rte_unused,
 170                       uint16_t tpid)
 171 {
 172         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 173         struct fsl_mc_io *dpni = dev->process_private;
 174         int ret = -ENOTSUP;
 175
 176         PMD_INIT_FUNC_TRACE();
 177
 178         /* nothing to be done for standard vlan tpids */
 179         if (tpid == 0x8100 || tpid == 0x88A8)
 180                 return 0;
 181
 182         ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
 183                                    priv->token, tpid);
 184         if (ret < 0)
 185                 DPAA2_PMD_INFO("Unable to set vlan tpid = %d", ret);
 186         /* if already configured tpids, remove them first */
 187         if (ret == -EBUSY) {
 188                 struct dpni_custom_tpid_cfg tpid_list = {0};
 189
 190                 ret = dpni_get_custom_tpid(dpni, CMD_PRI_LOW,
 191                                    priv->token, &tpid_list);
 192                 if (ret < 0)
 193                         goto fail;
 194                 ret = dpni_remove_custom_tpid(dpni, CMD_PRI_LOW,
 195                                    priv->token, tpid_list.tpid1);
 196                 if (ret < 0)
 197                         goto fail;
 198                 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
 199                                            priv->token, tpid);
 200         }
 201 fail:
 202         return ret;
 203 }
 204
 205 static int
 206 dpaa2_fw_version_get(struct rte_eth_dev *dev,
 207                      char *fw_version,
 208                      size_t fw_size)
 209 {
 210         int ret;
 211         struct fsl_mc_io *dpni = dev->process_private;
 212         struct mc_soc_version mc_plat_info = {0};
 213         struct mc_version mc_ver_info = {0};
 214
 215         PMD_INIT_FUNC_TRACE();
 216
 217         if (mc_get_soc_version(dpni, CMD_PRI_LOW, &mc_plat_info))
 218                 DPAA2_PMD_WARN("\tmc_get_soc_version failed");
 219
 220         if (mc_get_version(dpni, CMD_PRI_LOW, &mc_ver_info))
 221                 DPAA2_PMD_WARN("\tmc_get_version failed");
 222
 223         ret = snprintf(fw_version, fw_size,
 224                        "%x-%d.%d.%d",
 225                        mc_plat_info.svr,
 226                        mc_ver_info.major,
 227                        mc_ver_info.minor,
 228                        mc_ver_info.revision);
 229         if (ret < 0)
 230                 return -EINVAL;
 231
 232         ret += 1; /* add the size of '\0' */
 233         if (fw_size < (size_t)ret)
 234                 return ret;
 235         else
 236                 return 0;
 237 }
 238
 239 static int
 240 dpaa2_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
 241 {
 242         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 243
 244         PMD_INIT_FUNC_TRACE();
 245
 246         dev_info->max_mac_addrs = priv->max_mac_filters;
 247         dev_info->max_rx_pktlen = DPAA2_MAX_RX_PKT_LEN;
 248         dev_info->min_rx_bufsize = DPAA2_MIN_RX_BUF_SIZE;
 249         dev_info->max_rx_queues = (uint16_t)priv->nb_rx_queues;
 250         dev_info->max_tx_queues = (uint16_t)priv->nb_tx_queues;
 251         dev_info->rx_offload_capa = dev_rx_offloads_sup |
 252                                         dev_rx_offloads_nodis;
 253         dev_info->tx_offload_capa = dev_tx_offloads_sup |
 254                                         dev_tx_offloads_nodis;
 255         dev_info->speed_capa = ETH_LINK_SPEED_1G |
 256                         ETH_LINK_SPEED_2_5G |
 257                         ETH_LINK_SPEED_10G;
 258
 259         dev_info->max_hash_mac_addrs = 0;
 260         dev_info->max_vfs = 0;
 261         dev_info->max_vmdq_pools = ETH_16_POOLS;
 262         dev_info->flow_type_rss_offloads = DPAA2_RSS_OFFLOAD_ALL;
 263
 264         dev_info->default_rxportconf.burst_size = dpaa2_dqrr_size;
 265         /* same is rx size for best perf */
 266         dev_info->default_txportconf.burst_size = dpaa2_dqrr_size;
 267
 268         dev_info->default_rxportconf.nb_queues = 1;
 269         dev_info->default_txportconf.nb_queues = 1;
 270         dev_info->default_txportconf.ring_size = CONG_ENTER_TX_THRESHOLD;
 271         dev_info->default_rxportconf.ring_size = DPAA2_RX_DEFAULT_NBDESC;
 272
 273         if (dpaa2_svr_family == SVR_LX2160A) {
 274                 dev_info->speed_capa |= ETH_LINK_SPEED_25G |
 275                                 ETH_LINK_SPEED_40G |
 276                                 ETH_LINK_SPEED_50G |
 277                                 ETH_LINK_SPEED_100G;
 278         }
 279
 280         return 0;
 281 }
 282
 283 static int
 284 dpaa2_dev_rx_burst_mode_get(struct rte_eth_dev *dev,
 285                         __rte_unused uint16_t queue_id,
 286                         struct rte_eth_burst_mode *mode)
 287 {
 288         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 289         int ret = -EINVAL;
 290         unsigned int i;
 291         const struct burst_info {
 292                 uint64_t flags;
 293                 const char *output;
 294         } rx_offload_map[] = {
 295                         {DEV_RX_OFFLOAD_CHECKSUM, " Checksum,"},
 296                         {DEV_RX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
 297                         {DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
 298                         {DEV_RX_OFFLOAD_OUTER_UDP_CKSUM, " Outer UDP csum,"},
 299                         {DEV_RX_OFFLOAD_VLAN_STRIP, " VLAN strip,"},
 300                         {DEV_RX_OFFLOAD_VLAN_FILTER, " VLAN filter,"},
 301                         {DEV_RX_OFFLOAD_JUMBO_FRAME, " Jumbo frame,"},
 302                         {DEV_RX_OFFLOAD_TIMESTAMP, " Timestamp,"},
 303                         {DEV_RX_OFFLOAD_RSS_HASH, " RSS,"},
 304                         {DEV_RX_OFFLOAD_SCATTER, " Scattered,"}
 305         };
 306
 307         /* Update Rx offload info */
 308         for (i = 0; i < RTE_DIM(rx_offload_map); i++) {
 309                 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) {
 310                         snprintf(mode->info, sizeof(mode->info), "%s",
 311                                 rx_offload_map[i].output);
 312                         ret = 0;
 313                         break;
 314                 }
 315         }
 316         return ret;
 317 }
 318
 319 static int
 320 dpaa2_dev_tx_burst_mode_get(struct rte_eth_dev *dev,
 321                         __rte_unused uint16_t queue_id,
 322                         struct rte_eth_burst_mode *mode)
 323 {
 324         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 325         int ret = -EINVAL;
 326         unsigned int i;
 327         const struct burst_info {
 328                 uint64_t flags;
 329                 const char *output;
 330         } tx_offload_map[] = {
 331                         {DEV_TX_OFFLOAD_VLAN_INSERT, " VLAN Insert,"},
 332                         {DEV_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"},
 333                         {DEV_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"},
 334                         {DEV_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"},
 335                         {DEV_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
 336                         {DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
 337                         {DEV_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"},
 338                         {DEV_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"},
 339                         {DEV_TX_OFFLOAD_MULTI_SEGS, " Scattered,"}
 340         };
 341
 342         /* Update Tx offload info */
 343         for (i = 0; i < RTE_DIM(tx_offload_map); i++) {
 344                 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) {
 345                         snprintf(mode->info, sizeof(mode->info), "%s",
 346                                 tx_offload_map[i].output);
 347                         ret = 0;
 348                         break;
 349                 }
 350         }
 351         return ret;
 352 }
 353
 354 static int
 355 dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev)
 356 {
 357         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 358         uint16_t dist_idx;
 359         uint32_t vq_id;
 360         uint8_t num_rxqueue_per_tc;
 361         struct dpaa2_queue *mc_q, *mcq;
 362         uint32_t tot_queues;
 363         int i;
 364         struct dpaa2_queue *dpaa2_q;
 365
 366         PMD_INIT_FUNC_TRACE();
 367
 368         num_rxqueue_per_tc = (priv->nb_rx_queues / priv->num_rx_tc);
 369         if (priv->flags & DPAA2_TX_CONF_ENABLE)
 370                 tot_queues = priv->nb_rx_queues + 2 * priv->nb_tx_queues;
 371         else
 372                 tot_queues = priv->nb_rx_queues + priv->nb_tx_queues;
 373         mc_q = rte_malloc(NULL, sizeof(struct dpaa2_queue) * tot_queues,
 374                           RTE_CACHE_LINE_SIZE);
 375         if (!mc_q) {
 376                 DPAA2_PMD_ERR("Memory allocation failed for rx/tx queues");
 377                 return -1;
 378         }
 379
 380         for (i = 0; i < priv->nb_rx_queues; i++) {
 381                 mc_q->eth_data = dev->data;
 382                 priv->rx_vq[i] = mc_q++;
 383                 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
 384                 dpaa2_q->q_storage = rte_malloc("dq_storage",
 385                                         sizeof(struct queue_storage_info_t),
 386                                         RTE_CACHE_LINE_SIZE);
 387                 if (!dpaa2_q->q_storage)
 388                         goto fail;
 389
 390                 memset(dpaa2_q->q_storage, 0,
 391                        sizeof(struct queue_storage_info_t));
 392                 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
 393                         goto fail;
 394         }
 395
 396         if (dpaa2_enable_err_queue) {
 397                 priv->rx_err_vq = rte_zmalloc("dpni_rx_err",
 398                         sizeof(struct dpaa2_queue), 0);
 399
 400                 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq;
 401                 dpaa2_q->q_storage = rte_malloc("err_dq_storage",
 402                                         sizeof(struct queue_storage_info_t) *
 403                                         RTE_MAX_LCORE,
 404                                         RTE_CACHE_LINE_SIZE);
 405                 if (!dpaa2_q->q_storage)
 406                         goto fail;
 407
 408                 memset(dpaa2_q->q_storage, 0,
 409                        sizeof(struct queue_storage_info_t));
 410                 for (i = 0; i < RTE_MAX_LCORE; i++)
 411                         if (dpaa2_alloc_dq_storage(&dpaa2_q->q_storage[i]))
 412                                 goto fail;
 413         }
 414
 415         for (i = 0; i < priv->nb_tx_queues; i++) {
 416                 mc_q->eth_data = dev->data;
 417                 mc_q->flow_id = 0xffff;
 418                 priv->tx_vq[i] = mc_q++;
 419                 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
 420                 dpaa2_q->cscn = rte_malloc(NULL,
 421                                            sizeof(struct qbman_result), 16);
 422                 if (!dpaa2_q->cscn)
 423                         goto fail_tx;
 424         }
 425
 426         if (priv->flags & DPAA2_TX_CONF_ENABLE) {
 427                 /*Setup tx confirmation queues*/
 428                 for (i = 0; i < priv->nb_tx_queues; i++) {
 429                         mc_q->eth_data = dev->data;
 430                         mc_q->tc_index = i;
 431                         mc_q->flow_id = 0;
 432                         priv->tx_conf_vq[i] = mc_q++;
 433                         dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
 434                         dpaa2_q->q_storage =
 435                                 rte_malloc("dq_storage",
 436                                         sizeof(struct queue_storage_info_t),
 437                                         RTE_CACHE_LINE_SIZE);
 438                         if (!dpaa2_q->q_storage)
 439                                 goto fail_tx_conf;
 440
 441                         memset(dpaa2_q->q_storage, 0,
 442                                sizeof(struct queue_storage_info_t));
 443                         if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
 444                                 goto fail_tx_conf;
 445                 }
 446         }
 447
 448         vq_id = 0;
 449         for (dist_idx = 0; dist_idx < priv->nb_rx_queues; dist_idx++) {
 450                 mcq = (struct dpaa2_queue *)priv->rx_vq[vq_id];
 451                 mcq->tc_index = dist_idx / num_rxqueue_per_tc;
 452                 mcq->flow_id = dist_idx % num_rxqueue_per_tc;
 453                 vq_id++;
 454         }
 455
 456         return 0;
 457 fail_tx_conf:
 458         i -= 1;
 459         while (i >= 0) {
 460                 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
 461                 rte_free(dpaa2_q->q_storage);
 462                 priv->tx_conf_vq[i--] = NULL;
 463         }
 464         i = priv->nb_tx_queues;
 465 fail_tx:
 466         i -= 1;
 467         while (i >= 0) {
 468                 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
 469                 rte_free(dpaa2_q->cscn);
 470                 priv->tx_vq[i--] = NULL;
 471         }
 472         i = priv->nb_rx_queues;
 473 fail:
 474         i -= 1;
 475         mc_q = priv->rx_vq[0];
 476         while (i >= 0) {
 477                 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
 478                 dpaa2_free_dq_storage(dpaa2_q->q_storage);
 479                 rte_free(dpaa2_q->q_storage);
 480                 priv->rx_vq[i--] = NULL;
 481         }
 482
 483         if (dpaa2_enable_err_queue) {
 484                 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq;
 485                 if (dpaa2_q->q_storage)
 486                         dpaa2_free_dq_storage(dpaa2_q->q_storage);
 487                 rte_free(dpaa2_q->q_storage);
 488         }
 489
 490         rte_free(mc_q);
 491         return -1;
 492 }
 493
 494 static void
 495 dpaa2_free_rx_tx_queues(struct rte_eth_dev *dev)
 496 {
 497         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 498         struct dpaa2_queue *dpaa2_q;
 499         int i;
 500
 501         PMD_INIT_FUNC_TRACE();
 502
 503         /* Queue allocation base */
 504         if (priv->rx_vq[0]) {
 505                 /* cleaning up queue storage */
 506                 for (i = 0; i < priv->nb_rx_queues; i++) {
 507                         dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
 508                         if (dpaa2_q->q_storage)
 509                                 rte_free(dpaa2_q->q_storage);
 510                 }
 511                 /* cleanup tx queue cscn */
 512                 for (i = 0; i < priv->nb_tx_queues; i++) {
 513                         dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
 514                         rte_free(dpaa2_q->cscn);
 515                 }
 516                 if (priv->flags & DPAA2_TX_CONF_ENABLE) {
 517                         /* cleanup tx conf queue storage */
 518                         for (i = 0; i < priv->nb_tx_queues; i++) {
 519                                 dpaa2_q = (struct dpaa2_queue *)
 520                                                 priv->tx_conf_vq[i];
 521                                 rte_free(dpaa2_q->q_storage);
 522                         }
 523                 }
 524                 /*free memory for all queues (RX+TX) */
 525                 rte_free(priv->rx_vq[0]);
 526                 priv->rx_vq[0] = NULL;
 527         }
 528 }
 529
 530 static int
 531 dpaa2_eth_dev_configure(struct rte_eth_dev *dev)
 532 {
 533         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 534         struct fsl_mc_io *dpni = dev->process_private;
 535         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 536         uint64_t rx_offloads = eth_conf->rxmode.offloads;
 537         uint64_t tx_offloads = eth_conf->txmode.offloads;
 538         int rx_l3_csum_offload = false;
 539         int rx_l4_csum_offload = false;
 540         int tx_l3_csum_offload = false;
 541         int tx_l4_csum_offload = false;
 542         int ret, tc_index;
 543
 544         PMD_INIT_FUNC_TRACE();
 545
 546         /* Rx offloads which are enabled by default */
 547         if (dev_rx_offloads_nodis & ~rx_offloads) {
 548                 DPAA2_PMD_INFO(
 549                 "Some of rx offloads enabled by default - requested 0x%" PRIx64
 550                 " fixed are 0x%" PRIx64,
 551                 rx_offloads, dev_rx_offloads_nodis);
 552         }
 553
 554         /* Tx offloads which are enabled by default */
 555         if (dev_tx_offloads_nodis & ~tx_offloads) {
 556                 DPAA2_PMD_INFO(
 557                 "Some of tx offloads enabled by default - requested 0x%" PRIx64
 558                 " fixed are 0x%" PRIx64,
 559                 tx_offloads, dev_tx_offloads_nodis);
 560         }
 561
 562         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 563                 if (eth_conf->rxmode.max_rx_pkt_len <= DPAA2_MAX_RX_PKT_LEN) {
 564                         ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW,
 565                                 priv->token, eth_conf->rxmode.max_rx_pkt_len
 566                                 - RTE_ETHER_CRC_LEN);
 567                         if (ret) {
 568                                 DPAA2_PMD_ERR(
 569                                         "Unable to set mtu. check config");
 570                                 return ret;
 571                         }
 572                         dev->data->mtu =
 573                                 dev->data->dev_conf.rxmode.max_rx_pkt_len -
 574                                 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN -
 575                                 VLAN_TAG_SIZE;
 576                                 DPAA2_PMD_INFO("MTU configured for the device: %d",
 577                                                 dev->data->mtu);
 578                 } else {
 579                         return -1;
 580                 }
 581         }
 582
 583         if (eth_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) {
 584                 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
 585                         ret = dpaa2_setup_flow_dist(dev,
 586                                         eth_conf->rx_adv_conf.rss_conf.rss_hf,
 587                                         tc_index);
 588                         if (ret) {
 589                                 DPAA2_PMD_ERR(
 590                                         "Unable to set flow distribution on tc%d."
 591                                         "Check queue config", tc_index);
 592                                 return ret;
 593                         }
 594                 }
 595         }
 596
 597         if (rx_offloads & DEV_RX_OFFLOAD_IPV4_CKSUM)
 598                 rx_l3_csum_offload = true;
 599
 600         if ((rx_offloads & DEV_RX_OFFLOAD_UDP_CKSUM) ||
 601                 (rx_offloads & DEV_RX_OFFLOAD_TCP_CKSUM) ||
 602                 (rx_offloads & DEV_RX_OFFLOAD_SCTP_CKSUM))
 603                 rx_l4_csum_offload = true;
 604
 605         ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 606                                DPNI_OFF_RX_L3_CSUM, rx_l3_csum_offload);
 607         if (ret) {
 608                 DPAA2_PMD_ERR("Error to set RX l3 csum:Error = %d", ret);
 609                 return ret;
 610         }
 611
 612         ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 613                                DPNI_OFF_RX_L4_CSUM, rx_l4_csum_offload);
 614         if (ret) {
 615                 DPAA2_PMD_ERR("Error to get RX l4 csum:Error = %d", ret);
 616                 return ret;
 617         }
 618
 619 #if !defined(RTE_LIBRTE_IEEE1588)
 620         if (rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP)
 621 #endif
 622         {
 623                 ret = rte_mbuf_dyn_rx_timestamp_register(
 624                                 &dpaa2_timestamp_dynfield_offset,
 625                                 &dpaa2_timestamp_rx_dynflag);
 626                 if (ret != 0) {
 627                         DPAA2_PMD_ERR("Error to register timestamp field/flag");
 628                         return -rte_errno;
 629                 }
 630                 dpaa2_enable_ts[dev->data->port_id] = true;
 631         }
 632
 633         if (tx_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)
 634                 tx_l3_csum_offload = true;
 635
 636         if ((tx_offloads & DEV_TX_OFFLOAD_UDP_CKSUM) ||
 637                 (tx_offloads & DEV_TX_OFFLOAD_TCP_CKSUM) ||
 638                 (tx_offloads & DEV_TX_OFFLOAD_SCTP_CKSUM))
 639                 tx_l4_csum_offload = true;
 640
 641         ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 642                                DPNI_OFF_TX_L3_CSUM, tx_l3_csum_offload);
 643         if (ret) {
 644                 DPAA2_PMD_ERR("Error to set TX l3 csum:Error = %d", ret);
 645                 return ret;
 646         }
 647
 648         ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 649                                DPNI_OFF_TX_L4_CSUM, tx_l4_csum_offload);
 650         if (ret) {
 651                 DPAA2_PMD_ERR("Error to get TX l4 csum:Error = %d", ret);
 652                 return ret;
 653         }
 654
 655         /* Enabling hash results in FD requires setting DPNI_FLCTYPE_HASH in
 656          * dpni_set_offload API. Setting this FLCTYPE for DPNI sets the FD[SC]
 657          * to 0 for LS2 in the hardware thus disabling data/annotation
 658          * stashing. For LX2 this is fixed in hardware and thus hash result and
 659          * parse results can be received in FD using this option.
 660          */
 661         if (dpaa2_svr_family == SVR_LX2160A) {
 662                 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 663                                        DPNI_FLCTYPE_HASH, true);
 664                 if (ret) {
 665                         DPAA2_PMD_ERR("Error setting FLCTYPE: Err = %d", ret);
 666                         return ret;
 667                 }
 668         }
 669
 670         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 671                 dpaa2_vlan_offload_set(dev, ETH_VLAN_FILTER_MASK);
 672
 673         dpaa2_tm_init(dev);
 674
 675         return 0;
 676 }
 677
 678 /* Function to setup RX flow information. It contains traffic class ID,
 679  * flow ID, destination configuration etc.
 680  */
 681 static int
 682 dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev,
 683                          uint16_t rx_queue_id,
 684                          uint16_t nb_rx_desc,
 685                          unsigned int socket_id __rte_unused,
 686                          const struct rte_eth_rxconf *rx_conf,
 687                          struct rte_mempool *mb_pool)
 688 {
 689         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 690         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
 691         struct dpaa2_queue *dpaa2_q;
 692         struct dpni_queue cfg;
 693         uint8_t options = 0;
 694         uint8_t flow_id;
 695         uint32_t bpid;
 696         int i, ret;
 697
 698         PMD_INIT_FUNC_TRACE();
 699
 700         DPAA2_PMD_DEBUG("dev =%p, queue =%d, pool = %p, conf =%p",
 701                         dev, rx_queue_id, mb_pool, rx_conf);
 702
 703         /* Rx deferred start is not supported */
 704         if (rx_conf->rx_deferred_start) {
 705                 DPAA2_PMD_ERR("%p:Rx deferred start not supported",
 706                                 (void *)dev);
 707                 return -EINVAL;
 708         }
 709
 710         if (!priv->bp_list || priv->bp_list->mp != mb_pool) {
 711                 bpid = mempool_to_bpid(mb_pool);
 712                 ret = dpaa2_attach_bp_list(priv,
 713                                            rte_dpaa2_bpid_info[bpid].bp_list);
 714                 if (ret)
 715                         return ret;
 716         }
 717         dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];
 718         dpaa2_q->mb_pool = mb_pool; /**< mbuf pool to populate RX ring. */
 719         dpaa2_q->bp_array = rte_dpaa2_bpid_info;
 720         dpaa2_q->nb_desc = UINT16_MAX;
 721         dpaa2_q->offloads = rx_conf->offloads;
 722
 723         /*Get the flow id from given VQ id*/
 724         flow_id = dpaa2_q->flow_id;
 725         memset(&cfg, 0, sizeof(struct dpni_queue));
 726
 727         options = options | DPNI_QUEUE_OPT_USER_CTX;
 728         cfg.user_context = (size_t)(dpaa2_q);
 729
 730         /* check if a private cgr available. */
 731         for (i = 0; i < priv->max_cgs; i++) {
 732                 if (!priv->cgid_in_use[i]) {
 733                         priv->cgid_in_use[i] = 1;
 734                         break;
 735                 }
 736         }
 737
 738         if (i < priv->max_cgs) {
 739                 options |= DPNI_QUEUE_OPT_SET_CGID;
 740                 cfg.cgid = i;
 741                 dpaa2_q->cgid = cfg.cgid;
 742         } else {
 743                 dpaa2_q->cgid = 0xff;
 744         }
 745
 746         /*if ls2088 or rev2 device, enable the stashing */
 747
 748         if ((dpaa2_svr_family & 0xffff0000) != SVR_LS2080A) {
 749                 options |= DPNI_QUEUE_OPT_FLC;
 750                 cfg.flc.stash_control = true;
 751                 cfg.flc.value &= 0xFFFFFFFFFFFFFFC0;
 752                 /* 00 00 00 - last 6 bit represent annotation, context stashing,
 753                  * data stashing setting 01 01 00 (0x14)
 754                  * (in following order ->DS AS CS)
 755                  * to enable 1 line data, 1 line annotation.
 756                  * For LX2, this setting should be 01 00 00 (0x10)
 757                  */
 758                 if ((dpaa2_svr_family & 0xffff0000) == SVR_LX2160A)
 759                         cfg.flc.value |= 0x10;
 760                 else
 761                         cfg.flc.value |= 0x14;
 762         }
 763         ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_RX,
 764                              dpaa2_q->tc_index, flow_id, options, &cfg);
 765         if (ret) {
 766                 DPAA2_PMD_ERR("Error in setting the rx flow: = %d", ret);
 767                 return -1;
 768         }
 769
 770         if (!(priv->flags & DPAA2_RX_TAILDROP_OFF)) {
 771                 struct dpni_taildrop taildrop;
 772
 773                 taildrop.enable = 1;
 774                 dpaa2_q->nb_desc = nb_rx_desc;
 775                 /* Private CGR will use tail drop length as nb_rx_desc.
 776                  * for rest cases we can use standard byte based tail drop.
 777                  * There is no HW restriction, but number of CGRs are limited,
 778                  * hence this restriction is placed.
 779                  */
 780                 if (dpaa2_q->cgid != 0xff) {
 781                         /*enabling per rx queue congestion control */
 782                         taildrop.threshold = nb_rx_desc;
 783                         taildrop.units = DPNI_CONGESTION_UNIT_FRAMES;
 784                         taildrop.oal = 0;
 785                         DPAA2_PMD_DEBUG("Enabling CG Tail Drop on queue = %d",
 786                                         rx_queue_id);
 787                         ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
 788                                                 DPNI_CP_CONGESTION_GROUP,
 789                                                 DPNI_QUEUE_RX,
 790                                                 dpaa2_q->tc_index,
 791                                                 dpaa2_q->cgid, &taildrop);
 792                 } else {
 793                         /*enabling per rx queue congestion control */
 794                         taildrop.threshold = CONG_THRESHOLD_RX_BYTES_Q;
 795                         taildrop.units = DPNI_CONGESTION_UNIT_BYTES;
 796                         taildrop.oal = CONG_RX_OAL;
 797                         DPAA2_PMD_DEBUG("Enabling Byte based Drop on queue= %d",
 798                                         rx_queue_id);
 799                         ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
 800                                                 DPNI_CP_QUEUE, DPNI_QUEUE_RX,
 801                                                 dpaa2_q->tc_index, flow_id,
 802                                                 &taildrop);
 803                 }
 804                 if (ret) {
 805                         DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
 806                                       ret);
 807                         return -1;
 808                 }
 809         } else { /* Disable tail Drop */
 810                 struct dpni_taildrop taildrop = {0};
 811                 DPAA2_PMD_INFO("Tail drop is disabled on queue");
 812
 813                 taildrop.enable = 0;
 814                 if (dpaa2_q->cgid != 0xff) {
 815                         ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
 816                                         DPNI_CP_CONGESTION_GROUP, DPNI_QUEUE_RX,
 817                                         dpaa2_q->tc_index,
 818                                         dpaa2_q->cgid, &taildrop);
 819                 } else {
 820                         ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
 821                                         DPNI_CP_QUEUE, DPNI_QUEUE_RX,
 822                                         dpaa2_q->tc_index, flow_id, &taildrop);
 823                 }
 824                 if (ret) {
 825                         DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
 826                                       ret);
 827                         return -1;
 828                 }
 829         }
 830
 831         dev->data->rx_queues[rx_queue_id] = dpaa2_q;
 832         return 0;
 833 }
 834
 835 static int
 836 dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev,
 837                          uint16_t tx_queue_id,
 838                          uint16_t nb_tx_desc,
 839                          unsigned int socket_id __rte_unused,
 840                          const struct rte_eth_txconf *tx_conf)
 841 {
 842         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 843         struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)
 844                 priv->tx_vq[tx_queue_id];
 845         struct dpaa2_queue *dpaa2_tx_conf_q = (struct dpaa2_queue *)
 846                 priv->tx_conf_vq[tx_queue_id];
 847         struct fsl_mc_io *dpni = dev->process_private;
 848         struct dpni_queue tx_conf_cfg;
 849         struct dpni_queue tx_flow_cfg;
 850         uint8_t options = 0, flow_id;
 851         struct dpni_queue_id qid;
 852         uint32_t tc_id;
 853         int ret;
 854
 855         PMD_INIT_FUNC_TRACE();
 856
 857         /* Tx deferred start is not supported */
 858         if (tx_conf->tx_deferred_start) {
 859                 DPAA2_PMD_ERR("%p:Tx deferred start not supported",
 860                                 (void *)dev);
 861                 return -EINVAL;
 862         }
 863
 864         dpaa2_q->nb_desc = UINT16_MAX;
 865         dpaa2_q->offloads = tx_conf->offloads;
 866
 867         /* Return if queue already configured */
 868         if (dpaa2_q->flow_id != 0xffff) {
 869                 dev->data->tx_queues[tx_queue_id] = dpaa2_q;
 870                 return 0;
 871         }
 872
 873         memset(&tx_conf_cfg, 0, sizeof(struct dpni_queue));
 874         memset(&tx_flow_cfg, 0, sizeof(struct dpni_queue));
 875
 876         tc_id = tx_queue_id;
 877         flow_id = 0;
 878
 879         ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_TX,
 880                         tc_id, flow_id, options, &tx_flow_cfg);
 881         if (ret) {
 882                 DPAA2_PMD_ERR("Error in setting the tx flow: "
 883                         "tc_id=%d, flow=%d err=%d",
 884                         tc_id, flow_id, ret);
 885                         return -1;
 886         }
 887
 888         dpaa2_q->flow_id = flow_id;
 889
 890         if (tx_queue_id == 0) {
 891                 /*Set tx-conf and error configuration*/
 892                 if (priv->flags & DPAA2_TX_CONF_ENABLE)
 893                         ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
 894                                                             priv->token,
 895                                                             DPNI_CONF_AFFINE);
 896                 else
 897                         ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
 898                                                             priv->token,
 899                                                             DPNI_CONF_DISABLE);
 900                 if (ret) {
 901                         DPAA2_PMD_ERR("Error in set tx conf mode settings: "
 902                                       "err=%d", ret);
 903                         return -1;
 904                 }
 905         }
 906         dpaa2_q->tc_index = tc_id;
 907
 908         ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
 909                              DPNI_QUEUE_TX, dpaa2_q->tc_index,
 910                              dpaa2_q->flow_id, &tx_flow_cfg, &qid);
 911         if (ret) {
 912                 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
 913                 return -1;
 914         }
 915         dpaa2_q->fqid = qid.fqid;
 916
 917         if (!(priv->flags & DPAA2_TX_CGR_OFF)) {
 918                 struct dpni_congestion_notification_cfg cong_notif_cfg = {0};
 919
 920                 dpaa2_q->nb_desc = nb_tx_desc;
 921
 922                 cong_notif_cfg.units = DPNI_CONGESTION_UNIT_FRAMES;
 923                 cong_notif_cfg.threshold_entry = nb_tx_desc;
 924                 /* Notify that the queue is not congested when the data in
 925                  * the queue is below this thershold.(90% of value)
 926                  */
 927                 cong_notif_cfg.threshold_exit = (nb_tx_desc * 9) / 10;
 928                 cong_notif_cfg.message_ctx = 0;
 929                 cong_notif_cfg.message_iova =
 930                                 (size_t)DPAA2_VADDR_TO_IOVA(dpaa2_q->cscn);
 931                 cong_notif_cfg.dest_cfg.dest_type = DPNI_DEST_NONE;
 932                 cong_notif_cfg.notification_mode =
 933                                          DPNI_CONG_OPT_WRITE_MEM_ON_ENTER |
 934                                          DPNI_CONG_OPT_WRITE_MEM_ON_EXIT |
 935                                          DPNI_CONG_OPT_COHERENT_WRITE;
 936                 cong_notif_cfg.cg_point = DPNI_CP_QUEUE;
 937
 938                 ret = dpni_set_congestion_notification(dpni, CMD_PRI_LOW,
 939                                                        priv->token,
 940                                                        DPNI_QUEUE_TX,
 941                                                        tc_id,
 942                                                        &cong_notif_cfg);
 943                 if (ret) {
 944                         DPAA2_PMD_ERR(
 945                            "Error in setting tx congestion notification: "
 946                            "err=%d", ret);
 947                         return -ret;
 948                 }
 949         }
 950         dpaa2_q->cb_eqresp_free = dpaa2_dev_free_eqresp_buf;
 951         dev->data->tx_queues[tx_queue_id] = dpaa2_q;
 952
 953         if (priv->flags & DPAA2_TX_CONF_ENABLE) {
 954                 dpaa2_q->tx_conf_queue = dpaa2_tx_conf_q;
 955                 options = options | DPNI_QUEUE_OPT_USER_CTX;
 956                 tx_conf_cfg.user_context = (size_t)(dpaa2_q);
 957                 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
 958                              DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
 959                              dpaa2_tx_conf_q->flow_id, options, &tx_conf_cfg);
 960                 if (ret) {
 961                         DPAA2_PMD_ERR("Error in setting the tx conf flow: "
 962                               "tc_index=%d, flow=%d err=%d",
 963                               dpaa2_tx_conf_q->tc_index,
 964                               dpaa2_tx_conf_q->flow_id, ret);
 965                         return -1;
 966                 }
 967
 968                 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
 969                              DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
 970                              dpaa2_tx_conf_q->flow_id, &tx_conf_cfg, &qid);
 971                 if (ret) {
 972                         DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
 973                         return -1;
 974                 }
 975                 dpaa2_tx_conf_q->fqid = qid.fqid;
 976         }
 977         return 0;
 978 }
 979
 980 static void
 981 dpaa2_dev_rx_queue_release(void *q __rte_unused)
 982 {
 983         struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)q;
 984         struct dpaa2_dev_priv *priv = dpaa2_q->eth_data->dev_private;
 985         struct fsl_mc_io *dpni =
 986                 (struct fsl_mc_io *)priv->eth_dev->process_private;
 987         uint8_t options = 0;
 988         int ret;
 989         struct dpni_queue cfg;
 990
 991         memset(&cfg, 0, sizeof(struct dpni_queue));
 992         PMD_INIT_FUNC_TRACE();
 993         if (dpaa2_q->cgid != 0xff) {
 994                 options = DPNI_QUEUE_OPT_CLEAR_CGID;
 995                 cfg.cgid = dpaa2_q->cgid;
 996
 997                 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
 998                                      DPNI_QUEUE_RX,
 999                                      dpaa2_q->tc_index, dpaa2_q->flow_id,
1000                                      options, &cfg);
1001                 if (ret)
1002                         DPAA2_PMD_ERR("Unable to clear CGR from q=%u err=%d",
1003                                         dpaa2_q->fqid, ret);
1004                 priv->cgid_in_use[dpaa2_q->cgid] = 0;
1005                 dpaa2_q->cgid = 0xff;
1006         }
1007 }
1008
1009 static uint32_t
1010 dpaa2_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1011 {
1012         int32_t ret;
1013         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1014         struct dpaa2_queue *dpaa2_q;
1015         struct qbman_swp *swp;
1016         struct qbman_fq_query_np_rslt state;
1017         uint32_t frame_cnt = 0;
1018
1019         if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
1020                 ret = dpaa2_affine_qbman_swp();
1021                 if (ret) {
1022                         DPAA2_PMD_ERR(
1023                                 "Failed to allocate IO portal, tid: %d\n",
1024                                 rte_gettid());
1025                         return -EINVAL;
1026                 }
1027         }
1028         swp = DPAA2_PER_LCORE_PORTAL;
1029
1030         dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];
1031
1032         if (qbman_fq_query_state(swp, dpaa2_q->fqid, &state) == 0) {
1033                 frame_cnt = qbman_fq_state_frame_count(&state);
1034                 DPAA2_PMD_DP_DEBUG("RX frame count for q(%d) is %u",
1035                                 rx_queue_id, frame_cnt);
1036         }
1037         return frame_cnt;
1038 }
1039
1040 static const uint32_t *
1041 dpaa2_supported_ptypes_get(struct rte_eth_dev *dev)
1042 {
1043         static const uint32_t ptypes[] = {
1044                 /*todo -= add more types */
1045                 RTE_PTYPE_L2_ETHER,
1046                 RTE_PTYPE_L3_IPV4,
1047                 RTE_PTYPE_L3_IPV4_EXT,
1048                 RTE_PTYPE_L3_IPV6,
1049                 RTE_PTYPE_L3_IPV6_EXT,
1050                 RTE_PTYPE_L4_TCP,
1051                 RTE_PTYPE_L4_UDP,
1052                 RTE_PTYPE_L4_SCTP,
1053                 RTE_PTYPE_L4_ICMP,
1054                 RTE_PTYPE_UNKNOWN
1055         };
1056
1057         if (dev->rx_pkt_burst == dpaa2_dev_prefetch_rx ||
1058                 dev->rx_pkt_burst == dpaa2_dev_rx ||
1059                 dev->rx_pkt_burst == dpaa2_dev_loopback_rx)
1060                 return ptypes;
1061         return NULL;
1062 }
1063
1064 /**
1065  * Dpaa2 link Interrupt handler
1066  *
1067  * @param param
1068  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1069  *
1070  * @return
1071  *  void
1072  */
1073 static void
1074 dpaa2_interrupt_handler(void *param)
1075 {
1076         struct rte_eth_dev *dev = param;
1077         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1078         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1079         int ret;
1080         int irq_index = DPNI_IRQ_INDEX;
1081         unsigned int status = 0, clear = 0;
1082
1083         PMD_INIT_FUNC_TRACE();
1084
1085         if (dpni == NULL) {
1086                 DPAA2_PMD_ERR("dpni is NULL");
1087                 return;
1088         }
1089
1090         ret = dpni_get_irq_status(dpni, CMD_PRI_LOW, priv->token,
1091                                   irq_index, &status);
1092         if (unlikely(ret)) {
1093                 DPAA2_PMD_ERR("Can't get irq status (err %d)", ret);
1094                 clear = 0xffffffff;
1095                 goto out;
1096         }
1097
1098         if (status & DPNI_IRQ_EVENT_LINK_CHANGED) {
1099                 clear = DPNI_IRQ_EVENT_LINK_CHANGED;
1100                 dpaa2_dev_link_update(dev, 0);
1101                 /* calling all the apps registered for link status event */
1102                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1103         }
1104 out:
1105         ret = dpni_clear_irq_status(dpni, CMD_PRI_LOW, priv->token,
1106                                     irq_index, clear);
1107         if (unlikely(ret))
1108                 DPAA2_PMD_ERR("Can't clear irq status (err %d)", ret);
1109 }
1110
1111 static int
1112 dpaa2_eth_setup_irqs(struct rte_eth_dev *dev, int enable)
1113 {
1114         int err = 0;
1115         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1116         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1117         int irq_index = DPNI_IRQ_INDEX;
1118         unsigned int mask = DPNI_IRQ_EVENT_LINK_CHANGED;
1119
1120         PMD_INIT_FUNC_TRACE();
1121
1122         err = dpni_set_irq_mask(dpni, CMD_PRI_LOW, priv->token,
1123                                 irq_index, mask);
1124         if (err < 0) {
1125                 DPAA2_PMD_ERR("Error: dpni_set_irq_mask():%d (%s)", err,
1126                               strerror(-err));
1127                 return err;
1128         }
1129
1130         err = dpni_set_irq_enable(dpni, CMD_PRI_LOW, priv->token,
1131                                   irq_index, enable);
1132         if (err < 0)
1133                 DPAA2_PMD_ERR("Error: dpni_set_irq_enable():%d (%s)", err,
1134                               strerror(-err));
1135
1136         return err;
1137 }
1138
1139 static int
1140 dpaa2_dev_start(struct rte_eth_dev *dev)
1141 {
1142         struct rte_device *rdev = dev->device;
1143         struct rte_dpaa2_device *dpaa2_dev;
1144         struct rte_eth_dev_data *data = dev->data;
1145         struct dpaa2_dev_priv *priv = data->dev_private;
1146         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1147         struct dpni_queue cfg;
1148         struct dpni_error_cfg   err_cfg;
1149         uint16_t qdid;
1150         struct dpni_queue_id qid;
1151         struct dpaa2_queue *dpaa2_q;
1152         int ret, i;
1153         struct rte_intr_handle *intr_handle;
1154
1155         dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device);
1156         intr_handle = &dpaa2_dev->intr_handle;
1157
1158         PMD_INIT_FUNC_TRACE();
1159
1160         ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1161         if (ret) {
1162                 DPAA2_PMD_ERR("Failure in enabling dpni %d device: err=%d",
1163                               priv->hw_id, ret);
1164                 return ret;
1165         }
1166
1167         /* Power up the phy. Needed to make the link go UP */
1168         dpaa2_dev_set_link_up(dev);
1169
1170         ret = dpni_get_qdid(dpni, CMD_PRI_LOW, priv->token,
1171                             DPNI_QUEUE_TX, &qdid);
1172         if (ret) {
1173                 DPAA2_PMD_ERR("Error in getting qdid: err=%d", ret);
1174                 return ret;
1175         }
1176         priv->qdid = qdid;
1177
1178         for (i = 0; i < data->nb_rx_queues; i++) {
1179                 dpaa2_q = (struct dpaa2_queue *)data->rx_queues[i];
1180                 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
1181                                      DPNI_QUEUE_RX, dpaa2_q->tc_index,
1182                                        dpaa2_q->flow_id, &cfg, &qid);
1183                 if (ret) {
1184                         DPAA2_PMD_ERR("Error in getting flow information: "
1185                                       "err=%d", ret);
1186                         return ret;
1187                 }
1188                 dpaa2_q->fqid = qid.fqid;
1189         }
1190
1191         if (dpaa2_enable_err_queue) {
1192                 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
1193                                      DPNI_QUEUE_RX_ERR, 0, 0, &cfg, &qid);
1194                 if (ret) {
1195                         DPAA2_PMD_ERR("Error getting rx err flow information: err=%d",
1196                                                 ret);
1197                         return ret;
1198                 }
1199                 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq;
1200                 dpaa2_q->fqid = qid.fqid;
1201                 dpaa2_q->eth_data = dev->data;
1202
1203                 err_cfg.errors =  DPNI_ERROR_DISC;
1204                 err_cfg.error_action = DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE;
1205         } else {
1206                 /* checksum errors, send them to normal path
1207                  * and set it in annotation
1208                  */
1209                 err_cfg.errors = DPNI_ERROR_L3CE | DPNI_ERROR_L4CE;
1210
1211                 /* if packet with parse error are not to be dropped */
1212                 err_cfg.errors |= DPNI_ERROR_PHE;
1213
1214                 err_cfg.error_action = DPNI_ERROR_ACTION_CONTINUE;
1215         }
1216         err_cfg.set_frame_annotation = true;
1217
1218         ret = dpni_set_errors_behavior(dpni, CMD_PRI_LOW,
1219                                        priv->token, &err_cfg);
1220         if (ret) {
1221                 DPAA2_PMD_ERR("Error to dpni_set_errors_behavior: code = %d",
1222                               ret);
1223                 return ret;
1224         }
1225
1226         /* if the interrupts were configured on this devices*/
1227         if (intr_handle && (intr_handle->fd) &&
1228             (dev->data->dev_conf.intr_conf.lsc != 0)) {
1229                 /* Registering LSC interrupt handler */
1230                 rte_intr_callback_register(intr_handle,
1231                                            dpaa2_interrupt_handler,
1232                                            (void *)dev);
1233
1234                 /* enable vfio intr/eventfd mapping
1235                  * Interrupt index 0 is required, so we can not use
1236                  * rte_intr_enable.
1237                  */
1238                 rte_dpaa2_intr_enable(intr_handle, DPNI_IRQ_INDEX);
1239
1240                 /* enable dpni_irqs */
1241                 dpaa2_eth_setup_irqs(dev, 1);
1242         }
1243
1244         /* Change the tx burst function if ordered queues are used */
1245         if (priv->en_ordered)
1246                 dev->tx_pkt_burst = dpaa2_dev_tx_ordered;
1247
1248         return 0;
1249 }
1250
1251 /**
1252  *  This routine disables all traffic on the adapter by issuing a
1253  *  global reset on the MAC.
1254  */
1255 static int
1256 dpaa2_dev_stop(struct rte_eth_dev *dev)
1257 {
1258         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1259         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1260         int ret;
1261         struct rte_eth_link link;
1262         struct rte_intr_handle *intr_handle = dev->intr_handle;
1263
1264         PMD_INIT_FUNC_TRACE();
1265
1266         /* reset interrupt callback  */
1267         if (intr_handle && (intr_handle->fd) &&
1268             (dev->data->dev_conf.intr_conf.lsc != 0)) {
1269                 /*disable dpni irqs */
1270                 dpaa2_eth_setup_irqs(dev, 0);
1271
1272                 /* disable vfio intr before callback unregister */
1273                 rte_dpaa2_intr_disable(intr_handle, DPNI_IRQ_INDEX);
1274
1275                 /* Unregistering LSC interrupt handler */
1276                 rte_intr_callback_unregister(intr_handle,
1277                                              dpaa2_interrupt_handler,
1278                                              (void *)dev);
1279         }
1280
1281         dpaa2_dev_set_link_down(dev);
1282
1283         ret = dpni_disable(dpni, CMD_PRI_LOW, priv->token);
1284         if (ret) {
1285                 DPAA2_PMD_ERR("Failure (ret %d) in disabling dpni %d dev",
1286                               ret, priv->hw_id);
1287                 return ret;
1288         }
1289
1290         /* clear the recorded link status */
1291         memset(&link, 0, sizeof(link));
1292         rte_eth_linkstatus_set(dev, &link);
1293
1294         return 0;
1295 }
1296
1297 static int
1298 dpaa2_dev_close(struct rte_eth_dev *dev)
1299 {
1300         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1301         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1302         int i, ret;
1303         struct rte_eth_link link;
1304
1305         PMD_INIT_FUNC_TRACE();
1306
1307         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1308                 return 0;
1309
1310         if (!dpni) {
1311                 DPAA2_PMD_WARN("Already closed or not started");
1312                 return -1;
1313         }
1314
1315         dpaa2_tm_deinit(dev);
1316         dpaa2_flow_clean(dev);
1317         /* Clean the device first */
1318         ret = dpni_reset(dpni, CMD_PRI_LOW, priv->token);
1319         if (ret) {
1320                 DPAA2_PMD_ERR("Failure cleaning dpni device: err=%d", ret);
1321                 return -1;
1322         }
1323
1324         memset(&link, 0, sizeof(link));
1325         rte_eth_linkstatus_set(dev, &link);
1326
1327         /* Free private queues memory */
1328         dpaa2_free_rx_tx_queues(dev);
1329         /* Close the device at underlying layer*/
1330         ret = dpni_close(dpni, CMD_PRI_LOW, priv->token);
1331         if (ret) {
1332                 DPAA2_PMD_ERR("Failure closing dpni device with err code %d",
1333                               ret);
1334         }
1335
1336         /* Free the allocated memory for ethernet private data and dpni*/
1337         priv->hw = NULL;
1338         dev->process_private = NULL;
1339         rte_free(dpni);
1340
1341         for (i = 0; i < MAX_TCS; i++)
1342                 rte_free((void *)(size_t)priv->extract.tc_extract_param[i]);
1343
1344         if (priv->extract.qos_extract_param)
1345                 rte_free((void *)(size_t)priv->extract.qos_extract_param);
1346
1347         DPAA2_PMD_INFO("%s: netdev deleted", dev->data->name);
1348         return 0;
1349 }
1350
1351 static int
1352 dpaa2_dev_promiscuous_enable(
1353                 struct rte_eth_dev *dev)
1354 {
1355         int ret;
1356         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1357         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1358
1359         PMD_INIT_FUNC_TRACE();
1360
1361         if (dpni == NULL) {
1362                 DPAA2_PMD_ERR("dpni is NULL");
1363                 return -ENODEV;
1364         }
1365
1366         ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1367         if (ret < 0)
1368                 DPAA2_PMD_ERR("Unable to enable U promisc mode %d", ret);
1369
1370         ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1371         if (ret < 0)
1372                 DPAA2_PMD_ERR("Unable to enable M promisc mode %d", ret);
1373
1374         return ret;
1375 }
1376
1377 static int
1378 dpaa2_dev_promiscuous_disable(
1379                 struct rte_eth_dev *dev)
1380 {
1381         int ret;
1382         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1383         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1384
1385         PMD_INIT_FUNC_TRACE();
1386
1387         if (dpni == NULL) {
1388                 DPAA2_PMD_ERR("dpni is NULL");
1389                 return -ENODEV;
1390         }
1391
1392         ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1393         if (ret < 0)
1394                 DPAA2_PMD_ERR("Unable to disable U promisc mode %d", ret);
1395
1396         if (dev->data->all_multicast == 0) {
1397                 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW,
1398                                                  priv->token, false);
1399                 if (ret < 0)
1400                         DPAA2_PMD_ERR("Unable to disable M promisc mode %d",
1401                                       ret);
1402         }
1403
1404         return ret;
1405 }
1406
1407 static int
1408 dpaa2_dev_allmulticast_enable(
1409                 struct rte_eth_dev *dev)
1410 {
1411         int ret;
1412         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1413         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1414
1415         PMD_INIT_FUNC_TRACE();
1416
1417         if (dpni == NULL) {
1418                 DPAA2_PMD_ERR("dpni is NULL");
1419                 return -ENODEV;
1420         }
1421
1422         ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1423         if (ret < 0)
1424                 DPAA2_PMD_ERR("Unable to enable multicast mode %d", ret);
1425
1426         return ret;
1427 }
1428
1429 static int
1430 dpaa2_dev_allmulticast_disable(struct rte_eth_dev *dev)
1431 {
1432         int ret;
1433         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1434         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1435
1436         PMD_INIT_FUNC_TRACE();
1437
1438         if (dpni == NULL) {
1439                 DPAA2_PMD_ERR("dpni is NULL");
1440                 return -ENODEV;
1441         }
1442
1443         /* must remain on for all promiscuous */
1444         if (dev->data->promiscuous == 1)
1445                 return 0;
1446
1447         ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1448         if (ret < 0)
1449                 DPAA2_PMD_ERR("Unable to disable multicast mode %d", ret);
1450
1451         return ret;
1452 }
1453
1454 static int
1455 dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1456 {
1457         int ret;
1458         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1459         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1460         uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
1461                                 + VLAN_TAG_SIZE;
1462
1463         PMD_INIT_FUNC_TRACE();
1464
1465         if (dpni == NULL) {
1466                 DPAA2_PMD_ERR("dpni is NULL");
1467                 return -EINVAL;
1468         }
1469
1470         /* check that mtu is within the allowed range */
1471         if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA2_MAX_RX_PKT_LEN)
1472                 return -EINVAL;
1473
1474         if (frame_size > DPAA2_ETH_MAX_LEN)
1475                 dev->data->dev_conf.rxmode.offloads |=
1476                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
1477         else
1478                 dev->data->dev_conf.rxmode.offloads &=
1479                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1480
1481         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1482
1483         /* Set the Max Rx frame length as 'mtu' +
1484          * Maximum Ethernet header length
1485          */
1486         ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, priv->token,
1487                                         frame_size - RTE_ETHER_CRC_LEN);
1488         if (ret) {
1489                 DPAA2_PMD_ERR("Setting the max frame length failed");
1490                 return -1;
1491         }
1492         DPAA2_PMD_INFO("MTU configured for the device: %d", mtu);
1493         return 0;
1494 }
1495
1496 static int
1497 dpaa2_dev_add_mac_addr(struct rte_eth_dev *dev,
1498                        struct rte_ether_addr *addr,
1499                        __rte_unused uint32_t index,
1500                        __rte_unused uint32_t pool)
1501 {
1502         int ret;
1503         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1504         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1505
1506         PMD_INIT_FUNC_TRACE();
1507
1508         if (dpni == NULL) {
1509                 DPAA2_PMD_ERR("dpni is NULL");
1510                 return -1;
1511         }
1512
1513         ret = dpni_add_mac_addr(dpni, CMD_PRI_LOW, priv->token,
1514                                 addr->addr_bytes, 0, 0, 0);
1515         if (ret)
1516                 DPAA2_PMD_ERR(
1517                         "error: Adding the MAC ADDR failed: err = %d", ret);
1518         return 0;
1519 }
1520
1521 static void
1522 dpaa2_dev_remove_mac_addr(struct rte_eth_dev *dev,
1523                           uint32_t index)
1524 {
1525         int ret;
1526         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1527         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1528         struct rte_eth_dev_data *data = dev->data;
1529         struct rte_ether_addr *macaddr;
1530
1531         PMD_INIT_FUNC_TRACE();
1532
1533         macaddr = &data->mac_addrs[index];
1534
1535         if (dpni == NULL) {
1536                 DPAA2_PMD_ERR("dpni is NULL");
1537                 return;
1538         }
1539
1540         ret = dpni_remove_mac_addr(dpni, CMD_PRI_LOW,
1541                                    priv->token, macaddr->addr_bytes);
1542         if (ret)
1543                 DPAA2_PMD_ERR(
1544                         "error: Removing the MAC ADDR failed: err = %d", ret);
1545 }
1546
1547 static int
1548 dpaa2_dev_set_mac_addr(struct rte_eth_dev *dev,
1549                        struct rte_ether_addr *addr)
1550 {
1551         int ret;
1552         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1553         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1554
1555         PMD_INIT_FUNC_TRACE();
1556
1557         if (dpni == NULL) {
1558                 DPAA2_PMD_ERR("dpni is NULL");
1559                 return -EINVAL;
1560         }
1561
1562         ret = dpni_set_primary_mac_addr(dpni, CMD_PRI_LOW,
1563                                         priv->token, addr->addr_bytes);
1564
1565         if (ret)
1566                 DPAA2_PMD_ERR(
1567                         "error: Setting the MAC ADDR failed %d", ret);
1568
1569         return ret;
1570 }
1571
1572 static
1573 int dpaa2_dev_stats_get(struct rte_eth_dev *dev,
1574                          struct rte_eth_stats *stats)
1575 {
1576         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1577         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1578         int32_t  retcode;
1579         uint8_t page0 = 0, page1 = 1, page2 = 2;
1580         union dpni_statistics value;
1581         int i;
1582         struct dpaa2_queue *dpaa2_rxq, *dpaa2_txq;
1583
1584         memset(&value, 0, sizeof(union dpni_statistics));
1585
1586         PMD_INIT_FUNC_TRACE();
1587
1588         if (!dpni) {
1589                 DPAA2_PMD_ERR("dpni is NULL");
1590                 return -EINVAL;
1591         }
1592
1593         if (!stats) {
1594                 DPAA2_PMD_ERR("stats is NULL");
1595                 return -EINVAL;
1596         }
1597
1598         /*Get Counters from page_0*/
1599         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1600                                       page0, 0, &value);
1601         if (retcode)
1602                 goto err;
1603
1604         stats->ipackets = value.page_0.ingress_all_frames;
1605         stats->ibytes = value.page_0.ingress_all_bytes;
1606
1607         /*Get Counters from page_1*/
1608         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1609                                       page1, 0, &value);
1610         if (retcode)
1611                 goto err;
1612
1613         stats->opackets = value.page_1.egress_all_frames;
1614         stats->obytes = value.page_1.egress_all_bytes;
1615
1616         /*Get Counters from page_2*/
1617         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1618                                       page2, 0, &value);
1619         if (retcode)
1620                 goto err;
1621
1622         /* Ingress drop frame count due to configured rules */
1623         stats->ierrors = value.page_2.ingress_filtered_frames;
1624         /* Ingress drop frame count due to error */
1625         stats->ierrors += value.page_2.ingress_discarded_frames;
1626
1627         stats->oerrors = value.page_2.egress_discarded_frames;
1628         stats->imissed = value.page_2.ingress_nobuffer_discards;
1629
1630         /* Fill in per queue stats */
1631         for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) &&
1632                 (i < priv->nb_rx_queues || i < priv->nb_tx_queues); ++i) {
1633                 dpaa2_rxq = (struct dpaa2_queue *)priv->rx_vq[i];
1634                 dpaa2_txq = (struct dpaa2_queue *)priv->tx_vq[i];
1635                 if (dpaa2_rxq)
1636                         stats->q_ipackets[i] = dpaa2_rxq->rx_pkts;
1637                 if (dpaa2_txq)
1638                         stats->q_opackets[i] = dpaa2_txq->tx_pkts;
1639
1640                 /* Byte counting is not implemented */
1641                 stats->q_ibytes[i]   = 0;
1642                 stats->q_obytes[i]   = 0;
1643         }
1644
1645         return 0;
1646
1647 err:
1648         DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1649         return retcode;
1650 };
1651
1652 static int
1653 dpaa2_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1654                      unsigned int n)
1655 {
1656         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1657         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1658         int32_t  retcode;
1659         union dpni_statistics value[5] = {};
1660         unsigned int i = 0, num = RTE_DIM(dpaa2_xstats_strings);
1661
1662         if (n < num)
1663                 return num;
1664
1665         if (xstats == NULL)
1666                 return 0;
1667
1668         /* Get Counters from page_0*/
1669         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1670                                       0, 0, &value[0]);
1671         if (retcode)
1672                 goto err;
1673
1674         /* Get Counters from page_1*/
1675         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1676                                       1, 0, &value[1]);
1677         if (retcode)
1678                 goto err;
1679
1680         /* Get Counters from page_2*/
1681         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1682                                       2, 0, &value[2]);
1683         if (retcode)
1684                 goto err;
1685
1686         for (i = 0; i < priv->max_cgs; i++) {
1687                 if (!priv->cgid_in_use[i]) {
1688                         /* Get Counters from page_4*/
1689                         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW,
1690                                                       priv->token,
1691                                                       4, 0, &value[4]);
1692                         if (retcode)
1693                                 goto err;
1694                         break;
1695                 }
1696         }
1697
1698         for (i = 0; i < num; i++) {
1699                 xstats[i].id = i;
1700                 xstats[i].value = value[dpaa2_xstats_strings[i].page_id].
1701                         raw.counter[dpaa2_xstats_strings[i].stats_id];
1702         }
1703         return i;
1704 err:
1705         DPAA2_PMD_ERR("Error in obtaining extended stats (%d)", retcode);
1706         return retcode;
1707 }
1708
1709 static int
1710 dpaa2_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1711                        struct rte_eth_xstat_name *xstats_names,
1712                        unsigned int limit)
1713 {
1714         unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1715
1716         if (limit < stat_cnt)
1717                 return stat_cnt;
1718
1719         if (xstats_names != NULL)
1720                 for (i = 0; i < stat_cnt; i++)
1721                         strlcpy(xstats_names[i].name,
1722                                 dpaa2_xstats_strings[i].name,
1723                                 sizeof(xstats_names[i].name));
1724
1725         return stat_cnt;
1726 }
1727
1728 static int
1729 dpaa2_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1730                        uint64_t *values, unsigned int n)
1731 {
1732         unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1733         uint64_t values_copy[stat_cnt];
1734
1735         if (!ids) {
1736                 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1737                 struct fsl_mc_io *dpni =
1738                         (struct fsl_mc_io *)dev->process_private;
1739                 int32_t  retcode;
1740                 union dpni_statistics value[5] = {};
1741
1742                 if (n < stat_cnt)
1743                         return stat_cnt;
1744
1745                 if (!values)
1746                         return 0;
1747
1748                 /* Get Counters from page_0*/
1749                 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1750                                               0, 0, &value[0]);
1751                 if (retcode)
1752                         return 0;
1753
1754                 /* Get Counters from page_1*/
1755                 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1756                                               1, 0, &value[1]);
1757                 if (retcode)
1758                         return 0;
1759
1760                 /* Get Counters from page_2*/
1761                 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1762                                               2, 0, &value[2]);
1763                 if (retcode)
1764                         return 0;
1765
1766                 /* Get Counters from page_4*/
1767                 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1768                                               4, 0, &value[4]);
1769                 if (retcode)
1770                         return 0;
1771
1772                 for (i = 0; i < stat_cnt; i++) {
1773                         values[i] = value[dpaa2_xstats_strings[i].page_id].
1774                                 raw.counter[dpaa2_xstats_strings[i].stats_id];
1775                 }
1776                 return stat_cnt;
1777         }
1778
1779         dpaa2_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
1780
1781         for (i = 0; i < n; i++) {
1782                 if (ids[i] >= stat_cnt) {
1783                         DPAA2_PMD_ERR("xstats id value isn't valid");
1784                         return -1;
1785                 }
1786                 values[i] = values_copy[ids[i]];
1787         }
1788         return n;
1789 }
1790
1791 static int
1792 dpaa2_xstats_get_names_by_id(
1793         struct rte_eth_dev *dev,
1794         const uint64_t *ids,
1795         struct rte_eth_xstat_name *xstats_names,
1796         unsigned int limit)
1797 {
1798         unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1799         struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
1800
1801         if (!ids)
1802                 return dpaa2_xstats_get_names(dev, xstats_names, limit);
1803
1804         dpaa2_xstats_get_names(dev, xstats_names_copy, limit);
1805
1806         for (i = 0; i < limit; i++) {
1807                 if (ids[i] >= stat_cnt) {
1808                         DPAA2_PMD_ERR("xstats id value isn't valid");
1809                         return -1;
1810                 }
1811                 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
1812         }
1813         return limit;
1814 }
1815
1816 static int
1817 dpaa2_dev_stats_reset(struct rte_eth_dev *dev)
1818 {
1819         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1820         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1821         int retcode;
1822         int i;
1823         struct dpaa2_queue *dpaa2_q;
1824
1825         PMD_INIT_FUNC_TRACE();
1826
1827         if (dpni == NULL) {
1828                 DPAA2_PMD_ERR("dpni is NULL");
1829                 return -EINVAL;
1830         }
1831
1832         retcode =  dpni_reset_statistics(dpni, CMD_PRI_LOW, priv->token);
1833         if (retcode)
1834                 goto error;
1835
1836         /* Reset the per queue stats in dpaa2_queue structure */
1837         for (i = 0; i < priv->nb_rx_queues; i++) {
1838                 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
1839                 if (dpaa2_q)
1840                         dpaa2_q->rx_pkts = 0;
1841         }
1842
1843         for (i = 0; i < priv->nb_tx_queues; i++) {
1844                 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
1845                 if (dpaa2_q)
1846                         dpaa2_q->tx_pkts = 0;
1847         }
1848
1849         return 0;
1850
1851 error:
1852         DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1853         return retcode;
1854 };
1855
1856 /* return 0 means link status changed, -1 means not changed */
1857 static int
1858 dpaa2_dev_link_update(struct rte_eth_dev *dev,
1859                       int wait_to_complete)
1860 {
1861         int ret;
1862         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1863         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1864         struct rte_eth_link link;
1865         struct dpni_link_state state = {0};
1866         uint8_t count;
1867
1868         if (dpni == NULL) {
1869                 DPAA2_PMD_ERR("dpni is NULL");
1870                 return 0;
1871         }
1872
1873         for (count = 0; count <= MAX_REPEAT_TIME; count++) {
1874                 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token,
1875                                           &state);
1876                 if (ret < 0) {
1877                         DPAA2_PMD_DEBUG("error: dpni_get_link_state %d", ret);
1878                         return -1;
1879                 }
1880                 if (state.up == ETH_LINK_DOWN &&
1881                     wait_to_complete)
1882                         rte_delay_ms(CHECK_INTERVAL);
1883                 else
1884                         break;
1885         }
1886
1887         memset(&link, 0, sizeof(struct rte_eth_link));
1888         link.link_status = state.up;
1889         link.link_speed = state.rate;
1890
1891         if (state.options & DPNI_LINK_OPT_HALF_DUPLEX)
1892                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1893         else
1894                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1895
1896         ret = rte_eth_linkstatus_set(dev, &link);
1897         if (ret == -1)
1898                 DPAA2_PMD_DEBUG("No change in status");
1899         else
1900                 DPAA2_PMD_INFO("Port %d Link is %s\n", dev->data->port_id,
1901                                link.link_status ? "Up" : "Down");
1902
1903         return ret;
1904 }
1905
1906 /**
1907  * Toggle the DPNI to enable, if not already enabled.
1908  * This is not strictly PHY up/down - it is more of logical toggling.
1909  */
1910 static int
1911 dpaa2_dev_set_link_up(struct rte_eth_dev *dev)
1912 {
1913         int ret = -EINVAL;
1914         struct dpaa2_dev_priv *priv;
1915         struct fsl_mc_io *dpni;
1916         int en = 0;
1917         struct dpni_link_state state = {0};
1918
1919         priv = dev->data->dev_private;
1920         dpni = (struct fsl_mc_io *)dev->process_private;
1921
1922         if (dpni == NULL) {
1923                 DPAA2_PMD_ERR("dpni is NULL");
1924                 return ret;
1925         }
1926
1927         /* Check if DPNI is currently enabled */
1928         ret = dpni_is_enabled(dpni, CMD_PRI_LOW, priv->token, &en);
1929         if (ret) {
1930                 /* Unable to obtain dpni status; Not continuing */
1931                 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1932                 return -EINVAL;
1933         }
1934
1935         /* Enable link if not already enabled */
1936         if (!en) {
1937                 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1938                 if (ret) {
1939                         DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1940                         return -EINVAL;
1941                 }
1942         }
1943         ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1944         if (ret < 0) {
1945                 DPAA2_PMD_DEBUG("Unable to get link state (%d)", ret);
1946                 return -1;
1947         }
1948
1949         /* changing tx burst function to start enqueues */
1950         dev->tx_pkt_burst = dpaa2_dev_tx;
1951         dev->data->dev_link.link_status = state.up;
1952         dev->data->dev_link.link_speed = state.rate;
1953
1954         if (state.up)
1955                 DPAA2_PMD_INFO("Port %d Link is Up", dev->data->port_id);
1956         else
1957                 DPAA2_PMD_INFO("Port %d Link is Down", dev->data->port_id);
1958         return ret;
1959 }
1960
1961 /**
1962  * Toggle the DPNI to disable, if not already disabled.
1963  * This is not strictly PHY up/down - it is more of logical toggling.
1964  */
1965 static int
1966 dpaa2_dev_set_link_down(struct rte_eth_dev *dev)
1967 {
1968         int ret = -EINVAL;
1969         struct dpaa2_dev_priv *priv;
1970         struct fsl_mc_io *dpni;
1971         int dpni_enabled = 0;
1972         int retries = 10;
1973
1974         PMD_INIT_FUNC_TRACE();
1975
1976         priv = dev->data->dev_private;
1977         dpni = (struct fsl_mc_io *)dev->process_private;
1978
1979         if (dpni == NULL) {
1980                 DPAA2_PMD_ERR("Device has not yet been configured");
1981                 return ret;
1982         }
1983
1984         /*changing  tx burst function to avoid any more enqueues */
1985         dev->tx_pkt_burst = dummy_dev_tx;
1986
1987         /* Loop while dpni_disable() attempts to drain the egress FQs
1988          * and confirm them back to us.
1989          */
1990         do {
1991                 ret = dpni_disable(dpni, 0, priv->token);
1992                 if (ret) {
1993                         DPAA2_PMD_ERR("dpni disable failed (%d)", ret);
1994                         return ret;
1995                 }
1996                 ret = dpni_is_enabled(dpni, 0, priv->token, &dpni_enabled);
1997                 if (ret) {
1998                         DPAA2_PMD_ERR("dpni enable check failed (%d)", ret);
1999                         return ret;
2000                 }
2001                 if (dpni_enabled)
2002                         /* Allow the MC some slack */
2003                         rte_delay_us(100 * 1000);
2004         } while (dpni_enabled && --retries);
2005
2006         if (!retries) {
2007                 DPAA2_PMD_WARN("Retry count exceeded disabling dpni");
2008                 /* todo- we may have to manually cleanup queues.
2009                  */
2010         } else {
2011                 DPAA2_PMD_INFO("Port %d Link DOWN successful",
2012                                dev->data->port_id);
2013         }
2014
2015         dev->data->dev_link.link_status = 0;
2016
2017         return ret;
2018 }
2019
2020 static int
2021 dpaa2_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2022 {
2023         int ret = -EINVAL;
2024         struct dpaa2_dev_priv *priv;
2025         struct fsl_mc_io *dpni;
2026         struct dpni_link_state state = {0};
2027
2028         PMD_INIT_FUNC_TRACE();
2029
2030         priv = dev->data->dev_private;
2031         dpni = (struct fsl_mc_io *)dev->process_private;
2032
2033         if (dpni == NULL || fc_conf == NULL) {
2034                 DPAA2_PMD_ERR("device not configured");
2035                 return ret;
2036         }
2037
2038         ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
2039         if (ret) {
2040                 DPAA2_PMD_ERR("error: dpni_get_link_state %d", ret);
2041                 return ret;
2042         }
2043
2044         memset(fc_conf, 0, sizeof(struct rte_eth_fc_conf));
2045         if (state.options & DPNI_LINK_OPT_PAUSE) {
2046                 /* DPNI_LINK_OPT_PAUSE set
2047                  *  if ASYM_PAUSE not set,
2048                  *      RX Side flow control (handle received Pause frame)
2049                  *      TX side flow control (send Pause frame)
2050                  *  if ASYM_PAUSE set,
2051                  *      RX Side flow control (handle received Pause frame)
2052                  *      No TX side flow control (send Pause frame disabled)
2053                  */
2054                 if (!(state.options & DPNI_LINK_OPT_ASYM_PAUSE))
2055                         fc_conf->mode = RTE_FC_FULL;
2056                 else
2057                         fc_conf->mode = RTE_FC_RX_PAUSE;
2058         } else {
2059                 /* DPNI_LINK_OPT_PAUSE not set
2060                  *  if ASYM_PAUSE set,
2061                  *      TX side flow control (send Pause frame)
2062                  *      No RX side flow control (No action on pause frame rx)
2063                  *  if ASYM_PAUSE not set,
2064                  *      Flow control disabled
2065                  */
2066                 if (state.options & DPNI_LINK_OPT_ASYM_PAUSE)
2067                         fc_conf->mode = RTE_FC_TX_PAUSE;
2068                 else
2069                         fc_conf->mode = RTE_FC_NONE;
2070         }
2071
2072         return ret;
2073 }
2074
2075 static int
2076 dpaa2_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2077 {
2078         int ret = -EINVAL;
2079         struct dpaa2_dev_priv *priv;
2080         struct fsl_mc_io *dpni;
2081         struct dpni_link_state state = {0};
2082         struct dpni_link_cfg cfg = {0};
2083
2084         PMD_INIT_FUNC_TRACE();
2085
2086         priv = dev->data->dev_private;
2087         dpni = (struct fsl_mc_io *)dev->process_private;
2088
2089         if (dpni == NULL) {
2090                 DPAA2_PMD_ERR("dpni is NULL");
2091                 return ret;
2092         }
2093
2094         /* It is necessary to obtain the current state before setting fc_conf
2095          * as MC would return error in case rate, autoneg or duplex values are
2096          * different.
2097          */
2098         ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
2099         if (ret) {
2100                 DPAA2_PMD_ERR("Unable to get link state (err=%d)", ret);
2101                 return -1;
2102         }
2103
2104         /* Disable link before setting configuration */
2105         dpaa2_dev_set_link_down(dev);
2106
2107         /* Based on fc_conf, update cfg */
2108         cfg.rate = state.rate;
2109         cfg.options = state.options;
2110
2111         /* update cfg with fc_conf */
2112         switch (fc_conf->mode) {
2113         case RTE_FC_FULL:
2114                 /* Full flow control;
2115                  * OPT_PAUSE set, ASYM_PAUSE not set
2116                  */
2117                 cfg.options |= DPNI_LINK_OPT_PAUSE;
2118                 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
2119                 break;
2120         case RTE_FC_TX_PAUSE:
2121                 /* Enable RX flow control
2122                  * OPT_PAUSE not set;
2123                  * ASYM_PAUSE set;
2124                  */
2125                 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
2126                 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
2127                 break;
2128         case RTE_FC_RX_PAUSE:
2129                 /* Enable TX Flow control
2130                  * OPT_PAUSE set
2131                  * ASYM_PAUSE set
2132                  */
2133                 cfg.options |= DPNI_LINK_OPT_PAUSE;
2134                 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
2135                 break;
2136         case RTE_FC_NONE:
2137                 /* Disable Flow control
2138                  * OPT_PAUSE not set
2139                  * ASYM_PAUSE not set
2140                  */
2141                 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
2142                 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
2143                 break;
2144         default:
2145                 DPAA2_PMD_ERR("Incorrect Flow control flag (%d)",
2146                               fc_conf->mode);
2147                 return -1;
2148         }
2149
2150         ret = dpni_set_link_cfg(dpni, CMD_PRI_LOW, priv->token, &cfg);
2151         if (ret)
2152                 DPAA2_PMD_ERR("Unable to set Link configuration (err=%d)",
2153                               ret);
2154
2155         /* Enable link */
2156         dpaa2_dev_set_link_up(dev);
2157
2158         return ret;
2159 }
2160
2161 static int
2162 dpaa2_dev_rss_hash_update(struct rte_eth_dev *dev,
2163                           struct rte_eth_rss_conf *rss_conf)
2164 {
2165         struct rte_eth_dev_data *data = dev->data;
2166         struct dpaa2_dev_priv *priv = data->dev_private;
2167         struct rte_eth_conf *eth_conf = &data->dev_conf;
2168         int ret, tc_index;
2169
2170         PMD_INIT_FUNC_TRACE();
2171
2172         if (rss_conf->rss_hf) {
2173                 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
2174                         ret = dpaa2_setup_flow_dist(dev, rss_conf->rss_hf,
2175                                 tc_index);
2176                         if (ret) {
2177                                 DPAA2_PMD_ERR("Unable to set flow dist on tc%d",
2178                                         tc_index);
2179                                 return ret;
2180                         }
2181                 }
2182         } else {
2183                 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
2184                         ret = dpaa2_remove_flow_dist(dev, tc_index);
2185                         if (ret) {
2186                                 DPAA2_PMD_ERR(
2187                                         "Unable to remove flow dist on tc%d",
2188                                         tc_index);
2189                                 return ret;
2190                         }
2191                 }
2192         }
2193         eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf;
2194         return 0;
2195 }
2196
2197 static int
2198 dpaa2_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2199                             struct rte_eth_rss_conf *rss_conf)
2200 {
2201         struct rte_eth_dev_data *data = dev->data;
2202         struct rte_eth_conf *eth_conf = &data->dev_conf;
2203
2204         /* dpaa2 does not support rss_key, so length should be 0*/
2205         rss_conf->rss_key_len = 0;
2206         rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf;
2207         return 0;
2208 }
2209
2210 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev,
2211                 int eth_rx_queue_id,
2212                 struct dpaa2_dpcon_dev *dpcon,
2213                 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
2214 {
2215         struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2216         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2217         struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2218         uint8_t flow_id = dpaa2_ethq->flow_id;
2219         struct dpni_queue cfg;
2220         uint8_t options, priority;
2221         int ret;
2222
2223         if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_PARALLEL)
2224                 dpaa2_ethq->cb = dpaa2_dev_process_parallel_event;
2225         else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC)
2226                 dpaa2_ethq->cb = dpaa2_dev_process_atomic_event;
2227         else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED)
2228                 dpaa2_ethq->cb = dpaa2_dev_process_ordered_event;
2229         else
2230                 return -EINVAL;
2231
2232         priority = (RTE_EVENT_DEV_PRIORITY_LOWEST / queue_conf->ev.priority) *
2233                    (dpcon->num_priorities - 1);
2234
2235         memset(&cfg, 0, sizeof(struct dpni_queue));
2236         options = DPNI_QUEUE_OPT_DEST;
2237         cfg.destination.type = DPNI_DEST_DPCON;
2238         cfg.destination.id = dpcon->dpcon_id;
2239         cfg.destination.priority = priority;
2240
2241         if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) {
2242                 options |= DPNI_QUEUE_OPT_HOLD_ACTIVE;
2243                 cfg.destination.hold_active = 1;
2244         }
2245
2246         if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED &&
2247                         !eth_priv->en_ordered) {
2248                 struct opr_cfg ocfg;
2249
2250                 /* Restoration window size = 256 frames */
2251                 ocfg.oprrws = 3;
2252                 /* Restoration window size = 512 frames for LX2 */
2253                 if (dpaa2_svr_family == SVR_LX2160A)
2254                         ocfg.oprrws = 4;
2255                 /* Auto advance NESN window enabled */
2256                 ocfg.oa = 1;
2257                 /* Late arrival window size disabled */
2258                 ocfg.olws = 0;
2259                 /* ORL resource exhaustaion advance NESN disabled */
2260                 ocfg.oeane = 0;
2261                 /* Loose ordering enabled */
2262                 ocfg.oloe = 1;
2263                 eth_priv->en_loose_ordered = 1;
2264                 /* Strict ordering enabled if explicitly set */
2265                 if (getenv("DPAA2_STRICT_ORDERING_ENABLE")) {
2266                         ocfg.oloe = 0;
2267                         eth_priv->en_loose_ordered = 0;
2268                 }
2269
2270                 ret = dpni_set_opr(dpni, CMD_PRI_LOW, eth_priv->token,
2271                                    dpaa2_ethq->tc_index, flow_id,
2272                                    OPR_OPT_CREATE, &ocfg, 0);
2273                 if (ret) {
2274                         DPAA2_PMD_ERR("Error setting opr: ret: %d\n", ret);
2275                         return ret;
2276                 }
2277
2278                 eth_priv->en_ordered = 1;
2279         }
2280
2281         options |= DPNI_QUEUE_OPT_USER_CTX;
2282         cfg.user_context = (size_t)(dpaa2_ethq);
2283
2284         ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2285                              dpaa2_ethq->tc_index, flow_id, options, &cfg);
2286         if (ret) {
2287                 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2288                 return ret;
2289         }
2290
2291         memcpy(&dpaa2_ethq->ev, &queue_conf->ev, sizeof(struct rte_event));
2292
2293         return 0;
2294 }
2295
2296 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev,
2297                 int eth_rx_queue_id)
2298 {
2299         struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2300         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2301         struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2302         uint8_t flow_id = dpaa2_ethq->flow_id;
2303         struct dpni_queue cfg;
2304         uint8_t options;
2305         int ret;
2306
2307         memset(&cfg, 0, sizeof(struct dpni_queue));
2308         options = DPNI_QUEUE_OPT_DEST;
2309         cfg.destination.type = DPNI_DEST_NONE;
2310
2311         ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2312                              dpaa2_ethq->tc_index, flow_id, options, &cfg);
2313         if (ret)
2314                 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2315
2316         return ret;
2317 }
2318
2319 static int
2320 dpaa2_dev_flow_ops_get(struct rte_eth_dev *dev,
2321                        const struct rte_flow_ops **ops)
2322 {
2323         if (!dev)
2324                 return -ENODEV;
2325
2326         *ops = &dpaa2_flow_ops;
2327         return 0;
2328 }
2329
2330 static void
2331 dpaa2_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2332         struct rte_eth_rxq_info *qinfo)
2333 {
2334         struct dpaa2_queue *rxq;
2335         struct dpaa2_dev_priv *priv = dev->data->dev_private;
2336         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2337         uint16_t max_frame_length;
2338
2339         rxq = (struct dpaa2_queue *)dev->data->rx_queues[queue_id];
2340
2341         qinfo->mp = rxq->mb_pool;
2342         qinfo->scattered_rx = dev->data->scattered_rx;
2343         qinfo->nb_desc = rxq->nb_desc;
2344         if (dpni_get_max_frame_length(dpni, CMD_PRI_LOW, priv->token,
2345                                 &max_frame_length) == 0)
2346                 qinfo->rx_buf_size = max_frame_length;
2347
2348         qinfo->conf.rx_free_thresh = 1;
2349         qinfo->conf.rx_drop_en = 1;
2350         qinfo->conf.rx_deferred_start = 0;
2351         qinfo->conf.offloads = rxq->offloads;
2352 }
2353
2354 static void
2355 dpaa2_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2356         struct rte_eth_txq_info *qinfo)
2357 {
2358         struct dpaa2_queue *txq;
2359
2360         txq = dev->data->tx_queues[queue_id];
2361
2362         qinfo->nb_desc = txq->nb_desc;
2363         qinfo->conf.tx_thresh.pthresh = 0;
2364         qinfo->conf.tx_thresh.hthresh = 0;
2365         qinfo->conf.tx_thresh.wthresh = 0;
2366
2367         qinfo->conf.tx_free_thresh = 0;
2368         qinfo->conf.tx_rs_thresh = 0;
2369         qinfo->conf.offloads = txq->offloads;
2370         qinfo->conf.tx_deferred_start = 0;
2371 }
2372
2373 static int
2374 dpaa2_tm_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops)
2375 {
2376         *(const void **)ops = &dpaa2_tm_ops;
2377
2378         return 0;
2379 }
2380
2381 void
2382 rte_pmd_dpaa2_thread_init(void)
2383 {
2384         int ret;
2385
2386         if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
2387                 ret = dpaa2_affine_qbman_swp();
2388                 if (ret) {
2389                         DPAA2_PMD_ERR(
2390                                 "Failed to allocate IO portal, tid: %d\n",
2391                                 rte_gettid());
2392                         return;
2393                 }
2394         }
2395 }
2396
2397 static struct eth_dev_ops dpaa2_ethdev_ops = {
2398         .dev_configure    = dpaa2_eth_dev_configure,
2399         .dev_start            = dpaa2_dev_start,
2400         .dev_stop             = dpaa2_dev_stop,
2401         .dev_close            = dpaa2_dev_close,
2402         .promiscuous_enable   = dpaa2_dev_promiscuous_enable,
2403         .promiscuous_disable  = dpaa2_dev_promiscuous_disable,
2404         .allmulticast_enable  = dpaa2_dev_allmulticast_enable,
2405         .allmulticast_disable = dpaa2_dev_allmulticast_disable,
2406         .dev_set_link_up      = dpaa2_dev_set_link_up,
2407         .dev_set_link_down    = dpaa2_dev_set_link_down,
2408         .link_update       = dpaa2_dev_link_update,
2409         .stats_get             = dpaa2_dev_stats_get,
2410         .xstats_get            = dpaa2_dev_xstats_get,
2411         .xstats_get_by_id     = dpaa2_xstats_get_by_id,
2412         .xstats_get_names_by_id = dpaa2_xstats_get_names_by_id,
2413         .xstats_get_names      = dpaa2_xstats_get_names,
2414         .stats_reset       = dpaa2_dev_stats_reset,
2415         .xstats_reset         = dpaa2_dev_stats_reset,
2416         .fw_version_get    = dpaa2_fw_version_get,
2417         .dev_infos_get     = dpaa2_dev_info_get,
2418         .dev_supported_ptypes_get = dpaa2_supported_ptypes_get,
2419         .mtu_set           = dpaa2_dev_mtu_set,
2420         .vlan_filter_set      = dpaa2_vlan_filter_set,
2421         .vlan_offload_set     = dpaa2_vlan_offload_set,
2422         .vlan_tpid_set        = dpaa2_vlan_tpid_set,
2423         .rx_queue_setup    = dpaa2_dev_rx_queue_setup,
2424         .rx_queue_release  = dpaa2_dev_rx_queue_release,
2425         .tx_queue_setup    = dpaa2_dev_tx_queue_setup,
2426         .rx_burst_mode_get = dpaa2_dev_rx_burst_mode_get,
2427         .tx_burst_mode_get = dpaa2_dev_tx_burst_mode_get,
2428         .flow_ctrl_get        = dpaa2_flow_ctrl_get,
2429         .flow_ctrl_set        = dpaa2_flow_ctrl_set,
2430         .mac_addr_add         = dpaa2_dev_add_mac_addr,
2431         .mac_addr_remove      = dpaa2_dev_remove_mac_addr,
2432         .mac_addr_set         = dpaa2_dev_set_mac_addr,
2433         .rss_hash_update      = dpaa2_dev_rss_hash_update,
2434         .rss_hash_conf_get    = dpaa2_dev_rss_hash_conf_get,
2435         .flow_ops_get         = dpaa2_dev_flow_ops_get,
2436         .rxq_info_get         = dpaa2_rxq_info_get,
2437         .txq_info_get         = dpaa2_txq_info_get,
2438         .tm_ops_get           = dpaa2_tm_ops_get,
2439 #if defined(RTE_LIBRTE_IEEE1588)
2440         .timesync_enable      = dpaa2_timesync_enable,
2441         .timesync_disable     = dpaa2_timesync_disable,
2442         .timesync_read_time   = dpaa2_timesync_read_time,
2443         .timesync_write_time  = dpaa2_timesync_write_time,
2444         .timesync_adjust_time = dpaa2_timesync_adjust_time,
2445         .timesync_read_rx_timestamp = dpaa2_timesync_read_rx_timestamp,
2446         .timesync_read_tx_timestamp = dpaa2_timesync_read_tx_timestamp,
2447 #endif
2448 };
2449
2450 /* Populate the mac address from physically available (u-boot/firmware) and/or
2451  * one set by higher layers like MC (restool) etc.
2452  * Returns the table of MAC entries (multiple entries)
2453  */
2454 static int
2455 populate_mac_addr(struct fsl_mc_io *dpni_dev, struct dpaa2_dev_priv *priv,
2456                   struct rte_ether_addr *mac_entry)
2457 {
2458         int ret;
2459         struct rte_ether_addr phy_mac, prime_mac;
2460
2461         memset(&phy_mac, 0, sizeof(struct rte_ether_addr));
2462         memset(&prime_mac, 0, sizeof(struct rte_ether_addr));
2463
2464         /* Get the physical device MAC address */
2465         ret = dpni_get_port_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2466                                      phy_mac.addr_bytes);
2467         if (ret) {
2468                 DPAA2_PMD_ERR("DPNI get physical port MAC failed: %d", ret);
2469                 goto cleanup;
2470         }
2471
2472         ret = dpni_get_primary_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2473                                         prime_mac.addr_bytes);
2474         if (ret) {
2475                 DPAA2_PMD_ERR("DPNI get Prime port MAC failed: %d", ret);
2476                 goto cleanup;
2477         }
2478
2479         /* Now that both MAC have been obtained, do:
2480          *  if not_empty_mac(phy) && phy != Prime, overwrite prime with Phy
2481          *     and return phy
2482          *  If empty_mac(phy), return prime.
2483          *  if both are empty, create random MAC, set as prime and return
2484          */
2485         if (!rte_is_zero_ether_addr(&phy_mac)) {
2486                 /* If the addresses are not same, overwrite prime */
2487                 if (!rte_is_same_ether_addr(&phy_mac, &prime_mac)) {
2488                         ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2489                                                         priv->token,
2490                                                         phy_mac.addr_bytes);
2491                         if (ret) {
2492                                 DPAA2_PMD_ERR("Unable to set MAC Address: %d",
2493                                               ret);
2494                                 goto cleanup;
2495                         }
2496                         memcpy(&prime_mac, &phy_mac,
2497                                 sizeof(struct rte_ether_addr));
2498                 }
2499         } else if (rte_is_zero_ether_addr(&prime_mac)) {
2500                 /* In case phys and prime, both are zero, create random MAC */
2501                 rte_eth_random_addr(prime_mac.addr_bytes);
2502                 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2503                                                 priv->token,
2504                                                 prime_mac.addr_bytes);
2505                 if (ret) {
2506                         DPAA2_PMD_ERR("Unable to set MAC Address: %d", ret);
2507                         goto cleanup;
2508                 }
2509         }
2510
2511         /* prime_mac the final MAC address */
2512         memcpy(mac_entry, &prime_mac, sizeof(struct rte_ether_addr));
2513         return 0;
2514
2515 cleanup:
2516         return -1;
2517 }
2518
2519 static int
2520 check_devargs_handler(__rte_unused const char *key, const char *value,
2521                       __rte_unused void *opaque)
2522 {
2523         if (strcmp(value, "1"))
2524                 return -1;
2525
2526         return 0;
2527 }
2528
2529 static int
2530 dpaa2_get_devargs(struct rte_devargs *devargs, const char *key)
2531 {
2532         struct rte_kvargs *kvlist;
2533
2534         if (!devargs)
2535                 return 0;
2536
2537         kvlist = rte_kvargs_parse(devargs->args, NULL);
2538         if (!kvlist)
2539                 return 0;
2540
2541         if (!rte_kvargs_count(kvlist, key)) {
2542                 rte_kvargs_free(kvlist);
2543                 return 0;
2544         }
2545
2546         if (rte_kvargs_process(kvlist, key,
2547                                check_devargs_handler, NULL) < 0) {
2548                 rte_kvargs_free(kvlist);
2549                 return 0;
2550         }
2551         rte_kvargs_free(kvlist);
2552
2553         return 1;
2554 }
2555
2556 static int
2557 dpaa2_dev_init(struct rte_eth_dev *eth_dev)
2558 {
2559         struct rte_device *dev = eth_dev->device;
2560         struct rte_dpaa2_device *dpaa2_dev;
2561         struct fsl_mc_io *dpni_dev;
2562         struct dpni_attr attr;
2563         struct dpaa2_dev_priv *priv = eth_dev->data->dev_private;
2564         struct dpni_buffer_layout layout;
2565         int ret, hw_id, i;
2566
2567         PMD_INIT_FUNC_TRACE();
2568
2569         dpni_dev = rte_malloc(NULL, sizeof(struct fsl_mc_io), 0);
2570         if (!dpni_dev) {
2571                 DPAA2_PMD_ERR("Memory allocation failed for dpni device");
2572                 return -1;
2573         }
2574         dpni_dev->regs = dpaa2_get_mcp_ptr(MC_PORTAL_INDEX);
2575         eth_dev->process_private = (void *)dpni_dev;
2576
2577         /* For secondary processes, the primary has done all the work */
2578         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2579                 /* In case of secondary, only burst and ops API need to be
2580                  * plugged.
2581                  */
2582                 eth_dev->dev_ops = &dpaa2_ethdev_ops;
2583                 eth_dev->rx_queue_count = dpaa2_dev_rx_queue_count;
2584                 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE))
2585                         eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2586                 else if (dpaa2_get_devargs(dev->devargs,
2587                                         DRIVER_NO_PREFETCH_MODE))
2588                         eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2589                 else
2590                         eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2591                 eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2592                 return 0;
2593         }
2594
2595         dpaa2_dev = container_of(dev, struct rte_dpaa2_device, device);
2596
2597         hw_id = dpaa2_dev->object_id;
2598         ret = dpni_open(dpni_dev, CMD_PRI_LOW, hw_id, &priv->token);
2599         if (ret) {
2600                 DPAA2_PMD_ERR(
2601                              "Failure in opening dpni@%d with err code %d",
2602                              hw_id, ret);
2603                 rte_free(dpni_dev);
2604                 return -1;
2605         }
2606
2607         /* Clean the device first */
2608         ret = dpni_reset(dpni_dev, CMD_PRI_LOW, priv->token);
2609         if (ret) {
2610                 DPAA2_PMD_ERR("Failure cleaning dpni@%d with err code %d",
2611                               hw_id, ret);
2612                 goto init_err;
2613         }
2614
2615         ret = dpni_get_attributes(dpni_dev, CMD_PRI_LOW, priv->token, &attr);
2616         if (ret) {
2617                 DPAA2_PMD_ERR(
2618                              "Failure in get dpni@%d attribute, err code %d",
2619                              hw_id, ret);
2620                 goto init_err;
2621         }
2622
2623         priv->num_rx_tc = attr.num_rx_tcs;
2624         priv->qos_entries = attr.qos_entries;
2625         priv->fs_entries = attr.fs_entries;
2626         priv->dist_queues = attr.num_queues;
2627
2628         /* only if the custom CG is enabled */
2629         if (attr.options & DPNI_OPT_CUSTOM_CG)
2630                 priv->max_cgs = attr.num_cgs;
2631         else
2632                 priv->max_cgs = 0;
2633
2634         for (i = 0; i < priv->max_cgs; i++)
2635                 priv->cgid_in_use[i] = 0;
2636
2637         for (i = 0; i < attr.num_rx_tcs; i++)
2638                 priv->nb_rx_queues += attr.num_queues;
2639
2640         /* Using number of TX queues as number of TX TCs */
2641         priv->nb_tx_queues = attr.num_tx_tcs;
2642
2643         DPAA2_PMD_DEBUG("RX-TC= %d, rx_queues= %d, tx_queues=%d, max_cgs=%d",
2644                         priv->num_rx_tc, priv->nb_rx_queues,
2645                         priv->nb_tx_queues, priv->max_cgs);
2646
2647         priv->hw = dpni_dev;
2648         priv->hw_id = hw_id;
2649         priv->options = attr.options;
2650         priv->max_mac_filters = attr.mac_filter_entries;
2651         priv->max_vlan_filters = attr.vlan_filter_entries;
2652         priv->flags = 0;
2653 #if defined(RTE_LIBRTE_IEEE1588)
2654         printf("DPDK IEEE1588 is enabled\n");
2655         priv->flags |= DPAA2_TX_CONF_ENABLE;
2656 #endif
2657         /* Used with ``fslmc:dpni.1,drv_tx_conf=1`` */
2658         if (dpaa2_get_devargs(dev->devargs, DRIVER_TX_CONF)) {
2659                 priv->flags |= DPAA2_TX_CONF_ENABLE;
2660                 DPAA2_PMD_INFO("TX_CONF Enabled");
2661         }
2662
2663         if (dpaa2_get_devargs(dev->devargs, DRIVER_ERROR_QUEUE)) {
2664                 dpaa2_enable_err_queue = 1;
2665                 DPAA2_PMD_INFO("Enable error queue");
2666         }
2667
2668         /* Allocate memory for hardware structure for queues */
2669         ret = dpaa2_alloc_rx_tx_queues(eth_dev);
2670         if (ret) {
2671                 DPAA2_PMD_ERR("Queue allocation Failed");
2672                 goto init_err;
2673         }
2674
2675         /* Allocate memory for storing MAC addresses.
2676          * Table of mac_filter_entries size is allocated so that RTE ether lib
2677          * can add MAC entries when rte_eth_dev_mac_addr_add is called.
2678          */
2679         eth_dev->data->mac_addrs = rte_zmalloc("dpni",
2680                 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries, 0);
2681         if (eth_dev->data->mac_addrs == NULL) {
2682                 DPAA2_PMD_ERR(
2683                    "Failed to allocate %d bytes needed to store MAC addresses",
2684                    RTE_ETHER_ADDR_LEN * attr.mac_filter_entries);
2685                 ret = -ENOMEM;
2686                 goto init_err;
2687         }
2688
2689         ret = populate_mac_addr(dpni_dev, priv, &eth_dev->data->mac_addrs[0]);
2690         if (ret) {
2691                 DPAA2_PMD_ERR("Unable to fetch MAC Address for device");
2692                 rte_free(eth_dev->data->mac_addrs);
2693                 eth_dev->data->mac_addrs = NULL;
2694                 goto init_err;
2695         }
2696
2697         /* ... tx buffer layout ... */
2698         memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2699         if (priv->flags & DPAA2_TX_CONF_ENABLE) {
2700                 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
2701                                  DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2702                 layout.pass_timestamp = true;
2703         } else {
2704                 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2705         }
2706         layout.pass_frame_status = 1;
2707         ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2708                                      DPNI_QUEUE_TX, &layout);
2709         if (ret) {
2710                 DPAA2_PMD_ERR("Error (%d) in setting tx buffer layout", ret);
2711                 goto init_err;
2712         }
2713
2714         /* ... tx-conf and error buffer layout ... */
2715         memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2716         if (priv->flags & DPAA2_TX_CONF_ENABLE) {
2717                 layout.options = DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2718                 layout.pass_timestamp = true;
2719         }
2720         layout.options |= DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2721         layout.pass_frame_status = 1;
2722         ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2723                                      DPNI_QUEUE_TX_CONFIRM, &layout);
2724         if (ret) {
2725                 DPAA2_PMD_ERR("Error (%d) in setting tx-conf buffer layout",
2726                              ret);
2727                 goto init_err;
2728         }
2729
2730         eth_dev->dev_ops = &dpaa2_ethdev_ops;
2731
2732         if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE)) {
2733                 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2734                 DPAA2_PMD_INFO("Loopback mode");
2735         } else if (dpaa2_get_devargs(dev->devargs, DRIVER_NO_PREFETCH_MODE)) {
2736                 eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2737                 DPAA2_PMD_INFO("No Prefetch mode");
2738         } else {
2739                 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2740         }
2741         eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2742
2743         /*Init fields w.r.t. classficaition*/
2744         memset(&priv->extract.qos_key_extract, 0,
2745                 sizeof(struct dpaa2_key_extract));
2746         priv->extract.qos_extract_param = (size_t)rte_malloc(NULL, 256, 64);
2747         if (!priv->extract.qos_extract_param) {
2748                 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow "
2749                             " classificaiton ", ret);
2750                 goto init_err;
2751         }
2752         priv->extract.qos_key_extract.key_info.ipv4_src_offset =
2753                 IP_ADDRESS_OFFSET_INVALID;
2754         priv->extract.qos_key_extract.key_info.ipv4_dst_offset =
2755                 IP_ADDRESS_OFFSET_INVALID;
2756         priv->extract.qos_key_extract.key_info.ipv6_src_offset =
2757                 IP_ADDRESS_OFFSET_INVALID;
2758         priv->extract.qos_key_extract.key_info.ipv6_dst_offset =
2759                 IP_ADDRESS_OFFSET_INVALID;
2760
2761         for (i = 0; i < MAX_TCS; i++) {
2762                 memset(&priv->extract.tc_key_extract[i], 0,
2763                         sizeof(struct dpaa2_key_extract));
2764                 priv->extract.tc_extract_param[i] =
2765                         (size_t)rte_malloc(NULL, 256, 64);
2766                 if (!priv->extract.tc_extract_param[i]) {
2767                         DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow classificaiton",
2768                                      ret);
2769                         goto init_err;
2770                 }
2771                 priv->extract.tc_key_extract[i].key_info.ipv4_src_offset =
2772                         IP_ADDRESS_OFFSET_INVALID;
2773                 priv->extract.tc_key_extract[i].key_info.ipv4_dst_offset =
2774                         IP_ADDRESS_OFFSET_INVALID;
2775                 priv->extract.tc_key_extract[i].key_info.ipv6_src_offset =
2776                         IP_ADDRESS_OFFSET_INVALID;
2777                 priv->extract.tc_key_extract[i].key_info.ipv6_dst_offset =
2778                         IP_ADDRESS_OFFSET_INVALID;
2779         }
2780
2781         ret = dpni_set_max_frame_length(dpni_dev, CMD_PRI_LOW, priv->token,
2782                                         RTE_ETHER_MAX_LEN - RTE_ETHER_CRC_LEN
2783                                         + VLAN_TAG_SIZE);
2784         if (ret) {
2785                 DPAA2_PMD_ERR("Unable to set mtu. check config");
2786                 goto init_err;
2787         }
2788
2789         /*TODO To enable soft parser support DPAA2 driver needs to integrate
2790          * with external entity to receive byte code for software sequence
2791          * and same will be offload to the H/W using MC interface.
2792          * Currently it is assumed that DPAA2 driver has byte code by some
2793          * mean and same if offloaded to H/W.
2794          */
2795         if (getenv("DPAA2_ENABLE_SOFT_PARSER")) {
2796                 WRIOP_SS_INITIALIZER(priv);
2797                 ret = dpaa2_eth_load_wriop_soft_parser(priv, DPNI_SS_INGRESS);
2798                 if (ret < 0) {
2799                         DPAA2_PMD_ERR(" Error(%d) in loading softparser\n",
2800                                       ret);
2801                         return ret;
2802                 }
2803
2804                 ret = dpaa2_eth_enable_wriop_soft_parser(priv,
2805                                                          DPNI_SS_INGRESS);
2806                 if (ret < 0) {
2807                         DPAA2_PMD_ERR(" Error(%d) in enabling softparser\n",
2808                                       ret);
2809                         return ret;
2810                 }
2811         }
2812         RTE_LOG(INFO, PMD, "%s: netdev created\n", eth_dev->data->name);
2813         return 0;
2814 init_err:
2815         dpaa2_dev_close(eth_dev);
2816
2817         return ret;
2818 }
2819
2820 int dpaa2_dev_is_dpaa2(struct rte_eth_dev *dev)
2821 {
2822         return dev->device->driver == &rte_dpaa2_pmd.driver;
2823 }
2824
2825 static int
2826 rte_dpaa2_probe(struct rte_dpaa2_driver *dpaa2_drv,
2827                 struct rte_dpaa2_device *dpaa2_dev)
2828 {
2829         struct rte_eth_dev *eth_dev;
2830         struct dpaa2_dev_priv *dev_priv;
2831         int diag;
2832
2833         if ((DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE) >
2834                 RTE_PKTMBUF_HEADROOM) {
2835                 DPAA2_PMD_ERR(
2836                 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA2 Annotation req(%d)",
2837                 RTE_PKTMBUF_HEADROOM,
2838                 DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE);
2839
2840                 return -1;
2841         }
2842
2843         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2844                 eth_dev = rte_eth_dev_allocate(dpaa2_dev->device.name);
2845                 if (!eth_dev)
2846                         return -ENODEV;
2847                 dev_priv = rte_zmalloc("ethdev private structure",
2848                                        sizeof(struct dpaa2_dev_priv),
2849                                        RTE_CACHE_LINE_SIZE);
2850                 if (dev_priv == NULL) {
2851                         DPAA2_PMD_CRIT(
2852                                 "Unable to allocate memory for private data");
2853                         rte_eth_dev_release_port(eth_dev);
2854                         return -ENOMEM;
2855                 }
2856                 eth_dev->data->dev_private = (void *)dev_priv;
2857                 /* Store a pointer to eth_dev in dev_private */
2858                 dev_priv->eth_dev = eth_dev;
2859         } else {
2860                 eth_dev = rte_eth_dev_attach_secondary(dpaa2_dev->device.name);
2861                 if (!eth_dev) {
2862                         DPAA2_PMD_DEBUG("returning enodev");
2863                         return -ENODEV;
2864                 }
2865         }
2866
2867         eth_dev->device = &dpaa2_dev->device;
2868
2869         dpaa2_dev->eth_dev = eth_dev;
2870         eth_dev->data->rx_mbuf_alloc_failed = 0;
2871
2872         if (dpaa2_drv->drv_flags & RTE_DPAA2_DRV_INTR_LSC)
2873                 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;
2874
2875         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2876
2877         /* Invoke PMD device initialization function */
2878         diag = dpaa2_dev_init(eth_dev);
2879         if (diag == 0) {
2880                 rte_eth_dev_probing_finish(eth_dev);
2881                 return 0;
2882         }
2883
2884         rte_eth_dev_release_port(eth_dev);
2885         return diag;
2886 }
2887
2888 static int
2889 rte_dpaa2_remove(struct rte_dpaa2_device *dpaa2_dev)
2890 {
2891         struct rte_eth_dev *eth_dev;
2892         int ret;
2893
2894         eth_dev = dpaa2_dev->eth_dev;
2895         dpaa2_dev_close(eth_dev);
2896         ret = rte_eth_dev_release_port(eth_dev);
2897
2898         return ret;
2899 }
2900
2901 static struct rte_dpaa2_driver rte_dpaa2_pmd = {
2902         .drv_flags = RTE_DPAA2_DRV_INTR_LSC | RTE_DPAA2_DRV_IOVA_AS_VA,
2903         .drv_type = DPAA2_ETH,
2904         .probe = rte_dpaa2_probe,
2905         .remove = rte_dpaa2_remove,
2906 };
2907
2908 RTE_PMD_REGISTER_DPAA2(NET_DPAA2_PMD_DRIVER_NAME, rte_dpaa2_pmd);
2909 RTE_PMD_REGISTER_PARAM_STRING(NET_DPAA2_PMD_DRIVER_NAME,
2910                 DRIVER_LOOPBACK_MODE "=<int> "
2911                 DRIVER_NO_PREFETCH_MODE "=<int>"
2912                 DRIVER_TX_CONF "=<int>"
2913                 DRIVER_ERROR_QUEUE "=<int>");
2914 RTE_LOG_REGISTER_DEFAULT(dpaa2_logtype_pmd, NOTICE);