drivers/net/dpaa2/dpaa2_ethdev.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  *   Copyright (c) 2015-2016 Freescale Semiconductor, Inc. All rights reserved.
   4  *   Copyright 2016 NXP
   5  *
   6  */
   7
   8 #ifndef _DPAA2_ETHDEV_H
   9 #define _DPAA2_ETHDEV_H
  10
  11 #include <rte_event_eth_rx_adapter.h>
  12 #include <rte_pmd_dpaa2.h>
  13
  14 #include <dpaa2_hw_pvt.h>
  15
  16 #include <mc/fsl_dpni.h>
  17 #include <mc/fsl_mc_sys.h>
  18
  19 #define DPAA2_MIN_RX_BUF_SIZE 512
  20 #define DPAA2_MAX_RX_PKT_LEN  10240 /*WRIOP support*/
  21
  22 #define MAX_TCS                 DPNI_MAX_TC
  23 #define MAX_RX_QUEUES           128
  24 #define MAX_TX_QUEUES           16
  25
  26 /*default tc to be used for ,congestion, distribution etc configuration. */
  27 #define DPAA2_DEF_TC            0
  28
  29 /* Threshold for a Tx queue to *Enter* Congestion state.
  30  */
  31 #define CONG_ENTER_TX_THRESHOLD   512
  32
  33 /* Threshold for a queue to *Exit* Congestion state.
  34  */
  35 #define CONG_EXIT_TX_THRESHOLD    480
  36
  37 #define CONG_RETRY_COUNT 18000
  38
  39 /* RX queue tail drop threshold
  40  * currently considering 64 KB packets
  41  */
  42 #define CONG_THRESHOLD_RX_BYTES_Q  (64 * 1024)
  43 #define CONG_RX_OAL     128
  44
  45 /* Size of the input SMMU mapped memory required by MC */
  46 #define DIST_PARAM_IOVA_SIZE 256
  47
  48 /* Enable TX Congestion control support
  49  * default is disable
  50  */
  51 #define DPAA2_TX_CGR_OFF        0x01
  52
  53 /* Disable RX tail drop, default is enable */
  54 #define DPAA2_RX_TAILDROP_OFF   0x04
  55
  56 #define DPAA2_RSS_OFFLOAD_ALL ( \
  57         ETH_RSS_L2_PAYLOAD | \
  58         ETH_RSS_IP | \
  59         ETH_RSS_UDP | \
  60         ETH_RSS_TCP | \
  61         ETH_RSS_SCTP)
  62
  63 /* LX2 FRC Parsed values (Little Endian) */
  64 #define DPAA2_PKT_TYPE_ETHER            0x0060
  65 #define DPAA2_PKT_TYPE_IPV4             0x0000
  66 #define DPAA2_PKT_TYPE_IPV6             0x0020
  67 #define DPAA2_PKT_TYPE_IPV4_EXT \
  68                         (0x0001 | DPAA2_PKT_TYPE_IPV4)
  69 #define DPAA2_PKT_TYPE_IPV6_EXT \
  70                         (0x0001 | DPAA2_PKT_TYPE_IPV6)
  71 #define DPAA2_PKT_TYPE_IPV4_TCP \
  72                         (0x000e | DPAA2_PKT_TYPE_IPV4)
  73 #define DPAA2_PKT_TYPE_IPV6_TCP \
  74                         (0x000e | DPAA2_PKT_TYPE_IPV6)
  75 #define DPAA2_PKT_TYPE_IPV4_UDP \
  76                         (0x0010 | DPAA2_PKT_TYPE_IPV4)
  77 #define DPAA2_PKT_TYPE_IPV6_UDP \
  78                         (0x0010 | DPAA2_PKT_TYPE_IPV6)
  79 #define DPAA2_PKT_TYPE_IPV4_SCTP        \
  80                         (0x000f | DPAA2_PKT_TYPE_IPV4)
  81 #define DPAA2_PKT_TYPE_IPV6_SCTP        \
  82                         (0x000f | DPAA2_PKT_TYPE_IPV6)
  83 #define DPAA2_PKT_TYPE_IPV4_ICMP \
  84                         (0x0003 | DPAA2_PKT_TYPE_IPV4_EXT)
  85 #define DPAA2_PKT_TYPE_IPV6_ICMP \
  86                         (0x0003 | DPAA2_PKT_TYPE_IPV6_EXT)
  87 #define DPAA2_PKT_TYPE_VLAN_1           0x0160
  88 #define DPAA2_PKT_TYPE_VLAN_2           0x0260
  89
  90 /* enable timestamp in mbuf*/
  91 extern enum pmd_dpaa2_ts dpaa2_enable_ts;
  92
  93 #define DPAA2_QOS_TABLE_RECONFIGURE     1
  94 #define DPAA2_FS_TABLE_RECONFIGURE      2
  95
  96 /*Externaly defined*/
  97 extern const struct rte_flow_ops dpaa2_flow_ops;
  98 extern enum rte_filter_type dpaa2_filter_type;
  99
 100 struct dpaa2_dev_priv {
 101         void *hw;
 102         int32_t hw_id;
 103         int32_t qdid;
 104         uint16_t token;
 105         uint8_t nb_tx_queues;
 106         uint8_t nb_rx_queues;
 107         uint32_t options;
 108         void *rx_vq[MAX_RX_QUEUES];
 109         void *tx_vq[MAX_TX_QUEUES];
 110
 111         struct dpaa2_bp_list *bp_list; /**<Attached buffer pool list */
 112         uint8_t max_mac_filters;
 113         uint8_t max_vlan_filters;
 114         uint8_t num_rx_tc;
 115         uint8_t flags; /*dpaa2 config flags */
 116         uint8_t en_ordered;
 117         uint8_t en_loose_ordered;
 118         uint8_t max_cgs;
 119         uint8_t cgid_in_use[MAX_RX_QUEUES];
 120
 121         struct pattern_s {
 122                 uint8_t item_count;
 123                 uint8_t pattern_type[DPKG_MAX_NUM_OF_EXTRACTS];
 124         } pattern[MAX_TCS + 1];
 125
 126         struct extract_s {
 127                 struct dpkg_profile_cfg qos_key_cfg;
 128                 struct dpkg_profile_cfg fs_key_cfg[MAX_TCS];
 129                 uint64_t qos_extract_param;
 130                 uint64_t fs_extract_param[MAX_TCS];
 131         } extract;
 132         LIST_HEAD(, rte_flow) flows; /**< Configured flow rule handles. */
 133 };
 134
 135 int dpaa2_distset_to_dpkg_profile_cfg(uint64_t req_dist_set,
 136                                       struct dpkg_profile_cfg *kg_cfg);
 137
 138 int dpaa2_setup_flow_dist(struct rte_eth_dev *eth_dev,
 139                           uint64_t req_dist_set);
 140
 141 int dpaa2_remove_flow_dist(struct rte_eth_dev *eth_dev,
 142                            uint8_t tc_index);
 143
 144 int dpaa2_attach_bp_list(struct dpaa2_dev_priv *priv, void *blist);
 145
 146 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev,
 147                 int eth_rx_queue_id,
 148                 uint16_t dpcon_id,
 149                 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf);
 150
 151 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev,
 152                 int eth_rx_queue_id);
 153
 154 uint16_t dpaa2_dev_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts);
 155
 156 uint16_t dpaa2_dev_loopback_rx(void *queue, struct rte_mbuf **bufs,
 157                                 uint16_t nb_pkts);
 158
 159 uint16_t dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs,
 160                                uint16_t nb_pkts);
 161 void dpaa2_dev_process_parallel_event(struct qbman_swp *swp,
 162                                       const struct qbman_fd *fd,
 163                                       const struct qbman_result *dq,
 164                                       struct dpaa2_queue *rxq,
 165                                       struct rte_event *ev);
 166 void dpaa2_dev_process_atomic_event(struct qbman_swp *swp,
 167                                     const struct qbman_fd *fd,
 168                                     const struct qbman_result *dq,
 169                                     struct dpaa2_queue *rxq,
 170                                     struct rte_event *ev);
 171 void dpaa2_dev_process_ordered_event(struct qbman_swp *swp,
 172                                      const struct qbman_fd *fd,
 173                                      const struct qbman_result *dq,
 174                                      struct dpaa2_queue *rxq,
 175                                      struct rte_event *ev);
 176 uint16_t dpaa2_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts);
 177 uint16_t dpaa2_dev_tx_ordered(void *queue, struct rte_mbuf **bufs,
 178                               uint16_t nb_pkts);
 179 uint16_t dummy_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts);
 180 void dpaa2_dev_free_eqresp_buf(uint16_t eqresp_ci);
 181 void dpaa2_flow_clean(struct rte_eth_dev *dev);
 182
 183 #endif /* _DPAA2_ETHDEV_H */