drivers/net/dpaa2/dpaa2_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  *   Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
   4  *   Copyright 2016 NXP
   5  *
   6  */
   7
   8 #include <time.h>
   9 #include <net/if.h>
  10
  11 #include <rte_mbuf.h>
  12 #include <rte_ethdev_driver.h>
  13 #include <rte_malloc.h>
  14 #include <rte_memcpy.h>
  15 #include <rte_string_fns.h>
  16 #include <rte_dev.h>
  17
  18 #include <rte_fslmc.h>
  19 #include <fslmc_logs.h>
  20 #include <fslmc_vfio.h>
  21 #include <dpaa2_hw_pvt.h>
  22 #include <dpaa2_hw_dpio.h>
  23 #include <dpaa2_hw_mempool.h>
  24
  25 #include "dpaa2_ethdev.h"
  26 #include "base/dpaa2_hw_dpni_annot.h"
  27
  28 #define DPAA2_MBUF_TO_CONTIG_FD(_mbuf, _fd, _bpid)  do { \
  29         DPAA2_SET_FD_ADDR(_fd, DPAA2_MBUF_VADDR_TO_IOVA(_mbuf)); \
  30         DPAA2_SET_FD_LEN(_fd, _mbuf->data_len); \
  31         DPAA2_SET_ONLY_FD_BPID(_fd, _bpid); \
  32         DPAA2_SET_FD_OFFSET(_fd, _mbuf->data_off); \
  33         DPAA2_SET_FD_ASAL(_fd, DPAA2_ASAL_VAL); \
  34 } while (0)
  35
  36 static inline void __attribute__((hot))
  37 dpaa2_dev_rx_parse_frc(struct rte_mbuf *m, uint16_t frc)
  38 {
  39         PMD_RX_LOG(DEBUG, "frc = 0x%x   ", frc);
  40
  41         m->packet_type = RTE_PTYPE_UNKNOWN;
  42         switch (frc) {
  43         case DPAA2_PKT_TYPE_ETHER:
  44                 m->packet_type = RTE_PTYPE_L2_ETHER;
  45                 break;
  46         case DPAA2_PKT_TYPE_IPV4:
  47                 m->packet_type = RTE_PTYPE_L2_ETHER |
  48                         RTE_PTYPE_L3_IPV4;
  49                 break;
  50         case DPAA2_PKT_TYPE_IPV6:
  51                 m->packet_type = RTE_PTYPE_L2_ETHER |
  52                         RTE_PTYPE_L3_IPV6;
  53                 break;
  54         case DPAA2_PKT_TYPE_IPV4_EXT:
  55                 m->packet_type = RTE_PTYPE_L2_ETHER |
  56                         RTE_PTYPE_L3_IPV4_EXT;
  57                 break;
  58         case DPAA2_PKT_TYPE_IPV6_EXT:
  59                 m->packet_type = RTE_PTYPE_L2_ETHER |
  60                         RTE_PTYPE_L3_IPV6_EXT;
  61                 break;
  62         case DPAA2_PKT_TYPE_IPV4_TCP:
  63                 m->packet_type = RTE_PTYPE_L2_ETHER |
  64                         RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_TCP;
  65                 break;
  66         case DPAA2_PKT_TYPE_IPV6_TCP:
  67                 m->packet_type = RTE_PTYPE_L2_ETHER |
  68                         RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_TCP;
  69                 break;
  70         case DPAA2_PKT_TYPE_IPV4_UDP:
  71                 m->packet_type = RTE_PTYPE_L2_ETHER |
  72                         RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_UDP;
  73                 break;
  74         case DPAA2_PKT_TYPE_IPV6_UDP:
  75                 m->packet_type = RTE_PTYPE_L2_ETHER |
  76                         RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_UDP;
  77                 break;
  78         case DPAA2_PKT_TYPE_IPV4_SCTP:
  79                 m->packet_type = RTE_PTYPE_L2_ETHER |
  80                         RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_SCTP;
  81                 break;
  82         case DPAA2_PKT_TYPE_IPV6_SCTP:
  83                 m->packet_type = RTE_PTYPE_L2_ETHER |
  84                         RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_SCTP;
  85                 break;
  86         case DPAA2_PKT_TYPE_IPV4_ICMP:
  87                 m->packet_type = RTE_PTYPE_L2_ETHER |
  88                         RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_ICMP;
  89                 break;
  90         case DPAA2_PKT_TYPE_IPV6_ICMP:
  91                 m->packet_type = RTE_PTYPE_L2_ETHER |
  92                         RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_ICMP;
  93                 break;
  94         case DPAA2_PKT_TYPE_VLAN_1:
  95         case DPAA2_PKT_TYPE_VLAN_2:
  96                 m->ol_flags |= PKT_RX_VLAN;
  97                 break;
  98         /* More switch cases can be added */
  99         /* TODO: Add handling for checksum error check from FRC */
 100         default:
 101                 m->packet_type = RTE_PTYPE_UNKNOWN;
 102         }
 103 }
 104
 105 static inline uint32_t __attribute__((hot))
 106 dpaa2_dev_rx_parse_slow(struct dpaa2_annot_hdr *annotation)
 107 {
 108         uint32_t pkt_type = RTE_PTYPE_UNKNOWN;
 109
 110         PMD_RX_LOG(DEBUG, "annotation = 0x%" PRIx64, annotation->word4);
 111         if (BIT_ISSET_AT_POS(annotation->word3, L2_ARP_PRESENT)) {
 112                 pkt_type = RTE_PTYPE_L2_ETHER_ARP;
 113                 goto parse_done;
 114         } else if (BIT_ISSET_AT_POS(annotation->word3, L2_ETH_MAC_PRESENT)) {
 115                 pkt_type = RTE_PTYPE_L2_ETHER;
 116         } else {
 117                 goto parse_done;
 118         }
 119
 120         if (BIT_ISSET_AT_POS(annotation->word4, L3_IPV4_1_PRESENT |
 121                              L3_IPV4_N_PRESENT)) {
 122                 pkt_type |= RTE_PTYPE_L3_IPV4;
 123                 if (BIT_ISSET_AT_POS(annotation->word4, L3_IP_1_OPT_PRESENT |
 124                         L3_IP_N_OPT_PRESENT))
 125                         pkt_type |= RTE_PTYPE_L3_IPV4_EXT;
 126
 127         } else if (BIT_ISSET_AT_POS(annotation->word4, L3_IPV6_1_PRESENT |
 128                   L3_IPV6_N_PRESENT)) {
 129                 pkt_type |= RTE_PTYPE_L3_IPV6;
 130                 if (BIT_ISSET_AT_POS(annotation->word4, L3_IP_1_OPT_PRESENT |
 131                     L3_IP_N_OPT_PRESENT))
 132                         pkt_type |= RTE_PTYPE_L3_IPV6_EXT;
 133         } else {
 134                 goto parse_done;
 135         }
 136
 137         if (BIT_ISSET_AT_POS(annotation->word4, L3_IP_1_FIRST_FRAGMENT |
 138             L3_IP_1_MORE_FRAGMENT |
 139             L3_IP_N_FIRST_FRAGMENT |
 140             L3_IP_N_MORE_FRAGMENT)) {
 141                 pkt_type |= RTE_PTYPE_L4_FRAG;
 142                 goto parse_done;
 143         } else {
 144                 pkt_type |= RTE_PTYPE_L4_NONFRAG;
 145         }
 146
 147         if (BIT_ISSET_AT_POS(annotation->word4, L3_PROTO_UDP_PRESENT))
 148                 pkt_type |= RTE_PTYPE_L4_UDP;
 149
 150         else if (BIT_ISSET_AT_POS(annotation->word4, L3_PROTO_TCP_PRESENT))
 151                 pkt_type |= RTE_PTYPE_L4_TCP;
 152
 153         else if (BIT_ISSET_AT_POS(annotation->word4, L3_PROTO_SCTP_PRESENT))
 154                 pkt_type |= RTE_PTYPE_L4_SCTP;
 155
 156         else if (BIT_ISSET_AT_POS(annotation->word4, L3_PROTO_ICMP_PRESENT))
 157                 pkt_type |= RTE_PTYPE_L4_ICMP;
 158
 159         else if (BIT_ISSET_AT_POS(annotation->word4, L3_IP_UNKNOWN_PROTOCOL))
 160                 pkt_type |= RTE_PTYPE_UNKNOWN;
 161
 162 parse_done:
 163         return pkt_type;
 164 }
 165
 166 static inline uint32_t __attribute__((hot))
 167 dpaa2_dev_rx_parse(struct rte_mbuf *mbuf, void *hw_annot_addr)
 168 {
 169         struct dpaa2_annot_hdr *annotation =
 170                         (struct dpaa2_annot_hdr *)hw_annot_addr;
 171
 172         PMD_RX_LOG(DEBUG, "annotation = 0x%" PRIx64, annotation->word4);
 173
 174         /* Check offloads first */
 175         if (BIT_ISSET_AT_POS(annotation->word3,
 176                              L2_VLAN_1_PRESENT | L2_VLAN_N_PRESENT))
 177                 mbuf->ol_flags |= PKT_RX_VLAN;
 178
 179         if (BIT_ISSET_AT_POS(annotation->word8, DPAA2_ETH_FAS_L3CE))
 180                 mbuf->ol_flags |= PKT_RX_IP_CKSUM_BAD;
 181         else if (BIT_ISSET_AT_POS(annotation->word8, DPAA2_ETH_FAS_L4CE))
 182                 mbuf->ol_flags |= PKT_RX_L4_CKSUM_BAD;
 183
 184         /* Return some common types from parse processing */
 185         switch (annotation->word4) {
 186         case DPAA2_L3_IPv4:
 187                 return RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4;
 188         case DPAA2_L3_IPv6:
 189                 return  RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6;
 190         case DPAA2_L3_IPv4_TCP:
 191                 return  RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4 |
 192                                 RTE_PTYPE_L4_TCP;
 193         case DPAA2_L3_IPv4_UDP:
 194                 return  RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4 |
 195                                 RTE_PTYPE_L4_UDP;
 196         case DPAA2_L3_IPv6_TCP:
 197                 return  RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6 |
 198                                 RTE_PTYPE_L4_TCP;
 199         case DPAA2_L3_IPv6_UDP:
 200                 return  RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6 |
 201                                 RTE_PTYPE_L4_UDP;
 202         default:
 203                 PMD_RX_LOG(DEBUG, "Slow parse the parsing results\n");
 204                 break;
 205         }
 206
 207         return dpaa2_dev_rx_parse_slow(annotation);
 208 }
 209
 210 static inline struct rte_mbuf *__attribute__((hot))
 211 eth_sg_fd_to_mbuf(const struct qbman_fd *fd)
 212 {
 213         struct qbman_sge *sgt, *sge;
 214         size_t sg_addr, fd_addr;
 215         int i = 0;
 216         struct rte_mbuf *first_seg, *next_seg, *cur_seg, *temp;
 217
 218         fd_addr = (size_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd));
 219
 220         /* Get Scatter gather table address */
 221         sgt = (struct qbman_sge *)(fd_addr + DPAA2_GET_FD_OFFSET(fd));
 222
 223         sge = &sgt[i++];
 224         sg_addr = (size_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FLE_ADDR(sge));
 225
 226         /* First Scatter gather entry */
 227         first_seg = DPAA2_INLINE_MBUF_FROM_BUF(sg_addr,
 228                 rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size);
 229         /* Prepare all the metadata for first segment */
 230         first_seg->buf_addr = (uint8_t *)sg_addr;
 231         first_seg->ol_flags = 0;
 232         first_seg->data_off = DPAA2_GET_FLE_OFFSET(sge);
 233         first_seg->data_len = sge->length  & 0x1FFFF;
 234         first_seg->pkt_len = DPAA2_GET_FD_LEN(fd);
 235         first_seg->nb_segs = 1;
 236         first_seg->next = NULL;
 237         if (dpaa2_svr_family == SVR_LX2160A)
 238                 dpaa2_dev_rx_parse_frc(first_seg,
 239                                 DPAA2_GET_FD_FRC_PARSE_SUM(fd));
 240         else
 241                 first_seg->packet_type = dpaa2_dev_rx_parse(first_seg,
 242                         (void *)((size_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd))
 243                          + DPAA2_FD_PTA_SIZE));
 244
 245         rte_mbuf_refcnt_set(first_seg, 1);
 246         cur_seg = first_seg;
 247         while (!DPAA2_SG_IS_FINAL(sge)) {
 248                 sge = &sgt[i++];
 249                 sg_addr = (size_t)DPAA2_IOVA_TO_VADDR(
 250                                 DPAA2_GET_FLE_ADDR(sge));
 251                 next_seg = DPAA2_INLINE_MBUF_FROM_BUF(sg_addr,
 252                         rte_dpaa2_bpid_info[DPAA2_GET_FLE_BPID(sge)].meta_data_size);
 253                 next_seg->buf_addr  = (uint8_t *)sg_addr;
 254                 next_seg->data_off  = DPAA2_GET_FLE_OFFSET(sge);
 255                 next_seg->data_len  = sge->length  & 0x1FFFF;
 256                 first_seg->nb_segs += 1;
 257                 rte_mbuf_refcnt_set(next_seg, 1);
 258                 cur_seg->next = next_seg;
 259                 next_seg->next = NULL;
 260                 cur_seg = next_seg;
 261         }
 262         temp = DPAA2_INLINE_MBUF_FROM_BUF(fd_addr,
 263                 rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size);
 264         rte_mbuf_refcnt_set(temp, 1);
 265         rte_pktmbuf_free_seg(temp);
 266
 267         return (void *)first_seg;
 268 }
 269
 270 static inline struct rte_mbuf *__attribute__((hot))
 271 eth_fd_to_mbuf(const struct qbman_fd *fd)
 272 {
 273         struct rte_mbuf *mbuf = DPAA2_INLINE_MBUF_FROM_BUF(
 274                 DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd)),
 275                      rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size);
 276
 277         /* need to repopulated some of the fields,
 278          * as they may have changed in last transmission
 279          */
 280         mbuf->nb_segs = 1;
 281         mbuf->ol_flags = 0;
 282         mbuf->data_off = DPAA2_GET_FD_OFFSET(fd);
 283         mbuf->data_len = DPAA2_GET_FD_LEN(fd);
 284         mbuf->pkt_len = mbuf->data_len;
 285         mbuf->next = NULL;
 286         rte_mbuf_refcnt_set(mbuf, 1);
 287
 288         /* Parse the packet */
 289         /* parse results for LX2 are there in FRC field of FD.
 290          * For other DPAA2 platforms , parse results are after
 291          * the private - sw annotation area
 292          */
 293
 294         if (dpaa2_svr_family == SVR_LX2160A)
 295                 dpaa2_dev_rx_parse_frc(mbuf, DPAA2_GET_FD_FRC_PARSE_SUM(fd));
 296         else
 297                 mbuf->packet_type = dpaa2_dev_rx_parse(mbuf,
 298                         (void *)((size_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd))
 299                          + DPAA2_FD_PTA_SIZE));
 300
 301         PMD_RX_LOG(DEBUG, "to mbuf - mbuf =%p, mbuf->buf_addr =%p, off = %d,"
 302                 "fd_off=%d fd =%" PRIx64 ", meta = %d  bpid =%d, len=%d\n",
 303                 (void *)mbuf, (void *)mbuf->buf_addr, mbuf->data_off,
 304                 DPAA2_GET_FD_OFFSET(fd), DPAA2_GET_FD_ADDR(fd),
 305                 rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size,
 306                 DPAA2_GET_FD_BPID(fd), DPAA2_GET_FD_LEN(fd));
 307
 308         return mbuf;
 309 }
 310
 311 static int __attribute__ ((noinline)) __attribute__((hot))
 312 eth_mbuf_to_sg_fd(struct rte_mbuf *mbuf,
 313                   struct qbman_fd *fd, uint16_t bpid)
 314 {
 315         struct rte_mbuf *cur_seg = mbuf, *prev_seg, *mi, *temp;
 316         struct qbman_sge *sgt, *sge = NULL;
 317         int i;
 318
 319         if (unlikely(mbuf->ol_flags & PKT_TX_VLAN_PKT)) {
 320                 int ret = rte_vlan_insert(&mbuf);
 321                 if (ret)
 322                         return ret;
 323         }
 324
 325         temp = rte_pktmbuf_alloc(mbuf->pool);
 326         if (temp == NULL) {
 327                 PMD_TX_LOG(ERR, "No memory to allocate S/G table");
 328                 return -ENOMEM;
 329         }
 330
 331         DPAA2_SET_FD_ADDR(fd, DPAA2_MBUF_VADDR_TO_IOVA(temp));
 332         DPAA2_SET_FD_LEN(fd, mbuf->pkt_len);
 333         DPAA2_SET_ONLY_FD_BPID(fd, bpid);
 334         DPAA2_SET_FD_OFFSET(fd, temp->data_off);
 335         DPAA2_SET_FD_ASAL(fd, DPAA2_ASAL_VAL);
 336         DPAA2_FD_SET_FORMAT(fd, qbman_fd_sg);
 337         /*Set Scatter gather table and Scatter gather entries*/
 338         sgt = (struct qbman_sge *)(
 339                         (size_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd))
 340                         + DPAA2_GET_FD_OFFSET(fd));
 341
 342         for (i = 0; i < mbuf->nb_segs; i++) {
 343                 sge = &sgt[i];
 344                 /*Resetting the buffer pool id and offset field*/
 345                 sge->fin_bpid_offset = 0;
 346                 DPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(cur_seg));
 347                 DPAA2_SET_FLE_OFFSET(sge, cur_seg->data_off);
 348                 sge->length = cur_seg->data_len;
 349                 if (RTE_MBUF_DIRECT(cur_seg)) {
 350                         if (rte_mbuf_refcnt_read(cur_seg) > 1) {
 351                                 /* If refcnt > 1, invalid bpid is set to ensure
 352                                  * buffer is not freed by HW
 353                                  */
 354                                 DPAA2_SET_FLE_IVP(sge);
 355                                 rte_mbuf_refcnt_update(cur_seg, -1);
 356                         } else
 357                                 DPAA2_SET_FLE_BPID(sge,
 358                                                 mempool_to_bpid(cur_seg->pool));
 359                         cur_seg = cur_seg->next;
 360                 } else {
 361                         /* Get owner MBUF from indirect buffer */
 362                         mi = rte_mbuf_from_indirect(cur_seg);
 363                         if (rte_mbuf_refcnt_read(mi) > 1) {
 364                                 /* If refcnt > 1, invalid bpid is set to ensure
 365                                  * owner buffer is not freed by HW
 366                                  */
 367                                 DPAA2_SET_FLE_IVP(sge);
 368                         } else {
 369                                 DPAA2_SET_FLE_BPID(sge,
 370                                                    mempool_to_bpid(mi->pool));
 371                                 rte_mbuf_refcnt_update(mi, 1);
 372                         }
 373                         prev_seg = cur_seg;
 374                         cur_seg = cur_seg->next;
 375                         prev_seg->next = NULL;
 376                         rte_pktmbuf_free(prev_seg);
 377                 }
 378         }
 379         DPAA2_SG_SET_FINAL(sge, true);
 380         return 0;
 381 }
 382
 383 static void
 384 eth_mbuf_to_fd(struct rte_mbuf *mbuf,
 385                struct qbman_fd *fd, uint16_t bpid) __attribute__((unused));
 386
 387 static void __attribute__ ((noinline)) __attribute__((hot))
 388 eth_mbuf_to_fd(struct rte_mbuf *mbuf,
 389                struct qbman_fd *fd, uint16_t bpid)
 390 {
 391         if (unlikely(mbuf->ol_flags & PKT_TX_VLAN_PKT)) {
 392                 if (rte_vlan_insert(&mbuf)) {
 393                         rte_pktmbuf_free(mbuf);
 394                         return;
 395                 }
 396         }
 397
 398         DPAA2_MBUF_TO_CONTIG_FD(mbuf, fd, bpid);
 399
 400         PMD_TX_LOG(DEBUG, "mbuf =%p, mbuf->buf_addr =%p, off = %d,"
 401                 "fd_off=%d fd =%" PRIx64 ", meta = %d  bpid =%d, len=%d\n",
 402                 (void *)mbuf, mbuf->buf_addr, mbuf->data_off,
 403                 DPAA2_GET_FD_OFFSET(fd), DPAA2_GET_FD_ADDR(fd),
 404                 rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size,
 405                 DPAA2_GET_FD_BPID(fd), DPAA2_GET_FD_LEN(fd));
 406         if (RTE_MBUF_DIRECT(mbuf)) {
 407                 if (rte_mbuf_refcnt_read(mbuf) > 1) {
 408                         DPAA2_SET_FD_IVP(fd);
 409                         rte_mbuf_refcnt_update(mbuf, -1);
 410                 }
 411         } else {
 412                 struct rte_mbuf *mi;
 413
 414                 mi = rte_mbuf_from_indirect(mbuf);
 415                 if (rte_mbuf_refcnt_read(mi) > 1)
 416                         DPAA2_SET_FD_IVP(fd);
 417                 else
 418                         rte_mbuf_refcnt_update(mi, 1);
 419                 rte_pktmbuf_free(mbuf);
 420         }
 421 }
 422
 423 static inline int __attribute__((hot))
 424 eth_copy_mbuf_to_fd(struct rte_mbuf *mbuf,
 425                     struct qbman_fd *fd, uint16_t bpid)
 426 {
 427         struct rte_mbuf *m;
 428         void *mb = NULL;
 429
 430         if (unlikely(mbuf->ol_flags & PKT_TX_VLAN_PKT)) {
 431                 int ret = rte_vlan_insert(&mbuf);
 432                 if (ret)
 433                         return ret;
 434         }
 435
 436         if (rte_dpaa2_mbuf_alloc_bulk(
 437                 rte_dpaa2_bpid_info[bpid].bp_list->mp, &mb, 1)) {
 438                 PMD_TX_LOG(WARNING, "Unable to allocated DPAA2 buffer");
 439                 return -1;
 440         }
 441         m = (struct rte_mbuf *)mb;
 442         memcpy((char *)m->buf_addr + mbuf->data_off,
 443                (void *)((char *)mbuf->buf_addr + mbuf->data_off),
 444                 mbuf->pkt_len);
 445
 446         /* Copy required fields */
 447         m->data_off = mbuf->data_off;
 448         m->ol_flags = mbuf->ol_flags;
 449         m->packet_type = mbuf->packet_type;
 450         m->tx_offload = mbuf->tx_offload;
 451
 452         DPAA2_MBUF_TO_CONTIG_FD(m, fd, bpid);
 453
 454         PMD_TX_LOG(DEBUG, " mbuf %p BMAN buf addr %p",
 455                    (void *)mbuf, mbuf->buf_addr);
 456
 457         PMD_TX_LOG(DEBUG,
 458                 "fd_off=%d fd =%" PRIx64 ", meta = %d  bpid =%d, len=%d\n",
 459                 DPAA2_GET_FD_OFFSET(fd),
 460                 DPAA2_GET_FD_ADDR(fd),
 461                 rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size,
 462                 DPAA2_GET_FD_BPID(fd),
 463                 DPAA2_GET_FD_LEN(fd));
 464
 465         return 0;
 466 }
 467
 468 uint16_t
 469 dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)
 470 {
 471         /* Function receive frames for a given device and VQ*/
 472         struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)queue;
 473         struct qbman_result *dq_storage, *dq_storage1 = NULL;
 474         uint32_t fqid = dpaa2_q->fqid;
 475         int ret, num_rx = 0;
 476         uint8_t pending, status;
 477         struct qbman_swp *swp;
 478         const struct qbman_fd *fd, *next_fd;
 479         struct qbman_pull_desc pulldesc;
 480         struct queue_storage_info_t *q_storage = dpaa2_q->q_storage;
 481         struct rte_eth_dev *dev = dpaa2_q->dev;
 482
 483         if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
 484                 ret = dpaa2_affine_qbman_swp();
 485                 if (ret) {
 486                         RTE_LOG(ERR, PMD, "Failure in affining portal\n");
 487                         return 0;
 488                 }
 489         }
 490         swp = DPAA2_PER_LCORE_PORTAL;
 491         if (unlikely(!q_storage->active_dqs)) {
 492                 q_storage->toggle = 0;
 493                 dq_storage = q_storage->dq_storage[q_storage->toggle];
 494                 q_storage->last_num_pkts = (nb_pkts > DPAA2_DQRR_RING_SIZE) ?
 495                                                DPAA2_DQRR_RING_SIZE : nb_pkts;
 496                 qbman_pull_desc_clear(&pulldesc);
 497                 qbman_pull_desc_set_numframes(&pulldesc,
 498                                               q_storage->last_num_pkts);
 499                 qbman_pull_desc_set_fq(&pulldesc, fqid);
 500                 qbman_pull_desc_set_storage(&pulldesc, dq_storage,
 501                         (dma_addr_t)(DPAA2_VADDR_TO_IOVA(dq_storage)), 1);
 502                 if (check_swp_active_dqs(DPAA2_PER_LCORE_DPIO->index)) {
 503                         while (!qbman_check_command_complete(
 504                                get_swp_active_dqs(DPAA2_PER_LCORE_DPIO->index)))
 505                                 ;
 506                         clear_swp_active_dqs(DPAA2_PER_LCORE_DPIO->index);
 507                 }
 508                 while (1) {
 509                         if (qbman_swp_pull(swp, &pulldesc)) {
 510                                 PMD_RX_LOG(WARNING, "VDQ command is not issued."
 511                                            "QBMAN is busy\n");
 512                                 /* Portal was busy, try again */
 513                                 continue;
 514                         }
 515                         break;
 516                 }
 517                 q_storage->active_dqs = dq_storage;
 518                 q_storage->active_dpio_id = DPAA2_PER_LCORE_DPIO->index;
 519                 set_swp_active_dqs(DPAA2_PER_LCORE_DPIO->index, dq_storage);
 520         }
 521
 522         dq_storage = q_storage->active_dqs;
 523         rte_prefetch0((void *)(size_t)(dq_storage));
 524         rte_prefetch0((void *)(size_t)(dq_storage + 1));
 525
 526         /* Prepare next pull descriptor. This will give space for the
 527          * prefething done on DQRR entries
 528          */
 529         q_storage->toggle ^= 1;
 530         dq_storage1 = q_storage->dq_storage[q_storage->toggle];
 531         qbman_pull_desc_clear(&pulldesc);
 532         qbman_pull_desc_set_numframes(&pulldesc, DPAA2_DQRR_RING_SIZE);
 533         qbman_pull_desc_set_fq(&pulldesc, fqid);
 534         qbman_pull_desc_set_storage(&pulldesc, dq_storage1,
 535                 (dma_addr_t)(DPAA2_VADDR_TO_IOVA(dq_storage1)), 1);
 536
 537         /* Check if the previous issued command is completed.
 538          * Also seems like the SWP is shared between the Ethernet Driver
 539          * and the SEC driver.
 540          */
 541         while (!qbman_check_command_complete(dq_storage))
 542                 ;
 543         if (dq_storage == get_swp_active_dqs(q_storage->active_dpio_id))
 544                 clear_swp_active_dqs(q_storage->active_dpio_id);
 545
 546         pending = 1;
 547
 548         do {
 549                 /* Loop until the dq_storage is updated with
 550                  * new token by QBMAN
 551                  */
 552                 while (!qbman_check_new_result(dq_storage))
 553                         ;
 554                 rte_prefetch0((void *)((size_t)(dq_storage + 2)));
 555                 /* Check whether Last Pull command is Expired and
 556                  * setting Condition for Loop termination
 557                  */
 558                 if (qbman_result_DQ_is_pull_complete(dq_storage)) {
 559                         pending = 0;
 560                         /* Check for valid frame. */
 561                         status = qbman_result_DQ_flags(dq_storage);
 562                         if (unlikely((status & QBMAN_DQ_STAT_VALIDFRAME) == 0))
 563                                 continue;
 564                 }
 565                 fd = qbman_result_DQ_fd(dq_storage);
 566
 567                 next_fd = qbman_result_DQ_fd(dq_storage + 1);
 568                 /* Prefetch Annotation address for the parse results */
 569                 rte_prefetch0((void *)(size_t)(DPAA2_GET_FD_ADDR(next_fd)
 570                                 + DPAA2_FD_PTA_SIZE + 16));
 571
 572                 if (unlikely(DPAA2_FD_GET_FORMAT(fd) == qbman_fd_sg))
 573                         bufs[num_rx] = eth_sg_fd_to_mbuf(fd);
 574                 else
 575                         bufs[num_rx] = eth_fd_to_mbuf(fd);
 576                 bufs[num_rx]->port = dev->data->port_id;
 577
 578                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
 579                         rte_vlan_strip(bufs[num_rx]);
 580
 581                 dq_storage++;
 582                 num_rx++;
 583         } while (pending);
 584
 585         if (check_swp_active_dqs(DPAA2_PER_LCORE_DPIO->index)) {
 586                 while (!qbman_check_command_complete(
 587                        get_swp_active_dqs(DPAA2_PER_LCORE_DPIO->index)))
 588                         ;
 589                 clear_swp_active_dqs(DPAA2_PER_LCORE_DPIO->index);
 590         }
 591         /* issue a volatile dequeue command for next pull */
 592         while (1) {
 593                 if (qbman_swp_pull(swp, &pulldesc)) {
 594                         PMD_RX_LOG(WARNING, "VDQ command is not issued."
 595                                    "QBMAN is busy\n");
 596                         continue;
 597                 }
 598                 break;
 599         }
 600         q_storage->active_dqs = dq_storage1;
 601         q_storage->active_dpio_id = DPAA2_PER_LCORE_DPIO->index;
 602         set_swp_active_dqs(DPAA2_PER_LCORE_DPIO->index, dq_storage1);
 603
 604         dpaa2_q->rx_pkts += num_rx;
 605
 606         return num_rx;
 607 }
 608
 609 void __attribute__((hot))
 610 dpaa2_dev_process_parallel_event(struct qbman_swp *swp,
 611                                  const struct qbman_fd *fd,
 612                                  const struct qbman_result *dq,
 613                                  struct dpaa2_queue *rxq,
 614                                  struct rte_event *ev)
 615 {
 616         rte_prefetch0((void *)(size_t)(DPAA2_GET_FD_ADDR(fd) +
 617                 DPAA2_FD_PTA_SIZE + 16));
 618
 619         ev->flow_id = rxq->ev.flow_id;
 620         ev->sub_event_type = rxq->ev.sub_event_type;
 621         ev->event_type = RTE_EVENT_TYPE_ETHDEV;
 622         ev->op = RTE_EVENT_OP_NEW;
 623         ev->sched_type = rxq->ev.sched_type;
 624         ev->queue_id = rxq->ev.queue_id;
 625         ev->priority = rxq->ev.priority;
 626
 627         ev->mbuf = eth_fd_to_mbuf(fd);
 628
 629         qbman_swp_dqrr_consume(swp, dq);
 630 }
 631
 632 void __attribute__((hot))
 633 dpaa2_dev_process_atomic_event(struct qbman_swp *swp __attribute__((unused)),
 634                                const struct qbman_fd *fd,
 635                                const struct qbman_result *dq,
 636                                struct dpaa2_queue *rxq,
 637                                struct rte_event *ev)
 638 {
 639         uint8_t dqrr_index;
 640
 641         rte_prefetch0((void *)(size_t)(DPAA2_GET_FD_ADDR(fd) +
 642                 DPAA2_FD_PTA_SIZE + 16));
 643
 644         ev->flow_id = rxq->ev.flow_id;
 645         ev->sub_event_type = rxq->ev.sub_event_type;
 646         ev->event_type = RTE_EVENT_TYPE_ETHDEV;
 647         ev->op = RTE_EVENT_OP_NEW;
 648         ev->sched_type = rxq->ev.sched_type;
 649         ev->queue_id = rxq->ev.queue_id;
 650         ev->priority = rxq->ev.priority;
 651
 652         ev->mbuf = eth_fd_to_mbuf(fd);
 653
 654         dqrr_index = qbman_get_dqrr_idx(dq);
 655         ev->mbuf->seqn = dqrr_index + 1;
 656         DPAA2_PER_LCORE_DQRR_SIZE++;
 657         DPAA2_PER_LCORE_DQRR_HELD |= 1 << dqrr_index;
 658         DPAA2_PER_LCORE_DQRR_MBUF(dqrr_index) = ev->mbuf;
 659 }
 660
 661 /*
 662  * Callback to handle sending packets through WRIOP based interface
 663  */
 664 uint16_t
 665 dpaa2_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)
 666 {
 667         /* Function to transmit the frames to given device and VQ*/
 668         uint32_t loop, retry_count;
 669         int32_t ret;
 670         struct qbman_fd fd_arr[MAX_TX_RING_SLOTS];
 671         struct rte_mbuf *mi;
 672         uint32_t frames_to_send;
 673         struct rte_mempool *mp;
 674         struct qbman_eq_desc eqdesc;
 675         struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)queue;
 676         struct qbman_swp *swp;
 677         uint16_t num_tx = 0;
 678         uint16_t bpid;
 679         struct rte_eth_dev *dev = dpaa2_q->dev;
 680         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 681         uint32_t flags[MAX_TX_RING_SLOTS] = {0};
 682
 683         if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
 684                 ret = dpaa2_affine_qbman_swp();
 685                 if (ret) {
 686                         RTE_LOG(ERR, PMD, "Failure in affining portal\n");
 687                         return 0;
 688                 }
 689         }
 690         swp = DPAA2_PER_LCORE_PORTAL;
 691
 692         PMD_TX_LOG(DEBUG, "===> dev =%p, fqid =%d", dev, dpaa2_q->fqid);
 693
 694         /*Prepare enqueue descriptor*/
 695         qbman_eq_desc_clear(&eqdesc);
 696         qbman_eq_desc_set_no_orp(&eqdesc, DPAA2_EQ_RESP_ERR_FQ);
 697         qbman_eq_desc_set_response(&eqdesc, 0, 0);
 698         qbman_eq_desc_set_qd(&eqdesc, priv->qdid,
 699                              dpaa2_q->flow_id, dpaa2_q->tc_index);
 700         /*Clear the unused FD fields before sending*/
 701         while (nb_pkts) {
 702                 /*Check if the queue is congested*/
 703                 retry_count = 0;
 704                 while (qbman_result_SCN_state(dpaa2_q->cscn)) {
 705                         retry_count++;
 706                         /* Retry for some time before giving up */
 707                         if (retry_count > CONG_RETRY_COUNT)
 708                                 goto skip_tx;
 709                 }
 710
 711                 frames_to_send = (nb_pkts >> 3) ? MAX_TX_RING_SLOTS : nb_pkts;
 712
 713                 for (loop = 0; loop < frames_to_send; loop++) {
 714                         if ((*bufs)->seqn) {
 715                                 uint8_t dqrr_index = (*bufs)->seqn - 1;
 716
 717                                 flags[loop] = QBMAN_ENQUEUE_FLAG_DCA |
 718                                                 dqrr_index;
 719                                 DPAA2_PER_LCORE_DQRR_SIZE--;
 720                                 DPAA2_PER_LCORE_DQRR_HELD &= ~(1 << dqrr_index);
 721                                 (*bufs)->seqn = DPAA2_INVALID_MBUF_SEQN;
 722                         }
 723
 724                         fd_arr[loop].simple.frc = 0;
 725                         DPAA2_RESET_FD_CTRL((&fd_arr[loop]));
 726                         DPAA2_SET_FD_FLC((&fd_arr[loop]), (size_t)NULL);
 727                         if (likely(RTE_MBUF_DIRECT(*bufs))) {
 728                                 mp = (*bufs)->pool;
 729                                 /* Check the basic scenario and set
 730                                  * the FD appropriately here itself.
 731                                  */
 732                                 if (likely(mp && mp->ops_index ==
 733                                     priv->bp_list->dpaa2_ops_index &&
 734                                     (*bufs)->nb_segs == 1 &&
 735                                     rte_mbuf_refcnt_read((*bufs)) == 1)) {
 736                                         if (unlikely((*bufs)->ol_flags
 737                                                 & PKT_TX_VLAN_PKT)) {
 738                                                 ret = rte_vlan_insert(bufs);
 739                                                 if (ret)
 740                                                         goto send_n_return;
 741                                         }
 742                                         DPAA2_MBUF_TO_CONTIG_FD((*bufs),
 743                                         &fd_arr[loop], mempool_to_bpid(mp));
 744                                         bufs++;
 745                                         continue;
 746                                 }
 747                         } else {
 748                                 mi = rte_mbuf_from_indirect(*bufs);
 749                                 mp = mi->pool;
 750                         }
 751                         /* Not a hw_pkt pool allocated frame */
 752                         if (unlikely(!mp || !priv->bp_list)) {
 753                                 PMD_TX_LOG(ERR, "err: no bpool attached");
 754                                 goto send_n_return;
 755                         }
 756
 757                         if (mp->ops_index != priv->bp_list->dpaa2_ops_index) {
 758                                 PMD_TX_LOG(ERR, "non hw offload bufffer ");
 759                                 /* alloc should be from the default buffer pool
 760                                  * attached to this interface
 761                                  */
 762                                 bpid = priv->bp_list->buf_pool.bpid;
 763
 764                                 if (unlikely((*bufs)->nb_segs > 1)) {
 765                                         PMD_TX_LOG(ERR, "S/G support not added"
 766                                                 " for non hw offload buffer");
 767                                         goto send_n_return;
 768                                 }
 769                                 if (eth_copy_mbuf_to_fd(*bufs,
 770                                                         &fd_arr[loop], bpid)) {
 771                                         goto send_n_return;
 772                                 }
 773                                 /* free the original packet */
 774                                 rte_pktmbuf_free(*bufs);
 775                         } else {
 776                                 bpid = mempool_to_bpid(mp);
 777                                 if (unlikely((*bufs)->nb_segs > 1)) {
 778                                         if (eth_mbuf_to_sg_fd(*bufs,
 779                                                         &fd_arr[loop], bpid))
 780                                                 goto send_n_return;
 781                                 } else {
 782                                         eth_mbuf_to_fd(*bufs,
 783                                                        &fd_arr[loop], bpid);
 784                                 }
 785                         }
 786                         bufs++;
 787                 }
 788                 loop = 0;
 789                 while (loop < frames_to_send) {
 790                         loop += qbman_swp_enqueue_multiple(swp, &eqdesc,
 791                                         &fd_arr[loop], &flags[loop],
 792                                         frames_to_send - loop);
 793                 }
 794
 795                 num_tx += frames_to_send;
 796                 nb_pkts -= frames_to_send;
 797         }
 798         dpaa2_q->tx_pkts += num_tx;
 799         return num_tx;
 800
 801 send_n_return:
 802         /* send any already prepared fd */
 803         if (loop) {
 804                 unsigned int i = 0;
 805
 806                 while (i < loop) {
 807                         i += qbman_swp_enqueue_multiple(swp, &eqdesc,
 808                                                         &fd_arr[i],
 809                                                         &flags[loop],
 810                                                         loop - i);
 811                 }
 812                 num_tx += loop;
 813         }
 814 skip_tx:
 815         dpaa2_q->tx_pkts += num_tx;
 816         return num_tx;
 817 }
 818
 819 /**
 820  * Dummy DPDK callback for TX.
 821  *
 822  * This function is used to temporarily replace the real callback during
 823  * unsafe control operations on the queue, or in case of error.
 824  *
 825  * @param dpdk_txq
 826  *   Generic pointer to TX queue structure.
 827  * @param[in] pkts
 828  *   Packets to transmit.
 829  * @param pkts_n
 830  *   Number of packets in array.
 831  *
 832  * @return
 833  *   Number of packets successfully transmitted (<= pkts_n).
 834  */
 835 uint16_t
 836 dummy_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)
 837 {
 838         (void)queue;
 839         (void)bufs;
 840         (void)nb_pkts;
 841         return 0;
 842 }