drivers/net/dpaa2/dpaa2_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  *   Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
   4  *   Copyright 2016-2018 NXP
   5  *
   6  */
   7
   8 #include <time.h>
   9 #include <net/if.h>
  10
  11 #include <rte_mbuf.h>
  12 #include <rte_ethdev_driver.h>
  13 #include <rte_malloc.h>
  14 #include <rte_memcpy.h>
  15 #include <rte_string_fns.h>
  16 #include <rte_dev.h>
  17
  18 #include <rte_fslmc.h>
  19 #include <fslmc_vfio.h>
  20 #include <dpaa2_hw_pvt.h>
  21 #include <dpaa2_hw_dpio.h>
  22 #include <dpaa2_hw_mempool.h>
  23
  24 #include "dpaa2_pmd_logs.h"
  25 #include "dpaa2_ethdev.h"
  26 #include "base/dpaa2_hw_dpni_annot.h"
  27
  28 #define DPAA2_MBUF_TO_CONTIG_FD(_mbuf, _fd, _bpid)  do { \
  29         DPAA2_SET_FD_ADDR(_fd, DPAA2_MBUF_VADDR_TO_IOVA(_mbuf)); \
  30         DPAA2_SET_FD_LEN(_fd, _mbuf->data_len); \
  31         DPAA2_SET_ONLY_FD_BPID(_fd, _bpid); \
  32         DPAA2_SET_FD_OFFSET(_fd, _mbuf->data_off); \
  33         DPAA2_SET_FD_ASAL(_fd, DPAA2_ASAL_VAL); \
  34 } while (0)
  35
  36 static inline void __attribute__((hot))
  37 dpaa2_dev_rx_parse_new(struct rte_mbuf *m, const struct qbman_fd *fd)
  38 {
  39         uint16_t frc = DPAA2_GET_FD_FRC_PARSE_SUM(fd);
  40
  41         DPAA2_PMD_DP_DEBUG("frc = 0x%x\t", frc);
  42
  43         m->packet_type = RTE_PTYPE_UNKNOWN;
  44         switch (frc) {
  45         case DPAA2_PKT_TYPE_ETHER:
  46                 m->packet_type = RTE_PTYPE_L2_ETHER;
  47                 break;
  48         case DPAA2_PKT_TYPE_IPV4:
  49                 m->packet_type = RTE_PTYPE_L2_ETHER |
  50                         RTE_PTYPE_L3_IPV4;
  51                 break;
  52         case DPAA2_PKT_TYPE_IPV6:
  53                 m->packet_type = RTE_PTYPE_L2_ETHER |
  54                         RTE_PTYPE_L3_IPV6;
  55                 break;
  56         case DPAA2_PKT_TYPE_IPV4_EXT:
  57                 m->packet_type = RTE_PTYPE_L2_ETHER |
  58                         RTE_PTYPE_L3_IPV4_EXT;
  59                 break;
  60         case DPAA2_PKT_TYPE_IPV6_EXT:
  61                 m->packet_type = RTE_PTYPE_L2_ETHER |
  62                         RTE_PTYPE_L3_IPV6_EXT;
  63                 break;
  64         case DPAA2_PKT_TYPE_IPV4_TCP:
  65                 m->packet_type = RTE_PTYPE_L2_ETHER |
  66                         RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_TCP;
  67                 break;
  68         case DPAA2_PKT_TYPE_IPV6_TCP:
  69                 m->packet_type = RTE_PTYPE_L2_ETHER |
  70                         RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_TCP;
  71                 break;
  72         case DPAA2_PKT_TYPE_IPV4_UDP:
  73                 m->packet_type = RTE_PTYPE_L2_ETHER |
  74                         RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_UDP;
  75                 break;
  76         case DPAA2_PKT_TYPE_IPV6_UDP:
  77                 m->packet_type = RTE_PTYPE_L2_ETHER |
  78                         RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_UDP;
  79                 break;
  80         case DPAA2_PKT_TYPE_IPV4_SCTP:
  81                 m->packet_type = RTE_PTYPE_L2_ETHER |
  82                         RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_SCTP;
  83                 break;
  84         case DPAA2_PKT_TYPE_IPV6_SCTP:
  85                 m->packet_type = RTE_PTYPE_L2_ETHER |
  86                         RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_SCTP;
  87                 break;
  88         case DPAA2_PKT_TYPE_IPV4_ICMP:
  89                 m->packet_type = RTE_PTYPE_L2_ETHER |
  90                         RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_ICMP;
  91                 break;
  92         case DPAA2_PKT_TYPE_IPV6_ICMP:
  93                 m->packet_type = RTE_PTYPE_L2_ETHER |
  94                         RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_ICMP;
  95                 break;
  96         case DPAA2_PKT_TYPE_VLAN_1:
  97         case DPAA2_PKT_TYPE_VLAN_2:
  98                 m->ol_flags |= PKT_RX_VLAN;
  99                 break;
 100         /* More switch cases can be added */
 101         /* TODO: Add handling for checksum error check from FRC */
 102         default:
 103                 m->packet_type = RTE_PTYPE_UNKNOWN;
 104         }
 105         m->hash.rss = fd->simple.flc_hi;
 106         m->ol_flags |= PKT_RX_RSS_HASH;
 107 }
 108
 109 static inline uint32_t __attribute__((hot))
 110 dpaa2_dev_rx_parse_slow(struct dpaa2_annot_hdr *annotation)
 111 {
 112         uint32_t pkt_type = RTE_PTYPE_UNKNOWN;
 113
 114         DPAA2_PMD_DP_DEBUG("(slow parse) Annotation = 0x%" PRIx64 "\t",
 115                            annotation->word4);
 116         if (BIT_ISSET_AT_POS(annotation->word3, L2_ARP_PRESENT)) {
 117                 pkt_type = RTE_PTYPE_L2_ETHER_ARP;
 118                 goto parse_done;
 119         } else if (BIT_ISSET_AT_POS(annotation->word3, L2_ETH_MAC_PRESENT)) {
 120                 pkt_type = RTE_PTYPE_L2_ETHER;
 121         } else {
 122                 goto parse_done;
 123         }
 124
 125         if (BIT_ISSET_AT_POS(annotation->word4, L3_IPV4_1_PRESENT |
 126                              L3_IPV4_N_PRESENT)) {
 127                 pkt_type |= RTE_PTYPE_L3_IPV4;
 128                 if (BIT_ISSET_AT_POS(annotation->word4, L3_IP_1_OPT_PRESENT |
 129                         L3_IP_N_OPT_PRESENT))
 130                         pkt_type |= RTE_PTYPE_L3_IPV4_EXT;
 131
 132         } else if (BIT_ISSET_AT_POS(annotation->word4, L3_IPV6_1_PRESENT |
 133                   L3_IPV6_N_PRESENT)) {
 134                 pkt_type |= RTE_PTYPE_L3_IPV6;
 135                 if (BIT_ISSET_AT_POS(annotation->word4, L3_IP_1_OPT_PRESENT |
 136                     L3_IP_N_OPT_PRESENT))
 137                         pkt_type |= RTE_PTYPE_L3_IPV6_EXT;
 138         } else {
 139                 goto parse_done;
 140         }
 141
 142         if (BIT_ISSET_AT_POS(annotation->word4, L3_IP_1_FIRST_FRAGMENT |
 143             L3_IP_1_MORE_FRAGMENT |
 144             L3_IP_N_FIRST_FRAGMENT |
 145             L3_IP_N_MORE_FRAGMENT)) {
 146                 pkt_type |= RTE_PTYPE_L4_FRAG;
 147                 goto parse_done;
 148         } else {
 149                 pkt_type |= RTE_PTYPE_L4_NONFRAG;
 150         }
 151
 152         if (BIT_ISSET_AT_POS(annotation->word4, L3_PROTO_UDP_PRESENT))
 153                 pkt_type |= RTE_PTYPE_L4_UDP;
 154
 155         else if (BIT_ISSET_AT_POS(annotation->word4, L3_PROTO_TCP_PRESENT))
 156                 pkt_type |= RTE_PTYPE_L4_TCP;
 157
 158         else if (BIT_ISSET_AT_POS(annotation->word4, L3_PROTO_SCTP_PRESENT))
 159                 pkt_type |= RTE_PTYPE_L4_SCTP;
 160
 161         else if (BIT_ISSET_AT_POS(annotation->word4, L3_PROTO_ICMP_PRESENT))
 162                 pkt_type |= RTE_PTYPE_L4_ICMP;
 163
 164         else if (BIT_ISSET_AT_POS(annotation->word4, L3_IP_UNKNOWN_PROTOCOL))
 165                 pkt_type |= RTE_PTYPE_UNKNOWN;
 166
 167 parse_done:
 168         return pkt_type;
 169 }
 170
 171 static inline uint32_t __attribute__((hot))
 172 dpaa2_dev_rx_parse(struct rte_mbuf *mbuf, void *hw_annot_addr)
 173 {
 174         struct dpaa2_annot_hdr *annotation =
 175                         (struct dpaa2_annot_hdr *)hw_annot_addr;
 176
 177         DPAA2_PMD_DP_DEBUG("(fast parse) Annotation = 0x%" PRIx64 "\t",
 178                            annotation->word4);
 179
 180         /* Check offloads first */
 181         if (BIT_ISSET_AT_POS(annotation->word3,
 182                              L2_VLAN_1_PRESENT | L2_VLAN_N_PRESENT))
 183                 mbuf->ol_flags |= PKT_RX_VLAN;
 184
 185         if (BIT_ISSET_AT_POS(annotation->word8, DPAA2_ETH_FAS_L3CE))
 186                 mbuf->ol_flags |= PKT_RX_IP_CKSUM_BAD;
 187         else if (BIT_ISSET_AT_POS(annotation->word8, DPAA2_ETH_FAS_L4CE))
 188                 mbuf->ol_flags |= PKT_RX_L4_CKSUM_BAD;
 189
 190         /* Return some common types from parse processing */
 191         switch (annotation->word4) {
 192         case DPAA2_L3_IPv4:
 193                 return RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4;
 194         case DPAA2_L3_IPv6:
 195                 return  RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6;
 196         case DPAA2_L3_IPv4_TCP:
 197                 return  RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4 |
 198                                 RTE_PTYPE_L4_TCP;
 199         case DPAA2_L3_IPv4_UDP:
 200                 return  RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4 |
 201                                 RTE_PTYPE_L4_UDP;
 202         case DPAA2_L3_IPv6_TCP:
 203                 return  RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6 |
 204                                 RTE_PTYPE_L4_TCP;
 205         case DPAA2_L3_IPv6_UDP:
 206                 return  RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6 |
 207                                 RTE_PTYPE_L4_UDP;
 208         default:
 209                 break;
 210         }
 211
 212         return dpaa2_dev_rx_parse_slow(annotation);
 213 }
 214
 215 static inline struct rte_mbuf *__attribute__((hot))
 216 eth_sg_fd_to_mbuf(const struct qbman_fd *fd)
 217 {
 218         struct qbman_sge *sgt, *sge;
 219         size_t sg_addr, fd_addr;
 220         int i = 0;
 221         struct rte_mbuf *first_seg, *next_seg, *cur_seg, *temp;
 222
 223         fd_addr = (size_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd));
 224
 225         /* Get Scatter gather table address */
 226         sgt = (struct qbman_sge *)(fd_addr + DPAA2_GET_FD_OFFSET(fd));
 227
 228         sge = &sgt[i++];
 229         sg_addr = (size_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FLE_ADDR(sge));
 230
 231         /* First Scatter gather entry */
 232         first_seg = DPAA2_INLINE_MBUF_FROM_BUF(sg_addr,
 233                 rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size);
 234         /* Prepare all the metadata for first segment */
 235         first_seg->buf_addr = (uint8_t *)sg_addr;
 236         first_seg->ol_flags = 0;
 237         first_seg->data_off = DPAA2_GET_FLE_OFFSET(sge);
 238         first_seg->data_len = sge->length  & 0x1FFFF;
 239         first_seg->pkt_len = DPAA2_GET_FD_LEN(fd);
 240         first_seg->nb_segs = 1;
 241         first_seg->next = NULL;
 242         if (dpaa2_svr_family == SVR_LX2160A)
 243                 dpaa2_dev_rx_parse_new(first_seg, fd);
 244         else
 245                 first_seg->packet_type = dpaa2_dev_rx_parse(first_seg,
 246                         (void *)((size_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd))
 247                          + DPAA2_FD_PTA_SIZE));
 248
 249         rte_mbuf_refcnt_set(first_seg, 1);
 250         cur_seg = first_seg;
 251         while (!DPAA2_SG_IS_FINAL(sge)) {
 252                 sge = &sgt[i++];
 253                 sg_addr = (size_t)DPAA2_IOVA_TO_VADDR(
 254                                 DPAA2_GET_FLE_ADDR(sge));
 255                 next_seg = DPAA2_INLINE_MBUF_FROM_BUF(sg_addr,
 256                         rte_dpaa2_bpid_info[DPAA2_GET_FLE_BPID(sge)].meta_data_size);
 257                 next_seg->buf_addr  = (uint8_t *)sg_addr;
 258                 next_seg->data_off  = DPAA2_GET_FLE_OFFSET(sge);
 259                 next_seg->data_len  = sge->length  & 0x1FFFF;
 260                 first_seg->nb_segs += 1;
 261                 rte_mbuf_refcnt_set(next_seg, 1);
 262                 cur_seg->next = next_seg;
 263                 next_seg->next = NULL;
 264                 cur_seg = next_seg;
 265         }
 266         temp = DPAA2_INLINE_MBUF_FROM_BUF(fd_addr,
 267                 rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size);
 268         rte_mbuf_refcnt_set(temp, 1);
 269         rte_pktmbuf_free_seg(temp);
 270
 271         return (void *)first_seg;
 272 }
 273
 274 static inline struct rte_mbuf *__attribute__((hot))
 275 eth_fd_to_mbuf(const struct qbman_fd *fd)
 276 {
 277         struct rte_mbuf *mbuf = DPAA2_INLINE_MBUF_FROM_BUF(
 278                 DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd)),
 279                      rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size);
 280
 281         /* need to repopulated some of the fields,
 282          * as they may have changed in last transmission
 283          */
 284         mbuf->nb_segs = 1;
 285         mbuf->ol_flags = 0;
 286         mbuf->data_off = DPAA2_GET_FD_OFFSET(fd);
 287         mbuf->data_len = DPAA2_GET_FD_LEN(fd);
 288         mbuf->pkt_len = mbuf->data_len;
 289         mbuf->next = NULL;
 290         rte_mbuf_refcnt_set(mbuf, 1);
 291
 292         /* Parse the packet */
 293         /* parse results for LX2 are there in FRC field of FD.
 294          * For other DPAA2 platforms , parse results are after
 295          * the private - sw annotation area
 296          */
 297
 298         if (dpaa2_svr_family == SVR_LX2160A)
 299                 dpaa2_dev_rx_parse_new(mbuf, fd);
 300         else
 301                 mbuf->packet_type = dpaa2_dev_rx_parse(mbuf,
 302                         (void *)((size_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd))
 303                          + DPAA2_FD_PTA_SIZE));
 304
 305         DPAA2_PMD_DP_DEBUG("to mbuf - mbuf =%p, mbuf->buf_addr =%p, off = %d,"
 306                 "fd_off=%d fd =%" PRIx64 ", meta = %d  bpid =%d, len=%d\n",
 307                 mbuf, mbuf->buf_addr, mbuf->data_off,
 308                 DPAA2_GET_FD_OFFSET(fd), DPAA2_GET_FD_ADDR(fd),
 309                 rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size,
 310                 DPAA2_GET_FD_BPID(fd), DPAA2_GET_FD_LEN(fd));
 311
 312         return mbuf;
 313 }
 314
 315 static int __attribute__ ((noinline)) __attribute__((hot))
 316 eth_mbuf_to_sg_fd(struct rte_mbuf *mbuf,
 317                   struct qbman_fd *fd, uint16_t bpid)
 318 {
 319         struct rte_mbuf *cur_seg = mbuf, *prev_seg, *mi, *temp;
 320         struct qbman_sge *sgt, *sge = NULL;
 321         int i;
 322
 323         temp = rte_pktmbuf_alloc(mbuf->pool);
 324         if (temp == NULL) {
 325                 DPAA2_PMD_DP_DEBUG("No memory to allocate S/G table\n");
 326                 return -ENOMEM;
 327         }
 328
 329         DPAA2_SET_FD_ADDR(fd, DPAA2_MBUF_VADDR_TO_IOVA(temp));
 330         DPAA2_SET_FD_LEN(fd, mbuf->pkt_len);
 331         DPAA2_SET_ONLY_FD_BPID(fd, bpid);
 332         DPAA2_SET_FD_OFFSET(fd, temp->data_off);
 333         DPAA2_SET_FD_ASAL(fd, DPAA2_ASAL_VAL);
 334         DPAA2_FD_SET_FORMAT(fd, qbman_fd_sg);
 335         /*Set Scatter gather table and Scatter gather entries*/
 336         sgt = (struct qbman_sge *)(
 337                         (size_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd))
 338                         + DPAA2_GET_FD_OFFSET(fd));
 339
 340         for (i = 0; i < mbuf->nb_segs; i++) {
 341                 sge = &sgt[i];
 342                 /*Resetting the buffer pool id and offset field*/
 343                 sge->fin_bpid_offset = 0;
 344                 DPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(cur_seg));
 345                 DPAA2_SET_FLE_OFFSET(sge, cur_seg->data_off);
 346                 sge->length = cur_seg->data_len;
 347                 if (RTE_MBUF_DIRECT(cur_seg)) {
 348                         if (rte_mbuf_refcnt_read(cur_seg) > 1) {
 349                                 /* If refcnt > 1, invalid bpid is set to ensure
 350                                  * buffer is not freed by HW
 351                                  */
 352                                 DPAA2_SET_FLE_IVP(sge);
 353                                 rte_mbuf_refcnt_update(cur_seg, -1);
 354                         } else
 355                                 DPAA2_SET_FLE_BPID(sge,
 356                                                 mempool_to_bpid(cur_seg->pool));
 357                         cur_seg = cur_seg->next;
 358                 } else {
 359                         /* Get owner MBUF from indirect buffer */
 360                         mi = rte_mbuf_from_indirect(cur_seg);
 361                         if (rte_mbuf_refcnt_read(mi) > 1) {
 362                                 /* If refcnt > 1, invalid bpid is set to ensure
 363                                  * owner buffer is not freed by HW
 364                                  */
 365                                 DPAA2_SET_FLE_IVP(sge);
 366                         } else {
 367                                 DPAA2_SET_FLE_BPID(sge,
 368                                                    mempool_to_bpid(mi->pool));
 369                                 rte_mbuf_refcnt_update(mi, 1);
 370                         }
 371                         prev_seg = cur_seg;
 372                         cur_seg = cur_seg->next;
 373                         prev_seg->next = NULL;
 374                         rte_pktmbuf_free(prev_seg);
 375                 }
 376         }
 377         DPAA2_SG_SET_FINAL(sge, true);
 378         return 0;
 379 }
 380
 381 static void
 382 eth_mbuf_to_fd(struct rte_mbuf *mbuf,
 383                struct qbman_fd *fd, uint16_t bpid) __attribute__((unused));
 384
 385 static void __attribute__ ((noinline)) __attribute__((hot))
 386 eth_mbuf_to_fd(struct rte_mbuf *mbuf,
 387                struct qbman_fd *fd, uint16_t bpid)
 388 {
 389         DPAA2_MBUF_TO_CONTIG_FD(mbuf, fd, bpid);
 390
 391         DPAA2_PMD_DP_DEBUG("mbuf =%p, mbuf->buf_addr =%p, off = %d,"
 392                 "fd_off=%d fd =%" PRIx64 ", meta = %d  bpid =%d, len=%d\n",
 393                 mbuf, mbuf->buf_addr, mbuf->data_off,
 394                 DPAA2_GET_FD_OFFSET(fd), DPAA2_GET_FD_ADDR(fd),
 395                 rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size,
 396                 DPAA2_GET_FD_BPID(fd), DPAA2_GET_FD_LEN(fd));
 397         if (RTE_MBUF_DIRECT(mbuf)) {
 398                 if (rte_mbuf_refcnt_read(mbuf) > 1) {
 399                         DPAA2_SET_FD_IVP(fd);
 400                         rte_mbuf_refcnt_update(mbuf, -1);
 401                 }
 402         } else {
 403                 struct rte_mbuf *mi;
 404
 405                 mi = rte_mbuf_from_indirect(mbuf);
 406                 if (rte_mbuf_refcnt_read(mi) > 1)
 407                         DPAA2_SET_FD_IVP(fd);
 408                 else
 409                         rte_mbuf_refcnt_update(mi, 1);
 410                 rte_pktmbuf_free(mbuf);
 411         }
 412 }
 413
 414 static inline int __attribute__((hot))
 415 eth_copy_mbuf_to_fd(struct rte_mbuf *mbuf,
 416                     struct qbman_fd *fd, uint16_t bpid)
 417 {
 418         struct rte_mbuf *m;
 419         void *mb = NULL;
 420
 421         if (rte_dpaa2_mbuf_alloc_bulk(
 422                 rte_dpaa2_bpid_info[bpid].bp_list->mp, &mb, 1)) {
 423                 DPAA2_PMD_DP_DEBUG("Unable to allocated DPAA2 buffer\n");
 424                 return -1;
 425         }
 426         m = (struct rte_mbuf *)mb;
 427         memcpy((char *)m->buf_addr + mbuf->data_off,
 428                (void *)((char *)mbuf->buf_addr + mbuf->data_off),
 429                 mbuf->pkt_len);
 430
 431         /* Copy required fields */
 432         m->data_off = mbuf->data_off;
 433         m->ol_flags = mbuf->ol_flags;
 434         m->packet_type = mbuf->packet_type;
 435         m->tx_offload = mbuf->tx_offload;
 436
 437         DPAA2_MBUF_TO_CONTIG_FD(m, fd, bpid);
 438
 439         DPAA2_PMD_DP_DEBUG(
 440                 "mbuf: %p, BMAN buf addr: %p, fdaddr: %" PRIx64 ", bpid: %d,"
 441                 " meta: %d, off: %d, len: %d\n",
 442                 (void *)mbuf,
 443                 mbuf->buf_addr,
 444                 DPAA2_GET_FD_ADDR(fd),
 445                 DPAA2_GET_FD_BPID(fd),
 446                 rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size,
 447                 DPAA2_GET_FD_OFFSET(fd),
 448                 DPAA2_GET_FD_LEN(fd));
 449
 450 return 0;
 451 }
 452
 453 /* This function assumes that caller will be keep the same value for nb_pkts
 454  * across calls per queue, if that is not the case, better use non-prefetch
 455  * version of rx call.
 456  * It will return the packets as requested in previous call without honoring
 457  * the current nb_pkts or bufs space.
 458  */
 459 uint16_t
 460 dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)
 461 {
 462         /* Function receive frames for a given device and VQ*/
 463         struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)queue;
 464         struct qbman_result *dq_storage, *dq_storage1 = NULL;
 465         uint32_t fqid = dpaa2_q->fqid;
 466         int ret, num_rx = 0, pull_size;
 467         uint8_t pending, status;
 468         struct qbman_swp *swp;
 469         const struct qbman_fd *fd, *next_fd;
 470         struct qbman_pull_desc pulldesc;
 471         struct queue_storage_info_t *q_storage = dpaa2_q->q_storage;
 472         struct rte_eth_dev *dev = dpaa2_q->dev;
 473
 474         if (unlikely(!DPAA2_PER_LCORE_ETHRX_DPIO)) {
 475                 ret = dpaa2_affine_qbman_ethrx_swp();
 476                 if (ret) {
 477                         DPAA2_PMD_ERR("Failure in affining portal");
 478                         return 0;
 479                 }
 480         }
 481         swp = DPAA2_PER_LCORE_ETHRX_PORTAL;
 482         pull_size = (nb_pkts > dpaa2_dqrr_size) ? dpaa2_dqrr_size : nb_pkts;
 483         if (unlikely(!q_storage->active_dqs)) {
 484                 q_storage->toggle = 0;
 485                 dq_storage = q_storage->dq_storage[q_storage->toggle];
 486                 q_storage->last_num_pkts = pull_size;
 487                 qbman_pull_desc_clear(&pulldesc);
 488                 qbman_pull_desc_set_numframes(&pulldesc,
 489                                               q_storage->last_num_pkts);
 490                 qbman_pull_desc_set_fq(&pulldesc, fqid);
 491                 qbman_pull_desc_set_storage(&pulldesc, dq_storage,
 492                         (uint64_t)(DPAA2_VADDR_TO_IOVA(dq_storage)), 1);
 493                 if (check_swp_active_dqs(DPAA2_PER_LCORE_ETHRX_DPIO->index)) {
 494                         while (!qbman_check_command_complete(
 495                                get_swp_active_dqs(
 496                                DPAA2_PER_LCORE_ETHRX_DPIO->index)))
 497                                 ;
 498                         clear_swp_active_dqs(DPAA2_PER_LCORE_ETHRX_DPIO->index);
 499                 }
 500                 while (1) {
 501                         if (qbman_swp_pull(swp, &pulldesc)) {
 502                                 DPAA2_PMD_DP_DEBUG("VDQ command is not issued."
 503                                                   " QBMAN is busy (1)\n");
 504                                 /* Portal was busy, try again */
 505                                 continue;
 506                         }
 507                         break;
 508                 }
 509                 q_storage->active_dqs = dq_storage;
 510                 q_storage->active_dpio_id = DPAA2_PER_LCORE_ETHRX_DPIO->index;
 511                 set_swp_active_dqs(DPAA2_PER_LCORE_ETHRX_DPIO->index,
 512                                    dq_storage);
 513         }
 514
 515         dq_storage = q_storage->active_dqs;
 516         rte_prefetch0((void *)(size_t)(dq_storage));
 517         rte_prefetch0((void *)(size_t)(dq_storage + 1));
 518
 519         /* Prepare next pull descriptor. This will give space for the
 520          * prefething done on DQRR entries
 521          */
 522         q_storage->toggle ^= 1;
 523         dq_storage1 = q_storage->dq_storage[q_storage->toggle];
 524         qbman_pull_desc_clear(&pulldesc);
 525         qbman_pull_desc_set_numframes(&pulldesc, pull_size);
 526         qbman_pull_desc_set_fq(&pulldesc, fqid);
 527         qbman_pull_desc_set_storage(&pulldesc, dq_storage1,
 528                 (uint64_t)(DPAA2_VADDR_TO_IOVA(dq_storage1)), 1);
 529
 530         /* Check if the previous issued command is completed.
 531          * Also seems like the SWP is shared between the Ethernet Driver
 532          * and the SEC driver.
 533          */
 534         while (!qbman_check_command_complete(dq_storage))
 535                 ;
 536         if (dq_storage == get_swp_active_dqs(q_storage->active_dpio_id))
 537                 clear_swp_active_dqs(q_storage->active_dpio_id);
 538
 539         pending = 1;
 540
 541         do {
 542                 /* Loop until the dq_storage is updated with
 543                  * new token by QBMAN
 544                  */
 545                 while (!qbman_check_new_result(dq_storage))
 546                         ;
 547                 rte_prefetch0((void *)((size_t)(dq_storage + 2)));
 548                 /* Check whether Last Pull command is Expired and
 549                  * setting Condition for Loop termination
 550                  */
 551                 if (qbman_result_DQ_is_pull_complete(dq_storage)) {
 552                         pending = 0;
 553                         /* Check for valid frame. */
 554                         status = qbman_result_DQ_flags(dq_storage);
 555                         if (unlikely((status & QBMAN_DQ_STAT_VALIDFRAME) == 0))
 556                                 continue;
 557                 }
 558                 fd = qbman_result_DQ_fd(dq_storage);
 559
 560                 if (dpaa2_svr_family != SVR_LX2160A) {
 561                         next_fd = qbman_result_DQ_fd(dq_storage + 1);
 562                         /* Prefetch Annotation address for the parse results */
 563                         rte_prefetch0((void *)(size_t)(DPAA2_GET_FD_ADDR(
 564                                       next_fd) + DPAA2_FD_PTA_SIZE + 16));
 565                 }
 566
 567                 if (unlikely(DPAA2_FD_GET_FORMAT(fd) == qbman_fd_sg))
 568                         bufs[num_rx] = eth_sg_fd_to_mbuf(fd);
 569                 else
 570                         bufs[num_rx] = eth_fd_to_mbuf(fd);
 571                 bufs[num_rx]->port = dev->data->port_id;
 572
 573                 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 574                         rte_vlan_strip(bufs[num_rx]);
 575
 576                 dq_storage++;
 577                 num_rx++;
 578         } while (pending);
 579
 580         if (check_swp_active_dqs(DPAA2_PER_LCORE_ETHRX_DPIO->index)) {
 581                 while (!qbman_check_command_complete(
 582                        get_swp_active_dqs(DPAA2_PER_LCORE_ETHRX_DPIO->index)))
 583                         ;
 584                 clear_swp_active_dqs(DPAA2_PER_LCORE_ETHRX_DPIO->index);
 585         }
 586         /* issue a volatile dequeue command for next pull */
 587         while (1) {
 588                 if (qbman_swp_pull(swp, &pulldesc)) {
 589                         DPAA2_PMD_DP_DEBUG("VDQ command is not issued."
 590                                           "QBMAN is busy (2)\n");
 591                         continue;
 592                 }
 593                 break;
 594         }
 595         q_storage->active_dqs = dq_storage1;
 596         q_storage->active_dpio_id = DPAA2_PER_LCORE_ETHRX_DPIO->index;
 597         set_swp_active_dqs(DPAA2_PER_LCORE_ETHRX_DPIO->index, dq_storage1);
 598
 599         dpaa2_q->rx_pkts += num_rx;
 600
 601         return num_rx;
 602 }
 603
 604 void __attribute__((hot))
 605 dpaa2_dev_process_parallel_event(struct qbman_swp *swp,
 606                                  const struct qbman_fd *fd,
 607                                  const struct qbman_result *dq,
 608                                  struct dpaa2_queue *rxq,
 609                                  struct rte_event *ev)
 610 {
 611         rte_prefetch0((void *)(size_t)(DPAA2_GET_FD_ADDR(fd) +
 612                 DPAA2_FD_PTA_SIZE + 16));
 613
 614         ev->flow_id = rxq->ev.flow_id;
 615         ev->sub_event_type = rxq->ev.sub_event_type;
 616         ev->event_type = RTE_EVENT_TYPE_ETHDEV;
 617         ev->op = RTE_EVENT_OP_NEW;
 618         ev->sched_type = rxq->ev.sched_type;
 619         ev->queue_id = rxq->ev.queue_id;
 620         ev->priority = rxq->ev.priority;
 621
 622         ev->mbuf = eth_fd_to_mbuf(fd);
 623
 624         qbman_swp_dqrr_consume(swp, dq);
 625 }
 626
 627 void __attribute__((hot))
 628 dpaa2_dev_process_atomic_event(struct qbman_swp *swp __attribute__((unused)),
 629                                const struct qbman_fd *fd,
 630                                const struct qbman_result *dq,
 631                                struct dpaa2_queue *rxq,
 632                                struct rte_event *ev)
 633 {
 634         uint8_t dqrr_index;
 635
 636         rte_prefetch0((void *)(size_t)(DPAA2_GET_FD_ADDR(fd) +
 637                 DPAA2_FD_PTA_SIZE + 16));
 638
 639         ev->flow_id = rxq->ev.flow_id;
 640         ev->sub_event_type = rxq->ev.sub_event_type;
 641         ev->event_type = RTE_EVENT_TYPE_ETHDEV;
 642         ev->op = RTE_EVENT_OP_NEW;
 643         ev->sched_type = rxq->ev.sched_type;
 644         ev->queue_id = rxq->ev.queue_id;
 645         ev->priority = rxq->ev.priority;
 646
 647         ev->mbuf = eth_fd_to_mbuf(fd);
 648
 649         dqrr_index = qbman_get_dqrr_idx(dq);
 650         ev->mbuf->seqn = dqrr_index + 1;
 651         DPAA2_PER_LCORE_DQRR_SIZE++;
 652         DPAA2_PER_LCORE_DQRR_HELD |= 1 << dqrr_index;
 653         DPAA2_PER_LCORE_DQRR_MBUF(dqrr_index) = ev->mbuf;
 654 }
 655
 656 /*
 657  * Callback to handle sending packets through WRIOP based interface
 658  */
 659 uint16_t
 660 dpaa2_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)
 661 {
 662         /* Function to transmit the frames to given device and VQ*/
 663         uint32_t loop, retry_count;
 664         int32_t ret;
 665         struct qbman_fd fd_arr[MAX_TX_RING_SLOTS];
 666         struct rte_mbuf *mi;
 667         uint32_t frames_to_send;
 668         struct rte_mempool *mp;
 669         struct qbman_eq_desc eqdesc;
 670         struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)queue;
 671         struct qbman_swp *swp;
 672         uint16_t num_tx = 0;
 673         uint16_t bpid;
 674         struct rte_eth_dev *dev = dpaa2_q->dev;
 675         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 676         uint32_t flags[MAX_TX_RING_SLOTS] = {0};
 677
 678         if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
 679                 ret = dpaa2_affine_qbman_swp();
 680                 if (ret) {
 681                         DPAA2_PMD_ERR("Failure in affining portal");
 682                         return 0;
 683                 }
 684         }
 685         swp = DPAA2_PER_LCORE_PORTAL;
 686
 687         DPAA2_PMD_DP_DEBUG("===> dev =%p, fqid =%d\n", dev, dpaa2_q->fqid);
 688
 689         /*Prepare enqueue descriptor*/
 690         qbman_eq_desc_clear(&eqdesc);
 691         qbman_eq_desc_set_no_orp(&eqdesc, DPAA2_EQ_RESP_ERR_FQ);
 692         qbman_eq_desc_set_response(&eqdesc, 0, 0);
 693         qbman_eq_desc_set_qd(&eqdesc, priv->qdid,
 694                              dpaa2_q->flow_id, dpaa2_q->tc_index);
 695         /*Clear the unused FD fields before sending*/
 696         while (nb_pkts) {
 697                 /*Check if the queue is congested*/
 698                 retry_count = 0;
 699                 while (qbman_result_SCN_state(dpaa2_q->cscn)) {
 700                         retry_count++;
 701                         /* Retry for some time before giving up */
 702                         if (retry_count > CONG_RETRY_COUNT)
 703                                 goto skip_tx;
 704                 }
 705
 706                 frames_to_send = (nb_pkts > dpaa2_eqcr_size) ?
 707                         dpaa2_eqcr_size : nb_pkts;
 708
 709                 for (loop = 0; loop < frames_to_send; loop++) {
 710                         if ((*bufs)->seqn) {
 711                                 uint8_t dqrr_index = (*bufs)->seqn - 1;
 712
 713                                 flags[loop] = QBMAN_ENQUEUE_FLAG_DCA |
 714                                                 dqrr_index;
 715                                 DPAA2_PER_LCORE_DQRR_SIZE--;
 716                                 DPAA2_PER_LCORE_DQRR_HELD &= ~(1 << dqrr_index);
 717                                 (*bufs)->seqn = DPAA2_INVALID_MBUF_SEQN;
 718                         }
 719
 720                         fd_arr[loop].simple.frc = 0;
 721                         DPAA2_RESET_FD_CTRL((&fd_arr[loop]));
 722                         DPAA2_SET_FD_FLC((&fd_arr[loop]), (size_t)NULL);
 723                         if (likely(RTE_MBUF_DIRECT(*bufs))) {
 724                                 mp = (*bufs)->pool;
 725                                 /* Check the basic scenario and set
 726                                  * the FD appropriately here itself.
 727                                  */
 728                                 if (likely(mp && mp->ops_index ==
 729                                     priv->bp_list->dpaa2_ops_index &&
 730                                     (*bufs)->nb_segs == 1 &&
 731                                     rte_mbuf_refcnt_read((*bufs)) == 1)) {
 732                                         if (unlikely(((*bufs)->ol_flags
 733                                                 & PKT_TX_VLAN_PKT) ||
 734                                                 (dev->data->dev_conf.txmode.offloads
 735                                                 & DEV_TX_OFFLOAD_VLAN_INSERT))) {
 736                                                 ret = rte_vlan_insert(bufs);
 737                                                 if (ret)
 738                                                         goto send_n_return;
 739                                         }
 740                                         DPAA2_MBUF_TO_CONTIG_FD((*bufs),
 741                                         &fd_arr[loop], mempool_to_bpid(mp));
 742                                         bufs++;
 743                                         continue;
 744                                 }
 745                         } else {
 746                                 mi = rte_mbuf_from_indirect(*bufs);
 747                                 mp = mi->pool;
 748                         }
 749                         /* Not a hw_pkt pool allocated frame */
 750                         if (unlikely(!mp || !priv->bp_list)) {
 751                                 DPAA2_PMD_ERR("Err: No buffer pool attached");
 752                                 goto send_n_return;
 753                         }
 754
 755                         if (unlikely(((*bufs)->ol_flags & PKT_TX_VLAN_PKT) ||
 756                                 (dev->data->dev_conf.txmode.offloads
 757                                 & DEV_TX_OFFLOAD_VLAN_INSERT))) {
 758                                 int ret = rte_vlan_insert(bufs);
 759                                 if (ret)
 760                                         goto send_n_return;
 761                         }
 762                         if (mp->ops_index != priv->bp_list->dpaa2_ops_index) {
 763                                 DPAA2_PMD_WARN("Non DPAA2 buffer pool");
 764                                 /* alloc should be from the default buffer pool
 765                                  * attached to this interface
 766                                  */
 767                                 bpid = priv->bp_list->buf_pool.bpid;
 768
 769                                 if (unlikely((*bufs)->nb_segs > 1)) {
 770                                         DPAA2_PMD_ERR("S/G support not added"
 771                                                 " for non hw offload buffer");
 772                                         goto send_n_return;
 773                                 }
 774                                 if (eth_copy_mbuf_to_fd(*bufs,
 775                                                         &fd_arr[loop], bpid)) {
 776                                         goto send_n_return;
 777                                 }
 778                                 /* free the original packet */
 779                                 rte_pktmbuf_free(*bufs);
 780                         } else {
 781                                 bpid = mempool_to_bpid(mp);
 782                                 if (unlikely((*bufs)->nb_segs > 1)) {
 783                                         if (eth_mbuf_to_sg_fd(*bufs,
 784                                                         &fd_arr[loop], bpid))
 785                                                 goto send_n_return;
 786                                 } else {
 787                                         eth_mbuf_to_fd(*bufs,
 788                                                        &fd_arr[loop], bpid);
 789                                 }
 790                         }
 791                         bufs++;
 792                 }
 793                 loop = 0;
 794                 while (loop < frames_to_send) {
 795                         loop += qbman_swp_enqueue_multiple(swp, &eqdesc,
 796                                         &fd_arr[loop], &flags[loop],
 797                                         frames_to_send - loop);
 798                 }
 799
 800                 num_tx += frames_to_send;
 801                 nb_pkts -= frames_to_send;
 802         }
 803         dpaa2_q->tx_pkts += num_tx;
 804         return num_tx;
 805
 806 send_n_return:
 807         /* send any already prepared fd */
 808         if (loop) {
 809                 unsigned int i = 0;
 810
 811                 while (i < loop) {
 812                         i += qbman_swp_enqueue_multiple(swp, &eqdesc,
 813                                                         &fd_arr[i],
 814                                                         &flags[loop],
 815                                                         loop - i);
 816                 }
 817                 num_tx += loop;
 818         }
 819 skip_tx:
 820         dpaa2_q->tx_pkts += num_tx;
 821         return num_tx;
 822 }
 823
 824 /**
 825  * Dummy DPDK callback for TX.
 826  *
 827  * This function is used to temporarily replace the real callback during
 828  * unsafe control operations on the queue, or in case of error.
 829  *
 830  * @param dpdk_txq
 831  *   Generic pointer to TX queue structure.
 832  * @param[in] pkts
 833  *   Packets to transmit.
 834  * @param pkts_n
 835  *   Number of packets in array.
 836  *
 837  * @return
 838  *   Number of packets successfully transmitted (<= pkts_n).
 839  */
 840 uint16_t
 841 dummy_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)
 842 {
 843         (void)queue;
 844         (void)bufs;
 845         (void)nb_pkts;
 846         return 0;
 847 }