drivers/net/dpaa2/dpaa2_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  *   Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
   4  *   Copyright 2016-2018 NXP
   5  *
   6  */
   7
   8 #include <time.h>
   9 #include <net/if.h>
  10
  11 #include <rte_mbuf.h>
  12 #include <rte_ethdev_driver.h>
  13 #include <rte_malloc.h>
  14 #include <rte_memcpy.h>
  15 #include <rte_string_fns.h>
  16 #include <rte_dev.h>
  17
  18 #include <rte_fslmc.h>
  19 #include <fslmc_vfio.h>
  20 #include <dpaa2_hw_pvt.h>
  21 #include <dpaa2_hw_dpio.h>
  22 #include <dpaa2_hw_mempool.h>
  23
  24 #include "dpaa2_pmd_logs.h"
  25 #include "dpaa2_ethdev.h"
  26 #include "base/dpaa2_hw_dpni_annot.h"
  27
  28 #define DPAA2_MBUF_TO_CONTIG_FD(_mbuf, _fd, _bpid)  do { \
  29         DPAA2_SET_FD_ADDR(_fd, DPAA2_MBUF_VADDR_TO_IOVA(_mbuf)); \
  30         DPAA2_SET_FD_LEN(_fd, _mbuf->data_len); \
  31         DPAA2_SET_ONLY_FD_BPID(_fd, _bpid); \
  32         DPAA2_SET_FD_OFFSET(_fd, _mbuf->data_off); \
  33         DPAA2_SET_FD_FRC(_fd, 0);               \
  34         DPAA2_RESET_FD_CTRL(_fd);               \
  35         DPAA2_RESET_FD_FLC(_fd);                \
  36 } while (0)
  37
  38 static inline void __attribute__((hot))
  39 dpaa2_dev_rx_parse_new(struct rte_mbuf *m, const struct qbman_fd *fd)
  40 {
  41         uint16_t frc = DPAA2_GET_FD_FRC_PARSE_SUM(fd);
  42
  43         DPAA2_PMD_DP_DEBUG("frc = 0x%x\t", frc);
  44
  45         m->packet_type = RTE_PTYPE_UNKNOWN;
  46         switch (frc) {
  47         case DPAA2_PKT_TYPE_ETHER:
  48                 m->packet_type = RTE_PTYPE_L2_ETHER;
  49                 break;
  50         case DPAA2_PKT_TYPE_IPV4:
  51                 m->packet_type = RTE_PTYPE_L2_ETHER |
  52                         RTE_PTYPE_L3_IPV4;
  53                 break;
  54         case DPAA2_PKT_TYPE_IPV6:
  55                 m->packet_type = RTE_PTYPE_L2_ETHER |
  56                         RTE_PTYPE_L3_IPV6;
  57                 break;
  58         case DPAA2_PKT_TYPE_IPV4_EXT:
  59                 m->packet_type = RTE_PTYPE_L2_ETHER |
  60                         RTE_PTYPE_L3_IPV4_EXT;
  61                 break;
  62         case DPAA2_PKT_TYPE_IPV6_EXT:
  63                 m->packet_type = RTE_PTYPE_L2_ETHER |
  64                         RTE_PTYPE_L3_IPV6_EXT;
  65                 break;
  66         case DPAA2_PKT_TYPE_IPV4_TCP:
  67                 m->packet_type = RTE_PTYPE_L2_ETHER |
  68                         RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_TCP;
  69                 break;
  70         case DPAA2_PKT_TYPE_IPV6_TCP:
  71                 m->packet_type = RTE_PTYPE_L2_ETHER |
  72                         RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_TCP;
  73                 break;
  74         case DPAA2_PKT_TYPE_IPV4_UDP:
  75                 m->packet_type = RTE_PTYPE_L2_ETHER |
  76                         RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_UDP;
  77                 break;
  78         case DPAA2_PKT_TYPE_IPV6_UDP:
  79                 m->packet_type = RTE_PTYPE_L2_ETHER |
  80                         RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_UDP;
  81                 break;
  82         case DPAA2_PKT_TYPE_IPV4_SCTP:
  83                 m->packet_type = RTE_PTYPE_L2_ETHER |
  84                         RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_SCTP;
  85                 break;
  86         case DPAA2_PKT_TYPE_IPV6_SCTP:
  87                 m->packet_type = RTE_PTYPE_L2_ETHER |
  88                         RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_SCTP;
  89                 break;
  90         case DPAA2_PKT_TYPE_IPV4_ICMP:
  91                 m->packet_type = RTE_PTYPE_L2_ETHER |
  92                         RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_ICMP;
  93                 break;
  94         case DPAA2_PKT_TYPE_IPV6_ICMP:
  95                 m->packet_type = RTE_PTYPE_L2_ETHER |
  96                         RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_ICMP;
  97                 break;
  98         case DPAA2_PKT_TYPE_VLAN_1:
  99         case DPAA2_PKT_TYPE_VLAN_2:
 100                 m->ol_flags |= PKT_RX_VLAN;
 101                 break;
 102         /* More switch cases can be added */
 103         /* TODO: Add handling for checksum error check from FRC */
 104         default:
 105                 m->packet_type = RTE_PTYPE_UNKNOWN;
 106         }
 107         m->hash.rss = fd->simple.flc_hi;
 108         m->ol_flags |= PKT_RX_RSS_HASH;
 109 }
 110
 111 static inline uint32_t __attribute__((hot))
 112 dpaa2_dev_rx_parse_slow(struct dpaa2_annot_hdr *annotation)
 113 {
 114         uint32_t pkt_type = RTE_PTYPE_UNKNOWN;
 115
 116         DPAA2_PMD_DP_DEBUG("(slow parse) Annotation = 0x%" PRIx64 "\t",
 117                            annotation->word4);
 118         if (BIT_ISSET_AT_POS(annotation->word3, L2_ARP_PRESENT)) {
 119                 pkt_type = RTE_PTYPE_L2_ETHER_ARP;
 120                 goto parse_done;
 121         } else if (BIT_ISSET_AT_POS(annotation->word3, L2_ETH_MAC_PRESENT)) {
 122                 pkt_type = RTE_PTYPE_L2_ETHER;
 123         } else {
 124                 goto parse_done;
 125         }
 126
 127         if (BIT_ISSET_AT_POS(annotation->word4, L3_IPV4_1_PRESENT |
 128                              L3_IPV4_N_PRESENT)) {
 129                 pkt_type |= RTE_PTYPE_L3_IPV4;
 130                 if (BIT_ISSET_AT_POS(annotation->word4, L3_IP_1_OPT_PRESENT |
 131                         L3_IP_N_OPT_PRESENT))
 132                         pkt_type |= RTE_PTYPE_L3_IPV4_EXT;
 133
 134         } else if (BIT_ISSET_AT_POS(annotation->word4, L3_IPV6_1_PRESENT |
 135                   L3_IPV6_N_PRESENT)) {
 136                 pkt_type |= RTE_PTYPE_L3_IPV6;
 137                 if (BIT_ISSET_AT_POS(annotation->word4, L3_IP_1_OPT_PRESENT |
 138                     L3_IP_N_OPT_PRESENT))
 139                         pkt_type |= RTE_PTYPE_L3_IPV6_EXT;
 140         } else {
 141                 goto parse_done;
 142         }
 143
 144         if (BIT_ISSET_AT_POS(annotation->word4, L3_IP_1_FIRST_FRAGMENT |
 145             L3_IP_1_MORE_FRAGMENT |
 146             L3_IP_N_FIRST_FRAGMENT |
 147             L3_IP_N_MORE_FRAGMENT)) {
 148                 pkt_type |= RTE_PTYPE_L4_FRAG;
 149                 goto parse_done;
 150         } else {
 151                 pkt_type |= RTE_PTYPE_L4_NONFRAG;
 152         }
 153
 154         if (BIT_ISSET_AT_POS(annotation->word4, L3_PROTO_UDP_PRESENT))
 155                 pkt_type |= RTE_PTYPE_L4_UDP;
 156
 157         else if (BIT_ISSET_AT_POS(annotation->word4, L3_PROTO_TCP_PRESENT))
 158                 pkt_type |= RTE_PTYPE_L4_TCP;
 159
 160         else if (BIT_ISSET_AT_POS(annotation->word4, L3_PROTO_SCTP_PRESENT))
 161                 pkt_type |= RTE_PTYPE_L4_SCTP;
 162
 163         else if (BIT_ISSET_AT_POS(annotation->word4, L3_PROTO_ICMP_PRESENT))
 164                 pkt_type |= RTE_PTYPE_L4_ICMP;
 165
 166         else if (BIT_ISSET_AT_POS(annotation->word4, L3_IP_UNKNOWN_PROTOCOL))
 167                 pkt_type |= RTE_PTYPE_UNKNOWN;
 168
 169 parse_done:
 170         return pkt_type;
 171 }
 172
 173 static inline uint32_t __attribute__((hot))
 174 dpaa2_dev_rx_parse(struct rte_mbuf *mbuf, void *hw_annot_addr)
 175 {
 176         struct dpaa2_annot_hdr *annotation =
 177                         (struct dpaa2_annot_hdr *)hw_annot_addr;
 178
 179         DPAA2_PMD_DP_DEBUG("(fast parse) Annotation = 0x%" PRIx64 "\t",
 180                            annotation->word4);
 181
 182         /* Check offloads first */
 183         if (BIT_ISSET_AT_POS(annotation->word3,
 184                              L2_VLAN_1_PRESENT | L2_VLAN_N_PRESENT))
 185                 mbuf->ol_flags |= PKT_RX_VLAN;
 186
 187         if (BIT_ISSET_AT_POS(annotation->word8, DPAA2_ETH_FAS_L3CE))
 188                 mbuf->ol_flags |= PKT_RX_IP_CKSUM_BAD;
 189         else if (BIT_ISSET_AT_POS(annotation->word8, DPAA2_ETH_FAS_L4CE))
 190                 mbuf->ol_flags |= PKT_RX_L4_CKSUM_BAD;
 191
 192         /* Return some common types from parse processing */
 193         switch (annotation->word4) {
 194         case DPAA2_L3_IPv4:
 195                 return RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4;
 196         case DPAA2_L3_IPv6:
 197                 return  RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6;
 198         case DPAA2_L3_IPv4_TCP:
 199                 return  RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4 |
 200                                 RTE_PTYPE_L4_TCP;
 201         case DPAA2_L3_IPv4_UDP:
 202                 return  RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4 |
 203                                 RTE_PTYPE_L4_UDP;
 204         case DPAA2_L3_IPv6_TCP:
 205                 return  RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6 |
 206                                 RTE_PTYPE_L4_TCP;
 207         case DPAA2_L3_IPv6_UDP:
 208                 return  RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6 |
 209                                 RTE_PTYPE_L4_UDP;
 210         default:
 211                 break;
 212         }
 213
 214         return dpaa2_dev_rx_parse_slow(annotation);
 215 }
 216
 217 static inline struct rte_mbuf *__attribute__((hot))
 218 eth_sg_fd_to_mbuf(const struct qbman_fd *fd)
 219 {
 220         struct qbman_sge *sgt, *sge;
 221         size_t sg_addr, fd_addr;
 222         int i = 0;
 223         struct rte_mbuf *first_seg, *next_seg, *cur_seg, *temp;
 224
 225         fd_addr = (size_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd));
 226
 227         /* Get Scatter gather table address */
 228         sgt = (struct qbman_sge *)(fd_addr + DPAA2_GET_FD_OFFSET(fd));
 229
 230         sge = &sgt[i++];
 231         sg_addr = (size_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FLE_ADDR(sge));
 232
 233         /* First Scatter gather entry */
 234         first_seg = DPAA2_INLINE_MBUF_FROM_BUF(sg_addr,
 235                 rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size);
 236         /* Prepare all the metadata for first segment */
 237         first_seg->buf_addr = (uint8_t *)sg_addr;
 238         first_seg->ol_flags = 0;
 239         first_seg->data_off = DPAA2_GET_FLE_OFFSET(sge);
 240         first_seg->data_len = sge->length  & 0x1FFFF;
 241         first_seg->pkt_len = DPAA2_GET_FD_LEN(fd);
 242         first_seg->nb_segs = 1;
 243         first_seg->next = NULL;
 244         if (dpaa2_svr_family == SVR_LX2160A)
 245                 dpaa2_dev_rx_parse_new(first_seg, fd);
 246         else
 247                 first_seg->packet_type = dpaa2_dev_rx_parse(first_seg,
 248                         (void *)((size_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd))
 249                          + DPAA2_FD_PTA_SIZE));
 250
 251         rte_mbuf_refcnt_set(first_seg, 1);
 252         cur_seg = first_seg;
 253         while (!DPAA2_SG_IS_FINAL(sge)) {
 254                 sge = &sgt[i++];
 255                 sg_addr = (size_t)DPAA2_IOVA_TO_VADDR(
 256                                 DPAA2_GET_FLE_ADDR(sge));
 257                 next_seg = DPAA2_INLINE_MBUF_FROM_BUF(sg_addr,
 258                         rte_dpaa2_bpid_info[DPAA2_GET_FLE_BPID(sge)].meta_data_size);
 259                 next_seg->buf_addr  = (uint8_t *)sg_addr;
 260                 next_seg->data_off  = DPAA2_GET_FLE_OFFSET(sge);
 261                 next_seg->data_len  = sge->length  & 0x1FFFF;
 262                 first_seg->nb_segs += 1;
 263                 rte_mbuf_refcnt_set(next_seg, 1);
 264                 cur_seg->next = next_seg;
 265                 next_seg->next = NULL;
 266                 cur_seg = next_seg;
 267         }
 268         temp = DPAA2_INLINE_MBUF_FROM_BUF(fd_addr,
 269                 rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size);
 270         rte_mbuf_refcnt_set(temp, 1);
 271         rte_pktmbuf_free_seg(temp);
 272
 273         return (void *)first_seg;
 274 }
 275
 276 static inline struct rte_mbuf *__attribute__((hot))
 277 eth_fd_to_mbuf(const struct qbman_fd *fd)
 278 {
 279         struct rte_mbuf *mbuf = DPAA2_INLINE_MBUF_FROM_BUF(
 280                 DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd)),
 281                      rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size);
 282
 283         /* need to repopulated some of the fields,
 284          * as they may have changed in last transmission
 285          */
 286         mbuf->nb_segs = 1;
 287         mbuf->ol_flags = 0;
 288         mbuf->data_off = DPAA2_GET_FD_OFFSET(fd);
 289         mbuf->data_len = DPAA2_GET_FD_LEN(fd);
 290         mbuf->pkt_len = mbuf->data_len;
 291         mbuf->next = NULL;
 292         rte_mbuf_refcnt_set(mbuf, 1);
 293
 294         /* Parse the packet */
 295         /* parse results for LX2 are there in FRC field of FD.
 296          * For other DPAA2 platforms , parse results are after
 297          * the private - sw annotation area
 298          */
 299
 300         if (dpaa2_svr_family == SVR_LX2160A)
 301                 dpaa2_dev_rx_parse_new(mbuf, fd);
 302         else
 303                 mbuf->packet_type = dpaa2_dev_rx_parse(mbuf,
 304                         (void *)((size_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd))
 305                          + DPAA2_FD_PTA_SIZE));
 306
 307         DPAA2_PMD_DP_DEBUG("to mbuf - mbuf =%p, mbuf->buf_addr =%p, off = %d,"
 308                 "fd_off=%d fd =%" PRIx64 ", meta = %d  bpid =%d, len=%d\n",
 309                 mbuf, mbuf->buf_addr, mbuf->data_off,
 310                 DPAA2_GET_FD_OFFSET(fd), DPAA2_GET_FD_ADDR(fd),
 311                 rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size,
 312                 DPAA2_GET_FD_BPID(fd), DPAA2_GET_FD_LEN(fd));
 313
 314         return mbuf;
 315 }
 316
 317 static int __attribute__ ((noinline)) __attribute__((hot))
 318 eth_mbuf_to_sg_fd(struct rte_mbuf *mbuf,
 319                   struct qbman_fd *fd, uint16_t bpid)
 320 {
 321         struct rte_mbuf *cur_seg = mbuf, *prev_seg, *mi, *temp;
 322         struct qbman_sge *sgt, *sge = NULL;
 323         int i;
 324
 325         temp = rte_pktmbuf_alloc(mbuf->pool);
 326         if (temp == NULL) {
 327                 DPAA2_PMD_DP_DEBUG("No memory to allocate S/G table\n");
 328                 return -ENOMEM;
 329         }
 330
 331         DPAA2_SET_FD_ADDR(fd, DPAA2_MBUF_VADDR_TO_IOVA(temp));
 332         DPAA2_SET_FD_LEN(fd, mbuf->pkt_len);
 333         DPAA2_SET_ONLY_FD_BPID(fd, bpid);
 334         DPAA2_SET_FD_OFFSET(fd, temp->data_off);
 335         DPAA2_SET_FD_ASAL(fd, DPAA2_ASAL_VAL);
 336         DPAA2_FD_SET_FORMAT(fd, qbman_fd_sg);
 337         /*Set Scatter gather table and Scatter gather entries*/
 338         sgt = (struct qbman_sge *)(
 339                         (size_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd))
 340                         + DPAA2_GET_FD_OFFSET(fd));
 341
 342         for (i = 0; i < mbuf->nb_segs; i++) {
 343                 sge = &sgt[i];
 344                 /*Resetting the buffer pool id and offset field*/
 345                 sge->fin_bpid_offset = 0;
 346                 DPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(cur_seg));
 347                 DPAA2_SET_FLE_OFFSET(sge, cur_seg->data_off);
 348                 sge->length = cur_seg->data_len;
 349                 if (RTE_MBUF_DIRECT(cur_seg)) {
 350                         if (rte_mbuf_refcnt_read(cur_seg) > 1) {
 351                                 /* If refcnt > 1, invalid bpid is set to ensure
 352                                  * buffer is not freed by HW
 353                                  */
 354                                 DPAA2_SET_FLE_IVP(sge);
 355                                 rte_mbuf_refcnt_update(cur_seg, -1);
 356                         } else
 357                                 DPAA2_SET_FLE_BPID(sge,
 358                                                 mempool_to_bpid(cur_seg->pool));
 359                         cur_seg = cur_seg->next;
 360                 } else {
 361                         /* Get owner MBUF from indirect buffer */
 362                         mi = rte_mbuf_from_indirect(cur_seg);
 363                         if (rte_mbuf_refcnt_read(mi) > 1) {
 364                                 /* If refcnt > 1, invalid bpid is set to ensure
 365                                  * owner buffer is not freed by HW
 366                                  */
 367                                 DPAA2_SET_FLE_IVP(sge);
 368                         } else {
 369                                 DPAA2_SET_FLE_BPID(sge,
 370                                                    mempool_to_bpid(mi->pool));
 371                                 rte_mbuf_refcnt_update(mi, 1);
 372                         }
 373                         prev_seg = cur_seg;
 374                         cur_seg = cur_seg->next;
 375                         prev_seg->next = NULL;
 376                         rte_pktmbuf_free(prev_seg);
 377                 }
 378         }
 379         DPAA2_SG_SET_FINAL(sge, true);
 380         return 0;
 381 }
 382
 383 static void
 384 eth_mbuf_to_fd(struct rte_mbuf *mbuf,
 385                struct qbman_fd *fd, uint16_t bpid) __attribute__((unused));
 386
 387 static void __attribute__ ((noinline)) __attribute__((hot))
 388 eth_mbuf_to_fd(struct rte_mbuf *mbuf,
 389                struct qbman_fd *fd, uint16_t bpid)
 390 {
 391         DPAA2_MBUF_TO_CONTIG_FD(mbuf, fd, bpid);
 392
 393         DPAA2_PMD_DP_DEBUG("mbuf =%p, mbuf->buf_addr =%p, off = %d,"
 394                 "fd_off=%d fd =%" PRIx64 ", meta = %d  bpid =%d, len=%d\n",
 395                 mbuf, mbuf->buf_addr, mbuf->data_off,
 396                 DPAA2_GET_FD_OFFSET(fd), DPAA2_GET_FD_ADDR(fd),
 397                 rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size,
 398                 DPAA2_GET_FD_BPID(fd), DPAA2_GET_FD_LEN(fd));
 399         if (RTE_MBUF_DIRECT(mbuf)) {
 400                 if (rte_mbuf_refcnt_read(mbuf) > 1) {
 401                         DPAA2_SET_FD_IVP(fd);
 402                         rte_mbuf_refcnt_update(mbuf, -1);
 403                 }
 404         } else {
 405                 struct rte_mbuf *mi;
 406
 407                 mi = rte_mbuf_from_indirect(mbuf);
 408                 if (rte_mbuf_refcnt_read(mi) > 1)
 409                         DPAA2_SET_FD_IVP(fd);
 410                 else
 411                         rte_mbuf_refcnt_update(mi, 1);
 412                 rte_pktmbuf_free(mbuf);
 413         }
 414 }
 415
 416 static inline int __attribute__((hot))
 417 eth_copy_mbuf_to_fd(struct rte_mbuf *mbuf,
 418                     struct qbman_fd *fd, uint16_t bpid)
 419 {
 420         struct rte_mbuf *m;
 421         void *mb = NULL;
 422
 423         if (rte_dpaa2_mbuf_alloc_bulk(
 424                 rte_dpaa2_bpid_info[bpid].bp_list->mp, &mb, 1)) {
 425                 DPAA2_PMD_DP_DEBUG("Unable to allocated DPAA2 buffer\n");
 426                 return -1;
 427         }
 428         m = (struct rte_mbuf *)mb;
 429         memcpy((char *)m->buf_addr + mbuf->data_off,
 430                (void *)((char *)mbuf->buf_addr + mbuf->data_off),
 431                 mbuf->pkt_len);
 432
 433         /* Copy required fields */
 434         m->data_off = mbuf->data_off;
 435         m->ol_flags = mbuf->ol_flags;
 436         m->packet_type = mbuf->packet_type;
 437         m->tx_offload = mbuf->tx_offload;
 438
 439         DPAA2_MBUF_TO_CONTIG_FD(m, fd, bpid);
 440
 441         DPAA2_PMD_DP_DEBUG(
 442                 "mbuf: %p, BMAN buf addr: %p, fdaddr: %" PRIx64 ", bpid: %d,"
 443                 " meta: %d, off: %d, len: %d\n",
 444                 (void *)mbuf,
 445                 mbuf->buf_addr,
 446                 DPAA2_GET_FD_ADDR(fd),
 447                 DPAA2_GET_FD_BPID(fd),
 448                 rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size,
 449                 DPAA2_GET_FD_OFFSET(fd),
 450                 DPAA2_GET_FD_LEN(fd));
 451
 452 return 0;
 453 }
 454
 455 /* This function assumes that caller will be keep the same value for nb_pkts
 456  * across calls per queue, if that is not the case, better use non-prefetch
 457  * version of rx call.
 458  * It will return the packets as requested in previous call without honoring
 459  * the current nb_pkts or bufs space.
 460  */
 461 uint16_t
 462 dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)
 463 {
 464         /* Function receive frames for a given device and VQ*/
 465         struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)queue;
 466         struct qbman_result *dq_storage, *dq_storage1 = NULL;
 467         uint32_t fqid = dpaa2_q->fqid;
 468         int ret, num_rx = 0, pull_size;
 469         uint8_t pending, status;
 470         struct qbman_swp *swp;
 471         const struct qbman_fd *fd, *next_fd;
 472         struct qbman_pull_desc pulldesc;
 473         struct queue_storage_info_t *q_storage = dpaa2_q->q_storage;
 474         struct rte_eth_dev *dev = dpaa2_q->dev;
 475
 476         if (unlikely(!DPAA2_PER_LCORE_ETHRX_DPIO)) {
 477                 ret = dpaa2_affine_qbman_ethrx_swp();
 478                 if (ret) {
 479                         DPAA2_PMD_ERR("Failure in affining portal");
 480                         return 0;
 481                 }
 482         }
 483         swp = DPAA2_PER_LCORE_ETHRX_PORTAL;
 484         pull_size = (nb_pkts > dpaa2_dqrr_size) ? dpaa2_dqrr_size : nb_pkts;
 485         if (unlikely(!q_storage->active_dqs)) {
 486                 q_storage->toggle = 0;
 487                 dq_storage = q_storage->dq_storage[q_storage->toggle];
 488                 q_storage->last_num_pkts = pull_size;
 489                 qbman_pull_desc_clear(&pulldesc);
 490                 qbman_pull_desc_set_numframes(&pulldesc,
 491                                               q_storage->last_num_pkts);
 492                 qbman_pull_desc_set_fq(&pulldesc, fqid);
 493                 qbman_pull_desc_set_storage(&pulldesc, dq_storage,
 494                         (uint64_t)(DPAA2_VADDR_TO_IOVA(dq_storage)), 1);
 495                 if (check_swp_active_dqs(DPAA2_PER_LCORE_ETHRX_DPIO->index)) {
 496                         while (!qbman_check_command_complete(
 497                                get_swp_active_dqs(
 498                                DPAA2_PER_LCORE_ETHRX_DPIO->index)))
 499                                 ;
 500                         clear_swp_active_dqs(DPAA2_PER_LCORE_ETHRX_DPIO->index);
 501                 }
 502                 while (1) {
 503                         if (qbman_swp_pull(swp, &pulldesc)) {
 504                                 DPAA2_PMD_DP_DEBUG("VDQ command is not issued."
 505                                                   " QBMAN is busy (1)\n");
 506                                 /* Portal was busy, try again */
 507                                 continue;
 508                         }
 509                         break;
 510                 }
 511                 q_storage->active_dqs = dq_storage;
 512                 q_storage->active_dpio_id = DPAA2_PER_LCORE_ETHRX_DPIO->index;
 513                 set_swp_active_dqs(DPAA2_PER_LCORE_ETHRX_DPIO->index,
 514                                    dq_storage);
 515         }
 516
 517         dq_storage = q_storage->active_dqs;
 518         rte_prefetch0((void *)(size_t)(dq_storage));
 519         rte_prefetch0((void *)(size_t)(dq_storage + 1));
 520
 521         /* Prepare next pull descriptor. This will give space for the
 522          * prefething done on DQRR entries
 523          */
 524         q_storage->toggle ^= 1;
 525         dq_storage1 = q_storage->dq_storage[q_storage->toggle];
 526         qbman_pull_desc_clear(&pulldesc);
 527         qbman_pull_desc_set_numframes(&pulldesc, pull_size);
 528         qbman_pull_desc_set_fq(&pulldesc, fqid);
 529         qbman_pull_desc_set_storage(&pulldesc, dq_storage1,
 530                 (uint64_t)(DPAA2_VADDR_TO_IOVA(dq_storage1)), 1);
 531
 532         /* Check if the previous issued command is completed.
 533          * Also seems like the SWP is shared between the Ethernet Driver
 534          * and the SEC driver.
 535          */
 536         while (!qbman_check_command_complete(dq_storage))
 537                 ;
 538         if (dq_storage == get_swp_active_dqs(q_storage->active_dpio_id))
 539                 clear_swp_active_dqs(q_storage->active_dpio_id);
 540
 541         pending = 1;
 542
 543         do {
 544                 /* Loop until the dq_storage is updated with
 545                  * new token by QBMAN
 546                  */
 547                 while (!qbman_check_new_result(dq_storage))
 548                         ;
 549                 rte_prefetch0((void *)((size_t)(dq_storage + 2)));
 550                 /* Check whether Last Pull command is Expired and
 551                  * setting Condition for Loop termination
 552                  */
 553                 if (qbman_result_DQ_is_pull_complete(dq_storage)) {
 554                         pending = 0;
 555                         /* Check for valid frame. */
 556                         status = qbman_result_DQ_flags(dq_storage);
 557                         if (unlikely((status & QBMAN_DQ_STAT_VALIDFRAME) == 0))
 558                                 continue;
 559                 }
 560                 fd = qbman_result_DQ_fd(dq_storage);
 561
 562                 if (dpaa2_svr_family != SVR_LX2160A) {
 563                         next_fd = qbman_result_DQ_fd(dq_storage + 1);
 564                         /* Prefetch Annotation address for the parse results */
 565                         rte_prefetch0((void *)(size_t)(DPAA2_GET_FD_ADDR(
 566                                       next_fd) + DPAA2_FD_PTA_SIZE + 16));
 567                 }
 568
 569                 if (unlikely(DPAA2_FD_GET_FORMAT(fd) == qbman_fd_sg))
 570                         bufs[num_rx] = eth_sg_fd_to_mbuf(fd);
 571                 else
 572                         bufs[num_rx] = eth_fd_to_mbuf(fd);
 573                 bufs[num_rx]->port = dev->data->port_id;
 574
 575                 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 576                         rte_vlan_strip(bufs[num_rx]);
 577
 578                 dq_storage++;
 579                 num_rx++;
 580         } while (pending);
 581
 582         if (check_swp_active_dqs(DPAA2_PER_LCORE_ETHRX_DPIO->index)) {
 583                 while (!qbman_check_command_complete(
 584                        get_swp_active_dqs(DPAA2_PER_LCORE_ETHRX_DPIO->index)))
 585                         ;
 586                 clear_swp_active_dqs(DPAA2_PER_LCORE_ETHRX_DPIO->index);
 587         }
 588         /* issue a volatile dequeue command for next pull */
 589         while (1) {
 590                 if (qbman_swp_pull(swp, &pulldesc)) {
 591                         DPAA2_PMD_DP_DEBUG("VDQ command is not issued."
 592                                           "QBMAN is busy (2)\n");
 593                         continue;
 594                 }
 595                 break;
 596         }
 597         q_storage->active_dqs = dq_storage1;
 598         q_storage->active_dpio_id = DPAA2_PER_LCORE_ETHRX_DPIO->index;
 599         set_swp_active_dqs(DPAA2_PER_LCORE_ETHRX_DPIO->index, dq_storage1);
 600
 601         dpaa2_q->rx_pkts += num_rx;
 602
 603         return num_rx;
 604 }
 605
 606 void __attribute__((hot))
 607 dpaa2_dev_process_parallel_event(struct qbman_swp *swp,
 608                                  const struct qbman_fd *fd,
 609                                  const struct qbman_result *dq,
 610                                  struct dpaa2_queue *rxq,
 611                                  struct rte_event *ev)
 612 {
 613         rte_prefetch0((void *)(size_t)(DPAA2_GET_FD_ADDR(fd) +
 614                 DPAA2_FD_PTA_SIZE + 16));
 615
 616         ev->flow_id = rxq->ev.flow_id;
 617         ev->sub_event_type = rxq->ev.sub_event_type;
 618         ev->event_type = RTE_EVENT_TYPE_ETHDEV;
 619         ev->op = RTE_EVENT_OP_NEW;
 620         ev->sched_type = rxq->ev.sched_type;
 621         ev->queue_id = rxq->ev.queue_id;
 622         ev->priority = rxq->ev.priority;
 623
 624         ev->mbuf = eth_fd_to_mbuf(fd);
 625
 626         qbman_swp_dqrr_consume(swp, dq);
 627 }
 628
 629 void __attribute__((hot))
 630 dpaa2_dev_process_atomic_event(struct qbman_swp *swp __attribute__((unused)),
 631                                const struct qbman_fd *fd,
 632                                const struct qbman_result *dq,
 633                                struct dpaa2_queue *rxq,
 634                                struct rte_event *ev)
 635 {
 636         uint8_t dqrr_index;
 637
 638         rte_prefetch0((void *)(size_t)(DPAA2_GET_FD_ADDR(fd) +
 639                 DPAA2_FD_PTA_SIZE + 16));
 640
 641         ev->flow_id = rxq->ev.flow_id;
 642         ev->sub_event_type = rxq->ev.sub_event_type;
 643         ev->event_type = RTE_EVENT_TYPE_ETHDEV;
 644         ev->op = RTE_EVENT_OP_NEW;
 645         ev->sched_type = rxq->ev.sched_type;
 646         ev->queue_id = rxq->ev.queue_id;
 647         ev->priority = rxq->ev.priority;
 648
 649         ev->mbuf = eth_fd_to_mbuf(fd);
 650
 651         dqrr_index = qbman_get_dqrr_idx(dq);
 652         ev->mbuf->seqn = dqrr_index + 1;
 653         DPAA2_PER_LCORE_DQRR_SIZE++;
 654         DPAA2_PER_LCORE_DQRR_HELD |= 1 << dqrr_index;
 655         DPAA2_PER_LCORE_DQRR_MBUF(dqrr_index) = ev->mbuf;
 656 }
 657
 658 /*
 659  * Callback to handle sending packets through WRIOP based interface
 660  */
 661 uint16_t
 662 dpaa2_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)
 663 {
 664         /* Function to transmit the frames to given device and VQ*/
 665         uint32_t loop, retry_count;
 666         int32_t ret;
 667         struct qbman_fd fd_arr[MAX_TX_RING_SLOTS];
 668         struct rte_mbuf *mi;
 669         uint32_t frames_to_send;
 670         struct rte_mempool *mp;
 671         struct qbman_eq_desc eqdesc;
 672         struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)queue;
 673         struct qbman_swp *swp;
 674         uint16_t num_tx = 0;
 675         uint16_t bpid;
 676         struct rte_eth_dev *dev = dpaa2_q->dev;
 677         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 678         uint32_t flags[MAX_TX_RING_SLOTS] = {0};
 679
 680         if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
 681                 ret = dpaa2_affine_qbman_swp();
 682                 if (ret) {
 683                         DPAA2_PMD_ERR("Failure in affining portal");
 684                         return 0;
 685                 }
 686         }
 687         swp = DPAA2_PER_LCORE_PORTAL;
 688
 689         DPAA2_PMD_DP_DEBUG("===> dev =%p, fqid =%d\n", dev, dpaa2_q->fqid);
 690
 691         /*Prepare enqueue descriptor*/
 692         qbman_eq_desc_clear(&eqdesc);
 693         qbman_eq_desc_set_no_orp(&eqdesc, DPAA2_EQ_RESP_ERR_FQ);
 694         qbman_eq_desc_set_qd(&eqdesc, priv->qdid,
 695                              dpaa2_q->flow_id, dpaa2_q->tc_index);
 696         /*Clear the unused FD fields before sending*/
 697         while (nb_pkts) {
 698                 /*Check if the queue is congested*/
 699                 retry_count = 0;
 700                 while (qbman_result_SCN_state(dpaa2_q->cscn)) {
 701                         retry_count++;
 702                         /* Retry for some time before giving up */
 703                         if (retry_count > CONG_RETRY_COUNT)
 704                                 goto skip_tx;
 705                 }
 706
 707                 frames_to_send = (nb_pkts > dpaa2_eqcr_size) ?
 708                         dpaa2_eqcr_size : nb_pkts;
 709
 710                 for (loop = 0; loop < frames_to_send; loop++) {
 711                         if ((*bufs)->seqn) {
 712                                 uint8_t dqrr_index = (*bufs)->seqn - 1;
 713
 714                                 flags[loop] = QBMAN_ENQUEUE_FLAG_DCA |
 715                                                 dqrr_index;
 716                                 DPAA2_PER_LCORE_DQRR_SIZE--;
 717                                 DPAA2_PER_LCORE_DQRR_HELD &= ~(1 << dqrr_index);
 718                                 (*bufs)->seqn = DPAA2_INVALID_MBUF_SEQN;
 719                         }
 720
 721                         if (likely(RTE_MBUF_DIRECT(*bufs))) {
 722                                 mp = (*bufs)->pool;
 723                                 /* Check the basic scenario and set
 724                                  * the FD appropriately here itself.
 725                                  */
 726                                 if (likely(mp && mp->ops_index ==
 727                                     priv->bp_list->dpaa2_ops_index &&
 728                                     (*bufs)->nb_segs == 1 &&
 729                                     rte_mbuf_refcnt_read((*bufs)) == 1)) {
 730                                         if (unlikely(((*bufs)->ol_flags
 731                                                 & PKT_TX_VLAN_PKT) ||
 732                                                 (dev->data->dev_conf.txmode.offloads
 733                                                 & DEV_TX_OFFLOAD_VLAN_INSERT))) {
 734                                                 ret = rte_vlan_insert(bufs);
 735                                                 if (ret)
 736                                                         goto send_n_return;
 737                                         }
 738                                         DPAA2_MBUF_TO_CONTIG_FD((*bufs),
 739                                         &fd_arr[loop], mempool_to_bpid(mp));
 740                                         bufs++;
 741                                         continue;
 742                                 }
 743                         } else {
 744                                 mi = rte_mbuf_from_indirect(*bufs);
 745                                 mp = mi->pool;
 746                         }
 747                         /* Not a hw_pkt pool allocated frame */
 748                         if (unlikely(!mp || !priv->bp_list)) {
 749                                 DPAA2_PMD_ERR("Err: No buffer pool attached");
 750                                 goto send_n_return;
 751                         }
 752
 753                         if (unlikely(((*bufs)->ol_flags & PKT_TX_VLAN_PKT) ||
 754                                 (dev->data->dev_conf.txmode.offloads
 755                                 & DEV_TX_OFFLOAD_VLAN_INSERT))) {
 756                                 int ret = rte_vlan_insert(bufs);
 757                                 if (ret)
 758                                         goto send_n_return;
 759                         }
 760                         if (mp->ops_index != priv->bp_list->dpaa2_ops_index) {
 761                                 DPAA2_PMD_WARN("Non DPAA2 buffer pool");
 762                                 /* alloc should be from the default buffer pool
 763                                  * attached to this interface
 764                                  */
 765                                 bpid = priv->bp_list->buf_pool.bpid;
 766
 767                                 if (unlikely((*bufs)->nb_segs > 1)) {
 768                                         DPAA2_PMD_ERR("S/G support not added"
 769                                                 " for non hw offload buffer");
 770                                         goto send_n_return;
 771                                 }
 772                                 if (eth_copy_mbuf_to_fd(*bufs,
 773                                                         &fd_arr[loop], bpid)) {
 774                                         goto send_n_return;
 775                                 }
 776                                 /* free the original packet */
 777                                 rte_pktmbuf_free(*bufs);
 778                         } else {
 779                                 bpid = mempool_to_bpid(mp);
 780                                 if (unlikely((*bufs)->nb_segs > 1)) {
 781                                         if (eth_mbuf_to_sg_fd(*bufs,
 782                                                         &fd_arr[loop], bpid))
 783                                                 goto send_n_return;
 784                                 } else {
 785                                         eth_mbuf_to_fd(*bufs,
 786                                                        &fd_arr[loop], bpid);
 787                                 }
 788                         }
 789                         bufs++;
 790                 }
 791                 loop = 0;
 792                 while (loop < frames_to_send) {
 793                         loop += qbman_swp_enqueue_multiple(swp, &eqdesc,
 794                                         &fd_arr[loop], &flags[loop],
 795                                         frames_to_send - loop);
 796                 }
 797
 798                 num_tx += frames_to_send;
 799                 nb_pkts -= frames_to_send;
 800         }
 801         dpaa2_q->tx_pkts += num_tx;
 802         return num_tx;
 803
 804 send_n_return:
 805         /* send any already prepared fd */
 806         if (loop) {
 807                 unsigned int i = 0;
 808
 809                 while (i < loop) {
 810                         i += qbman_swp_enqueue_multiple(swp, &eqdesc,
 811                                                         &fd_arr[i],
 812                                                         &flags[loop],
 813                                                         loop - i);
 814                 }
 815                 num_tx += loop;
 816         }
 817 skip_tx:
 818         dpaa2_q->tx_pkts += num_tx;
 819         return num_tx;
 820 }
 821
 822 /**
 823  * Dummy DPDK callback for TX.
 824  *
 825  * This function is used to temporarily replace the real callback during
 826  * unsafe control operations on the queue, or in case of error.
 827  *
 828  * @param dpdk_txq
 829  *   Generic pointer to TX queue structure.
 830  * @param[in] pkts
 831  *   Packets to transmit.
 832  * @param pkts_n
 833  *   Number of packets in array.
 834  *
 835  * @return
 836  *   Number of packets successfully transmitted (<= pkts_n).
 837  */
 838 uint16_t
 839 dummy_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)
 840 {
 841         (void)queue;
 842         (void)bufs;
 843         (void)nb_pkts;
 844         return 0;
 845 }