drivers/net/e1000/base/e1000_ich8lan.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2001 - 2015 Intel Corporation
   3  */
   4
   5 /* 82562G 10/100 Network Connection
   6  * 82562G-2 10/100 Network Connection
   7  * 82562GT 10/100 Network Connection
   8  * 82562GT-2 10/100 Network Connection
   9  * 82562V 10/100 Network Connection
  10  * 82562V-2 10/100 Network Connection
  11  * 82566DC-2 Gigabit Network Connection
  12  * 82566DC Gigabit Network Connection
  13  * 82566DM-2 Gigabit Network Connection
  14  * 82566DM Gigabit Network Connection
  15  * 82566MC Gigabit Network Connection
  16  * 82566MM Gigabit Network Connection
  17  * 82567LM Gigabit Network Connection
  18  * 82567LF Gigabit Network Connection
  19  * 82567V Gigabit Network Connection
  20  * 82567LM-2 Gigabit Network Connection
  21  * 82567LF-2 Gigabit Network Connection
  22  * 82567V-2 Gigabit Network Connection
  23  * 82567LF-3 Gigabit Network Connection
  24  * 82567LM-3 Gigabit Network Connection
  25  * 82567LM-4 Gigabit Network Connection
  26  * 82577LM Gigabit Network Connection
  27  * 82577LC Gigabit Network Connection
  28  * 82578DM Gigabit Network Connection
  29  * 82578DC Gigabit Network Connection
  30  * 82579LM Gigabit Network Connection
  31  * 82579V Gigabit Network Connection
  32  * Ethernet Connection I217-LM
  33  * Ethernet Connection I217-V
  34  * Ethernet Connection I218-V
  35  * Ethernet Connection I218-LM
  36  * Ethernet Connection (2) I218-LM
  37  * Ethernet Connection (2) I218-V
  38  * Ethernet Connection (3) I218-LM
  39  * Ethernet Connection (3) I218-V
  40  */
  41
  42 #include "e1000_api.h"
  43
  44 STATIC s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
  45 STATIC s32  e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
  46 STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
  47 STATIC s32  e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);
  48 STATIC void e1000_release_nvm_ich8lan(struct e1000_hw *hw);
  49 STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
  50 STATIC bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
  51 STATIC int  e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
  52 STATIC int  e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
  53 STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw);
  54 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
  55 STATIC void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
  56                                               u8 *mc_addr_list,
  57                                               u32 mc_addr_count);
  58 #endif /* NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT */
  59 STATIC s32  e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
  60 STATIC s32  e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
  61 STATIC s32  e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
  62 STATIC s32  e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
  63                                             bool active);
  64 STATIC s32  e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
  65                                             bool active);
  66 STATIC s32  e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
  67                                    u16 words, u16 *data);
  68 STATIC s32  e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
  69                                u16 *data);
  70 STATIC s32  e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
  71                                     u16 words, u16 *data);
  72 STATIC s32  e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
  73 STATIC s32  e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
  74 STATIC s32  e1000_update_nvm_checksum_spt(struct e1000_hw *hw);
  75 STATIC s32  e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
  76                                             u16 *data);
  77 STATIC s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
  78 STATIC s32  e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
  79 STATIC s32  e1000_reset_hw_ich8lan(struct e1000_hw *hw);
  80 STATIC s32  e1000_init_hw_ich8lan(struct e1000_hw *hw);
  81 STATIC s32  e1000_setup_link_ich8lan(struct e1000_hw *hw);
  82 STATIC s32  e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
  83 STATIC s32  e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
  84 STATIC s32  e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
  85                                            u16 *speed, u16 *duplex);
  86 STATIC s32  e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
  87 STATIC s32  e1000_led_on_ich8lan(struct e1000_hw *hw);
  88 STATIC s32  e1000_led_off_ich8lan(struct e1000_hw *hw);
  89 STATIC s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
  90 STATIC s32  e1000_setup_led_pchlan(struct e1000_hw *hw);
  91 STATIC s32  e1000_cleanup_led_pchlan(struct e1000_hw *hw);
  92 STATIC s32  e1000_led_on_pchlan(struct e1000_hw *hw);
  93 STATIC s32  e1000_led_off_pchlan(struct e1000_hw *hw);
  94 STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
  95 STATIC s32  e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
  96 STATIC void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
  97 STATIC s32  e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
  98 STATIC s32  e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
  99                                           u32 offset, u8 *data);
 100 STATIC s32  e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 101                                           u8 size, u16 *data);
 102 STATIC s32  e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
 103                                             u32 *data);
 104 STATIC s32  e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
 105                                            u32 offset, u32 *data);
 106 STATIC s32  e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
 107                                              u32 offset, u32 data);
 108 STATIC s32  e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
 109                                                   u32 offset, u32 dword);
 110 STATIC s32  e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
 111                                           u32 offset, u16 *data);
 112 STATIC s32  e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 113                                                  u32 offset, u8 byte);
 114 STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 115 STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 116 STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
 117 STATIC s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 118 STATIC s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
 119 STATIC void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
 120
 121 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 122 /* Offset 04h HSFSTS */
 123 union ich8_hws_flash_status {
 124         struct ich8_hsfsts {
 125                 u16 flcdone:1; /* bit 0 Flash Cycle Done */
 126                 u16 flcerr:1; /* bit 1 Flash Cycle Error */
 127                 u16 dael:1; /* bit 2 Direct Access error Log */
 128                 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
 129                 u16 flcinprog:1; /* bit 5 flash cycle in Progress */
 130                 u16 reserved1:2; /* bit 13:6 Reserved */
 131                 u16 reserved2:6; /* bit 13:6 Reserved */
 132                 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
 133                 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
 134         } hsf_status;
 135         u16 regval;
 136 };
 137
 138 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
 139 /* Offset 06h FLCTL */
 140 union ich8_hws_flash_ctrl {
 141         struct ich8_hsflctl {
 142                 u16 flcgo:1;   /* 0 Flash Cycle Go */
 143                 u16 flcycle:2;   /* 2:1 Flash Cycle */
 144                 u16 reserved:5;   /* 7:3 Reserved  */
 145                 u16 fldbcount:2;   /* 9:8 Flash Data Byte Count */
 146                 u16 flockdn:6;   /* 15:10 Reserved */
 147         } hsf_ctrl;
 148         u16 regval;
 149 };
 150
 151 /* ICH Flash Region Access Permissions */
 152 union ich8_hws_flash_regacc {
 153         struct ich8_flracc {
 154                 u32 grra:8; /* 0:7 GbE region Read Access */
 155                 u32 grwa:8; /* 8:15 GbE region Write Access */
 156                 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
 157                 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
 158         } hsf_flregacc;
 159         u16 regval;
 160 };
 161
 162 /**
 163  *  e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
 164  *  @hw: pointer to the HW structure
 165  *
 166  *  Test access to the PHY registers by reading the PHY ID registers.  If
 167  *  the PHY ID is already known (e.g. resume path) compare it with known ID,
 168  *  otherwise assume the read PHY ID is correct if it is valid.
 169  *
 170  *  Assumes the sw/fw/hw semaphore is already acquired.
 171  **/
 172 STATIC bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
 173 {
 174         u16 phy_reg = 0;
 175         u32 phy_id = 0;
 176         s32 ret_val = 0;
 177         u16 retry_count;
 178         u32 mac_reg = 0;
 179
 180         for (retry_count = 0; retry_count < 2; retry_count++) {
 181                 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg);
 182                 if (ret_val || (phy_reg == 0xFFFF))
 183                         continue;
 184                 phy_id = (u32)(phy_reg << 16);
 185
 186                 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg);
 187                 if (ret_val || (phy_reg == 0xFFFF)) {
 188                         phy_id = 0;
 189                         continue;
 190                 }
 191                 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
 192                 break;
 193         }
 194
 195         if (hw->phy.id) {
 196                 if  (hw->phy.id == phy_id)
 197                         goto out;
 198         } else if (phy_id) {
 199                 hw->phy.id = phy_id;
 200                 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
 201                 goto out;
 202         }
 203
 204         /* In case the PHY needs to be in mdio slow mode,
 205          * set slow mode and try to get the PHY id again.
 206          */
 207         if (hw->mac.type < e1000_pch_lpt) {
 208                 hw->phy.ops.release(hw);
 209                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
 210                 if (!ret_val)
 211                         ret_val = e1000_get_phy_id(hw);
 212                 hw->phy.ops.acquire(hw);
 213         }
 214
 215         if (ret_val)
 216                 return false;
 217 out:
 218         if (hw->mac.type >= e1000_pch_lpt) {
 219                 /* Only unforce SMBus if ME is not active */
 220                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
 221                     E1000_ICH_FWSM_FW_VALID)) {
 222                         /* Unforce SMBus mode in PHY */
 223                         hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg);
 224                         phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
 225                         hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg);
 226
 227                         /* Unforce SMBus mode in MAC */
 228                         mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
 229                         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 230                         E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
 231                 }
 232         }
 233
 234         return true;
 235 }
 236
 237 /**
 238  *  e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
 239  *  @hw: pointer to the HW structure
 240  *
 241  *  Toggling the LANPHYPC pin value fully power-cycles the PHY and is
 242  *  used to reset the PHY to a quiescent state when necessary.
 243  **/
 244 STATIC void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
 245 {
 246         u32 mac_reg;
 247
 248         DEBUGFUNC("e1000_toggle_lanphypc_pch_lpt");
 249
 250         /* Set Phy Config Counter to 50msec */
 251         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
 252         mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
 253         mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
 254         E1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg);
 255
 256         /* Toggle LANPHYPC Value bit */
 257         mac_reg = E1000_READ_REG(hw, E1000_CTRL);
 258         mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
 259         mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
 260         E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
 261         E1000_WRITE_FLUSH(hw);
 262         msec_delay(1);
 263         mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
 264         E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
 265         E1000_WRITE_FLUSH(hw);
 266
 267         if (hw->mac.type < e1000_pch_lpt) {
 268                 msec_delay(50);
 269         } else {
 270                 u16 count = 20;
 271
 272                 do {
 273                         msec_delay(5);
 274                 } while (!(E1000_READ_REG(hw, E1000_CTRL_EXT) &
 275                            E1000_CTRL_EXT_LPCD) && count--);
 276
 277                 msec_delay(30);
 278         }
 279 }
 280
 281 /**
 282  *  e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
 283  *  @hw: pointer to the HW structure
 284  *
 285  *  Workarounds/flow necessary for PHY initialization during driver load
 286  *  and resume paths.
 287  **/
 288 STATIC s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
 289 {
 290         u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM);
 291         s32 ret_val;
 292
 293         DEBUGFUNC("e1000_init_phy_workarounds_pchlan");
 294
 295         /* Gate automatic PHY configuration by hardware on managed and
 296          * non-managed 82579 and newer adapters.
 297          */
 298         e1000_gate_hw_phy_config_ich8lan(hw, true);
 299
 300 #ifdef ULP_SUPPORT
 301         /* It is not possible to be certain of the current state of ULP
 302          * so forcibly disable it.
 303          */
 304         hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
 305
 306 #endif /* ULP_SUPPORT */
 307         ret_val = hw->phy.ops.acquire(hw);
 308         if (ret_val) {
 309                 DEBUGOUT("Failed to initialize PHY flow\n");
 310                 goto out;
 311         }
 312
 313         /* The MAC-PHY interconnect may be in SMBus mode.  If the PHY is
 314          * inaccessible and resetting the PHY is not blocked, toggle the
 315          * LANPHYPC Value bit to force the interconnect to PCIe mode.
 316          */
 317         switch (hw->mac.type) {
 318         case e1000_pch_lpt:
 319         case e1000_pch_spt:
 320         case e1000_pch_cnp:
 321                 if (e1000_phy_is_accessible_pchlan(hw))
 322                         break;
 323
 324                 /* Before toggling LANPHYPC, see if PHY is accessible by
 325                  * forcing MAC to SMBus mode first.
 326                  */
 327                 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
 328                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
 329                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
 330
 331                 /* Wait 50 milliseconds for MAC to finish any retries
 332                  * that it might be trying to perform from previous
 333                  * attempts to acknowledge any phy read requests.
 334                  */
 335                  msec_delay(50);
 336
 337                 /* fall-through */
 338         case e1000_pch2lan:
 339                 if (e1000_phy_is_accessible_pchlan(hw))
 340                         break;
 341
 342                 /* fall-through */
 343         case e1000_pchlan:
 344                 if ((hw->mac.type == e1000_pchlan) &&
 345                     (fwsm & E1000_ICH_FWSM_FW_VALID))
 346                         break;
 347
 348                 if (hw->phy.ops.check_reset_block(hw)) {
 349                         DEBUGOUT("Required LANPHYPC toggle blocked by ME\n");
 350                         ret_val = -E1000_ERR_PHY;
 351                         break;
 352                 }
 353
 354                 /* Toggle LANPHYPC Value bit */
 355                 e1000_toggle_lanphypc_pch_lpt(hw);
 356                 if (hw->mac.type >= e1000_pch_lpt) {
 357                         if (e1000_phy_is_accessible_pchlan(hw))
 358                                 break;
 359
 360                         /* Toggling LANPHYPC brings the PHY out of SMBus mode
 361                          * so ensure that the MAC is also out of SMBus mode
 362                          */
 363                         mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
 364                         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 365                         E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
 366
 367                         if (e1000_phy_is_accessible_pchlan(hw))
 368                                 break;
 369
 370                         ret_val = -E1000_ERR_PHY;
 371                 }
 372                 break;
 373         default:
 374                 break;
 375         }
 376
 377         hw->phy.ops.release(hw);
 378         if (!ret_val) {
 379
 380                 /* Check to see if able to reset PHY.  Print error if not */
 381                 if (hw->phy.ops.check_reset_block(hw)) {
 382                         ERROR_REPORT("Reset blocked by ME\n");
 383                         goto out;
 384                 }
 385
 386                 /* Reset the PHY before any access to it.  Doing so, ensures
 387                  * that the PHY is in a known good state before we read/write
 388                  * PHY registers.  The generic reset is sufficient here,
 389                  * because we haven't determined the PHY type yet.
 390                  */
 391                 ret_val = e1000_phy_hw_reset_generic(hw);
 392                 if (ret_val)
 393                         goto out;
 394
 395                 /* On a successful reset, possibly need to wait for the PHY
 396                  * to quiesce to an accessible state before returning control
 397                  * to the calling function.  If the PHY does not quiesce, then
 398                  * return E1000E_BLK_PHY_RESET, as this is the condition that
 399                  *  the PHY is in.
 400                  */
 401                 ret_val = hw->phy.ops.check_reset_block(hw);
 402                 if (ret_val)
 403                         ERROR_REPORT("ME blocked access to PHY after reset\n");
 404         }
 405
 406 out:
 407         /* Ungate automatic PHY configuration on non-managed 82579 */
 408         if ((hw->mac.type == e1000_pch2lan) &&
 409             !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
 410                 msec_delay(10);
 411                 e1000_gate_hw_phy_config_ich8lan(hw, false);
 412         }
 413
 414         return ret_val;
 415 }
 416
 417 /**
 418  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 419  *  @hw: pointer to the HW structure
 420  *
 421  *  Initialize family-specific PHY parameters and function pointers.
 422  **/
 423 STATIC s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 424 {
 425         struct e1000_phy_info *phy = &hw->phy;
 426         s32 ret_val;
 427
 428         DEBUGFUNC("e1000_init_phy_params_pchlan");
 429
 430         phy->addr               = 1;
 431         phy->reset_delay_us     = 100;
 432
 433         phy->ops.acquire        = e1000_acquire_swflag_ich8lan;
 434         phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
 435         phy->ops.get_cfg_done   = e1000_get_cfg_done_ich8lan;
 436         phy->ops.set_page       = e1000_set_page_igp;
 437         phy->ops.read_reg       = e1000_read_phy_reg_hv;
 438         phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
 439         phy->ops.read_reg_page  = e1000_read_phy_reg_page_hv;
 440         phy->ops.release        = e1000_release_swflag_ich8lan;
 441         phy->ops.reset          = e1000_phy_hw_reset_ich8lan;
 442         phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
 443         phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
 444         phy->ops.write_reg      = e1000_write_phy_reg_hv;
 445         phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
 446         phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
 447         phy->ops.power_up       = e1000_power_up_phy_copper;
 448         phy->ops.power_down     = e1000_power_down_phy_copper_ich8lan;
 449         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 450
 451         phy->id = e1000_phy_unknown;
 452
 453         ret_val = e1000_init_phy_workarounds_pchlan(hw);
 454         if (ret_val)
 455                 return ret_val;
 456
 457         if (phy->id == e1000_phy_unknown)
 458                 switch (hw->mac.type) {
 459                 default:
 460                         ret_val = e1000_get_phy_id(hw);
 461                         if (ret_val)
 462                                 return ret_val;
 463                         if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
 464                                 break;
 465                         /* fall-through */
 466                 case e1000_pch2lan:
 467                 case e1000_pch_lpt:
 468                 case e1000_pch_spt:
 469                 case e1000_pch_cnp:
 470                         /* In case the PHY needs to be in mdio slow mode,
 471                          * set slow mode and try to get the PHY id again.
 472                          */
 473                         ret_val = e1000_set_mdio_slow_mode_hv(hw);
 474                         if (ret_val)
 475                                 return ret_val;
 476                         ret_val = e1000_get_phy_id(hw);
 477                         if (ret_val)
 478                                 return ret_val;
 479                         break;
 480                 }
 481         phy->type = e1000_get_phy_type_from_id(phy->id);
 482
 483         switch (phy->type) {
 484         case e1000_phy_82577:
 485         case e1000_phy_82579:
 486         case e1000_phy_i217:
 487                 phy->ops.check_polarity = e1000_check_polarity_82577;
 488                 phy->ops.force_speed_duplex =
 489                         e1000_phy_force_speed_duplex_82577;
 490                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 491                 phy->ops.get_info = e1000_get_phy_info_82577;
 492                 phy->ops.commit = e1000_phy_sw_reset_generic;
 493                 break;
 494         case e1000_phy_82578:
 495                 phy->ops.check_polarity = e1000_check_polarity_m88;
 496                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 497                 phy->ops.get_cable_length = e1000_get_cable_length_m88;
 498                 phy->ops.get_info = e1000_get_phy_info_m88;
 499                 break;
 500         default:
 501                 ret_val = -E1000_ERR_PHY;
 502                 break;
 503         }
 504
 505         return ret_val;
 506 }
 507
 508 /**
 509  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 510  *  @hw: pointer to the HW structure
 511  *
 512  *  Initialize family-specific PHY parameters and function pointers.
 513  **/
 514 STATIC s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 515 {
 516         struct e1000_phy_info *phy = &hw->phy;
 517         s32 ret_val;
 518         u16 i = 0;
 519
 520         DEBUGFUNC("e1000_init_phy_params_ich8lan");
 521
 522         phy->addr               = 1;
 523         phy->reset_delay_us     = 100;
 524
 525         phy->ops.acquire        = e1000_acquire_swflag_ich8lan;
 526         phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
 527         phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
 528         phy->ops.get_cfg_done   = e1000_get_cfg_done_ich8lan;
 529         phy->ops.read_reg       = e1000_read_phy_reg_igp;
 530         phy->ops.release        = e1000_release_swflag_ich8lan;
 531         phy->ops.reset          = e1000_phy_hw_reset_ich8lan;
 532         phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
 533         phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
 534         phy->ops.write_reg      = e1000_write_phy_reg_igp;
 535         phy->ops.power_up       = e1000_power_up_phy_copper;
 536         phy->ops.power_down     = e1000_power_down_phy_copper_ich8lan;
 537
 538         /* We may need to do this twice - once for IGP and if that fails,
 539          * we'll set BM func pointers and try again
 540          */
 541         ret_val = e1000_determine_phy_address(hw);
 542         if (ret_val) {
 543                 phy->ops.write_reg = e1000_write_phy_reg_bm;
 544                 phy->ops.read_reg  = e1000_read_phy_reg_bm;
 545                 ret_val = e1000_determine_phy_address(hw);
 546                 if (ret_val) {
 547                         DEBUGOUT("Cannot determine PHY addr. Erroring out\n");
 548                         return ret_val;
 549                 }
 550         }
 551
 552         phy->id = 0;
 553         while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) &&
 554                (i++ < 100)) {
 555                 msec_delay(1);
 556                 ret_val = e1000_get_phy_id(hw);
 557                 if (ret_val)
 558                         return ret_val;
 559         }
 560
 561         /* Verify phy id */
 562         switch (phy->id) {
 563         case IGP03E1000_E_PHY_ID:
 564                 phy->type = e1000_phy_igp_3;
 565                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 566                 phy->ops.read_reg_locked = e1000_read_phy_reg_igp_locked;
 567                 phy->ops.write_reg_locked = e1000_write_phy_reg_igp_locked;
 568                 phy->ops.get_info = e1000_get_phy_info_igp;
 569                 phy->ops.check_polarity = e1000_check_polarity_igp;
 570                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
 571                 break;
 572         case IFE_E_PHY_ID:
 573         case IFE_PLUS_E_PHY_ID:
 574         case IFE_C_E_PHY_ID:
 575                 phy->type = e1000_phy_ife;
 576                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 577                 phy->ops.get_info = e1000_get_phy_info_ife;
 578                 phy->ops.check_polarity = e1000_check_polarity_ife;
 579                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
 580                 break;
 581         case BME1000_E_PHY_ID:
 582                 phy->type = e1000_phy_bm;
 583                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 584                 phy->ops.read_reg = e1000_read_phy_reg_bm;
 585                 phy->ops.write_reg = e1000_write_phy_reg_bm;
 586                 phy->ops.commit = e1000_phy_sw_reset_generic;
 587                 phy->ops.get_info = e1000_get_phy_info_m88;
 588                 phy->ops.check_polarity = e1000_check_polarity_m88;
 589                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 590                 break;
 591         default:
 592                 return -E1000_ERR_PHY;
 593                 break;
 594         }
 595
 596         return E1000_SUCCESS;
 597 }
 598
 599 /**
 600  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 601  *  @hw: pointer to the HW structure
 602  *
 603  *  Initialize family-specific NVM parameters and function
 604  *  pointers.
 605  **/
 606 STATIC s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 607 {
 608         struct e1000_nvm_info *nvm = &hw->nvm;
 609         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 610         u32 gfpreg, sector_base_addr, sector_end_addr;
 611         u16 i;
 612         u32 nvm_size;
 613
 614         DEBUGFUNC("e1000_init_nvm_params_ich8lan");
 615
 616         nvm->type = e1000_nvm_flash_sw;
 617
 618         if (hw->mac.type >= e1000_pch_spt) {
 619                 /* in SPT, gfpreg doesn't exist. NVM size is taken from the
 620                  * STRAP register. This is because in SPT the GbE Flash region
 621                  * is no longer accessed through the flash registers. Instead,
 622                  * the mechanism has changed, and the Flash region access
 623                  * registers are now implemented in GbE memory space.
 624                  */
 625                 nvm->flash_base_addr = 0;
 626                 nvm_size =
 627                     (((E1000_READ_REG(hw, E1000_STRAP) >> 1) & 0x1F) + 1)
 628                     * NVM_SIZE_MULTIPLIER;
 629                 nvm->flash_bank_size = nvm_size / 2;
 630                 /* Adjust to word count */
 631                 nvm->flash_bank_size /= sizeof(u16);
 632                 /* Set the base address for flash register access */
 633                 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;
 634         } else {
 635                 /* Can't read flash registers if register set isn't mapped. */
 636                 if (!hw->flash_address) {
 637                         DEBUGOUT("ERROR: Flash registers not mapped\n");
 638                         return -E1000_ERR_CONFIG;
 639                 }
 640
 641                 gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
 642
 643                 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
 644                  * Add 1 to sector_end_addr since this sector is included in
 645                  * the overall size.
 646                  */
 647                 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 648                 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 649
 650                 /* flash_base_addr is byte-aligned */
 651                 nvm->flash_base_addr = sector_base_addr
 652                                        << FLASH_SECTOR_ADDR_SHIFT;
 653
 654                 /* find total size of the NVM, then cut in half since the total
 655                  * size represents two separate NVM banks.
 656                  */
 657                 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
 658                                         << FLASH_SECTOR_ADDR_SHIFT);
 659                 nvm->flash_bank_size /= 2;
 660                 /* Adjust to word count */
 661                 nvm->flash_bank_size /= sizeof(u16);
 662         }
 663
 664         nvm->word_size = E1000_SHADOW_RAM_WORDS;
 665
 666         /* Clear shadow ram */
 667         for (i = 0; i < nvm->word_size; i++) {
 668                 dev_spec->shadow_ram[i].modified = false;
 669                 dev_spec->shadow_ram[i].value    = 0xFFFF;
 670         }
 671
 672         E1000_MUTEX_INIT(&dev_spec->nvm_mutex);
 673         E1000_MUTEX_INIT(&dev_spec->swflag_mutex);
 674
 675         /* Function Pointers */
 676         nvm->ops.acquire        = e1000_acquire_nvm_ich8lan;
 677         nvm->ops.release        = e1000_release_nvm_ich8lan;
 678         if (hw->mac.type >= e1000_pch_spt) {
 679                 nvm->ops.read   = e1000_read_nvm_spt;
 680                 nvm->ops.update = e1000_update_nvm_checksum_spt;
 681         } else {
 682                 nvm->ops.read   = e1000_read_nvm_ich8lan;
 683                 nvm->ops.update = e1000_update_nvm_checksum_ich8lan;
 684         }
 685         nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
 686         nvm->ops.validate       = e1000_validate_nvm_checksum_ich8lan;
 687         nvm->ops.write          = e1000_write_nvm_ich8lan;
 688
 689         return E1000_SUCCESS;
 690 }
 691
 692 /**
 693  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 694  *  @hw: pointer to the HW structure
 695  *
 696  *  Initialize family-specific MAC parameters and function
 697  *  pointers.
 698  **/
 699 STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
 700 {
 701         struct e1000_mac_info *mac = &hw->mac;
 702 #if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
 703         u16 pci_cfg;
 704 #endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */
 705
 706         DEBUGFUNC("e1000_init_mac_params_ich8lan");
 707
 708         /* Set media type function pointer */
 709         hw->phy.media_type = e1000_media_type_copper;
 710
 711         /* Set mta register count */
 712         mac->mta_reg_count = 32;
 713         /* Set rar entry count */
 714         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 715         if (mac->type == e1000_ich8lan)
 716                 mac->rar_entry_count--;
 717         /* Set if part includes ASF firmware */
 718         mac->asf_firmware_present = true;
 719         /* FWSM register */
 720         mac->has_fwsm = true;
 721         /* ARC subsystem not supported */
 722         mac->arc_subsystem_valid = false;
 723         /* Adaptive IFS supported */
 724         mac->adaptive_ifs = true;
 725
 726         /* Function pointers */
 727
 728         /* bus type/speed/width */
 729         mac->ops.get_bus_info = e1000_get_bus_info_ich8lan;
 730         /* function id */
 731         mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 732         /* reset */
 733         mac->ops.reset_hw = e1000_reset_hw_ich8lan;
 734         /* hw initialization */
 735         mac->ops.init_hw = e1000_init_hw_ich8lan;
 736         /* link setup */
 737         mac->ops.setup_link = e1000_setup_link_ich8lan;
 738         /* physical interface setup */
 739         mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan;
 740         /* check for link */
 741         mac->ops.check_for_link = e1000_check_for_copper_link_ich8lan;
 742         /* link info */
 743         mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan;
 744         /* multicast address update */
 745         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 746         /* clear hardware counters */
 747         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan;
 748
 749         /* LED and other operations */
 750         switch (mac->type) {
 751         case e1000_ich8lan:
 752         case e1000_ich9lan:
 753         case e1000_ich10lan:
 754                 /* check management mode */
 755                 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 756                 /* ID LED init */
 757                 mac->ops.id_led_init = e1000_id_led_init_generic;
 758                 /* blink LED */
 759                 mac->ops.blink_led = e1000_blink_led_generic;
 760                 /* setup LED */
 761                 mac->ops.setup_led = e1000_setup_led_generic;
 762                 /* cleanup LED */
 763                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 764                 /* turn on/off LED */
 765                 mac->ops.led_on = e1000_led_on_ich8lan;
 766                 mac->ops.led_off = e1000_led_off_ich8lan;
 767                 break;
 768         case e1000_pch2lan:
 769                 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
 770                 mac->ops.rar_set = e1000_rar_set_pch2lan;
 771                 /* fall-through */
 772         case e1000_pch_lpt:
 773         case e1000_pch_spt:
 774         case e1000_pch_cnp:
 775 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
 776                 /* multicast address update for pch2 */
 777                 mac->ops.update_mc_addr_list =
 778                         e1000_update_mc_addr_list_pch2lan;
 779                 /* fall-through */
 780 #endif
 781         case e1000_pchlan:
 782 #if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
 783                 /* save PCH revision_id */
 784                 e1000_read_pci_cfg(hw, E1000_PCI_REVISION_ID_REG, &pci_cfg);
 785                 /* SPT uses full byte for revision ID,
 786                  * as opposed to previous generations
 787                  */
 788                 if (hw->mac.type >= e1000_pch_spt)
 789                         hw->revision_id = (u8)(pci_cfg &= 0x00FF);
 790                 else
 791                         hw->revision_id = (u8)(pci_cfg &= 0x000F);
 792 #endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */
 793                 /* check management mode */
 794                 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 795                 /* ID LED init */
 796                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 797                 /* setup LED */
 798                 mac->ops.setup_led = e1000_setup_led_pchlan;
 799                 /* cleanup LED */
 800                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 801                 /* turn on/off LED */
 802                 mac->ops.led_on = e1000_led_on_pchlan;
 803                 mac->ops.led_off = e1000_led_off_pchlan;
 804                 break;
 805         default:
 806                 break;
 807         }
 808
 809         if (mac->type >= e1000_pch_lpt) {
 810                 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
 811                 mac->ops.rar_set = e1000_rar_set_pch_lpt;
 812                 mac->ops.setup_physical_interface = e1000_setup_copper_link_pch_lpt;
 813         }
 814
 815         /* Enable PCS Lock-loss workaround for ICH8 */
 816         if (mac->type == e1000_ich8lan)
 817                 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
 818
 819         return E1000_SUCCESS;
 820 }
 821
 822 /**
 823  *  __e1000_access_emi_reg_locked - Read/write EMI register
 824  *  @hw: pointer to the HW structure
 825  *  @addr: EMI address to program
 826  *  @data: pointer to value to read/write from/to the EMI address
 827  *  @read: boolean flag to indicate read or write
 828  *
 829  *  This helper function assumes the SW/FW/HW Semaphore is already acquired.
 830  **/
 831 STATIC s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
 832                                          u16 *data, bool read)
 833 {
 834         s32 ret_val;
 835
 836         DEBUGFUNC("__e1000_access_emi_reg_locked");
 837
 838         ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address);
 839         if (ret_val)
 840                 return ret_val;
 841
 842         if (read)
 843                 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA,
 844                                                       data);
 845         else
 846                 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
 847                                                        *data);
 848
 849         return ret_val;
 850 }
 851
 852 /**
 853  *  e1000_read_emi_reg_locked - Read Extended Management Interface register
 854  *  @hw: pointer to the HW structure
 855  *  @addr: EMI address to program
 856  *  @data: value to be read from the EMI address
 857  *
 858  *  Assumes the SW/FW/HW Semaphore is already acquired.
 859  **/
 860 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
 861 {
 862         DEBUGFUNC("e1000_read_emi_reg_locked");
 863
 864         return __e1000_access_emi_reg_locked(hw, addr, data, true);
 865 }
 866
 867 /**
 868  *  e1000_write_emi_reg_locked - Write Extended Management Interface register
 869  *  @hw: pointer to the HW structure
 870  *  @addr: EMI address to program
 871  *  @data: value to be written to the EMI address
 872  *
 873  *  Assumes the SW/FW/HW Semaphore is already acquired.
 874  **/
 875 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
 876 {
 877         DEBUGFUNC("e1000_read_emi_reg_locked");
 878
 879         return __e1000_access_emi_reg_locked(hw, addr, &data, false);
 880 }
 881
 882 /**
 883  *  e1000_set_eee_pchlan - Enable/disable EEE support
 884  *  @hw: pointer to the HW structure
 885  *
 886  *  Enable/disable EEE based on setting in dev_spec structure, the duplex of
 887  *  the link and the EEE capabilities of the link partner.  The LPI Control
 888  *  register bits will remain set only if/when link is up.
 889  *
 890  *  EEE LPI must not be asserted earlier than one second after link is up.
 891  *  On 82579, EEE LPI should not be enabled until such time otherwise there
 892  *  can be link issues with some switches.  Other devices can have EEE LPI
 893  *  enabled immediately upon link up since they have a timer in hardware which
 894  *  prevents LPI from being asserted too early.
 895  **/
 896 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 897 {
 898         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 899         s32 ret_val;
 900         u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
 901
 902         DEBUGFUNC("e1000_set_eee_pchlan");
 903
 904         switch (hw->phy.type) {
 905         case e1000_phy_82579:
 906                 lpa = I82579_EEE_LP_ABILITY;
 907                 pcs_status = I82579_EEE_PCS_STATUS;
 908                 adv_addr = I82579_EEE_ADVERTISEMENT;
 909                 break;
 910         case e1000_phy_i217:
 911                 lpa = I217_EEE_LP_ABILITY;
 912                 pcs_status = I217_EEE_PCS_STATUS;
 913                 adv_addr = I217_EEE_ADVERTISEMENT;
 914                 break;
 915         default:
 916                 return E1000_SUCCESS;
 917         }
 918
 919         ret_val = hw->phy.ops.acquire(hw);
 920         if (ret_val)
 921                 return ret_val;
 922
 923         ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
 924         if (ret_val)
 925                 goto release;
 926
 927         /* Clear bits that enable EEE in various speeds */
 928         lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
 929
 930         /* Enable EEE if not disabled by user */
 931         if (!dev_spec->eee_disable) {
 932                 /* Save off link partner's EEE ability */
 933                 ret_val = e1000_read_emi_reg_locked(hw, lpa,
 934                                                     &dev_spec->eee_lp_ability);
 935                 if (ret_val)
 936                         goto release;
 937
 938                 /* Read EEE advertisement */
 939                 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
 940                 if (ret_val)
 941                         goto release;
 942
 943                 /* Enable EEE only for speeds in which the link partner is
 944                  * EEE capable and for which we advertise EEE.
 945                  */
 946                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
 947                         lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
 948
 949                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
 950                         hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data);
 951                         if (data & NWAY_LPAR_100TX_FD_CAPS)
 952                                 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
 953                         else
 954                                 /* EEE is not supported in 100Half, so ignore
 955                                  * partner's EEE in 100 ability if full-duplex
 956                                  * is not advertised.
 957                                  */
 958                                 dev_spec->eee_lp_ability &=
 959                                     ~I82579_EEE_100_SUPPORTED;
 960                 }
 961         }
 962
 963         if (hw->phy.type == e1000_phy_82579) {
 964                 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
 965                                                     &data);
 966                 if (ret_val)
 967                         goto release;
 968
 969                 data &= ~I82579_LPI_100_PLL_SHUT;
 970                 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
 971                                                      data);
 972         }
 973
 974         /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
 975         ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
 976         if (ret_val)
 977                 goto release;
 978
 979         ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
 980 release:
 981         hw->phy.ops.release(hw);
 982
 983         return ret_val;
 984 }
 985
 986 /**
 987  *  e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
 988  *  @hw:   pointer to the HW structure
 989  *  @link: link up bool flag
 990  *
 991  *  When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
 992  *  preventing further DMA write requests.  Workaround the issue by disabling
 993  *  the de-assertion of the clock request when in 1Gpbs mode.
 994  *  Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
 995  *  speeds in order to avoid Tx hangs.
 996  **/
 997 STATIC s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
 998 {
 999         u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
1000         u32 status = E1000_READ_REG(hw, E1000_STATUS);
1001         s32 ret_val = E1000_SUCCESS;
1002         u16 reg;
1003
1004         if (link && (status & E1000_STATUS_SPEED_1000)) {
1005                 ret_val = hw->phy.ops.acquire(hw);
1006                 if (ret_val)
1007                         return ret_val;
1008
1009                 ret_val =
1010                     e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
1011                                                &reg);
1012                 if (ret_val)
1013                         goto release;
1014
1015                 ret_val =
1016                     e1000_write_kmrn_reg_locked(hw,
1017                                                 E1000_KMRNCTRLSTA_K1_CONFIG,
1018                                                 reg &
1019                                                 ~E1000_KMRNCTRLSTA_K1_ENABLE);
1020                 if (ret_val)
1021                         goto release;
1022
1023                 usec_delay(10);
1024
1025                 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
1026                                 fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
1027
1028                 ret_val =
1029                     e1000_write_kmrn_reg_locked(hw,
1030                                                 E1000_KMRNCTRLSTA_K1_CONFIG,
1031                                                 reg);
1032 release:
1033                 hw->phy.ops.release(hw);
1034         } else {
1035                 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
1036                 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
1037
1038                 if ((hw->phy.revision > 5) || !link ||
1039                     ((status & E1000_STATUS_SPEED_100) &&
1040                      (status & E1000_STATUS_FD)))
1041                         goto update_fextnvm6;
1042
1043                 ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, &reg);
1044                 if (ret_val)
1045                         return ret_val;
1046
1047                 /* Clear link status transmit timeout */
1048                 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
1049
1050                 if (status & E1000_STATUS_SPEED_100) {
1051                         /* Set inband Tx timeout to 5x10us for 100Half */
1052                         reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1053
1054                         /* Do not extend the K1 entry latency for 100Half */
1055                         fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1056                 } else {
1057                         /* Set inband Tx timeout to 50x10us for 10Full/Half */
1058                         reg |= 50 <<
1059                                I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1060
1061                         /* Extend the K1 entry latency for 10 Mbps */
1062                         fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1063                 }
1064
1065                 ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg);
1066                 if (ret_val)
1067                         return ret_val;
1068
1069 update_fextnvm6:
1070                 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1071         }
1072
1073         return ret_val;
1074 }
1075
1076 #ifdef ULP_SUPPORT
1077 /**
1078  *  e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1079  *  @hw: pointer to the HW structure
1080  *  @to_sx: boolean indicating a system power state transition to Sx
1081  *
1082  *  When link is down, configure ULP mode to significantly reduce the power
1083  *  to the PHY.  If on a Manageability Engine (ME) enabled system, tell the
1084  *  ME firmware to start the ULP configuration.  If not on an ME enabled
1085  *  system, configure the ULP mode by software.
1086  */
1087 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1088 {
1089         u32 mac_reg;
1090         s32 ret_val = E1000_SUCCESS;
1091         u16 phy_reg;
1092         u16 oem_reg = 0;
1093
1094         if ((hw->mac.type < e1000_pch_lpt) ||
1095             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1096             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1097             (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1098             (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1099             (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1100                 return 0;
1101
1102         if (!to_sx) {
1103                 int i = 0;
1104                 /* Poll up to 5 seconds for Cable Disconnected indication */
1105                 while (!(E1000_READ_REG(hw, E1000_FEXT) &
1106                          E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1107                         /* Bail if link is re-acquired */
1108                         if (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)
1109                                 return -E1000_ERR_PHY;
1110                         if (i++ == 100)
1111                                 break;
1112
1113                         msec_delay(50);
1114                 }
1115                 DEBUGOUT2("CABLE_DISCONNECTED %s set after %dmsec\n",
1116                           (E1000_READ_REG(hw, E1000_FEXT) &
1117                            E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not",
1118                           i * 50);
1119                 if (!(E1000_READ_REG(hw, E1000_FEXT) &
1120                     E1000_FEXT_PHY_CABLE_DISCONNECTED))
1121                         return 0;
1122         }
1123
1124         if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1125                 /* Request ME configure ULP mode in the PHY */
1126                 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1127                 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1128                 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1129
1130                 goto out;
1131         }
1132
1133         ret_val = hw->phy.ops.acquire(hw);
1134         if (ret_val)
1135                 goto out;
1136
1137         /* During S0 Idle keep the phy in PCI-E mode */
1138         if (hw->dev_spec.ich8lan.smbus_disable)
1139                 goto skip_smbus;
1140
1141         /* Force SMBus mode in PHY */
1142         ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1143         if (ret_val)
1144                 goto release;
1145         phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1146         e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1147
1148         /* Force SMBus mode in MAC */
1149         mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1150         mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1151         E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1152
1153         /* Si workaround for ULP entry flow on i127/rev6 h/w.  Enable
1154          * LPLU and disable Gig speed when entering ULP
1155          */
1156         if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) {
1157                 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
1158                                                        &oem_reg);
1159                 if (ret_val)
1160                         goto release;
1161
1162                 phy_reg = oem_reg;
1163                 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS;
1164
1165                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1166                                                         phy_reg);
1167
1168                 if (ret_val)
1169                         goto release;
1170         }
1171
1172 skip_smbus:
1173         if (!to_sx) {
1174                 /* Change the 'Link Status Change' interrupt to trigger
1175                  * on 'Cable Status Change'
1176                  */
1177                 ret_val = e1000_read_kmrn_reg_locked(hw,
1178                                                      E1000_KMRNCTRLSTA_OP_MODES,
1179                                                      &phy_reg);
1180                 if (ret_val)
1181                         goto release;
1182                 phy_reg |= E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC;
1183                 e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES,
1184                                             phy_reg);
1185         }
1186
1187         /* Set Inband ULP Exit, Reset to SMBus mode and
1188          * Disable SMBus Release on PERST# in PHY
1189          */
1190         ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1191         if (ret_val)
1192                 goto release;
1193         phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1194                     I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1195         if (to_sx) {
1196                 if (E1000_READ_REG(hw, E1000_WUFC) & E1000_WUFC_LNKC)
1197                         phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1198                 else
1199                         phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1200
1201                 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1202                 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT;
1203         } else {
1204                 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1205                 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP;
1206                 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1207         }
1208         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1209
1210         /* Set Disable SMBus Release on PERST# in MAC */
1211         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1212         mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1213         E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1214
1215         /* Commit ULP changes in PHY by starting auto ULP configuration */
1216         phy_reg |= I218_ULP_CONFIG1_START;
1217         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1218
1219         if (!to_sx) {
1220                 /* Disable Tx so that the MAC doesn't send any (buffered)
1221                  * packets to the PHY.
1222                  */
1223                 mac_reg = E1000_READ_REG(hw, E1000_TCTL);
1224                 mac_reg &= ~E1000_TCTL_EN;
1225                 E1000_WRITE_REG(hw, E1000_TCTL, mac_reg);
1226         }
1227
1228         if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&
1229             to_sx && (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1230                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1231                                                         oem_reg);
1232                 if (ret_val)
1233                         goto release;
1234         }
1235
1236 release:
1237         hw->phy.ops.release(hw);
1238 out:
1239         if (ret_val)
1240                 DEBUGOUT1("Error in ULP enable flow: %d\n", ret_val);
1241         else
1242                 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1243
1244         return ret_val;
1245 }
1246
1247 /**
1248  *  e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1249  *  @hw: pointer to the HW structure
1250  *  @force: boolean indicating whether or not to force disabling ULP
1251  *
1252  *  Un-configure ULP mode when link is up, the system is transitioned from
1253  *  Sx or the driver is unloaded.  If on a Manageability Engine (ME) enabled
1254  *  system, poll for an indication from ME that ULP has been un-configured.
1255  *  If not on an ME enabled system, un-configure the ULP mode by software.
1256  *
1257  *  During nominal operation, this function is called when link is acquired
1258  *  to disable ULP mode (force=false); otherwise, for example when unloading
1259  *  the driver or during Sx->S0 transitions, this is called with force=true
1260  *  to forcibly disable ULP.
1261
1262  *  When the cable is plugged in while the device is in D0, a Cable Status
1263  *  Change interrupt is generated which causes this function to be called
1264  *  to partially disable ULP mode and restart autonegotiation.  This function
1265  *  is then called again due to the resulting Link Status Change interrupt
1266  *  to finish cleaning up after the ULP flow.
1267  */
1268 s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1269 {
1270         s32 ret_val = E1000_SUCCESS;
1271         u32 mac_reg;
1272         u16 phy_reg;
1273         int i = 0;
1274
1275         if ((hw->mac.type < e1000_pch_lpt) ||
1276             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1277             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1278             (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1279             (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1280             (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1281                 return 0;
1282
1283         if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1284                 if (force) {
1285                         /* Request ME un-configure ULP mode in the PHY */
1286                         mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1287                         mac_reg &= ~E1000_H2ME_ULP;
1288                         mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1289                         E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1290                 }
1291
1292                 /* Poll up to 300msec for ME to clear ULP_CFG_DONE. */
1293                 while (E1000_READ_REG(hw, E1000_FWSM) &
1294                        E1000_FWSM_ULP_CFG_DONE) {
1295                         if (i++ == 30) {
1296                                 ret_val = -E1000_ERR_PHY;
1297                                 goto out;
1298                         }
1299
1300                         msec_delay(10);
1301                 }
1302                 DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1303
1304                 if (force) {
1305                         mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1306                         mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1307                         E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1308                 } else {
1309                         /* Clear H2ME.ULP after ME ULP configuration */
1310                         mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1311                         mac_reg &= ~E1000_H2ME_ULP;
1312                         E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1313
1314                         /* Restore link speed advertisements and restart
1315                          * Auto-negotiation
1316                          */
1317                         if (hw->mac.autoneg) {
1318                                 ret_val = e1000_phy_setup_autoneg(hw);
1319                                 if (ret_val)
1320                                         goto out;
1321                         } else {
1322                                 ret_val = e1000_setup_copper_link_generic(hw);
1323                                 if (ret_val)
1324                                         goto out;
1325                         }
1326                         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1327                 }
1328
1329                 goto out;
1330         }
1331
1332         ret_val = hw->phy.ops.acquire(hw);
1333         if (ret_val)
1334                 goto out;
1335
1336         /* Revert the change to the 'Link Status Change'
1337          * interrupt to trigger on 'Cable Status Change'
1338          */
1339         ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES,
1340                                              &phy_reg);
1341         if (ret_val)
1342                 goto release;
1343         phy_reg &= ~E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC;
1344         e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES, phy_reg);
1345
1346         if (force)
1347                 /* Toggle LANPHYPC Value bit */
1348                 e1000_toggle_lanphypc_pch_lpt(hw);
1349
1350         /* Unforce SMBus mode in PHY */
1351         ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1352         if (ret_val) {
1353                 /* The MAC might be in PCIe mode, so temporarily force to
1354                  * SMBus mode in order to access the PHY.
1355                  */
1356                 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1357                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1358                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1359
1360                 msec_delay(50);
1361
1362                 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1363                                                        &phy_reg);
1364                 if (ret_val)
1365                         goto release;
1366         }
1367         phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1368         e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1369
1370         /* Unforce SMBus mode in MAC */
1371         mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1372         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1373         E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1374
1375         /* When ULP mode was previously entered, K1 was disabled by the
1376          * hardware.  Re-Enable K1 in the PHY when exiting ULP.
1377          */
1378         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1379         if (ret_val)
1380                 goto release;
1381         phy_reg |= HV_PM_CTRL_K1_ENABLE;
1382         e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1383
1384         /* Clear ULP enabled configuration */
1385         ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1386         if (ret_val)
1387                 goto release;
1388         /* CSC interrupt received due to ULP Indication */
1389         if ((phy_reg & I218_ULP_CONFIG1_IND) || force) {
1390                 phy_reg &= ~(I218_ULP_CONFIG1_IND |
1391                              I218_ULP_CONFIG1_STICKY_ULP |
1392                              I218_ULP_CONFIG1_RESET_TO_SMBUS |
1393                              I218_ULP_CONFIG1_WOL_HOST |
1394                              I218_ULP_CONFIG1_INBAND_EXIT |
1395                              I218_ULP_CONFIG1_EN_ULP_LANPHYPC |
1396                              I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST |
1397                              I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1398                 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1399
1400                 /* Commit ULP changes by starting auto ULP configuration */
1401                 phy_reg |= I218_ULP_CONFIG1_START;
1402                 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1403
1404                 /* Clear Disable SMBus Release on PERST# in MAC */
1405                 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1406                 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1407                 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1408
1409                 if (!force) {
1410                         hw->phy.ops.release(hw);
1411
1412                         if (hw->mac.autoneg)
1413                                 e1000_phy_setup_autoneg(hw);
1414                         else
1415                                 e1000_setup_copper_link_generic(hw);
1416
1417                         e1000_sw_lcd_config_ich8lan(hw);
1418
1419                         e1000_oem_bits_config_ich8lan(hw, true);
1420
1421                         /* Set ULP state to unknown and return non-zero to
1422                          * indicate no link (yet) and re-enter on the next LSC
1423                          * to finish disabling ULP flow.
1424                          */
1425                         hw->dev_spec.ich8lan.ulp_state =
1426                             e1000_ulp_state_unknown;
1427
1428                         return 1;
1429                 }
1430         }
1431
1432         /* Re-enable Tx */
1433         mac_reg = E1000_READ_REG(hw, E1000_TCTL);
1434         mac_reg |= E1000_TCTL_EN;
1435         E1000_WRITE_REG(hw, E1000_TCTL, mac_reg);
1436
1437 release:
1438         hw->phy.ops.release(hw);
1439         if (force) {
1440                 hw->phy.ops.reset(hw);
1441                 msec_delay(50);
1442         }
1443 out:
1444         if (ret_val)
1445                 DEBUGOUT1("Error in ULP disable flow: %d\n", ret_val);
1446         else
1447                 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1448
1449         return ret_val;
1450 }
1451
1452 #endif /* ULP_SUPPORT */
1453
1454
1455 /**
1456  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1457  *  @hw: pointer to the HW structure
1458  *
1459  *  Checks to see of the link status of the hardware has changed.  If a
1460  *  change in link status has been detected, then we read the PHY registers
1461  *  to get the current speed/duplex if link exists.
1462  **/
1463 STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1464 {
1465         struct e1000_mac_info *mac = &hw->mac;
1466         s32 ret_val, tipg_reg = 0;
1467         u16 emi_addr, emi_val = 0;
1468         bool link = false;
1469         u16 phy_reg;
1470
1471         DEBUGFUNC("e1000_check_for_copper_link_ich8lan");
1472
1473         /* We only want to go out to the PHY registers to see if Auto-Neg
1474          * has completed and/or if our link status has changed.  The
1475          * get_link_status flag is set upon receiving a Link Status
1476          * Change or Rx Sequence Error interrupt.
1477          */
1478         if (!mac->get_link_status)
1479                 return E1000_SUCCESS;
1480
1481         if ((hw->mac.type < e1000_pch_lpt) ||
1482             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1483             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V)) {
1484                 /* First we want to see if the MII Status Register reports
1485                  * link.  If so, then we want to get the current speed/duplex
1486                  * of the PHY.
1487                  */
1488                 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1489                 if (ret_val)
1490                         return ret_val;
1491         } else {
1492                 /* Check the MAC's STATUS register to determine link state
1493                  * since the PHY could be inaccessible while in ULP mode.
1494                  */
1495                 link = !!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU);
1496                 if (link)
1497                         ret_val = e1000_disable_ulp_lpt_lp(hw, false);
1498                 else
1499                         ret_val = e1000_enable_ulp_lpt_lp(hw, false);
1500                 if (ret_val)
1501                         return ret_val;
1502         }
1503
1504         if (hw->mac.type == e1000_pchlan) {
1505                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1506                 if (ret_val)
1507                         return ret_val;
1508         }
1509
1510         /* When connected at 10Mbps half-duplex, some parts are excessively
1511          * aggressive resulting in many collisions. To avoid this, increase
1512          * the IPG and reduce Rx latency in the PHY.
1513          */
1514         if ((hw->mac.type >= e1000_pch2lan) && link) {
1515                 u16 speed, duplex;
1516
1517                 e1000_get_speed_and_duplex_copper_generic(hw, &speed, &duplex);
1518                 tipg_reg = E1000_READ_REG(hw, E1000_TIPG);
1519                 tipg_reg &= ~E1000_TIPG_IPGT_MASK;
1520
1521                 if (duplex == HALF_DUPLEX && speed == SPEED_10) {
1522                         tipg_reg |= 0xFF;
1523                         /* Reduce Rx latency in analog PHY */
1524                         emi_val = 0;
1525                 } else if (hw->mac.type >= e1000_pch_spt &&
1526                            duplex == FULL_DUPLEX && speed != SPEED_1000) {
1527                         tipg_reg |= 0xC;
1528                         emi_val = 1;
1529                 } else {
1530                         /* Roll back the default values */
1531                         tipg_reg |= 0x08;
1532                         emi_val = 1;
1533                 }
1534
1535                 E1000_WRITE_REG(hw, E1000_TIPG, tipg_reg);
1536
1537                 ret_val = hw->phy.ops.acquire(hw);
1538                 if (ret_val)
1539                         return ret_val;
1540
1541                 if (hw->mac.type == e1000_pch2lan)
1542                         emi_addr = I82579_RX_CONFIG;
1543                 else
1544                         emi_addr = I217_RX_CONFIG;
1545                 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
1546
1547
1548                 if (hw->mac.type >= e1000_pch_lpt) {
1549                         u16 phy_reg;
1550
1551                         hw->phy.ops.read_reg_locked(hw, I217_PLL_CLOCK_GATE_REG,
1552                                                     &phy_reg);
1553                         phy_reg &= ~I217_PLL_CLOCK_GATE_MASK;
1554                         if (speed == SPEED_100 || speed == SPEED_10)
1555                                 phy_reg |= 0x3E8;
1556                         else
1557                                 phy_reg |= 0xFA;
1558                         hw->phy.ops.write_reg_locked(hw,
1559                                                      I217_PLL_CLOCK_GATE_REG,
1560                                                      phy_reg);
1561
1562                         if (speed == SPEED_1000) {
1563                                 hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL,
1564                                                             &phy_reg);
1565
1566                                 phy_reg |= HV_PM_CTRL_K1_CLK_REQ;
1567
1568                                 hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL,
1569                                                              phy_reg);
1570                                 }
1571                  }
1572                 hw->phy.ops.release(hw);
1573
1574                 if (ret_val)
1575                         return ret_val;
1576
1577                 if (hw->mac.type >= e1000_pch_spt) {
1578                         u16 data;
1579                         u16 ptr_gap;
1580
1581                         if (speed == SPEED_1000) {
1582                                 ret_val = hw->phy.ops.acquire(hw);
1583                                 if (ret_val)
1584                                         return ret_val;
1585
1586                                 ret_val = hw->phy.ops.read_reg_locked(hw,
1587                                                               PHY_REG(776, 20),
1588                                                               &data);
1589                                 if (ret_val) {
1590                                         hw->phy.ops.release(hw);
1591                                         return ret_val;
1592                                 }
1593
1594                                 ptr_gap = (data & (0x3FF << 2)) >> 2;
1595                                 if (ptr_gap < 0x18) {
1596                                         data &= ~(0x3FF << 2);
1597                                         data |= (0x18 << 2);
1598                                         ret_val =
1599                                                 hw->phy.ops.write_reg_locked(hw,
1600                                                         PHY_REG(776, 20), data);
1601                                 }
1602                                 hw->phy.ops.release(hw);
1603                                 if (ret_val)
1604                                         return ret_val;
1605                         } else {
1606                                 ret_val = hw->phy.ops.acquire(hw);
1607                                 if (ret_val)
1608                                         return ret_val;
1609
1610                                 ret_val = hw->phy.ops.write_reg_locked(hw,
1611                                                              PHY_REG(776, 20),
1612                                                              0xC023);
1613                                 hw->phy.ops.release(hw);
1614                                 if (ret_val)
1615                                         return ret_val;
1616
1617                         }
1618                 }
1619         }
1620
1621         /* I217 Packet Loss issue:
1622          * ensure that FEXTNVM4 Beacon Duration is set correctly
1623          * on power up.
1624          * Set the Beacon Duration for I217 to 8 usec
1625          */
1626         if (hw->mac.type >= e1000_pch_lpt) {
1627                 u32 mac_reg;
1628
1629                 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
1630                 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1631                 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1632                 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
1633         }
1634
1635         /* Work-around I218 hang issue */
1636         if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1637             (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1638             (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) ||
1639             (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) {
1640                 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1641                 if (ret_val)
1642                         return ret_val;
1643         }
1644         /* Clear link partner's EEE ability */
1645         hw->dev_spec.ich8lan.eee_lp_ability = 0;
1646
1647         /* Configure K0s minimum time */
1648         if (hw->mac.type >= e1000_pch_lpt) {
1649                 e1000_configure_k0s_lpt(hw, K1_ENTRY_LATENCY, K1_MIN_TIME);
1650         }
1651
1652         if (hw->mac.type >= e1000_pch_lpt) {
1653                 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
1654
1655                 if (hw->mac.type == e1000_pch_spt) {
1656                         /* FEXTNVM6 K1-off workaround - for SPT only */
1657                         u32 pcieanacfg = E1000_READ_REG(hw, E1000_PCIEANACFG);
1658
1659                         if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE)
1660                                 fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE;
1661                         else
1662                                 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1663                 }
1664
1665                 if (hw->dev_spec.ich8lan.disable_k1_off == true)
1666                         fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1667
1668                 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1669         }
1670
1671         if (!link)
1672                 return E1000_SUCCESS; /* No link detected */
1673
1674         mac->get_link_status = false;
1675
1676         switch (hw->mac.type) {
1677         case e1000_pch2lan:
1678                 ret_val = e1000_k1_workaround_lv(hw);
1679                 if (ret_val)
1680                         return ret_val;
1681                 /* fall-thru */
1682         case e1000_pchlan:
1683                 if (hw->phy.type == e1000_phy_82578) {
1684                         ret_val = e1000_link_stall_workaround_hv(hw);
1685                         if (ret_val)
1686                                 return ret_val;
1687                 }
1688
1689                 /* Workaround for PCHx parts in half-duplex:
1690                  * Set the number of preambles removed from the packet
1691                  * when it is passed from the PHY to the MAC to prevent
1692                  * the MAC from misinterpreting the packet type.
1693                  */
1694                 hw->phy.ops.read_reg(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1695                 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1696
1697                 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FD) !=
1698                     E1000_STATUS_FD)
1699                         phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1700
1701                 hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1702                 break;
1703         default:
1704                 break;
1705         }
1706
1707         /* Check if there was DownShift, must be checked
1708          * immediately after link-up
1709          */
1710         e1000_check_downshift_generic(hw);
1711
1712         /* Enable/Disable EEE after link up */
1713         if (hw->phy.type > e1000_phy_82579) {
1714                 ret_val = e1000_set_eee_pchlan(hw);
1715                 if (ret_val)
1716                         return ret_val;
1717         }
1718
1719         /* If we are forcing speed/duplex, then we simply return since
1720          * we have already determined whether we have link or not.
1721          */
1722         if (!mac->autoneg)
1723                 return -E1000_ERR_CONFIG;
1724
1725         /* Auto-Neg is enabled.  Auto Speed Detection takes care
1726          * of MAC speed/duplex configuration.  So we only need to
1727          * configure Collision Distance in the MAC.
1728          */
1729         mac->ops.config_collision_dist(hw);
1730
1731         /* Configure Flow Control now that Auto-Neg has completed.
1732          * First, we need to restore the desired flow control
1733          * settings because we may have had to re-autoneg with a
1734          * different link partner.
1735          */
1736         ret_val = e1000_config_fc_after_link_up_generic(hw);
1737         if (ret_val)
1738                 DEBUGOUT("Error configuring flow control\n");
1739
1740         return ret_val;
1741 }
1742
1743 /**
1744  *  e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers
1745  *  @hw: pointer to the HW structure
1746  *
1747  *  Initialize family-specific function pointers for PHY, MAC, and NVM.
1748  **/
1749 void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
1750 {
1751         DEBUGFUNC("e1000_init_function_pointers_ich8lan");
1752
1753         hw->mac.ops.init_params = e1000_init_mac_params_ich8lan;
1754         hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;
1755         switch (hw->mac.type) {
1756         case e1000_ich8lan:
1757         case e1000_ich9lan:
1758         case e1000_ich10lan:
1759                 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
1760                 break;
1761         case e1000_pchlan:
1762         case e1000_pch2lan:
1763         case e1000_pch_lpt:
1764         case e1000_pch_spt:
1765         case e1000_pch_cnp:
1766                 hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
1767                 break;
1768         default:
1769                 break;
1770         }
1771 }
1772
1773 /**
1774  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1775  *  @hw: pointer to the HW structure
1776  *
1777  *  Acquires the mutex for performing NVM operations.
1778  **/
1779 STATIC s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
1780 {
1781         DEBUGFUNC("e1000_acquire_nvm_ich8lan");
1782
1783         E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1784
1785         return E1000_SUCCESS;
1786 }
1787
1788 /**
1789  *  e1000_release_nvm_ich8lan - Release NVM mutex
1790  *  @hw: pointer to the HW structure
1791  *
1792  *  Releases the mutex used while performing NVM operations.
1793  **/
1794 STATIC void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
1795 {
1796         DEBUGFUNC("e1000_release_nvm_ich8lan");
1797
1798         E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1799
1800         return;
1801 }
1802
1803 /**
1804  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
1805  *  @hw: pointer to the HW structure
1806  *
1807  *  Acquires the software control flag for performing PHY and select
1808  *  MAC CSR accesses.
1809  **/
1810 STATIC s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1811 {
1812         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1813         s32 ret_val = E1000_SUCCESS;
1814
1815         DEBUGFUNC("e1000_acquire_swflag_ich8lan");
1816
1817         E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1818
1819         while (timeout) {
1820                 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1821                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1822                         break;
1823
1824                 msec_delay_irq(1);
1825                 timeout--;
1826         }
1827
1828         if (!timeout) {
1829                 DEBUGOUT("SW has already locked the resource.\n");
1830                 ret_val = -E1000_ERR_CONFIG;
1831                 goto out;
1832         }
1833
1834         timeout = SW_FLAG_TIMEOUT;
1835
1836         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1837         E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1838
1839         while (timeout) {
1840                 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1841                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1842                         break;
1843
1844                 msec_delay_irq(1);
1845                 timeout--;
1846         }
1847
1848         if (!timeout) {
1849                 DEBUGOUT2("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1850                           E1000_READ_REG(hw, E1000_FWSM), extcnf_ctrl);
1851                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1852                 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1853                 ret_val = -E1000_ERR_CONFIG;
1854                 goto out;
1855         }
1856
1857 out:
1858         if (ret_val)
1859                 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1860
1861         return ret_val;
1862 }
1863
1864 /**
1865  *  e1000_release_swflag_ich8lan - Release software control flag
1866  *  @hw: pointer to the HW structure
1867  *
1868  *  Releases the software control flag for performing PHY and select
1869  *  MAC CSR accesses.
1870  **/
1871 STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1872 {
1873         u32 extcnf_ctrl;
1874
1875         DEBUGFUNC("e1000_release_swflag_ich8lan");
1876
1877         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1878
1879         if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1880                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1881                 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1882         } else {
1883                 DEBUGOUT("Semaphore unexpectedly released by sw/fw/hw\n");
1884         }
1885
1886         E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1887
1888         return;
1889 }
1890
1891 /**
1892  *  e1000_check_mng_mode_ich8lan - Checks management mode
1893  *  @hw: pointer to the HW structure
1894  *
1895  *  This checks if the adapter has any manageability enabled.
1896  *  This is a function pointer entry point only called by read/write
1897  *  routines for the PHY and NVM parts.
1898  **/
1899 STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1900 {
1901         u32 fwsm;
1902
1903         DEBUGFUNC("e1000_check_mng_mode_ich8lan");
1904
1905         fwsm = E1000_READ_REG(hw, E1000_FWSM);
1906
1907         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1908                ((fwsm & E1000_FWSM_MODE_MASK) ==
1909                 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1910 }
1911
1912 /**
1913  *  e1000_check_mng_mode_pchlan - Checks management mode
1914  *  @hw: pointer to the HW structure
1915  *
1916  *  This checks if the adapter has iAMT enabled.
1917  *  This is a function pointer entry point only called by read/write
1918  *  routines for the PHY and NVM parts.
1919  **/
1920 STATIC bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1921 {
1922         u32 fwsm;
1923
1924         DEBUGFUNC("e1000_check_mng_mode_pchlan");
1925
1926         fwsm = E1000_READ_REG(hw, E1000_FWSM);
1927
1928         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1929                (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1930 }
1931
1932 /**
1933  *  e1000_rar_set_pch2lan - Set receive address register
1934  *  @hw: pointer to the HW structure
1935  *  @addr: pointer to the receive address
1936  *  @index: receive address array register
1937  *
1938  *  Sets the receive address array register at index to the address passed
1939  *  in by addr.  For 82579, RAR[0] is the base address register that is to
1940  *  contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1941  *  Use SHRA[0-3] in place of those reserved for ME.
1942  **/
1943 STATIC int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1944 {
1945         u32 rar_low, rar_high;
1946
1947         DEBUGFUNC("e1000_rar_set_pch2lan");
1948
1949         /* HW expects these in little endian so we reverse the byte order
1950          * from network order (big endian) to little endian
1951          */
1952         rar_low = ((u32) addr[0] |
1953                    ((u32) addr[1] << 8) |
1954                    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
1955
1956         rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
1957
1958         /* If MAC address zero, no need to set the AV bit */
1959         if (rar_low || rar_high)
1960                 rar_high |= E1000_RAH_AV;
1961
1962         if (index == 0) {
1963                 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
1964                 E1000_WRITE_FLUSH(hw);
1965                 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
1966                 E1000_WRITE_FLUSH(hw);
1967                 return E1000_SUCCESS;
1968         }
1969
1970         /* RAR[1-6] are owned by manageability.  Skip those and program the
1971          * next address into the SHRA register array.
1972          */
1973         if (index < (u32) (hw->mac.rar_entry_count)) {
1974                 s32 ret_val;
1975
1976                 ret_val = e1000_acquire_swflag_ich8lan(hw);
1977                 if (ret_val)
1978                         goto out;
1979
1980                 E1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low);
1981                 E1000_WRITE_FLUSH(hw);
1982                 E1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high);
1983                 E1000_WRITE_FLUSH(hw);
1984
1985                 e1000_release_swflag_ich8lan(hw);
1986
1987                 /* verify the register updates */
1988                 if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) &&
1989                     (E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high))
1990                         return E1000_SUCCESS;
1991
1992                 DEBUGOUT2("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1993                          (index - 1), E1000_READ_REG(hw, E1000_FWSM));
1994         }
1995
1996 out:
1997         DEBUGOUT1("Failed to write receive address at index %d\n", index);
1998         return -E1000_ERR_CONFIG;
1999 }
2000
2001 /**
2002  *  e1000_rar_set_pch_lpt - Set receive address registers
2003  *  @hw: pointer to the HW structure
2004  *  @addr: pointer to the receive address
2005  *  @index: receive address array register
2006  *
2007  *  Sets the receive address register array at index to the address passed
2008  *  in by addr. For LPT, RAR[0] is the base address register that is to
2009  *  contain the MAC address. SHRA[0-10] are the shared receive address
2010  *  registers that are shared between the Host and manageability engine (ME).
2011  **/
2012 STATIC int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
2013 {
2014         u32 rar_low, rar_high;
2015         u32 wlock_mac;
2016
2017         DEBUGFUNC("e1000_rar_set_pch_lpt");
2018
2019         /* HW expects these in little endian so we reverse the byte order
2020          * from network order (big endian) to little endian
2021          */
2022         rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
2023                    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
2024
2025         rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
2026
2027         /* If MAC address zero, no need to set the AV bit */
2028         if (rar_low || rar_high)
2029                 rar_high |= E1000_RAH_AV;
2030
2031         if (index == 0) {
2032                 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
2033                 E1000_WRITE_FLUSH(hw);
2034                 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
2035                 E1000_WRITE_FLUSH(hw);
2036                 return E1000_SUCCESS;
2037         }
2038
2039         /* The manageability engine (ME) can lock certain SHRAR registers that
2040          * it is using - those registers are unavailable for use.
2041          */
2042         if (index < hw->mac.rar_entry_count) {
2043                 wlock_mac = E1000_READ_REG(hw, E1000_FWSM) &
2044                             E1000_FWSM_WLOCK_MAC_MASK;
2045                 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
2046
2047                 /* Check if all SHRAR registers are locked */
2048                 if (wlock_mac == 1)
2049                         goto out;
2050
2051                 if ((wlock_mac == 0) || (index <= wlock_mac)) {
2052                         s32 ret_val;
2053
2054                         ret_val = e1000_acquire_swflag_ich8lan(hw);
2055
2056                         if (ret_val)
2057                                 goto out;
2058
2059                         E1000_WRITE_REG(hw, E1000_SHRAL_PCH_LPT(index - 1),
2060                                         rar_low);
2061                         E1000_WRITE_FLUSH(hw);
2062                         E1000_WRITE_REG(hw, E1000_SHRAH_PCH_LPT(index - 1),
2063                                         rar_high);
2064                         E1000_WRITE_FLUSH(hw);
2065
2066                         e1000_release_swflag_ich8lan(hw);
2067
2068                         /* verify the register updates */
2069                         if ((E1000_READ_REG(hw, E1000_SHRAL_PCH_LPT(index - 1)) == rar_low) &&
2070                             (E1000_READ_REG(hw, E1000_SHRAH_PCH_LPT(index - 1)) == rar_high))
2071                                 return E1000_SUCCESS;
2072                 }
2073         }
2074
2075 out:
2076         DEBUGOUT1("Failed to write receive address at index %d\n", index);
2077         return -E1000_ERR_CONFIG;
2078 }
2079
2080 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
2081 /**
2082  *  e1000_update_mc_addr_list_pch2lan - Update Multicast addresses
2083  *  @hw: pointer to the HW structure
2084  *  @mc_addr_list: array of multicast addresses to program
2085  *  @mc_addr_count: number of multicast addresses to program
2086  *
2087  *  Updates entire Multicast Table Array of the PCH2 MAC and PHY.
2088  *  The caller must have a packed mc_addr_list of multicast addresses.
2089  **/
2090 STATIC void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
2091                                               u8 *mc_addr_list,
2092                                               u32 mc_addr_count)
2093 {
2094         u16 phy_reg = 0;
2095         int i;
2096         s32 ret_val;
2097
2098         DEBUGFUNC("e1000_update_mc_addr_list_pch2lan");
2099
2100         e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count);
2101
2102         ret_val = hw->phy.ops.acquire(hw);
2103         if (ret_val)
2104                 return;
2105
2106         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2107         if (ret_val)
2108                 goto release;
2109
2110         for (i = 0; i < hw->mac.mta_reg_count; i++) {
2111                 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
2112                                            (u16)(hw->mac.mta_shadow[i] &
2113                                                  0xFFFF));
2114                 hw->phy.ops.write_reg_page(hw, (BM_MTA(i) + 1),
2115                                            (u16)((hw->mac.mta_shadow[i] >> 16) &
2116                                                  0xFFFF));
2117         }
2118
2119         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2120
2121 release:
2122         hw->phy.ops.release(hw);
2123 }
2124
2125 #endif /* NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT */
2126 /**
2127  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
2128  *  @hw: pointer to the HW structure
2129  *
2130  *  Checks if firmware is blocking the reset of the PHY.
2131  *  This is a function pointer entry point only called by
2132  *  reset routines.
2133  **/
2134 STATIC s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
2135 {
2136         u32 fwsm;
2137         bool blocked = false;
2138         int i = 0;
2139
2140         DEBUGFUNC("e1000_check_reset_block_ich8lan");
2141
2142         do {
2143                 fwsm = E1000_READ_REG(hw, E1000_FWSM);
2144                 if (!(fwsm & E1000_ICH_FWSM_RSPCIPHY)) {
2145                         blocked = true;
2146                         msec_delay(10);
2147                         continue;
2148                 }
2149                 blocked = false;
2150         } while (blocked && (i++ < 30));
2151         return blocked ? E1000_BLK_PHY_RESET : E1000_SUCCESS;
2152 }
2153
2154 /**
2155  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2156  *  @hw: pointer to the HW structure
2157  *
2158  *  Assumes semaphore already acquired.
2159  *
2160  **/
2161 STATIC s32 e1000_write_smbus_addr(struct e1000_hw *hw)
2162 {
2163         u16 phy_data;
2164         u32 strap = E1000_READ_REG(hw, E1000_STRAP);
2165         u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
2166                 E1000_STRAP_SMT_FREQ_SHIFT;
2167         s32 ret_val;
2168
2169         strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
2170
2171         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2172         if (ret_val)
2173                 return ret_val;
2174
2175         phy_data &= ~HV_SMB_ADDR_MASK;
2176         phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
2177         phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
2178
2179         if (hw->phy.type == e1000_phy_i217) {
2180                 /* Restore SMBus frequency */
2181                 if (freq--) {
2182                         phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
2183                         phy_data |= (freq & (1 << 0)) <<
2184                                 HV_SMB_ADDR_FREQ_LOW_SHIFT;
2185                         phy_data |= (freq & (1 << 1)) <<
2186                                 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
2187                 } else {
2188                         DEBUGOUT("Unsupported SMB frequency in PHY\n");
2189                 }
2190         }
2191
2192         return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
2193 }
2194
2195 /**
2196  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2197  *  @hw:   pointer to the HW structure
2198  *
2199  *  SW should configure the LCD from the NVM extended configuration region
2200  *  as a workaround for certain parts.
2201  **/
2202 STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2203 {
2204         struct e1000_phy_info *phy = &hw->phy;
2205         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
2206         s32 ret_val = E1000_SUCCESS;
2207         u16 word_addr, reg_data, reg_addr, phy_page = 0;
2208
2209         DEBUGFUNC("e1000_sw_lcd_config_ich8lan");
2210
2211         /* Initialize the PHY from the NVM on ICH platforms.  This
2212          * is needed due to an issue where the NVM configuration is
2213          * not properly autoloaded after power transitions.
2214          * Therefore, after each PHY reset, we will load the
2215          * configuration data out of the NVM manually.
2216          */
2217         switch (hw->mac.type) {
2218         case e1000_ich8lan:
2219                 if (phy->type != e1000_phy_igp_3)
2220                         return ret_val;
2221
2222                 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_AMT) ||
2223                     (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) {
2224                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2225                         break;
2226                 }
2227                 /* Fall-thru */
2228         case e1000_pchlan:
2229         case e1000_pch2lan:
2230         case e1000_pch_lpt:
2231         case e1000_pch_spt:
2232         case e1000_pch_cnp:
2233                 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2234                 break;
2235         default:
2236                 return ret_val;
2237         }
2238
2239         ret_val = hw->phy.ops.acquire(hw);
2240         if (ret_val)
2241                 return ret_val;
2242
2243         data = E1000_READ_REG(hw, E1000_FEXTNVM);
2244         if (!(data & sw_cfg_mask))
2245                 goto release;
2246
2247         /* Make sure HW does not configure LCD from PHY
2248          * extended configuration before SW configuration
2249          */
2250         data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2251         if ((hw->mac.type < e1000_pch2lan) &&
2252             (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2253                         goto release;
2254
2255         cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE);
2256         cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2257         cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2258         if (!cnf_size)
2259                 goto release;
2260
2261         cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2262         cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2263
2264         if (((hw->mac.type == e1000_pchlan) &&
2265              !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2266             (hw->mac.type > e1000_pchlan)) {
2267                 /* HW configures the SMBus address and LEDs when the
2268                  * OEM and LCD Write Enable bits are set in the NVM.
2269                  * When both NVM bits are cleared, SW will configure
2270                  * them instead.
2271                  */
2272                 ret_val = e1000_write_smbus_addr(hw);
2273                 if (ret_val)
2274                         goto release;
2275
2276                 data = E1000_READ_REG(hw, E1000_LEDCTL);
2277                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2278                                                         (u16)data);
2279                 if (ret_val)
2280                         goto release;
2281         }
2282
2283         /* Configure LCD from extended configuration region. */
2284
2285         /* cnf_base_addr is in DWORD */
2286         word_addr = (u16)(cnf_base_addr << 1);
2287
2288         for (i = 0; i < cnf_size; i++) {
2289                 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
2290                                            &reg_data);
2291                 if (ret_val)
2292                         goto release;
2293
2294                 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
2295                                            1, &reg_addr);
2296                 if (ret_val)
2297                         goto release;
2298
2299                 /* Save off the PHY page for future writes. */
2300                 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2301                         phy_page = reg_data;
2302                         continue;
2303                 }
2304
2305                 reg_addr &= PHY_REG_MASK;
2306                 reg_addr |= phy_page;
2307
2308                 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
2309                                                     reg_data);
2310                 if (ret_val)
2311                         goto release;
2312         }
2313
2314 release:
2315         hw->phy.ops.release(hw);
2316         return ret_val;
2317 }
2318
2319 /**
2320  *  e1000_k1_gig_workaround_hv - K1 Si workaround
2321  *  @hw:   pointer to the HW structure
2322  *  @link: link up bool flag
2323  *
2324  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2325  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
2326  *  If link is down, the function will restore the default K1 setting located
2327  *  in the NVM.
2328  **/
2329 STATIC s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2330 {
2331         s32 ret_val = E1000_SUCCESS;
2332         u16 status_reg = 0;
2333         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2334
2335         DEBUGFUNC("e1000_k1_gig_workaround_hv");
2336
2337         if (hw->mac.type != e1000_pchlan)
2338                 return E1000_SUCCESS;
2339
2340         /* Wrap the whole flow with the sw flag */
2341         ret_val = hw->phy.ops.acquire(hw);
2342         if (ret_val)
2343                 return ret_val;
2344
2345         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2346         if (link) {
2347                 if (hw->phy.type == e1000_phy_82578) {
2348                         ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
2349                                                               &status_reg);
2350                         if (ret_val)
2351                                 goto release;
2352
2353                         status_reg &= (BM_CS_STATUS_LINK_UP |
2354                                        BM_CS_STATUS_RESOLVED |
2355                                        BM_CS_STATUS_SPEED_MASK);
2356
2357                         if (status_reg == (BM_CS_STATUS_LINK_UP |
2358                                            BM_CS_STATUS_RESOLVED |
2359                                            BM_CS_STATUS_SPEED_1000))
2360                                 k1_enable = false;
2361                 }
2362
2363                 if (hw->phy.type == e1000_phy_82577) {
2364                         ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
2365                                                               &status_reg);
2366                         if (ret_val)
2367                                 goto release;
2368
2369                         status_reg &= (HV_M_STATUS_LINK_UP |
2370                                        HV_M_STATUS_AUTONEG_COMPLETE |
2371                                        HV_M_STATUS_SPEED_MASK);
2372
2373                         if (status_reg == (HV_M_STATUS_LINK_UP |
2374                                            HV_M_STATUS_AUTONEG_COMPLETE |
2375                                            HV_M_STATUS_SPEED_1000))
2376                                 k1_enable = false;
2377                 }
2378
2379                 /* Link stall fix for link up */
2380                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2381                                                        0x0100);
2382                 if (ret_val)
2383                         goto release;
2384
2385         } else {
2386                 /* Link stall fix for link down */
2387                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2388                                                        0x4100);
2389                 if (ret_val)
2390                         goto release;
2391         }
2392
2393         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2394
2395 release:
2396         hw->phy.ops.release(hw);
2397
2398         return ret_val;
2399 }
2400
2401 /**
2402  *  e1000_configure_k1_ich8lan - Configure K1 power state
2403  *  @hw: pointer to the HW structure
2404  *  @enable: K1 state to configure
2405  *
2406  *  Configure the K1 power state based on the provided parameter.
2407  *  Assumes semaphore already acquired.
2408  *
2409  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2410  **/
2411 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2412 {
2413         s32 ret_val;
2414         u32 ctrl_reg = 0;
2415         u32 ctrl_ext = 0;
2416         u32 reg = 0;
2417         u16 kmrn_reg = 0;
2418
2419         DEBUGFUNC("e1000_configure_k1_ich8lan");
2420
2421         ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2422                                              &kmrn_reg);
2423         if (ret_val)
2424                 return ret_val;
2425
2426         if (k1_enable)
2427                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2428         else
2429                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2430
2431         ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2432                                               kmrn_reg);
2433         if (ret_val)
2434                 return ret_val;
2435
2436         usec_delay(20);
2437         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2438         ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
2439
2440         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2441         reg |= E1000_CTRL_FRCSPD;
2442         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2443
2444         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2445         E1000_WRITE_FLUSH(hw);
2446         usec_delay(20);
2447         E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
2448         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
2449         E1000_WRITE_FLUSH(hw);
2450         usec_delay(20);
2451
2452         return E1000_SUCCESS;
2453 }
2454
2455 /**
2456  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2457  *  @hw:       pointer to the HW structure
2458  *  @d0_state: boolean if entering d0 or d3 device state
2459  *
2460  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2461  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
2462  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
2463  **/
2464 STATIC s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2465 {
2466         s32 ret_val = 0;
2467         u32 mac_reg;
2468         u16 oem_reg;
2469
2470         DEBUGFUNC("e1000_oem_bits_config_ich8lan");
2471
2472         if (hw->mac.type < e1000_pchlan)
2473                 return ret_val;
2474
2475         ret_val = hw->phy.ops.acquire(hw);
2476         if (ret_val)
2477                 return ret_val;
2478
2479         if (hw->mac.type == e1000_pchlan) {
2480                 mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2481                 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2482                         goto release;
2483         }
2484
2485         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM);
2486         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2487                 goto release;
2488
2489         mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
2490
2491         ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
2492         if (ret_val)
2493                 goto release;
2494
2495         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2496
2497         if (d0_state) {
2498                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2499                         oem_reg |= HV_OEM_BITS_GBE_DIS;
2500
2501                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2502                         oem_reg |= HV_OEM_BITS_LPLU;
2503         } else {
2504                 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2505                     E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2506                         oem_reg |= HV_OEM_BITS_GBE_DIS;
2507
2508                 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2509                     E1000_PHY_CTRL_NOND0A_LPLU))
2510                         oem_reg |= HV_OEM_BITS_LPLU;
2511         }
2512
2513         /* Set Restart auto-neg to activate the bits */
2514         if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2515             !hw->phy.ops.check_reset_block(hw))
2516                 oem_reg |= HV_OEM_BITS_RESTART_AN;
2517
2518         ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
2519
2520 release:
2521         hw->phy.ops.release(hw);
2522
2523         return ret_val;
2524 }
2525
2526
2527 /**
2528  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2529  *  @hw:   pointer to the HW structure
2530  **/
2531 STATIC s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2532 {
2533         s32 ret_val;
2534         u16 data;
2535
2536         DEBUGFUNC("e1000_set_mdio_slow_mode_hv");
2537
2538         ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data);
2539         if (ret_val)
2540                 return ret_val;
2541
2542         data |= HV_KMRN_MDIO_SLOW;
2543
2544         ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data);
2545
2546         return ret_val;
2547 }
2548
2549 /**
2550  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2551  *  done after every PHY reset.
2552  **/
2553 STATIC s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2554 {
2555         s32 ret_val = E1000_SUCCESS;
2556         u16 phy_data;
2557
2558         DEBUGFUNC("e1000_hv_phy_workarounds_ich8lan");
2559
2560         if (hw->mac.type != e1000_pchlan)
2561                 return E1000_SUCCESS;
2562
2563         /* Set MDIO slow mode before any other MDIO access */
2564         if (hw->phy.type == e1000_phy_82577) {
2565                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2566                 if (ret_val)
2567                         return ret_val;
2568         }
2569
2570         if (((hw->phy.type == e1000_phy_82577) &&
2571              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2572             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2573                 /* Disable generation of early preamble */
2574                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
2575                 if (ret_val)
2576                         return ret_val;
2577
2578                 /* Preamble tuning for SSC */
2579                 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA,
2580                                                 0xA204);
2581                 if (ret_val)
2582                         return ret_val;
2583         }
2584
2585         if (hw->phy.type == e1000_phy_82578) {
2586                 /* Return registers to default by doing a soft reset then
2587                  * writing 0x3140 to the control register.
2588                  */
2589                 if (hw->phy.revision < 2) {
2590                         e1000_phy_sw_reset_generic(hw);
2591                         ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,
2592                                                         0x3140);
2593                 }
2594         }
2595
2596         /* Select page 0 */
2597         ret_val = hw->phy.ops.acquire(hw);
2598         if (ret_val)
2599                 return ret_val;
2600
2601         hw->phy.addr = 1;
2602         ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2603         hw->phy.ops.release(hw);
2604         if (ret_val)
2605                 return ret_val;
2606
2607         /* Configure the K1 Si workaround during phy reset assuming there is
2608          * link so that it disables K1 if link is in 1Gbps.
2609          */
2610         ret_val = e1000_k1_gig_workaround_hv(hw, true);
2611         if (ret_val)
2612                 return ret_val;
2613
2614         /* Workaround for link disconnects on a busy hub in half duplex */
2615         ret_val = hw->phy.ops.acquire(hw);
2616         if (ret_val)
2617                 return ret_val;
2618         ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2619         if (ret_val)
2620                 goto release;
2621         ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
2622                                                phy_data & 0x00FF);
2623         if (ret_val)
2624                 goto release;
2625
2626         /* set MSE higher to enable link to stay up when noise is high */
2627         ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2628 release:
2629         hw->phy.ops.release(hw);
2630
2631         return ret_val;
2632 }
2633
2634 /**
2635  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2636  *  @hw:   pointer to the HW structure
2637  **/
2638 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2639 {
2640         u32 mac_reg;
2641         u16 i, phy_reg = 0;
2642         s32 ret_val;
2643
2644         DEBUGFUNC("e1000_copy_rx_addrs_to_phy_ich8lan");
2645
2646         ret_val = hw->phy.ops.acquire(hw);
2647         if (ret_val)
2648                 return;
2649         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2650         if (ret_val)
2651                 goto release;
2652
2653         /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2654         for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2655                 mac_reg = E1000_READ_REG(hw, E1000_RAL(i));
2656                 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2657                                            (u16)(mac_reg & 0xFFFF));
2658                 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2659                                            (u16)((mac_reg >> 16) & 0xFFFF));
2660
2661                 mac_reg = E1000_READ_REG(hw, E1000_RAH(i));
2662                 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2663                                            (u16)(mac_reg & 0xFFFF));
2664                 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2665                                            (u16)((mac_reg & E1000_RAH_AV)
2666                                                  >> 16));
2667         }
2668
2669         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2670
2671 release:
2672         hw->phy.ops.release(hw);
2673 }
2674
2675 #ifndef CRC32_OS_SUPPORT
2676 STATIC u32 e1000_calc_rx_da_crc(u8 mac[])
2677 {
2678         u32 poly = 0xEDB88320;  /* Polynomial for 802.3 CRC calculation */
2679         u32 i, j, mask, crc;
2680
2681         DEBUGFUNC("e1000_calc_rx_da_crc");
2682
2683         crc = 0xffffffff;
2684         for (i = 0; i < 6; i++) {
2685                 crc = crc ^ mac[i];
2686                 for (j = 8; j > 0; j--) {
2687                         mask = (crc & 1) * (-1);
2688                         crc = (crc >> 1) ^ (poly & mask);
2689                 }
2690         }
2691         return ~crc;
2692 }
2693
2694 #endif /* CRC32_OS_SUPPORT */
2695 /**
2696  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2697  *  with 82579 PHY
2698  *  @hw: pointer to the HW structure
2699  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
2700  **/
2701 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2702 {
2703         s32 ret_val = E1000_SUCCESS;
2704         u16 phy_reg, data;
2705         u32 mac_reg;
2706         u16 i;
2707
2708         DEBUGFUNC("e1000_lv_jumbo_workaround_ich8lan");
2709
2710         if (hw->mac.type < e1000_pch2lan)
2711                 return E1000_SUCCESS;
2712
2713         /* disable Rx path while enabling/disabling workaround */
2714         hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg);
2715         ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20),
2716                                         phy_reg | (1 << 14));
2717         if (ret_val)
2718                 return ret_val;
2719
2720         if (enable) {
2721                 /* Write Rx addresses (rar_entry_count for RAL/H, and
2722                  * SHRAL/H) and initial CRC values to the MAC
2723                  */
2724                 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2725                         u8 mac_addr[ETH_ADDR_LEN] = {0};
2726                         u32 addr_high, addr_low;
2727
2728                         addr_high = E1000_READ_REG(hw, E1000_RAH(i));
2729                         if (!(addr_high & E1000_RAH_AV))
2730                                 continue;
2731                         addr_low = E1000_READ_REG(hw, E1000_RAL(i));
2732                         mac_addr[0] = (addr_low & 0xFF);
2733                         mac_addr[1] = ((addr_low >> 8) & 0xFF);
2734                         mac_addr[2] = ((addr_low >> 16) & 0xFF);
2735                         mac_addr[3] = ((addr_low >> 24) & 0xFF);
2736                         mac_addr[4] = (addr_high & 0xFF);
2737                         mac_addr[5] = ((addr_high >> 8) & 0xFF);
2738
2739 #ifndef CRC32_OS_SUPPORT
2740                         E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
2741                                         e1000_calc_rx_da_crc(mac_addr));
2742 #else /* CRC32_OS_SUPPORT */
2743                         E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
2744                                         E1000_CRC32(ETH_ADDR_LEN, mac_addr));
2745 #endif /* CRC32_OS_SUPPORT */
2746                 }
2747
2748                 /* Write Rx addresses to the PHY */
2749                 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2750
2751                 /* Enable jumbo frame workaround in the MAC */
2752                 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2753                 mac_reg &= ~(1 << 14);
2754                 mac_reg |= (7 << 15);
2755                 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2756
2757                 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2758                 mac_reg |= E1000_RCTL_SECRC;
2759                 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2760
2761                 ret_val = e1000_read_kmrn_reg_generic(hw,
2762                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2763                                                 &data);
2764                 if (ret_val)
2765                         return ret_val;
2766                 ret_val = e1000_write_kmrn_reg_generic(hw,
2767                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2768                                                 data | (1 << 0));
2769                 if (ret_val)
2770                         return ret_val;
2771                 ret_val = e1000_read_kmrn_reg_generic(hw,
2772                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2773                                                 &data);
2774                 if (ret_val)
2775                         return ret_val;
2776                 data &= ~(0xF << 8);
2777                 data |= (0xB << 8);
2778                 ret_val = e1000_write_kmrn_reg_generic(hw,
2779                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2780                                                 data);
2781                 if (ret_val)
2782                         return ret_val;
2783
2784                 /* Enable jumbo frame workaround in the PHY */
2785                 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2786                 data &= ~(0x7F << 5);
2787                 data |= (0x37 << 5);
2788                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2789                 if (ret_val)
2790                         return ret_val;
2791                 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2792                 data &= ~(1 << 13);
2793                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2794                 if (ret_val)
2795                         return ret_val;
2796                 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2797                 data &= ~(0x3FF << 2);
2798                 data |= (E1000_TX_PTR_GAP << 2);
2799                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2800                 if (ret_val)
2801                         return ret_val;
2802                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100);
2803                 if (ret_val)
2804                         return ret_val;
2805                 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2806                 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data |
2807                                                 (1 << 10));
2808                 if (ret_val)
2809                         return ret_val;
2810         } else {
2811                 /* Write MAC register values back to h/w defaults */
2812                 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2813                 mac_reg &= ~(0xF << 14);
2814                 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2815
2816                 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2817                 mac_reg &= ~E1000_RCTL_SECRC;
2818                 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2819
2820                 ret_val = e1000_read_kmrn_reg_generic(hw,
2821                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2822                                                 &data);
2823                 if (ret_val)
2824                         return ret_val;
2825                 ret_val = e1000_write_kmrn_reg_generic(hw,
2826                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2827                                                 data & ~(1 << 0));
2828                 if (ret_val)
2829                         return ret_val;
2830                 ret_val = e1000_read_kmrn_reg_generic(hw,
2831                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2832                                                 &data);
2833                 if (ret_val)
2834                         return ret_val;
2835                 data &= ~(0xF << 8);
2836                 data |= (0xB << 8);
2837                 ret_val = e1000_write_kmrn_reg_generic(hw,
2838                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2839                                                 data);
2840                 if (ret_val)
2841                         return ret_val;
2842
2843                 /* Write PHY register values back to h/w defaults */
2844                 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2845                 data &= ~(0x7F << 5);
2846                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2847                 if (ret_val)
2848                         return ret_val;
2849                 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2850                 data |= (1 << 13);
2851                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2852                 if (ret_val)
2853                         return ret_val;
2854                 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2855                 data &= ~(0x3FF << 2);
2856                 data |= (0x8 << 2);
2857                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2858                 if (ret_val)
2859                         return ret_val;
2860                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00);
2861                 if (ret_val)
2862                         return ret_val;
2863                 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2864                 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data &
2865                                                 ~(1 << 10));
2866                 if (ret_val)
2867                         return ret_val;
2868         }
2869
2870         /* re-enable Rx path after enabling/disabling workaround */
2871         return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg &
2872                                      ~(1 << 14));
2873 }
2874
2875 /**
2876  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2877  *  done after every PHY reset.
2878  **/
2879 STATIC s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2880 {
2881         s32 ret_val = E1000_SUCCESS;
2882
2883         DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan");
2884
2885         if (hw->mac.type != e1000_pch2lan)
2886                 return E1000_SUCCESS;
2887
2888         /* Set MDIO slow mode before any other MDIO access */
2889         ret_val = e1000_set_mdio_slow_mode_hv(hw);
2890         if (ret_val)
2891                 return ret_val;
2892
2893         ret_val = hw->phy.ops.acquire(hw);
2894         if (ret_val)
2895                 return ret_val;
2896         /* set MSE higher to enable link to stay up when noise is high */
2897         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2898         if (ret_val)
2899                 goto release;
2900         /* drop link after 5 times MSE threshold was reached */
2901         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2902 release:
2903         hw->phy.ops.release(hw);
2904
2905         return ret_val;
2906 }
2907
2908 /**
2909  *  e1000_k1_gig_workaround_lv - K1 Si workaround
2910  *  @hw:   pointer to the HW structure
2911  *
2912  *  Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2913  *  Disable K1 for 1000 and 100 speeds
2914  **/
2915 STATIC s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2916 {
2917         s32 ret_val = E1000_SUCCESS;
2918         u16 status_reg = 0;
2919
2920         DEBUGFUNC("e1000_k1_workaround_lv");
2921
2922         if (hw->mac.type != e1000_pch2lan)
2923                 return E1000_SUCCESS;
2924
2925         /* Set K1 beacon duration based on 10Mbs speed */
2926         ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg);
2927         if (ret_val)
2928                 return ret_val;
2929
2930         if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2931             == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2932                 if (status_reg &
2933                     (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
2934                         u16 pm_phy_reg;
2935
2936                         /* LV 1G/100 Packet drop issue wa  */
2937                         ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL,
2938                                                        &pm_phy_reg);
2939                         if (ret_val)
2940                                 return ret_val;
2941                         pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
2942                         ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL,
2943                                                         pm_phy_reg);
2944                         if (ret_val)
2945                                 return ret_val;
2946                 } else {
2947                         u32 mac_reg;
2948                         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
2949                         mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2950                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2951                         E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
2952                 }
2953         }
2954
2955         return ret_val;
2956 }
2957
2958 /**
2959  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2960  *  @hw:   pointer to the HW structure
2961  *  @gate: boolean set to true to gate, false to ungate
2962  *
2963  *  Gate/ungate the automatic PHY configuration via hardware; perform
2964  *  the configuration via software instead.
2965  **/
2966 STATIC void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2967 {
2968         u32 extcnf_ctrl;
2969
2970         DEBUGFUNC("e1000_gate_hw_phy_config_ich8lan");
2971
2972         if (hw->mac.type < e1000_pch2lan)
2973                 return;
2974
2975         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2976
2977         if (gate)
2978                 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2979         else
2980                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2981
2982         E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
2983 }
2984
2985 /**
2986  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
2987  *  @hw: pointer to the HW structure
2988  *
2989  *  Check the appropriate indication the MAC has finished configuring the
2990  *  PHY after a software reset.
2991  **/
2992 STATIC void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2993 {
2994         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2995
2996         DEBUGFUNC("e1000_lan_init_done_ich8lan");
2997
2998         /* Wait for basic configuration completes before proceeding */
2999         do {
3000                 data = E1000_READ_REG(hw, E1000_STATUS);
3001                 data &= E1000_STATUS_LAN_INIT_DONE;
3002                 usec_delay(100);
3003         } while ((!data) && --loop);
3004
3005         /* If basic configuration is incomplete before the above loop
3006          * count reaches 0, loading the configuration from NVM will
3007          * leave the PHY in a bad state possibly resulting in no link.
3008          */
3009         if (loop == 0)
3010                 DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n");
3011
3012         /* Clear the Init Done bit for the next init event */
3013         data = E1000_READ_REG(hw, E1000_STATUS);
3014         data &= ~E1000_STATUS_LAN_INIT_DONE;
3015         E1000_WRITE_REG(hw, E1000_STATUS, data);
3016 }
3017
3018 /**
3019  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
3020  *  @hw: pointer to the HW structure
3021  **/
3022 STATIC s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
3023 {
3024         s32 ret_val = E1000_SUCCESS;
3025         u16 reg;
3026
3027         DEBUGFUNC("e1000_post_phy_reset_ich8lan");
3028
3029         if (hw->phy.ops.check_reset_block(hw))
3030                 return E1000_SUCCESS;
3031
3032         /* Allow time for h/w to get to quiescent state after reset */
3033         msec_delay(10);
3034
3035         /* Perform any necessary post-reset workarounds */
3036         switch (hw->mac.type) {
3037         case e1000_pchlan:
3038                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
3039                 if (ret_val)
3040                         return ret_val;
3041                 break;
3042         case e1000_pch2lan:
3043                 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
3044                 if (ret_val)
3045                         return ret_val;
3046                 break;
3047         default:
3048                 break;
3049         }
3050
3051         /* Clear the host wakeup bit after lcd reset */
3052         if (hw->mac.type >= e1000_pchlan) {
3053                 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &reg);
3054                 reg &= ~BM_WUC_HOST_WU_BIT;
3055                 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg);
3056         }
3057
3058         /* Configure the LCD with the extended configuration region in NVM */
3059         ret_val = e1000_sw_lcd_config_ich8lan(hw);
3060         if (ret_val)
3061                 return ret_val;
3062
3063         /* Configure the LCD with the OEM bits in NVM */
3064         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
3065
3066         if (hw->mac.type == e1000_pch2lan) {
3067                 /* Ungate automatic PHY configuration on non-managed 82579 */
3068                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
3069                     E1000_ICH_FWSM_FW_VALID)) {
3070                         msec_delay(10);
3071                         e1000_gate_hw_phy_config_ich8lan(hw, false);
3072                 }
3073
3074                 /* Set EEE LPI Update Timer to 200usec */
3075                 ret_val = hw->phy.ops.acquire(hw);
3076                 if (ret_val)
3077                         return ret_val;
3078                 ret_val = e1000_write_emi_reg_locked(hw,
3079                                                      I82579_LPI_UPDATE_TIMER,
3080                                                      0x1387);
3081                 hw->phy.ops.release(hw);
3082         }
3083
3084         return ret_val;
3085 }
3086
3087 /**
3088  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
3089  *  @hw: pointer to the HW structure
3090  *
3091  *  Resets the PHY
3092  *  This is a function pointer entry point called by drivers
3093  *  or other shared routines.
3094  **/
3095 STATIC s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
3096 {
3097         s32 ret_val = E1000_SUCCESS;
3098
3099         DEBUGFUNC("e1000_phy_hw_reset_ich8lan");
3100
3101         /* Gate automatic PHY configuration by hardware on non-managed 82579 */
3102         if ((hw->mac.type == e1000_pch2lan) &&
3103             !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
3104                 e1000_gate_hw_phy_config_ich8lan(hw, true);
3105
3106         ret_val = e1000_phy_hw_reset_generic(hw);
3107         if (ret_val)
3108                 return ret_val;
3109
3110         return e1000_post_phy_reset_ich8lan(hw);
3111 }
3112
3113 /**
3114  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
3115  *  @hw: pointer to the HW structure
3116  *  @active: true to enable LPLU, false to disable
3117  *
3118  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
3119  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
3120  *  the phy speed. This function will manually set the LPLU bit and restart
3121  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
3122  *  since it configures the same bit.
3123  **/
3124 STATIC s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
3125 {
3126         s32 ret_val;
3127         u16 oem_reg;
3128
3129         DEBUGFUNC("e1000_set_lplu_state_pchlan");
3130         ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg);
3131         if (ret_val)
3132                 return ret_val;
3133
3134         if (active)
3135                 oem_reg |= HV_OEM_BITS_LPLU;
3136         else
3137                 oem_reg &= ~HV_OEM_BITS_LPLU;
3138
3139         if (!hw->phy.ops.check_reset_block(hw))
3140                 oem_reg |= HV_OEM_BITS_RESTART_AN;
3141
3142         return hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg);
3143 }
3144
3145 /**
3146  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
3147  *  @hw: pointer to the HW structure
3148  *  @active: true to enable LPLU, false to disable
3149  *
3150  *  Sets the LPLU D0 state according to the active flag.  When
3151  *  activating LPLU this function also disables smart speed
3152  *  and vice versa.  LPLU will not be activated unless the
3153  *  device autonegotiation advertisement meets standards of
3154  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
3155  *  This is a function pointer entry point only called by
3156  *  PHY setup routines.
3157  **/
3158 STATIC s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3159 {
3160         struct e1000_phy_info *phy = &hw->phy;
3161         u32 phy_ctrl;
3162         s32 ret_val = E1000_SUCCESS;
3163         u16 data;
3164
3165         DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan");
3166
3167         if (phy->type == e1000_phy_ife)
3168                 return E1000_SUCCESS;
3169
3170         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3171
3172         if (active) {
3173                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
3174                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3175
3176                 if (phy->type != e1000_phy_igp_3)
3177                         return E1000_SUCCESS;
3178
3179                 /* Call gig speed drop workaround on LPLU before accessing
3180                  * any PHY registers
3181                  */
3182                 if (hw->mac.type == e1000_ich8lan)
3183                         e1000_gig_downshift_workaround_ich8lan(hw);
3184
3185                 /* When LPLU is enabled, we should disable SmartSpeed */
3186                 ret_val = phy->ops.read_reg(hw,
3187                                             IGP01E1000_PHY_PORT_CONFIG,
3188                                             &data);
3189                 if (ret_val)
3190                         return ret_val;
3191                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3192                 ret_val = phy->ops.write_reg(hw,
3193                                              IGP01E1000_PHY_PORT_CONFIG,
3194                                              data);
3195                 if (ret_val)
3196                         return ret_val;
3197         } else {
3198                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
3199                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3200
3201                 if (phy->type != e1000_phy_igp_3)
3202                         return E1000_SUCCESS;
3203
3204                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
3205                  * during Dx states where the power conservation is most
3206                  * important.  During driver activity we should enable
3207                  * SmartSpeed, so performance is maintained.
3208                  */
3209                 if (phy->smart_speed == e1000_smart_speed_on) {
3210                         ret_val = phy->ops.read_reg(hw,
3211                                                     IGP01E1000_PHY_PORT_CONFIG,
3212                                                     &data);
3213                         if (ret_val)
3214                                 return ret_val;
3215
3216                         data |= IGP01E1000_PSCFR_SMART_SPEED;
3217                         ret_val = phy->ops.write_reg(hw,
3218                                                      IGP01E1000_PHY_PORT_CONFIG,
3219                                                      data);
3220                         if (ret_val)
3221                                 return ret_val;
3222                 } else if (phy->smart_speed == e1000_smart_speed_off) {
3223                         ret_val = phy->ops.read_reg(hw,
3224                                                     IGP01E1000_PHY_PORT_CONFIG,
3225                                                     &data);
3226                         if (ret_val)
3227                                 return ret_val;
3228
3229                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3230                         ret_val = phy->ops.write_reg(hw,
3231                                                      IGP01E1000_PHY_PORT_CONFIG,
3232                                                      data);
3233                         if (ret_val)
3234                                 return ret_val;
3235                 }
3236         }
3237
3238         return E1000_SUCCESS;
3239 }
3240
3241 /**
3242  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3243  *  @hw: pointer to the HW structure
3244  *  @active: true to enable LPLU, false to disable
3245  *
3246  *  Sets the LPLU D3 state according to the active flag.  When
3247  *  activating LPLU this function also disables smart speed
3248  *  and vice versa.  LPLU will not be activated unless the
3249  *  device autonegotiation advertisement meets standards of
3250  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
3251  *  This is a function pointer entry point only called by
3252  *  PHY setup routines.
3253  **/
3254 STATIC s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3255 {
3256         struct e1000_phy_info *phy = &hw->phy;
3257         u32 phy_ctrl;
3258         s32 ret_val = E1000_SUCCESS;
3259         u16 data;
3260
3261         DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan");
3262
3263         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3264
3265         if (!active) {
3266                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3267                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3268
3269                 if (phy->type != e1000_phy_igp_3)
3270                         return E1000_SUCCESS;
3271
3272                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
3273                  * during Dx states where the power conservation is most
3274                  * important.  During driver activity we should enable
3275                  * SmartSpeed, so performance is maintained.
3276                  */
3277                 if (phy->smart_speed == e1000_smart_speed_on) {
3278                         ret_val = phy->ops.read_reg(hw,
3279                                                     IGP01E1000_PHY_PORT_CONFIG,
3280                                                     &data);
3281                         if (ret_val)
3282                                 return ret_val;
3283
3284                         data |= IGP01E1000_PSCFR_SMART_SPEED;
3285                         ret_val = phy->ops.write_reg(hw,
3286                                                      IGP01E1000_PHY_PORT_CONFIG,
3287                                                      data);
3288                         if (ret_val)
3289                                 return ret_val;
3290                 } else if (phy->smart_speed == e1000_smart_speed_off) {
3291                         ret_val = phy->ops.read_reg(hw,
3292                                                     IGP01E1000_PHY_PORT_CONFIG,
3293                                                     &data);
3294                         if (ret_val)
3295                                 return ret_val;
3296
3297                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3298                         ret_val = phy->ops.write_reg(hw,
3299                                                      IGP01E1000_PHY_PORT_CONFIG,
3300                                                      data);
3301                         if (ret_val)
3302                                 return ret_val;
3303                 }
3304         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3305                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3306                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3307                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3308                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3309
3310                 if (phy->type != e1000_phy_igp_3)
3311                         return E1000_SUCCESS;
3312
3313                 /* Call gig speed drop workaround on LPLU before accessing
3314                  * any PHY registers
3315                  */
3316                 if (hw->mac.type == e1000_ich8lan)
3317                         e1000_gig_downshift_workaround_ich8lan(hw);
3318
3319                 /* When LPLU is enabled, we should disable SmartSpeed */
3320                 ret_val = phy->ops.read_reg(hw,
3321                                             IGP01E1000_PHY_PORT_CONFIG,
3322                                             &data);
3323                 if (ret_val)
3324                         return ret_val;
3325
3326                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3327                 ret_val = phy->ops.write_reg(hw,
3328                                              IGP01E1000_PHY_PORT_CONFIG,
3329                                              data);
3330         }
3331
3332         return ret_val;
3333 }
3334
3335 /**
3336  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3337  *  @hw: pointer to the HW structure
3338  *  @bank:  pointer to the variable that returns the active bank
3339  *
3340  *  Reads signature byte from the NVM using the flash access registers.
3341  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3342  **/
3343 STATIC s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3344 {
3345         u32 eecd;
3346         struct e1000_nvm_info *nvm = &hw->nvm;
3347         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3348         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3349         u32 nvm_dword = 0;
3350         u8 sig_byte = 0;
3351         s32 ret_val;
3352
3353         DEBUGFUNC("e1000_valid_nvm_bank_detect_ich8lan");
3354
3355         switch (hw->mac.type) {
3356         case e1000_pch_spt:
3357         case e1000_pch_cnp:
3358                 bank1_offset = nvm->flash_bank_size;
3359                 act_offset = E1000_ICH_NVM_SIG_WORD;
3360
3361                 /* set bank to 0 in case flash read fails */
3362                 *bank = 0;
3363
3364                 /* Check bank 0 */
3365                 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,
3366                                                          &nvm_dword);
3367                 if (ret_val)
3368                         return ret_val;
3369                 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3370                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3371                     E1000_ICH_NVM_SIG_VALUE) {
3372                         *bank = 0;
3373                         return E1000_SUCCESS;
3374                 }
3375
3376                 /* Check bank 1 */
3377                 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset +
3378                                                          bank1_offset,
3379                                                          &nvm_dword);
3380                 if (ret_val)
3381                         return ret_val;
3382                 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3383                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3384                     E1000_ICH_NVM_SIG_VALUE) {
3385                         *bank = 1;
3386                         return E1000_SUCCESS;
3387                 }
3388
3389                 DEBUGOUT("ERROR: No valid NVM bank present\n");
3390                 return -E1000_ERR_NVM;
3391         case e1000_ich8lan:
3392         case e1000_ich9lan:
3393                 eecd = E1000_READ_REG(hw, E1000_EECD);
3394                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3395                     E1000_EECD_SEC1VAL_VALID_MASK) {
3396                         if (eecd & E1000_EECD_SEC1VAL)
3397                                 *bank = 1;
3398                         else
3399                                 *bank = 0;
3400
3401                         return E1000_SUCCESS;
3402                 }
3403                 DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3404                 /* fall-thru */
3405         default:
3406                 /* set bank to 0 in case flash read fails */
3407                 *bank = 0;
3408
3409                 /* Check bank 0 */
3410                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3411                                                         &sig_byte);
3412                 if (ret_val)
3413                         return ret_val;
3414                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3415                     E1000_ICH_NVM_SIG_VALUE) {
3416                         *bank = 0;
3417                         return E1000_SUCCESS;
3418                 }
3419
3420                 /* Check bank 1 */
3421                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3422                                                         bank1_offset,
3423                                                         &sig_byte);
3424                 if (ret_val)
3425                         return ret_val;
3426                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3427                     E1000_ICH_NVM_SIG_VALUE) {
3428                         *bank = 1;
3429                         return E1000_SUCCESS;
3430                 }
3431
3432                 DEBUGOUT("ERROR: No valid NVM bank present\n");
3433                 return -E1000_ERR_NVM;
3434         }
3435 }
3436
3437 /**
3438  *  e1000_read_nvm_spt - NVM access for SPT
3439  *  @hw: pointer to the HW structure
3440  *  @offset: The offset (in bytes) of the word(s) to read.
3441  *  @words: Size of data to read in words.
3442  *  @data: pointer to the word(s) to read at offset.
3443  *
3444  *  Reads a word(s) from the NVM
3445  **/
3446 STATIC s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
3447                               u16 *data)
3448 {
3449         struct e1000_nvm_info *nvm = &hw->nvm;
3450         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3451         u32 act_offset;
3452         s32 ret_val = E1000_SUCCESS;
3453         u32 bank = 0;
3454         u32 dword = 0;
3455         u16 offset_to_read;
3456         u16 i;
3457
3458         DEBUGFUNC("e1000_read_nvm_spt");
3459
3460         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3461             (words == 0)) {
3462                 DEBUGOUT("nvm parameter(s) out of bounds\n");
3463                 ret_val = -E1000_ERR_NVM;
3464                 goto out;
3465         }
3466
3467         nvm->ops.acquire(hw);
3468
3469         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3470         if (ret_val != E1000_SUCCESS) {
3471                 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3472                 bank = 0;
3473         }
3474
3475         act_offset = (bank) ? nvm->flash_bank_size : 0;
3476         act_offset += offset;
3477
3478         ret_val = E1000_SUCCESS;
3479
3480         for (i = 0; i < words; i += 2) {
3481                 if (words - i == 1) {
3482                         if (dev_spec->shadow_ram[offset+i].modified) {
3483                                 data[i] = dev_spec->shadow_ram[offset+i].value;
3484                         } else {
3485                                 offset_to_read = act_offset + i -
3486                                                  ((act_offset + i) % 2);
3487                                 ret_val =
3488                                    e1000_read_flash_dword_ich8lan(hw,
3489                                                                  offset_to_read,
3490                                                                  &dword);
3491                                 if (ret_val)
3492                                         break;
3493                                 if ((act_offset + i) % 2 == 0)
3494                                         data[i] = (u16)(dword & 0xFFFF);
3495                                 else
3496                                         data[i] = (u16)((dword >> 16) & 0xFFFF);
3497                         }
3498                 } else {
3499                         offset_to_read = act_offset + i;
3500                         if (!(dev_spec->shadow_ram[offset+i].modified) ||
3501                             !(dev_spec->shadow_ram[offset+i+1].modified)) {
3502                                 ret_val =
3503                                    e1000_read_flash_dword_ich8lan(hw,
3504                                                                  offset_to_read,
3505                                                                  &dword);
3506                                 if (ret_val)
3507                                         break;
3508                         }
3509                         if (dev_spec->shadow_ram[offset+i].modified)
3510                                 data[i] = dev_spec->shadow_ram[offset+i].value;
3511                         else
3512                                 data[i] = (u16) (dword & 0xFFFF);
3513                         if (dev_spec->shadow_ram[offset+i].modified)
3514                                 data[i+1] =
3515                                    dev_spec->shadow_ram[offset+i+1].value;
3516                         else
3517                                 data[i+1] = (u16) (dword >> 16 & 0xFFFF);
3518                 }
3519         }
3520
3521         nvm->ops.release(hw);
3522
3523 out:
3524         if (ret_val)
3525                 DEBUGOUT1("NVM read error: %d\n", ret_val);
3526
3527         return ret_val;
3528 }
3529
3530 /**
3531  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
3532  *  @hw: pointer to the HW structure
3533  *  @offset: The offset (in bytes) of the word(s) to read.
3534  *  @words: Size of data to read in words
3535  *  @data: Pointer to the word(s) to read at offset.
3536  *
3537  *  Reads a word(s) from the NVM using the flash access registers.
3538  **/
3539 STATIC s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3540                                   u16 *data)
3541 {
3542         struct e1000_nvm_info *nvm = &hw->nvm;
3543         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3544         u32 act_offset;
3545         s32 ret_val = E1000_SUCCESS;
3546         u32 bank = 0;
3547         u16 i, word;
3548
3549         DEBUGFUNC("e1000_read_nvm_ich8lan");
3550
3551         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3552             (words == 0)) {
3553                 DEBUGOUT("nvm parameter(s) out of bounds\n");
3554                 ret_val = -E1000_ERR_NVM;
3555                 goto out;
3556         }
3557
3558         nvm->ops.acquire(hw);
3559
3560         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3561         if (ret_val != E1000_SUCCESS) {
3562                 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3563                 bank = 0;
3564         }
3565
3566         act_offset = (bank) ? nvm->flash_bank_size : 0;
3567         act_offset += offset;
3568
3569         ret_val = E1000_SUCCESS;
3570         for (i = 0; i < words; i++) {
3571                 if (dev_spec->shadow_ram[offset+i].modified) {
3572                         data[i] = dev_spec->shadow_ram[offset+i].value;
3573                 } else {
3574                         ret_val = e1000_read_flash_word_ich8lan(hw,
3575                                                                 act_offset + i,
3576                                                                 &word);
3577                         if (ret_val)
3578                                 break;
3579                         data[i] = word;
3580                 }
3581         }
3582
3583         nvm->ops.release(hw);
3584
3585 out:
3586         if (ret_val)
3587                 DEBUGOUT1("NVM read error: %d\n", ret_val);
3588
3589         return ret_val;
3590 }
3591
3592 /**
3593  *  e1000_flash_cycle_init_ich8lan - Initialize flash
3594  *  @hw: pointer to the HW structure
3595  *
3596  *  This function does initial flash setup so that a new read/write/erase cycle
3597  *  can be started.
3598  **/
3599 STATIC s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3600 {
3601         union ich8_hws_flash_status hsfsts;
3602         s32 ret_val = -E1000_ERR_NVM;
3603
3604         DEBUGFUNC("e1000_flash_cycle_init_ich8lan");
3605
3606         hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3607
3608         /* Check if the flash descriptor is valid */
3609         if (!hsfsts.hsf_status.fldesvalid) {
3610                 DEBUGOUT("Flash descriptor invalid.  SW Sequencing must be used.\n");
3611                 return -E1000_ERR_NVM;
3612         }
3613
3614         /* Clear FCERR and DAEL in hw status by writing 1 */
3615         hsfsts.hsf_status.flcerr = 1;
3616         hsfsts.hsf_status.dael = 1;
3617         if (hw->mac.type >= e1000_pch_spt)
3618                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3619                                       hsfsts.regval & 0xFFFF);
3620         else
3621                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3622
3623         /* Either we should have a hardware SPI cycle in progress
3624          * bit to check against, in order to start a new cycle or
3625          * FDONE bit should be changed in the hardware so that it
3626          * is 1 after hardware reset, which can then be used as an
3627          * indication whether a cycle is in progress or has been
3628          * completed.
3629          */
3630
3631         if (!hsfsts.hsf_status.flcinprog) {
3632                 /* There is no cycle running at present,
3633                  * so we can start a cycle.
3634                  * Begin by setting Flash Cycle Done.
3635                  */
3636                 hsfsts.hsf_status.flcdone = 1;
3637                 if (hw->mac.type >= e1000_pch_spt)
3638                         E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3639                                               hsfsts.regval & 0xFFFF);
3640                 else
3641                         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3642                                                 hsfsts.regval);
3643                 ret_val = E1000_SUCCESS;
3644         } else {
3645                 s32 i;
3646
3647                 /* Otherwise poll for sometime so the current
3648                  * cycle has a chance to end before giving up.
3649                  */
3650                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3651                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3652                                                               ICH_FLASH_HSFSTS);
3653                         if (!hsfsts.hsf_status.flcinprog) {
3654                                 ret_val = E1000_SUCCESS;
3655                                 break;
3656                         }
3657                         usec_delay(1);
3658                 }
3659                 if (ret_val == E1000_SUCCESS) {
3660                         /* Successful in waiting for previous cycle to timeout,
3661                          * now set the Flash Cycle Done.
3662                          */
3663                         hsfsts.hsf_status.flcdone = 1;
3664                         if (hw->mac.type >= e1000_pch_spt)
3665                                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3666                                                       hsfsts.regval & 0xFFFF);
3667                         else
3668                                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3669                                                         hsfsts.regval);
3670                 } else {
3671                         DEBUGOUT("Flash controller busy, cannot get access\n");
3672                 }
3673         }
3674
3675         return ret_val;
3676 }
3677
3678 /**
3679  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3680  *  @hw: pointer to the HW structure
3681  *  @timeout: maximum time to wait for completion
3682  *
3683  *  This function starts a flash cycle and waits for its completion.
3684  **/
3685 STATIC s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3686 {
3687         union ich8_hws_flash_ctrl hsflctl;
3688         union ich8_hws_flash_status hsfsts;
3689         u32 i = 0;
3690
3691         DEBUGFUNC("e1000_flash_cycle_ich8lan");
3692
3693         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3694         if (hw->mac.type >= e1000_pch_spt)
3695                 hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
3696         else
3697                 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3698         hsflctl.hsf_ctrl.flcgo = 1;
3699
3700         if (hw->mac.type >= e1000_pch_spt)
3701                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3702                                       hsflctl.regval << 16);
3703         else
3704                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3705
3706         /* wait till FDONE bit is set to 1 */
3707         do {
3708                 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3709                 if (hsfsts.hsf_status.flcdone)
3710                         break;
3711                 usec_delay(1);
3712         } while (i++ < timeout);
3713
3714         if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3715                 return E1000_SUCCESS;
3716
3717         return -E1000_ERR_NVM;
3718 }
3719
3720 /**
3721  *  e1000_read_flash_dword_ich8lan - Read dword from flash
3722  *  @hw: pointer to the HW structure
3723  *  @offset: offset to data location
3724  *  @data: pointer to the location for storing the data
3725  *
3726  *  Reads the flash dword at offset into data.  Offset is converted
3727  *  to bytes before read.
3728  **/
3729 STATIC s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset,
3730                                           u32 *data)
3731 {
3732         DEBUGFUNC("e1000_read_flash_dword_ich8lan");
3733
3734         if (!data)
3735                 return -E1000_ERR_NVM;
3736
3737         /* Must convert word offset into bytes. */
3738         offset <<= 1;
3739
3740         return e1000_read_flash_data32_ich8lan(hw, offset, data);
3741 }
3742
3743 /**
3744  *  e1000_read_flash_word_ich8lan - Read word from flash
3745  *  @hw: pointer to the HW structure
3746  *  @offset: offset to data location
3747  *  @data: pointer to the location for storing the data
3748  *
3749  *  Reads the flash word at offset into data.  Offset is converted
3750  *  to bytes before read.
3751  **/
3752 STATIC s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3753                                          u16 *data)
3754 {
3755         DEBUGFUNC("e1000_read_flash_word_ich8lan");
3756
3757         if (!data)
3758                 return -E1000_ERR_NVM;
3759
3760         /* Must convert offset into bytes. */
3761         offset <<= 1;
3762
3763         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3764 }
3765
3766 /**
3767  *  e1000_read_flash_byte_ich8lan - Read byte from flash
3768  *  @hw: pointer to the HW structure
3769  *  @offset: The offset of the byte to read.
3770  *  @data: Pointer to a byte to store the value read.
3771  *
3772  *  Reads a single byte from the NVM using the flash access registers.
3773  **/
3774 STATIC s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3775                                          u8 *data)
3776 {
3777         s32 ret_val;
3778         u16 word = 0;
3779
3780         /* In SPT, only 32 bits access is supported,
3781          * so this function should not be called.
3782          */
3783         if (hw->mac.type >= e1000_pch_spt)
3784                 return -E1000_ERR_NVM;
3785         else
3786                 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3787
3788         if (ret_val)
3789                 return ret_val;
3790
3791         *data = (u8)word;
3792
3793         return E1000_SUCCESS;
3794 }
3795
3796 /**
3797  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
3798  *  @hw: pointer to the HW structure
3799  *  @offset: The offset (in bytes) of the byte or word to read.
3800  *  @size: Size of data to read, 1=byte 2=word
3801  *  @data: Pointer to the word to store the value read.
3802  *
3803  *  Reads a byte or word from the NVM using the flash access registers.
3804  **/
3805 STATIC s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3806                                          u8 size, u16 *data)
3807 {
3808         union ich8_hws_flash_status hsfsts;
3809         union ich8_hws_flash_ctrl hsflctl;
3810         u32 flash_linear_addr;
3811         u32 flash_data = 0;
3812         s32 ret_val = -E1000_ERR_NVM;
3813         u8 count = 0;
3814
3815         DEBUGFUNC("e1000_read_flash_data_ich8lan");
3816
3817         if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3818                 return -E1000_ERR_NVM;
3819         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3820                              hw->nvm.flash_base_addr);
3821
3822         do {
3823                 usec_delay(1);
3824                 /* Steps */
3825                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3826                 if (ret_val != E1000_SUCCESS)
3827                         break;
3828                 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3829
3830                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3831                 hsflctl.hsf_ctrl.fldbcount = size - 1;
3832                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3833                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3834                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3835
3836                 ret_val = e1000_flash_cycle_ich8lan(hw,
3837                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
3838
3839                 /* Check if FCERR is set to 1, if set to 1, clear it
3840                  * and try the whole sequence a few more times, else
3841                  * read in (shift in) the Flash Data0, the order is
3842                  * least significant byte first msb to lsb
3843                  */
3844                 if (ret_val == E1000_SUCCESS) {
3845                         flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
3846                         if (size == 1)
3847                                 *data = (u8)(flash_data & 0x000000FF);
3848                         else if (size == 2)
3849                                 *data = (u16)(flash_data & 0x0000FFFF);
3850                         break;
3851                 } else {
3852                         /* If we've gotten here, then things are probably
3853                          * completely hosed, but if the error condition is
3854                          * detected, it won't hurt to give it another try...
3855                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3856                          */
3857                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3858                                                               ICH_FLASH_HSFSTS);
3859                         if (hsfsts.hsf_status.flcerr) {
3860                                 /* Repeat for some time before giving up. */
3861                                 continue;
3862                         } else if (!hsfsts.hsf_status.flcdone) {
3863                                 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3864                                 break;
3865                         }
3866                 }
3867         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3868
3869         return ret_val;
3870 }
3871
3872 /**
3873  *  e1000_read_flash_data32_ich8lan - Read dword from NVM
3874  *  @hw: pointer to the HW structure
3875  *  @offset: The offset (in bytes) of the dword to read.
3876  *  @data: Pointer to the dword to store the value read.
3877  *
3878  *  Reads a byte or word from the NVM using the flash access registers.
3879  **/
3880 STATIC s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
3881                                            u32 *data)
3882 {
3883         union ich8_hws_flash_status hsfsts;
3884         union ich8_hws_flash_ctrl hsflctl;
3885         u32 flash_linear_addr;
3886         s32 ret_val = -E1000_ERR_NVM;
3887         u8 count = 0;
3888
3889         DEBUGFUNC("e1000_read_flash_data_ich8lan");
3890
3891                 if (offset > ICH_FLASH_LINEAR_ADDR_MASK ||
3892                     hw->mac.type < e1000_pch_spt)
3893                         return -E1000_ERR_NVM;
3894         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3895                              hw->nvm.flash_base_addr);
3896
3897         do {
3898                 usec_delay(1);
3899                 /* Steps */
3900                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3901                 if (ret_val != E1000_SUCCESS)
3902                         break;
3903                 /* In SPT, This register is in Lan memory space, not flash.
3904                  * Therefore, only 32 bit access is supported
3905                  */
3906                 hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
3907
3908                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3909                 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
3910                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3911                 /* In SPT, This register is in Lan memory space, not flash.
3912                  * Therefore, only 32 bit access is supported
3913                  */
3914                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3915                                       (u32)hsflctl.regval << 16);
3916                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3917
3918                 ret_val = e1000_flash_cycle_ich8lan(hw,
3919                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
3920
3921                 /* Check if FCERR is set to 1, if set to 1, clear it
3922                  * and try the whole sequence a few more times, else
3923                  * read in (shift in) the Flash Data0, the order is
3924                  * least significant byte first msb to lsb
3925                  */
3926                 if (ret_val == E1000_SUCCESS) {
3927                         *data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
3928                         break;
3929                 } else {
3930                         /* If we've gotten here, then things are probably
3931                          * completely hosed, but if the error condition is
3932                          * detected, it won't hurt to give it another try...
3933                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3934                          */
3935                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3936                                                               ICH_FLASH_HSFSTS);
3937                         if (hsfsts.hsf_status.flcerr) {
3938                                 /* Repeat for some time before giving up. */
3939                                 continue;
3940                         } else if (!hsfsts.hsf_status.flcdone) {
3941                                 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3942                                 break;
3943                         }
3944                 }
3945         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3946
3947         return ret_val;
3948 }
3949
3950 /**
3951  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
3952  *  @hw: pointer to the HW structure
3953  *  @offset: The offset (in bytes) of the word(s) to write.
3954  *  @words: Size of data to write in words
3955  *  @data: Pointer to the word(s) to write at offset.
3956  *
3957  *  Writes a byte or word to the NVM using the flash access registers.
3958  **/
3959 STATIC s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3960                                    u16 *data)
3961 {
3962         struct e1000_nvm_info *nvm = &hw->nvm;
3963         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3964         u16 i;
3965
3966         DEBUGFUNC("e1000_write_nvm_ich8lan");
3967
3968         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3969             (words == 0)) {
3970                 DEBUGOUT("nvm parameter(s) out of bounds\n");
3971                 return -E1000_ERR_NVM;
3972         }
3973
3974         nvm->ops.acquire(hw);
3975
3976         for (i = 0; i < words; i++) {
3977                 dev_spec->shadow_ram[offset+i].modified = true;
3978                 dev_spec->shadow_ram[offset+i].value = data[i];
3979         }
3980
3981         nvm->ops.release(hw);
3982
3983         return E1000_SUCCESS;
3984 }
3985
3986 /**
3987  *  e1000_update_nvm_checksum_spt - Update the checksum for NVM
3988  *  @hw: pointer to the HW structure
3989  *
3990  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
3991  *  which writes the checksum to the shadow ram.  The changes in the shadow
3992  *  ram are then committed to the EEPROM by processing each bank at a time
3993  *  checking for the modified bit and writing only the pending changes.
3994  *  After a successful commit, the shadow ram is cleared and is ready for
3995  *  future writes.
3996  **/
3997 STATIC s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)
3998 {
3999         struct e1000_nvm_info *nvm = &hw->nvm;
4000         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4001         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
4002         s32 ret_val;
4003         u32 dword = 0;
4004
4005         DEBUGFUNC("e1000_update_nvm_checksum_spt");
4006
4007         ret_val = e1000_update_nvm_checksum_generic(hw);
4008         if (ret_val)
4009                 goto out;
4010
4011         if (nvm->type != e1000_nvm_flash_sw)
4012                 goto out;
4013
4014         nvm->ops.acquire(hw);
4015
4016         /* We're writing to the opposite bank so if we're on bank 1,
4017          * write to bank 0 etc.  We also need to erase the segment that
4018          * is going to be written
4019          */
4020         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
4021         if (ret_val != E1000_SUCCESS) {
4022                 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
4023                 bank = 0;
4024         }
4025
4026         if (bank == 0) {
4027                 new_bank_offset = nvm->flash_bank_size;
4028                 old_bank_offset = 0;
4029                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
4030                 if (ret_val)
4031                         goto release;
4032         } else {
4033                 old_bank_offset = nvm->flash_bank_size;
4034                 new_bank_offset = 0;
4035                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
4036                 if (ret_val)
4037                         goto release;
4038         }
4039         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i += 2) {
4040                 /* Determine whether to write the value stored
4041                  * in the other NVM bank or a modified value stored
4042                  * in the shadow RAM
4043                  */
4044                 ret_val = e1000_read_flash_dword_ich8lan(hw,
4045                                                          i + old_bank_offset,
4046                                                          &dword);
4047
4048                 if (dev_spec->shadow_ram[i].modified) {
4049                         dword &= 0xffff0000;
4050                         dword |= (dev_spec->shadow_ram[i].value & 0xffff);
4051                 }
4052                 if (dev_spec->shadow_ram[i + 1].modified) {
4053                         dword &= 0x0000ffff;
4054                         dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff)
4055                                   << 16);
4056                 }
4057                 if (ret_val)
4058                         break;
4059
4060                 /* If the word is 0x13, then make sure the signature bits
4061                  * (15:14) are 11b until the commit has completed.
4062                  * This will allow us to write 10b which indicates the
4063                  * signature is valid.  We want to do this after the write
4064                  * has completed so that we don't mark the segment valid
4065                  * while the write is still in progress
4066                  */
4067                 if (i == E1000_ICH_NVM_SIG_WORD - 1)
4068                         dword |= E1000_ICH_NVM_SIG_MASK << 16;
4069
4070                 /* Convert offset to bytes. */
4071                 act_offset = (i + new_bank_offset) << 1;
4072
4073                 usec_delay(100);
4074
4075                 /* Write the data to the new bank. Offset in words*/
4076                 act_offset = i + new_bank_offset;
4077                 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,
4078                                                                 dword);
4079                 if (ret_val)
4080                         break;
4081          }
4082
4083         /* Don't bother writing the segment valid bits if sector
4084          * programming failed.
4085          */
4086         if (ret_val) {
4087                 DEBUGOUT("Flash commit failed.\n");
4088                 goto release;
4089         }
4090
4091         /* Finally validate the new segment by setting bit 15:14
4092          * to 10b in word 0x13 , this can be done without an
4093          * erase as well since these bits are 11 to start with
4094          * and we need to change bit 14 to 0b
4095          */
4096         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4097
4098         /*offset in words but we read dword*/
4099         --act_offset;
4100         ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
4101
4102         if (ret_val)
4103                 goto release;
4104
4105         dword &= 0xBFFFFFFF;
4106         ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
4107
4108         if (ret_val)
4109                 goto release;
4110
4111         /* And invalidate the previously valid segment by setting
4112          * its signature word (0x13) high_byte to 0b. This can be
4113          * done without an erase because flash erase sets all bits
4114          * to 1's. We can write 1's to 0's without an erase
4115          */
4116         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
4117
4118         /* offset in words but we read dword*/
4119         act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1;
4120         ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
4121
4122         if (ret_val)
4123                 goto release;
4124
4125         dword &= 0x00FFFFFF;
4126         ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
4127
4128         if (ret_val)
4129                 goto release;
4130
4131         /* Great!  Everything worked, we can now clear the cached entries. */
4132         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4133                 dev_spec->shadow_ram[i].modified = false;
4134                 dev_spec->shadow_ram[i].value = 0xFFFF;
4135         }
4136
4137 release:
4138         nvm->ops.release(hw);
4139
4140         /* Reload the EEPROM, or else modifications will not appear
4141          * until after the next adapter reset.
4142          */
4143         if (!ret_val) {
4144                 nvm->ops.reload(hw);
4145                 msec_delay(10);
4146         }
4147
4148 out:
4149         if (ret_val)
4150                 DEBUGOUT1("NVM update error: %d\n", ret_val);
4151
4152         return ret_val;
4153 }
4154
4155 /**
4156  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
4157  *  @hw: pointer to the HW structure
4158  *
4159  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
4160  *  which writes the checksum to the shadow ram.  The changes in the shadow
4161  *  ram are then committed to the EEPROM by processing each bank at a time
4162  *  checking for the modified bit and writing only the pending changes.
4163  *  After a successful commit, the shadow ram is cleared and is ready for
4164  *  future writes.
4165  **/
4166 STATIC s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
4167 {
4168         struct e1000_nvm_info *nvm = &hw->nvm;
4169         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4170         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
4171         s32 ret_val;
4172         u16 data = 0;
4173
4174         DEBUGFUNC("e1000_update_nvm_checksum_ich8lan");
4175
4176         ret_val = e1000_update_nvm_checksum_generic(hw);
4177         if (ret_val)
4178                 goto out;
4179
4180         if (nvm->type != e1000_nvm_flash_sw)
4181                 goto out;
4182
4183         nvm->ops.acquire(hw);
4184
4185         /* We're writing to the opposite bank so if we're on bank 1,
4186          * write to bank 0 etc.  We also need to erase the segment that
4187          * is going to be written
4188          */
4189         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
4190         if (ret_val != E1000_SUCCESS) {
4191                 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
4192                 bank = 0;
4193         }
4194
4195         if (bank == 0) {
4196                 new_bank_offset = nvm->flash_bank_size;
4197                 old_bank_offset = 0;
4198                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
4199                 if (ret_val)
4200                         goto release;
4201         } else {
4202                 old_bank_offset = nvm->flash_bank_size;
4203                 new_bank_offset = 0;
4204                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
4205                 if (ret_val)
4206                         goto release;
4207         }
4208         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4209                 if (dev_spec->shadow_ram[i].modified) {
4210                         data = dev_spec->shadow_ram[i].value;
4211                 } else {
4212                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
4213                                                                 old_bank_offset,
4214                                                                 &data);
4215                         if (ret_val)
4216                                 break;
4217                 }
4218                 /* If the word is 0x13, then make sure the signature bits
4219                  * (15:14) are 11b until the commit has completed.
4220                  * This will allow us to write 10b which indicates the
4221                  * signature is valid.  We want to do this after the write
4222                  * has completed so that we don't mark the segment valid
4223                  * while the write is still in progress
4224                  */
4225                 if (i == E1000_ICH_NVM_SIG_WORD)
4226                         data |= E1000_ICH_NVM_SIG_MASK;
4227
4228                 /* Convert offset to bytes. */
4229                 act_offset = (i + new_bank_offset) << 1;
4230
4231                 usec_delay(100);
4232
4233                 /* Write the bytes to the new bank. */
4234                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4235                                                                act_offset,
4236                                                                (u8)data);
4237                 if (ret_val)
4238                         break;
4239
4240                 usec_delay(100);
4241                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4242                                                           act_offset + 1,
4243                                                           (u8)(data >> 8));
4244                 if (ret_val)
4245                         break;
4246         }
4247
4248         /* Don't bother writing the segment valid bits if sector
4249          * programming failed.
4250          */
4251         if (ret_val) {
4252                 DEBUGOUT("Flash commit failed.\n");
4253                 goto release;
4254         }
4255
4256         /* Finally validate the new segment by setting bit 15:14
4257          * to 10b in word 0x13 , this can be done without an
4258          * erase as well since these bits are 11 to start with
4259          * and we need to change bit 14 to 0b
4260          */
4261         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4262         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
4263         if (ret_val)
4264                 goto release;
4265
4266         data &= 0xBFFF;
4267         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset * 2 + 1,
4268                                                        (u8)(data >> 8));
4269         if (ret_val)
4270                 goto release;
4271
4272         /* And invalidate the previously valid segment by setting
4273          * its signature word (0x13) high_byte to 0b. This can be
4274          * done without an erase because flash erase sets all bits
4275          * to 1's. We can write 1's to 0's without an erase
4276          */
4277         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
4278
4279         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
4280
4281         if (ret_val)
4282                 goto release;
4283
4284         /* Great!  Everything worked, we can now clear the cached entries. */
4285         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4286                 dev_spec->shadow_ram[i].modified = false;
4287                 dev_spec->shadow_ram[i].value = 0xFFFF;
4288         }
4289
4290 release:
4291         nvm->ops.release(hw);
4292
4293         /* Reload the EEPROM, or else modifications will not appear
4294          * until after the next adapter reset.
4295          */
4296         if (!ret_val) {
4297                 nvm->ops.reload(hw);
4298                 msec_delay(10);
4299         }
4300
4301 out:
4302         if (ret_val)
4303                 DEBUGOUT1("NVM update error: %d\n", ret_val);
4304
4305         return ret_val;
4306 }
4307
4308 /**
4309  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
4310  *  @hw: pointer to the HW structure
4311  *
4312  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
4313  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
4314  *  calculated, in which case we need to calculate the checksum and set bit 6.
4315  **/
4316 STATIC s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
4317 {
4318         s32 ret_val;
4319         u16 data;
4320         u16 word;
4321         u16 valid_csum_mask;
4322
4323         DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan");
4324
4325         /* Read NVM and check Invalid Image CSUM bit.  If this bit is 0,
4326          * the checksum needs to be fixed.  This bit is an indication that
4327          * the NVM was prepared by OEM software and did not calculate
4328          * the checksum...a likely scenario.
4329          */
4330         switch (hw->mac.type) {
4331         case e1000_pch_lpt:
4332         case e1000_pch_spt:
4333         case e1000_pch_cnp:
4334                 word = NVM_COMPAT;
4335                 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
4336                 break;
4337         default:
4338                 word = NVM_FUTURE_INIT_WORD1;
4339                 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
4340                 break;
4341         }
4342
4343         ret_val = hw->nvm.ops.read(hw, word, 1, &data);
4344         if (ret_val)
4345                 return ret_val;
4346
4347         if (!(data & valid_csum_mask)) {
4348                 data |= valid_csum_mask;
4349                 ret_val = hw->nvm.ops.write(hw, word, 1, &data);
4350                 if (ret_val)
4351                         return ret_val;
4352                 ret_val = hw->nvm.ops.update(hw);
4353                 if (ret_val)
4354                         return ret_val;
4355         }
4356
4357         return e1000_validate_nvm_checksum_generic(hw);
4358 }
4359
4360 /**
4361  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
4362  *  @hw: pointer to the HW structure
4363  *  @offset: The offset (in bytes) of the byte/word to read.
4364  *  @size: Size of data to read, 1=byte 2=word
4365  *  @data: The byte(s) to write to the NVM.
4366  *
4367  *  Writes one/two bytes to the NVM using the flash access registers.
4368  **/
4369 STATIC s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
4370                                           u8 size, u16 data)
4371 {
4372         union ich8_hws_flash_status hsfsts;
4373         union ich8_hws_flash_ctrl hsflctl;
4374         u32 flash_linear_addr;
4375         u32 flash_data = 0;
4376         s32 ret_val;
4377         u8 count = 0;
4378
4379         DEBUGFUNC("e1000_write_ich8_data");
4380
4381         if (hw->mac.type >= e1000_pch_spt) {
4382                 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4383                         return -E1000_ERR_NVM;
4384         } else {
4385                 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4386                         return -E1000_ERR_NVM;
4387         }
4388
4389         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4390                              hw->nvm.flash_base_addr);
4391
4392         do {
4393                 usec_delay(1);
4394                 /* Steps */
4395                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4396                 if (ret_val != E1000_SUCCESS)
4397                         break;
4398                 /* In SPT, This register is in Lan memory space, not
4399                  * flash.  Therefore, only 32 bit access is supported
4400                  */
4401                 if (hw->mac.type >= e1000_pch_spt)
4402                         hsflctl.regval =
4403                             E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
4404                 else
4405                         hsflctl.regval =
4406                             E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
4407
4408                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
4409                 hsflctl.hsf_ctrl.fldbcount = size - 1;
4410                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4411                 /* In SPT, This register is in Lan memory space,
4412                  * not flash.  Therefore, only 32 bit access is
4413                  * supported
4414                  */
4415                 if (hw->mac.type >= e1000_pch_spt)
4416                         E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4417                                               hsflctl.regval << 16);
4418                 else
4419                         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4420                                                 hsflctl.regval);
4421
4422                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
4423
4424                 if (size == 1)
4425                         flash_data = (u32)data & 0x00FF;
4426                 else
4427                         flash_data = (u32)data;
4428
4429                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
4430
4431                 /* check if FCERR is set to 1 , if set to 1, clear it
4432                  * and try the whole sequence a few more times else done
4433                  */
4434                 ret_val =
4435                     e1000_flash_cycle_ich8lan(hw,
4436                                               ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4437                 if (ret_val == E1000_SUCCESS)
4438                         break;
4439
4440                 /* If we're here, then things are most likely
4441                  * completely hosed, but if the error condition
4442                  * is detected, it won't hurt to give it another
4443                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4444                  */
4445                 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4446                 if (hsfsts.hsf_status.flcerr)
4447                         /* Repeat for some time before giving up. */
4448                         continue;
4449                 if (!hsfsts.hsf_status.flcdone) {
4450                         DEBUGOUT("Timeout error - flash cycle did not complete.\n");
4451                         break;
4452                 }
4453         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4454
4455         return ret_val;
4456 }
4457
4458 /**
4459 *  e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM
4460 *  @hw: pointer to the HW structure
4461 *  @offset: The offset (in bytes) of the dwords to read.
4462 *  @data: The 4 bytes to write to the NVM.
4463 *
4464 *  Writes one/two/four bytes to the NVM using the flash access registers.
4465 **/
4466 STATIC s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
4467                                             u32 data)
4468 {
4469         union ich8_hws_flash_status hsfsts;
4470         union ich8_hws_flash_ctrl hsflctl;
4471         u32 flash_linear_addr;
4472         s32 ret_val;
4473         u8 count = 0;
4474
4475         DEBUGFUNC("e1000_write_flash_data32_ich8lan");
4476
4477         if (hw->mac.type >= e1000_pch_spt) {
4478                 if (offset > ICH_FLASH_LINEAR_ADDR_MASK)
4479                         return -E1000_ERR_NVM;
4480         }
4481         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4482                              hw->nvm.flash_base_addr);
4483         do {
4484                 usec_delay(1);
4485                 /* Steps */
4486                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4487                 if (ret_val != E1000_SUCCESS)
4488                         break;
4489
4490                 /* In SPT, This register is in Lan memory space, not
4491                  * flash.  Therefore, only 32 bit access is supported
4492                  */
4493                 if (hw->mac.type >= e1000_pch_spt)
4494                         hsflctl.regval = E1000_READ_FLASH_REG(hw,
4495                                                               ICH_FLASH_HSFSTS)
4496                                          >> 16;
4497                 else
4498                         hsflctl.regval = E1000_READ_FLASH_REG16(hw,
4499                                                               ICH_FLASH_HSFCTL);
4500
4501                 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
4502                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4503
4504                 /* In SPT, This register is in Lan memory space,
4505                  * not flash.  Therefore, only 32 bit access is
4506                  * supported
4507                  */
4508                 if (hw->mac.type >= e1000_pch_spt)
4509                         E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4510                                               hsflctl.regval << 16);
4511                 else
4512                         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4513                                                 hsflctl.regval);
4514
4515                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
4516
4517                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, data);
4518
4519                 /* check if FCERR is set to 1 , if set to 1, clear it
4520                  * and try the whole sequence a few more times else done
4521                  */
4522                 ret_val = e1000_flash_cycle_ich8lan(hw,
4523                                                ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4524
4525                 if (ret_val == E1000_SUCCESS)
4526                         break;
4527
4528                 /* If we're here, then things are most likely
4529                  * completely hosed, but if the error condition
4530                  * is detected, it won't hurt to give it another
4531                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4532                  */
4533                 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4534
4535                 if (hsfsts.hsf_status.flcerr)
4536                         /* Repeat for some time before giving up. */
4537                         continue;
4538                 if (!hsfsts.hsf_status.flcdone) {
4539                         DEBUGOUT("Timeout error - flash cycle did not complete.\n");
4540                         break;
4541                 }
4542         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4543
4544         return ret_val;
4545 }
4546
4547 /**
4548  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
4549  *  @hw: pointer to the HW structure
4550  *  @offset: The index of the byte to read.
4551  *  @data: The byte to write to the NVM.
4552  *
4553  *  Writes a single byte to the NVM using the flash access registers.
4554  **/
4555 STATIC s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
4556                                           u8 data)
4557 {
4558         u16 word = (u16)data;
4559
4560         DEBUGFUNC("e1000_write_flash_byte_ich8lan");
4561
4562         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
4563 }
4564
4565 /**
4566 *  e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM
4567 *  @hw: pointer to the HW structure
4568 *  @offset: The offset of the word to write.
4569 *  @dword: The dword to write to the NVM.
4570 *
4571 *  Writes a single dword to the NVM using the flash access registers.
4572 *  Goes through a retry algorithm before giving up.
4573 **/
4574 STATIC s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
4575                                                  u32 offset, u32 dword)
4576 {
4577         s32 ret_val;
4578         u16 program_retries;
4579
4580         DEBUGFUNC("e1000_retry_write_flash_dword_ich8lan");
4581
4582         /* Must convert word offset into bytes. */
4583         offset <<= 1;
4584
4585         ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4586
4587         if (!ret_val)
4588                 return ret_val;
4589         for (program_retries = 0; program_retries < 100; program_retries++) {
4590                 DEBUGOUT2("Retrying Byte %8.8X at offset %u\n", dword, offset);
4591                 usec_delay(100);
4592                 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4593                 if (ret_val == E1000_SUCCESS)
4594                         break;
4595         }
4596         if (program_retries == 100)
4597                 return -E1000_ERR_NVM;
4598
4599         return E1000_SUCCESS;
4600 }
4601
4602 /**
4603  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
4604  *  @hw: pointer to the HW structure
4605  *  @offset: The offset of the byte to write.
4606  *  @byte: The byte to write to the NVM.
4607  *
4608  *  Writes a single byte to the NVM using the flash access registers.
4609  *  Goes through a retry algorithm before giving up.
4610  **/
4611 STATIC s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
4612                                                 u32 offset, u8 byte)
4613 {
4614         s32 ret_val;
4615         u16 program_retries;
4616
4617         DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan");
4618
4619         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4620         if (!ret_val)
4621                 return ret_val;
4622
4623         for (program_retries = 0; program_retries < 100; program_retries++) {
4624                 DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset);
4625                 usec_delay(100);
4626                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4627                 if (ret_val == E1000_SUCCESS)
4628                         break;
4629         }
4630         if (program_retries == 100)
4631                 return -E1000_ERR_NVM;
4632
4633         return E1000_SUCCESS;
4634 }
4635
4636 /**
4637  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
4638  *  @hw: pointer to the HW structure
4639  *  @bank: 0 for first bank, 1 for second bank, etc.
4640  *
4641  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
4642  *  bank N is 4096 * N + flash_reg_addr.
4643  **/
4644 STATIC s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
4645 {
4646         struct e1000_nvm_info *nvm = &hw->nvm;
4647         union ich8_hws_flash_status hsfsts;
4648         union ich8_hws_flash_ctrl hsflctl;
4649         u32 flash_linear_addr;
4650         /* bank size is in 16bit words - adjust to bytes */
4651         u32 flash_bank_size = nvm->flash_bank_size * 2;
4652         s32 ret_val;
4653         s32 count = 0;
4654         s32 j, iteration, sector_size;
4655
4656         DEBUGFUNC("e1000_erase_flash_bank_ich8lan");
4657
4658         hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4659
4660         /* Determine HW Sector size: Read BERASE bits of hw flash status
4661          * register
4662          * 00: The Hw sector is 256 bytes, hence we need to erase 16
4663          *     consecutive sectors.  The start index for the nth Hw sector
4664          *     can be calculated as = bank * 4096 + n * 256
4665          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
4666          *     The start index for the nth Hw sector can be calculated
4667          *     as = bank * 4096
4668          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
4669          *     (ich9 only, otherwise error condition)
4670          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
4671          */
4672         switch (hsfsts.hsf_status.berasesz) {
4673         case 0:
4674                 /* Hw sector size 256 */
4675                 sector_size = ICH_FLASH_SEG_SIZE_256;
4676                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
4677                 break;
4678         case 1:
4679                 sector_size = ICH_FLASH_SEG_SIZE_4K;
4680                 iteration = 1;
4681                 break;
4682         case 2:
4683                 sector_size = ICH_FLASH_SEG_SIZE_8K;
4684                 iteration = 1;
4685                 break;
4686         case 3:
4687                 sector_size = ICH_FLASH_SEG_SIZE_64K;
4688                 iteration = 1;
4689                 break;
4690         default:
4691                 return -E1000_ERR_NVM;
4692         }
4693
4694         /* Start with the base address, then add the sector offset. */
4695         flash_linear_addr = hw->nvm.flash_base_addr;
4696         flash_linear_addr += (bank) ? flash_bank_size : 0;
4697
4698         for (j = 0; j < iteration; j++) {
4699                 do {
4700                         u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
4701
4702                         /* Steps */
4703                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
4704                         if (ret_val)
4705                                 return ret_val;
4706
4707                         /* Write a value 11 (block Erase) in Flash
4708                          * Cycle field in hw flash control
4709                          */
4710                         if (hw->mac.type >= e1000_pch_spt)
4711                                 hsflctl.regval =
4712                                     E1000_READ_FLASH_REG(hw,
4713                                                          ICH_FLASH_HSFSTS)>>16;
4714                         else
4715                                 hsflctl.regval =
4716                                     E1000_READ_FLASH_REG16(hw,
4717                                                            ICH_FLASH_HSFCTL);
4718
4719                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
4720                         if (hw->mac.type >= e1000_pch_spt)
4721                                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4722                                                       hsflctl.regval << 16);
4723                         else
4724                                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4725                                                         hsflctl.regval);
4726
4727                         /* Write the last 24 bits of an index within the
4728                          * block into Flash Linear address field in Flash
4729                          * Address.
4730                          */
4731                         flash_linear_addr += (j * sector_size);
4732                         E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR,
4733                                               flash_linear_addr);
4734
4735                         ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4736                         if (ret_val == E1000_SUCCESS)
4737                                 break;
4738
4739                         /* Check if FCERR is set to 1.  If 1,
4740                          * clear it and try the whole sequence
4741                          * a few more times else Done
4742                          */
4743                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
4744                                                       ICH_FLASH_HSFSTS);
4745                         if (hsfsts.hsf_status.flcerr)
4746                                 /* repeat for some time before giving up */
4747                                 continue;
4748                         else if (!hsfsts.hsf_status.flcdone)
4749                                 return ret_val;
4750                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
4751         }
4752
4753         return E1000_SUCCESS;
4754 }
4755
4756 /**
4757  *  e1000_valid_led_default_ich8lan - Set the default LED settings
4758  *  @hw: pointer to the HW structure
4759  *  @data: Pointer to the LED settings
4760  *
4761  *  Reads the LED default settings from the NVM to data.  If the NVM LED
4762  *  settings is all 0's or F's, set the LED default to a valid LED default
4763  *  setting.
4764  **/
4765 STATIC s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
4766 {
4767         s32 ret_val;
4768
4769         DEBUGFUNC("e1000_valid_led_default_ich8lan");
4770
4771         ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
4772         if (ret_val) {
4773                 DEBUGOUT("NVM Read Error\n");
4774                 return ret_val;
4775         }
4776
4777         if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
4778                 *data = ID_LED_DEFAULT_ICH8LAN;
4779
4780         return E1000_SUCCESS;
4781 }
4782
4783 /**
4784  *  e1000_id_led_init_pchlan - store LED configurations
4785  *  @hw: pointer to the HW structure
4786  *
4787  *  PCH does not control LEDs via the LEDCTL register, rather it uses
4788  *  the PHY LED configuration register.
4789  *
4790  *  PCH also does not have an "always on" or "always off" mode which
4791  *  complicates the ID feature.  Instead of using the "on" mode to indicate
4792  *  in ledctl_mode2 the LEDs to use for ID (see e1000_id_led_init_generic()),
4793  *  use "link_up" mode.  The LEDs will still ID on request if there is no
4794  *  link based on logic in e1000_led_[on|off]_pchlan().
4795  **/
4796 STATIC s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4797 {
4798         struct e1000_mac_info *mac = &hw->mac;
4799         s32 ret_val;
4800         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
4801         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
4802         u16 data, i, temp, shift;
4803
4804         DEBUGFUNC("e1000_id_led_init_pchlan");
4805
4806         /* Get default ID LED modes */
4807         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4808         if (ret_val)
4809                 return ret_val;
4810
4811         mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
4812         mac->ledctl_mode1 = mac->ledctl_default;
4813         mac->ledctl_mode2 = mac->ledctl_default;
4814
4815         for (i = 0; i < 4; i++) {
4816                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
4817                 shift = (i * 5);
4818                 switch (temp) {
4819                 case ID_LED_ON1_DEF2:
4820                 case ID_LED_ON1_ON2:
4821                 case ID_LED_ON1_OFF2:
4822                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4823                         mac->ledctl_mode1 |= (ledctl_on << shift);
4824                         break;
4825                 case ID_LED_OFF1_DEF2:
4826                 case ID_LED_OFF1_ON2:
4827                 case ID_LED_OFF1_OFF2:
4828                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4829                         mac->ledctl_mode1 |= (ledctl_off << shift);
4830                         break;
4831                 default:
4832                         /* Do nothing */
4833                         break;
4834                 }
4835                 switch (temp) {
4836                 case ID_LED_DEF1_ON2:
4837                 case ID_LED_ON1_ON2:
4838                 case ID_LED_OFF1_ON2:
4839                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4840                         mac->ledctl_mode2 |= (ledctl_on << shift);
4841                         break;
4842                 case ID_LED_DEF1_OFF2:
4843                 case ID_LED_ON1_OFF2:
4844                 case ID_LED_OFF1_OFF2:
4845                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4846                         mac->ledctl_mode2 |= (ledctl_off << shift);
4847                         break;
4848                 default:
4849                         /* Do nothing */
4850                         break;
4851                 }
4852         }
4853
4854         return E1000_SUCCESS;
4855 }
4856
4857 /**
4858  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4859  *  @hw: pointer to the HW structure
4860  *
4861  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4862  *  register, so the bus width is hard coded.
4863  **/
4864 STATIC s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4865 {
4866         struct e1000_bus_info *bus = &hw->bus;
4867         s32 ret_val;
4868
4869         DEBUGFUNC("e1000_get_bus_info_ich8lan");
4870
4871         ret_val = e1000_get_bus_info_pcie_generic(hw);
4872
4873         /* ICH devices are "PCI Express"-ish.  They have
4874          * a configuration space, but do not contain
4875          * PCI Express Capability registers, so bus width
4876          * must be hardcoded.
4877          */
4878         if (bus->width == e1000_bus_width_unknown)
4879                 bus->width = e1000_bus_width_pcie_x1;
4880
4881         return ret_val;
4882 }
4883
4884 /**
4885  *  e1000_reset_hw_ich8lan - Reset the hardware
4886  *  @hw: pointer to the HW structure
4887  *
4888  *  Does a full reset of the hardware which includes a reset of the PHY and
4889  *  MAC.
4890  **/
4891 STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4892 {
4893         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4894         u16 kum_cfg;
4895         u32 ctrl, reg;
4896         s32 ret_val;
4897
4898         DEBUGFUNC("e1000_reset_hw_ich8lan");
4899
4900         /* Prevent the PCI-E bus from sticking if there is no TLP connection
4901          * on the last TLP read/write transaction when MAC is reset.
4902          */
4903         ret_val = e1000_disable_pcie_master_generic(hw);
4904         if (ret_val)
4905                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
4906
4907         DEBUGOUT("Masking off all interrupts\n");
4908         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
4909
4910         /* Disable the Transmit and Receive units.  Then delay to allow
4911          * any pending transactions to complete before we hit the MAC
4912          * with the global reset.
4913          */
4914         E1000_WRITE_REG(hw, E1000_RCTL, 0);
4915         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
4916         E1000_WRITE_FLUSH(hw);
4917
4918         msec_delay(10);
4919
4920         /* Workaround for ICH8 bit corruption issue in FIFO memory */
4921         if (hw->mac.type == e1000_ich8lan) {
4922                 /* Set Tx and Rx buffer allocation to 8k apiece. */
4923                 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K);
4924                 /* Set Packet Buffer Size to 16k. */
4925                 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K);
4926         }
4927
4928         if (hw->mac.type == e1000_pchlan) {
4929                 /* Save the NVM K1 bit setting*/
4930                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
4931                 if (ret_val)
4932                         return ret_val;
4933
4934                 if (kum_cfg & E1000_NVM_K1_ENABLE)
4935                         dev_spec->nvm_k1_enabled = true;
4936                 else
4937                         dev_spec->nvm_k1_enabled = false;
4938         }
4939
4940         ctrl = E1000_READ_REG(hw, E1000_CTRL);
4941
4942         if (!hw->phy.ops.check_reset_block(hw)) {
4943                 /* Full-chip reset requires MAC and PHY reset at the same
4944                  * time to make sure the interface between MAC and the
4945                  * external PHY is reset.
4946                  */
4947                 ctrl |= E1000_CTRL_PHY_RST;
4948
4949                 /* Gate automatic PHY configuration by hardware on
4950                  * non-managed 82579
4951                  */
4952                 if ((hw->mac.type == e1000_pch2lan) &&
4953                     !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
4954                         e1000_gate_hw_phy_config_ich8lan(hw, true);
4955         }
4956         ret_val = e1000_acquire_swflag_ich8lan(hw);
4957         DEBUGOUT("Issuing a global reset to ich8lan\n");
4958         E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
4959         /* cannot issue a flush here because it hangs the hardware */
4960         msec_delay(20);
4961
4962         /* Set Phy Config Counter to 50msec */
4963         if (hw->mac.type == e1000_pch2lan) {
4964                 reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
4965                 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
4966                 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
4967                 E1000_WRITE_REG(hw, E1000_FEXTNVM3, reg);
4968         }
4969
4970         if (!ret_val)
4971                 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
4972
4973         if (ctrl & E1000_CTRL_PHY_RST) {
4974                 ret_val = hw->phy.ops.get_cfg_done(hw);
4975                 if (ret_val)
4976                         return ret_val;
4977
4978                 ret_val = e1000_post_phy_reset_ich8lan(hw);
4979                 if (ret_val)
4980                         return ret_val;
4981         }
4982
4983         /* For PCH, this write will make sure that any noise
4984          * will be detected as a CRC error and be dropped rather than show up
4985          * as a bad packet to the DMA engine.
4986          */
4987         if (hw->mac.type == e1000_pchlan)
4988                 E1000_WRITE_REG(hw, E1000_CRC_OFFSET, 0x65656565);
4989
4990         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
4991         E1000_READ_REG(hw, E1000_ICR);
4992
4993         reg = E1000_READ_REG(hw, E1000_KABGTXD);
4994         reg |= E1000_KABGTXD_BGSQLBIAS;
4995         E1000_WRITE_REG(hw, E1000_KABGTXD, reg);
4996
4997         return E1000_SUCCESS;
4998 }
4999
5000 /**
5001  *  e1000_init_hw_ich8lan - Initialize the hardware
5002  *  @hw: pointer to the HW structure
5003  *
5004  *  Prepares the hardware for transmit and receive by doing the following:
5005  *   - initialize hardware bits
5006  *   - initialize LED identification
5007  *   - setup receive address registers
5008  *   - setup flow control
5009  *   - setup transmit descriptors
5010  *   - clear statistics
5011  **/
5012 STATIC s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
5013 {
5014         struct e1000_mac_info *mac = &hw->mac;
5015         u32 ctrl_ext, txdctl, snoop;
5016         s32 ret_val;
5017         u16 i;
5018
5019         DEBUGFUNC("e1000_init_hw_ich8lan");
5020
5021         e1000_initialize_hw_bits_ich8lan(hw);
5022
5023         /* Initialize identification LED */
5024         ret_val = mac->ops.id_led_init(hw);
5025         /* An error is not fatal and we should not stop init due to this */
5026         if (ret_val)
5027                 DEBUGOUT("Error initializing identification LED\n");
5028
5029         /* Setup the receive address. */
5030         e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
5031
5032         /* Zero out the Multicast HASH table */
5033         DEBUGOUT("Zeroing the MTA\n");
5034         for (i = 0; i < mac->mta_reg_count; i++)
5035                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
5036
5037         /* The 82578 Rx buffer will stall if wakeup is enabled in host and
5038          * the ME.  Disable wakeup by clearing the host wakeup bit.
5039          * Reset the phy after disabling host wakeup to reset the Rx buffer.
5040          */
5041         if (hw->phy.type == e1000_phy_82578) {
5042                 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &i);
5043                 i &= ~BM_WUC_HOST_WU_BIT;
5044                 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, i);
5045                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
5046                 if (ret_val)
5047                         return ret_val;
5048         }
5049
5050         /* Setup link and flow control */
5051         ret_val = mac->ops.setup_link(hw);
5052
5053         /* Set the transmit descriptor write-back policy for both queues */
5054         txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
5055         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
5056                   E1000_TXDCTL_FULL_TX_DESC_WB);
5057         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
5058                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
5059         E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
5060         txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1));
5061         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
5062                   E1000_TXDCTL_FULL_TX_DESC_WB);
5063         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
5064                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
5065         E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl);
5066
5067         /* ICH8 has opposite polarity of no_snoop bits.
5068          * By default, we should use snoop behavior.
5069          */
5070         if (mac->type == e1000_ich8lan)
5071                 snoop = PCIE_ICH8_SNOOP_ALL;
5072         else
5073                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
5074         e1000_set_pcie_no_snoop_generic(hw, snoop);
5075
5076         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
5077         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
5078         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
5079
5080         /* Clear all of the statistics registers (clear on read).  It is
5081          * important that we do this after we have tried to establish link
5082          * because the symbol error count will increment wildly if there
5083          * is no link.
5084          */
5085         e1000_clear_hw_cntrs_ich8lan(hw);
5086
5087         return ret_val;
5088 }
5089
5090 /**
5091  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
5092  *  @hw: pointer to the HW structure
5093  *
5094  *  Sets/Clears required hardware bits necessary for correctly setting up the
5095  *  hardware for transmit and receive.
5096  **/
5097 STATIC void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
5098 {
5099         u32 reg;
5100
5101         DEBUGFUNC("e1000_initialize_hw_bits_ich8lan");
5102
5103         /* Extended Device Control */
5104         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
5105         reg |= (1 << 22);
5106         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
5107         if (hw->mac.type >= e1000_pchlan)
5108                 reg |= E1000_CTRL_EXT_PHYPDEN;
5109         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
5110
5111         /* Transmit Descriptor Control 0 */
5112         reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
5113         reg |= (1 << 22);
5114         E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
5115
5116         /* Transmit Descriptor Control 1 */
5117         reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
5118         reg |= (1 << 22);
5119         E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
5120
5121         /* Transmit Arbitration Control 0 */
5122         reg = E1000_READ_REG(hw, E1000_TARC(0));
5123         if (hw->mac.type == e1000_ich8lan)
5124                 reg |= (1 << 28) | (1 << 29);
5125         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
5126         E1000_WRITE_REG(hw, E1000_TARC(0), reg);
5127
5128         /* Transmit Arbitration Control 1 */
5129         reg = E1000_READ_REG(hw, E1000_TARC(1));
5130         if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
5131                 reg &= ~(1 << 28);
5132         else
5133                 reg |= (1 << 28);
5134         reg |= (1 << 24) | (1 << 26) | (1 << 30);
5135         E1000_WRITE_REG(hw, E1000_TARC(1), reg);
5136
5137         /* Device Status */
5138         if (hw->mac.type == e1000_ich8lan) {
5139                 reg = E1000_READ_REG(hw, E1000_STATUS);
5140                 reg &= ~(1U << 31);
5141                 E1000_WRITE_REG(hw, E1000_STATUS, reg);
5142         }
5143
5144         /* work-around descriptor data corruption issue during nfs v2 udp
5145          * traffic, just disable the nfs filtering capability
5146          */
5147         reg = E1000_READ_REG(hw, E1000_RFCTL);
5148         reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
5149
5150         /* Disable IPv6 extension header parsing because some malformed
5151          * IPv6 headers can hang the Rx.
5152          */
5153         if (hw->mac.type == e1000_ich8lan)
5154                 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
5155         E1000_WRITE_REG(hw, E1000_RFCTL, reg);
5156
5157         /* Enable ECC on Lynxpoint */
5158         if (hw->mac.type >= e1000_pch_lpt) {
5159                 reg = E1000_READ_REG(hw, E1000_PBECCSTS);
5160                 reg |= E1000_PBECCSTS_ECC_ENABLE;
5161                 E1000_WRITE_REG(hw, E1000_PBECCSTS, reg);
5162
5163                 reg = E1000_READ_REG(hw, E1000_CTRL);
5164                 reg |= E1000_CTRL_MEHE;
5165                 E1000_WRITE_REG(hw, E1000_CTRL, reg);
5166         }
5167
5168         return;
5169 }
5170
5171 /**
5172  *  e1000_setup_link_ich8lan - Setup flow control and link settings
5173  *  @hw: pointer to the HW structure
5174  *
5175  *  Determines which flow control settings to use, then configures flow
5176  *  control.  Calls the appropriate media-specific link configuration
5177  *  function.  Assuming the adapter has a valid link partner, a valid link
5178  *  should be established.  Assumes the hardware has previously been reset
5179  *  and the transmitter and receiver are not enabled.
5180  **/
5181 STATIC s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
5182 {
5183         s32 ret_val;
5184
5185         DEBUGFUNC("e1000_setup_link_ich8lan");
5186
5187         if (hw->phy.ops.check_reset_block(hw))
5188                 return E1000_SUCCESS;
5189
5190         /* ICH parts do not have a word in the NVM to determine
5191          * the default flow control setting, so we explicitly
5192          * set it to full.
5193          */
5194         if (hw->fc.requested_mode == e1000_fc_default)
5195                 hw->fc.requested_mode = e1000_fc_full;
5196
5197         /* Save off the requested flow control mode for use later.  Depending
5198          * on the link partner's capabilities, we may or may not use this mode.
5199          */
5200         hw->fc.current_mode = hw->fc.requested_mode;
5201
5202         DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
5203                 hw->fc.current_mode);
5204
5205         /* Continue to configure the copper link. */
5206         ret_val = hw->mac.ops.setup_physical_interface(hw);
5207         if (ret_val)
5208                 return ret_val;
5209
5210         E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
5211         if ((hw->phy.type == e1000_phy_82578) ||
5212             (hw->phy.type == e1000_phy_82579) ||
5213             (hw->phy.type == e1000_phy_i217) ||
5214             (hw->phy.type == e1000_phy_82577)) {
5215                 E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time);
5216
5217                 ret_val = hw->phy.ops.write_reg(hw,
5218                                              PHY_REG(BM_PORT_CTRL_PAGE, 27),
5219                                              hw->fc.pause_time);
5220                 if (ret_val)
5221                         return ret_val;
5222         }
5223
5224         return e1000_set_fc_watermarks_generic(hw);
5225 }
5226
5227 /**
5228  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
5229  *  @hw: pointer to the HW structure
5230  *
5231  *  Configures the kumeran interface to the PHY to wait the appropriate time
5232  *  when polling the PHY, then call the generic setup_copper_link to finish
5233  *  configuring the copper link.
5234  **/
5235 STATIC s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
5236 {
5237         u32 ctrl;
5238         s32 ret_val;
5239         u16 reg_data;
5240
5241         DEBUGFUNC("e1000_setup_copper_link_ich8lan");
5242
5243         ctrl = E1000_READ_REG(hw, E1000_CTRL);
5244         ctrl |= E1000_CTRL_SLU;
5245         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5246         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5247
5248         /* Set the mac to wait the maximum time between each iteration
5249          * and increase the max iterations when polling the phy;
5250          * this fixes erroneous timeouts at 10Mbps.
5251          */
5252         ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS,
5253                                                0xFFFF);
5254         if (ret_val)
5255                 return ret_val;
5256         ret_val = e1000_read_kmrn_reg_generic(hw,
5257                                               E1000_KMRNCTRLSTA_INBAND_PARAM,
5258                                               &reg_data);
5259         if (ret_val)
5260                 return ret_val;
5261         reg_data |= 0x3F;
5262         ret_val = e1000_write_kmrn_reg_generic(hw,
5263                                                E1000_KMRNCTRLSTA_INBAND_PARAM,
5264                                                reg_data);
5265         if (ret_val)
5266                 return ret_val;
5267
5268         switch (hw->phy.type) {
5269         case e1000_phy_igp_3:
5270                 ret_val = e1000_copper_link_setup_igp(hw);
5271                 if (ret_val)
5272                         return ret_val;
5273                 break;
5274         case e1000_phy_bm:
5275         case e1000_phy_82578:
5276                 ret_val = e1000_copper_link_setup_m88(hw);
5277                 if (ret_val)
5278                         return ret_val;
5279                 break;
5280         case e1000_phy_82577:
5281         case e1000_phy_82579:
5282                 ret_val = e1000_copper_link_setup_82577(hw);
5283                 if (ret_val)
5284                         return ret_val;
5285                 break;
5286         case e1000_phy_ife:
5287                 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
5288                                                &reg_data);
5289                 if (ret_val)
5290                         return ret_val;
5291
5292                 reg_data &= ~IFE_PMC_AUTO_MDIX;
5293
5294                 switch (hw->phy.mdix) {
5295                 case 1:
5296                         reg_data &= ~IFE_PMC_FORCE_MDIX;
5297                         break;
5298                 case 2:
5299                         reg_data |= IFE_PMC_FORCE_MDIX;
5300                         break;
5301                 case 0:
5302                 default:
5303                         reg_data |= IFE_PMC_AUTO_MDIX;
5304                         break;
5305                 }
5306                 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
5307                                                 reg_data);
5308                 if (ret_val)
5309                         return ret_val;
5310                 break;
5311         default:
5312                 break;
5313         }
5314
5315         return e1000_setup_copper_link_generic(hw);
5316 }
5317
5318 /**
5319  *  e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
5320  *  @hw: pointer to the HW structure
5321  *
5322  *  Calls the PHY specific link setup function and then calls the
5323  *  generic setup_copper_link to finish configuring the link for
5324  *  Lynxpoint PCH devices
5325  **/
5326 STATIC s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
5327 {
5328         u32 ctrl;
5329         s32 ret_val;
5330
5331         DEBUGFUNC("e1000_setup_copper_link_pch_lpt");
5332
5333         ctrl = E1000_READ_REG(hw, E1000_CTRL);
5334         ctrl |= E1000_CTRL_SLU;
5335         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5336         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5337
5338         ret_val = e1000_copper_link_setup_82577(hw);
5339         if (ret_val)
5340                 return ret_val;
5341
5342         return e1000_setup_copper_link_generic(hw);
5343 }
5344
5345 /**
5346  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
5347  *  @hw: pointer to the HW structure
5348  *  @speed: pointer to store current link speed
5349  *  @duplex: pointer to store the current link duplex
5350  *
5351  *  Calls the generic get_speed_and_duplex to retrieve the current link
5352  *  information and then calls the Kumeran lock loss workaround for links at
5353  *  gigabit speeds.
5354  **/
5355 STATIC s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
5356                                           u16 *duplex)
5357 {
5358         s32 ret_val;
5359
5360         DEBUGFUNC("e1000_get_link_up_info_ich8lan");
5361
5362         ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
5363         if (ret_val)
5364                 return ret_val;
5365
5366         if ((hw->mac.type == e1000_ich8lan) &&
5367             (hw->phy.type == e1000_phy_igp_3) &&
5368             (*speed == SPEED_1000)) {
5369                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
5370         }
5371
5372         return ret_val;
5373 }
5374
5375 /**
5376  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
5377  *  @hw: pointer to the HW structure
5378  *
5379  *  Work-around for 82566 Kumeran PCS lock loss:
5380  *  On link status change (i.e. PCI reset, speed change) and link is up and
5381  *  speed is gigabit-
5382  *    0) if workaround is optionally disabled do nothing
5383  *    1) wait 1ms for Kumeran link to come up
5384  *    2) check Kumeran Diagnostic register PCS lock loss bit
5385  *    3) if not set the link is locked (all is good), otherwise...
5386  *    4) reset the PHY
5387  *    5) repeat up to 10 times
5388  *  Note: this is only called for IGP3 copper when speed is 1gb.
5389  **/
5390 STATIC s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
5391 {
5392         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5393         u32 phy_ctrl;
5394         s32 ret_val;
5395         u16 i, data;
5396         bool link;
5397
5398         DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan");
5399
5400         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
5401                 return E1000_SUCCESS;
5402
5403         /* Make sure link is up before proceeding.  If not just return.
5404          * Attempting this while link is negotiating fouled up link
5405          * stability
5406          */
5407         ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
5408         if (!link)
5409                 return E1000_SUCCESS;
5410
5411         for (i = 0; i < 10; i++) {
5412                 /* read once to clear */
5413                 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
5414                 if (ret_val)
5415                         return ret_val;
5416                 /* and again to get new status */
5417                 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
5418                 if (ret_val)
5419                         return ret_val;
5420
5421                 /* check for PCS lock */
5422                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
5423                         return E1000_SUCCESS;
5424
5425                 /* Issue PHY reset */
5426                 hw->phy.ops.reset(hw);
5427                 msec_delay_irq(5);
5428         }
5429         /* Disable GigE link negotiation */
5430         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
5431         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
5432                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5433         E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
5434
5435         /* Call gig speed drop workaround on Gig disable before accessing
5436          * any PHY registers
5437          */
5438         e1000_gig_downshift_workaround_ich8lan(hw);
5439
5440         /* unable to acquire PCS lock */
5441         return -E1000_ERR_PHY;
5442 }
5443
5444 /**
5445  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
5446  *  @hw: pointer to the HW structure
5447  *  @state: boolean value used to set the current Kumeran workaround state
5448  *
5449  *  If ICH8, set the current Kumeran workaround state (enabled - true
5450  *  /disabled - false).
5451  **/
5452 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
5453                                                  bool state)
5454 {
5455         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5456
5457         DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan");
5458
5459         if (hw->mac.type != e1000_ich8lan) {
5460                 DEBUGOUT("Workaround applies to ICH8 only.\n");
5461                 return;
5462         }
5463
5464         dev_spec->kmrn_lock_loss_workaround_enabled = state;
5465
5466         return;
5467 }
5468
5469 /**
5470  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
5471  *  @hw: pointer to the HW structure
5472  *
5473  *  Workaround for 82566 power-down on D3 entry:
5474  *    1) disable gigabit link
5475  *    2) write VR power-down enable
5476  *    3) read it back
5477  *  Continue if successful, else issue LCD reset and repeat
5478  **/
5479 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
5480 {
5481         u32 reg;
5482         u16 data;
5483         u8  retry = 0;
5484
5485         DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan");
5486
5487         if (hw->phy.type != e1000_phy_igp_3)
5488                 return;
5489
5490         /* Try the workaround twice (if needed) */
5491         do {
5492                 /* Disable link */
5493                 reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
5494                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
5495                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5496                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);
5497
5498                 /* Call gig speed drop workaround on Gig disable before
5499                  * accessing any PHY registers
5500                  */
5501                 if (hw->mac.type == e1000_ich8lan)
5502                         e1000_gig_downshift_workaround_ich8lan(hw);
5503
5504                 /* Write VR power-down enable */
5505                 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
5506                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5507                 hw->phy.ops.write_reg(hw, IGP3_VR_CTRL,
5508                                       data | IGP3_VR_CTRL_MODE_SHUTDOWN);
5509
5510                 /* Read it back and test */
5511                 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
5512                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5513                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
5514                         break;
5515
5516                 /* Issue PHY reset and repeat at most one more time */
5517                 reg = E1000_READ_REG(hw, E1000_CTRL);
5518                 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST);
5519                 retry++;
5520         } while (retry);
5521 }
5522
5523 /**
5524  *  e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working
5525  *  @hw: pointer to the HW structure
5526  *
5527  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
5528  *  LPLU, Gig disable, MDIC PHY reset):
5529  *    1) Set Kumeran Near-end loopback
5530  *    2) Clear Kumeran Near-end loopback
5531  *  Should only be called for ICH8[m] devices with any 1G Phy.
5532  **/
5533 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
5534 {
5535         s32 ret_val;
5536         u16 reg_data;
5537
5538         DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan");
5539
5540         if ((hw->mac.type != e1000_ich8lan) ||
5541             (hw->phy.type == e1000_phy_ife))
5542                 return;
5543
5544         ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5545                                               &reg_data);
5546         if (ret_val)
5547                 return;
5548         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
5549         ret_val = e1000_write_kmrn_reg_generic(hw,
5550                                                E1000_KMRNCTRLSTA_DIAG_OFFSET,
5551                                                reg_data);
5552         if (ret_val)
5553                 return;
5554         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
5555         e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5556                                      reg_data);
5557 }
5558
5559 /**
5560  *  e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
5561  *  @hw: pointer to the HW structure
5562  *
5563  *  During S0 to Sx transition, it is possible the link remains at gig
5564  *  instead of negotiating to a lower speed.  Before going to Sx, set
5565  *  'Gig Disable' to force link speed negotiation to a lower speed based on
5566  *  the LPLU setting in the NVM or custom setting.  For PCH and newer parts,
5567  *  the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
5568  *  needs to be written.
5569  *  Parts that support (and are linked to a partner which support) EEE in
5570  *  100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
5571  *  than 10Mbps w/o EEE.
5572  **/
5573 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
5574 {
5575         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5576         u32 phy_ctrl;
5577         s32 ret_val;
5578
5579         DEBUGFUNC("e1000_suspend_workarounds_ich8lan");
5580
5581         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
5582         phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
5583
5584         if (hw->phy.type == e1000_phy_i217) {
5585                 u16 phy_reg, device_id = hw->device_id;
5586
5587                 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
5588                     (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
5589                     (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
5590                     (device_id == E1000_DEV_ID_PCH_I218_V3) ||
5591                     (hw->mac.type >= e1000_pch_spt)) {
5592                         u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
5593
5594                         E1000_WRITE_REG(hw, E1000_FEXTNVM6,
5595                                         fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
5596                 }
5597
5598                 ret_val = hw->phy.ops.acquire(hw);
5599                 if (ret_val)
5600                         goto out;
5601
5602                 if (!dev_spec->eee_disable) {
5603                         u16 eee_advert;
5604
5605                         ret_val =
5606                             e1000_read_emi_reg_locked(hw,
5607                                                       I217_EEE_ADVERTISEMENT,
5608                                                       &eee_advert);
5609                         if (ret_val)
5610                                 goto release;
5611
5612                         /* Disable LPLU if both link partners support 100BaseT
5613                          * EEE and 100Full is advertised on both ends of the
5614                          * link, and enable Auto Enable LPI since there will
5615                          * be no driver to enable LPI while in Sx.
5616                          */
5617                         if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
5618                             (dev_spec->eee_lp_ability &
5619                              I82579_EEE_100_SUPPORTED) &&
5620                             (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
5621                                 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
5622                                               E1000_PHY_CTRL_NOND0A_LPLU);
5623
5624                                 /* Set Auto Enable LPI after link up */
5625                                 hw->phy.ops.read_reg_locked(hw,
5626                                                             I217_LPI_GPIO_CTRL,
5627                                                             &phy_reg);
5628                                 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5629                                 hw->phy.ops.write_reg_locked(hw,
5630                                                              I217_LPI_GPIO_CTRL,
5631                                                              phy_reg);
5632                         }
5633                 }
5634
5635                 /* For i217 Intel Rapid Start Technology support,
5636                  * when the system is going into Sx and no manageability engine
5637                  * is present, the driver must configure proxy to reset only on
5638                  * power good.  LPI (Low Power Idle) state must also reset only
5639                  * on power good, as well as the MTA (Multicast table array).
5640                  * The SMBus release must also be disabled on LCD reset.
5641                  */
5642                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
5643                       E1000_ICH_FWSM_FW_VALID)) {
5644                         /* Enable proxy to reset only on power good. */
5645                         hw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL,
5646                                                     &phy_reg);
5647                         phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
5648                         hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL,
5649                                                      phy_reg);
5650
5651                         /* Set bit enable LPI (EEE) to reset only on
5652                          * power good.
5653                         */
5654                         hw->phy.ops.read_reg_locked(hw, I217_SxCTRL, &phy_reg);
5655                         phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
5656                         hw->phy.ops.write_reg_locked(hw, I217_SxCTRL, phy_reg);
5657
5658                         /* Disable the SMB release on LCD reset. */
5659                         hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, &phy_reg);
5660                         phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
5661                         hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
5662                 }
5663
5664                 /* Enable MTA to reset for Intel Rapid Start Technology
5665                  * Support
5666                  */
5667                 hw->phy.ops.read_reg_locked(hw, I217_CGFREG, &phy_reg);
5668                 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
5669                 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
5670
5671 release:
5672                 hw->phy.ops.release(hw);
5673         }
5674 out:
5675         E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
5676
5677         if (hw->mac.type == e1000_ich8lan)
5678                 e1000_gig_downshift_workaround_ich8lan(hw);
5679
5680         if (hw->mac.type >= e1000_pchlan) {
5681                 e1000_oem_bits_config_ich8lan(hw, false);
5682
5683                 /* Reset PHY to activate OEM bits on 82577/8 */
5684                 if (hw->mac.type == e1000_pchlan)
5685                         e1000_phy_hw_reset_generic(hw);
5686
5687                 ret_val = hw->phy.ops.acquire(hw);
5688                 if (ret_val)
5689                         return;
5690                 e1000_write_smbus_addr(hw);
5691                 hw->phy.ops.release(hw);
5692         }
5693
5694         return;
5695 }
5696
5697 /**
5698  *  e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
5699  *  @hw: pointer to the HW structure
5700  *
5701  *  During Sx to S0 transitions on non-managed devices or managed devices
5702  *  on which PHY resets are not blocked, if the PHY registers cannot be
5703  *  accessed properly by the s/w toggle the LANPHYPC value to power cycle
5704  *  the PHY.
5705  *  On i217, setup Intel Rapid Start Technology.
5706  **/
5707 u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
5708 {
5709         s32 ret_val;
5710
5711         DEBUGFUNC("e1000_resume_workarounds_pchlan");
5712         if (hw->mac.type < e1000_pch2lan)
5713                 return E1000_SUCCESS;
5714
5715         ret_val = e1000_init_phy_workarounds_pchlan(hw);
5716         if (ret_val) {
5717                 DEBUGOUT1("Failed to init PHY flow ret_val=%d\n", ret_val);
5718                 return ret_val;
5719         }
5720
5721         /* For i217 Intel Rapid Start Technology support when the system
5722          * is transitioning from Sx and no manageability engine is present
5723          * configure SMBus to restore on reset, disable proxy, and enable
5724          * the reset on MTA (Multicast table array).
5725          */
5726         if (hw->phy.type == e1000_phy_i217) {
5727                 u16 phy_reg;
5728
5729                 ret_val = hw->phy.ops.acquire(hw);
5730                 if (ret_val) {
5731                         DEBUGOUT("Failed to setup iRST\n");
5732                         return ret_val;
5733                 }
5734
5735                 /* Clear Auto Enable LPI after link up */
5736                 hw->phy.ops.read_reg_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5737                 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5738                 hw->phy.ops.write_reg_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5739
5740                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
5741                     E1000_ICH_FWSM_FW_VALID)) {
5742                         /* Restore clear on SMB if no manageability engine
5743                          * is present
5744                          */
5745                         ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR,
5746                                                               &phy_reg);
5747                         if (ret_val)
5748                                 goto release;
5749                         phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
5750                         hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
5751
5752                         /* Disable Proxy */
5753                         hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 0);
5754                 }
5755                 /* Enable reset on MTA */
5756                 ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG,
5757                                                       &phy_reg);
5758                 if (ret_val)
5759                         goto release;
5760                 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
5761                 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
5762 release:
5763                 if (ret_val)
5764                         DEBUGOUT1("Error %d in resume workarounds\n", ret_val);
5765                 hw->phy.ops.release(hw);
5766                 return ret_val;
5767         }
5768         return E1000_SUCCESS;
5769 }
5770
5771 /**
5772  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
5773  *  @hw: pointer to the HW structure
5774  *
5775  *  Return the LED back to the default configuration.
5776  **/
5777 STATIC s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
5778 {
5779         DEBUGFUNC("e1000_cleanup_led_ich8lan");
5780
5781         if (hw->phy.type == e1000_phy_ife)
5782                 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5783                                              0);
5784
5785         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
5786         return E1000_SUCCESS;
5787 }
5788
5789 /**
5790  *  e1000_led_on_ich8lan - Turn LEDs on
5791  *  @hw: pointer to the HW structure
5792  *
5793  *  Turn on the LEDs.
5794  **/
5795 STATIC s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5796 {
5797         DEBUGFUNC("e1000_led_on_ich8lan");
5798
5799         if (hw->phy.type == e1000_phy_ife)
5800                 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5801                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
5802
5803         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
5804         return E1000_SUCCESS;
5805 }
5806
5807 /**
5808  *  e1000_led_off_ich8lan - Turn LEDs off
5809  *  @hw: pointer to the HW structure
5810  *
5811  *  Turn off the LEDs.
5812  **/
5813 STATIC s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5814 {
5815         DEBUGFUNC("e1000_led_off_ich8lan");
5816
5817         if (hw->phy.type == e1000_phy_ife)
5818                 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5819                                (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
5820
5821         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
5822         return E1000_SUCCESS;
5823 }
5824
5825 /**
5826  *  e1000_setup_led_pchlan - Configures SW controllable LED
5827  *  @hw: pointer to the HW structure
5828  *
5829  *  This prepares the SW controllable LED for use.
5830  **/
5831 STATIC s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5832 {
5833         DEBUGFUNC("e1000_setup_led_pchlan");
5834
5835         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5836                                      (u16)hw->mac.ledctl_mode1);
5837 }
5838
5839 /**
5840  *  e1000_cleanup_led_pchlan - Restore the default LED operation
5841  *  @hw: pointer to the HW structure
5842  *
5843  *  Return the LED back to the default configuration.
5844  **/
5845 STATIC s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5846 {
5847         DEBUGFUNC("e1000_cleanup_led_pchlan");
5848
5849         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5850                                      (u16)hw->mac.ledctl_default);
5851 }
5852
5853 /**
5854  *  e1000_led_on_pchlan - Turn LEDs on
5855  *  @hw: pointer to the HW structure
5856  *
5857  *  Turn on the LEDs.
5858  **/
5859 STATIC s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5860 {
5861         u16 data = (u16)hw->mac.ledctl_mode2;
5862         u32 i, led;
5863
5864         DEBUGFUNC("e1000_led_on_pchlan");
5865
5866         /* If no link, then turn LED on by setting the invert bit
5867          * for each LED that's mode is "link_up" in ledctl_mode2.
5868          */
5869         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5870                 for (i = 0; i < 3; i++) {
5871                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5872                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
5873                             E1000_LEDCTL_MODE_LINK_UP)
5874                                 continue;
5875                         if (led & E1000_PHY_LED0_IVRT)
5876                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5877                         else
5878                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5879                 }
5880         }
5881
5882         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5883 }
5884
5885 /**
5886  *  e1000_led_off_pchlan - Turn LEDs off
5887  *  @hw: pointer to the HW structure
5888  *
5889  *  Turn off the LEDs.
5890  **/
5891 STATIC s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5892 {
5893         u16 data = (u16)hw->mac.ledctl_mode1;
5894         u32 i, led;
5895
5896         DEBUGFUNC("e1000_led_off_pchlan");
5897
5898         /* If no link, then turn LED off by clearing the invert bit
5899          * for each LED that's mode is "link_up" in ledctl_mode1.
5900          */
5901         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5902                 for (i = 0; i < 3; i++) {
5903                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5904                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
5905                             E1000_LEDCTL_MODE_LINK_UP)
5906                                 continue;
5907                         if (led & E1000_PHY_LED0_IVRT)
5908                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5909                         else
5910                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5911                 }
5912         }
5913
5914         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5915 }
5916
5917 /**
5918  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5919  *  @hw: pointer to the HW structure
5920  *
5921  *  Read appropriate register for the config done bit for completion status
5922  *  and configure the PHY through s/w for EEPROM-less parts.
5923  *
5924  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
5925  *  config done bit, so only an error is logged and continues.  If we were
5926  *  to return with error, EEPROM-less silicon would not be able to be reset
5927  *  or change link.
5928  **/
5929 STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
5930 {
5931         s32 ret_val = E1000_SUCCESS;
5932         u32 bank = 0;
5933         u32 status;
5934
5935         DEBUGFUNC("e1000_get_cfg_done_ich8lan");
5936
5937         e1000_get_cfg_done_generic(hw);
5938
5939         /* Wait for indication from h/w that it has completed basic config */
5940         if (hw->mac.type >= e1000_ich10lan) {
5941                 e1000_lan_init_done_ich8lan(hw);
5942         } else {
5943                 ret_val = e1000_get_auto_rd_done_generic(hw);
5944                 if (ret_val) {
5945                         /* When auto config read does not complete, do not
5946                          * return with an error. This can happen in situations
5947                          * where there is no eeprom and prevents getting link.
5948                          */
5949                         DEBUGOUT("Auto Read Done did not complete\n");
5950                         ret_val = E1000_SUCCESS;
5951                 }
5952         }
5953
5954         /* Clear PHY Reset Asserted bit */
5955         status = E1000_READ_REG(hw, E1000_STATUS);
5956         if (status & E1000_STATUS_PHYRA)
5957                 E1000_WRITE_REG(hw, E1000_STATUS, status & ~E1000_STATUS_PHYRA);
5958         else
5959                 DEBUGOUT("PHY Reset Asserted not set - needs delay\n");
5960
5961         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
5962         if (hw->mac.type <= e1000_ich9lan) {
5963                 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
5964                     (hw->phy.type == e1000_phy_igp_3)) {
5965                         e1000_phy_init_script_igp3(hw);
5966                 }
5967         } else {
5968                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
5969                         /* Maybe we should do a basic PHY config */
5970                         DEBUGOUT("EEPROM not present\n");
5971                         ret_val = -E1000_ERR_CONFIG;
5972                 }
5973         }
5974
5975         return ret_val;
5976 }
5977
5978 /**
5979  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
5980  * @hw: pointer to the HW structure
5981  *
5982  * In the case of a PHY power down to save power, or to turn off link during a
5983  * driver unload, or wake on lan is not enabled, remove the link.
5984  **/
5985 STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
5986 {
5987         /* If the management interface is not enabled, then power down */
5988         if (!(hw->mac.ops.check_mng_mode(hw) ||
5989               hw->phy.ops.check_reset_block(hw)))
5990                 e1000_power_down_phy_copper(hw);
5991
5992         return;
5993 }
5994
5995 /**
5996  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
5997  *  @hw: pointer to the HW structure
5998  *
5999  *  Clears hardware counters specific to the silicon family and calls
6000  *  clear_hw_cntrs_generic to clear all general purpose counters.
6001  **/
6002 STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
6003 {
6004         u16 phy_data;
6005         s32 ret_val;
6006
6007         DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan");
6008
6009         e1000_clear_hw_cntrs_base_generic(hw);
6010
6011         E1000_READ_REG(hw, E1000_ALGNERRC);
6012         E1000_READ_REG(hw, E1000_RXERRC);
6013         E1000_READ_REG(hw, E1000_TNCRS);
6014         E1000_READ_REG(hw, E1000_CEXTERR);
6015         E1000_READ_REG(hw, E1000_TSCTC);
6016         E1000_READ_REG(hw, E1000_TSCTFC);
6017
6018         E1000_READ_REG(hw, E1000_MGTPRC);
6019         E1000_READ_REG(hw, E1000_MGTPDC);
6020         E1000_READ_REG(hw, E1000_MGTPTC);
6021
6022         E1000_READ_REG(hw, E1000_IAC);
6023         E1000_READ_REG(hw, E1000_ICRXOC);
6024
6025         /* Clear PHY statistics registers */
6026         if ((hw->phy.type == e1000_phy_82578) ||
6027             (hw->phy.type == e1000_phy_82579) ||
6028             (hw->phy.type == e1000_phy_i217) ||
6029             (hw->phy.type == e1000_phy_82577)) {
6030                 ret_val = hw->phy.ops.acquire(hw);
6031                 if (ret_val)
6032                         return;
6033                 ret_val = hw->phy.ops.set_page(hw,
6034                                                HV_STATS_PAGE << IGP_PAGE_SHIFT);
6035                 if (ret_val)
6036                         goto release;
6037                 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
6038                 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
6039                 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
6040                 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
6041                 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
6042                 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
6043                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
6044                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
6045                 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
6046                 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
6047                 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
6048                 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
6049                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
6050                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
6051 release:
6052                 hw->phy.ops.release(hw);
6053         }
6054 }
6055
6056 /**
6057  *  e1000_configure_k0s_lpt - Configure K0s power state
6058  *  @hw: pointer to the HW structure
6059  *  @entry_latency: Tx idle period for entering K0s - valid values are 0 to 3.
6060  *      0 corresponds to 128ns, each value over 0 doubles the duration.
6061  *  @min_time: Minimum Tx idle period allowed  - valid values are 0 to 4.
6062  *      0 corresponds to 128ns, each value over 0 doubles the duration.
6063  *
6064  *  Configure the K1 power state based on the provided parameter.
6065  *  Assumes semaphore already acquired.
6066  *
6067  *  Success returns 0, Failure returns:
6068  *      -E1000_ERR_PHY (-2) in case of access error
6069  *      -E1000_ERR_PARAM (-4) in case of parameters error
6070  **/
6071 s32 e1000_configure_k0s_lpt(struct e1000_hw *hw, u8 entry_latency, u8 min_time)
6072 {
6073         s32 ret_val;
6074         u16 kmrn_reg = 0;
6075
6076         DEBUGFUNC("e1000_configure_k0s_lpt");
6077
6078         if (entry_latency > 3 || min_time > 4)
6079                 return -E1000_ERR_PARAM;
6080
6081         ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL,
6082                                              &kmrn_reg);
6083         if (ret_val)
6084                 return ret_val;
6085
6086         /* for now don't touch the latency */
6087         kmrn_reg &= ~(E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_MASK);
6088         kmrn_reg |= ((min_time << E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_SHIFT));
6089
6090         ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL,
6091                                               kmrn_reg);
6092         if (ret_val)
6093                 return ret_val;
6094
6095         return E1000_SUCCESS;
6096 }