1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
11 #include <rte_common.h>
12 #include <rte_interrupts.h>
13 #include <rte_byteorder.h>
14 #include <rte_debug.h>
16 #include <rte_bus_pci.h>
17 #include <rte_ether.h>
18 #include <rte_ethdev_driver.h>
19 #include <rte_ethdev_pci.h>
20 #include <rte_memory.h>
22 #include <rte_malloc.h>
25 #include "e1000_logs.h"
26 #include "base/e1000_api.h"
27 #include "e1000_ethdev.h"
29 #define EM_EIAC 0x000DC
31 #define PMD_ROUNDUP(x,y) (((x) + (y) - 1)/(y) * (y))
34 static int eth_em_configure(struct rte_eth_dev *dev);
35 static int eth_em_start(struct rte_eth_dev *dev);
36 static void eth_em_stop(struct rte_eth_dev *dev);
37 static int eth_em_close(struct rte_eth_dev *dev);
38 static int eth_em_promiscuous_enable(struct rte_eth_dev *dev);
39 static int eth_em_promiscuous_disable(struct rte_eth_dev *dev);
40 static int eth_em_allmulticast_enable(struct rte_eth_dev *dev);
41 static int eth_em_allmulticast_disable(struct rte_eth_dev *dev);
42 static int eth_em_link_update(struct rte_eth_dev *dev,
43 int wait_to_complete);
44 static int eth_em_stats_get(struct rte_eth_dev *dev,
45 struct rte_eth_stats *rte_stats);
46 static int eth_em_stats_reset(struct rte_eth_dev *dev);
47 static int eth_em_infos_get(struct rte_eth_dev *dev,
48 struct rte_eth_dev_info *dev_info);
49 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
50 struct rte_eth_fc_conf *fc_conf);
51 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
52 struct rte_eth_fc_conf *fc_conf);
53 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
54 static int eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev);
55 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
56 static int eth_em_interrupt_action(struct rte_eth_dev *dev,
57 struct rte_intr_handle *handle);
58 static void eth_em_interrupt_handler(void *param);
60 static int em_hw_init(struct e1000_hw *hw);
61 static int em_hardware_init(struct e1000_hw *hw);
62 static void em_hw_control_acquire(struct e1000_hw *hw);
63 static void em_hw_control_release(struct e1000_hw *hw);
64 static void em_init_manageability(struct e1000_hw *hw);
65 static void em_release_manageability(struct e1000_hw *hw);
67 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
69 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
70 uint16_t vlan_id, int on);
71 static int eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
72 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
73 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
74 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
75 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
78 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
79 uint16_t vlan_id, int on);
82 static int eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
83 static int eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
84 static void em_lsc_intr_disable(struct e1000_hw *hw);
85 static void em_rxq_intr_enable(struct e1000_hw *hw);
86 static void em_rxq_intr_disable(struct e1000_hw *hw);
88 static int eth_em_led_on(struct rte_eth_dev *dev);
89 static int eth_em_led_off(struct rte_eth_dev *dev);
91 static int em_get_rx_buffer_size(struct e1000_hw *hw);
92 static int eth_em_rar_set(struct rte_eth_dev *dev,
93 struct rte_ether_addr *mac_addr,
94 uint32_t index, uint32_t pool);
95 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
96 static int eth_em_default_mac_addr_set(struct rte_eth_dev *dev,
97 struct rte_ether_addr *addr);
99 static int eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
100 struct rte_ether_addr *mc_addr_set,
101 uint32_t nb_mc_addr);
103 #define EM_FC_PAUSE_TIME 0x0680
104 #define EM_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
105 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
107 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
110 * The set of PCI devices this driver supports
112 static const struct rte_pci_id pci_id_em_map[] = {
113 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82540EM) },
114 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_COPPER) },
115 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_FIBER) },
116 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_COPPER) },
117 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_FIBER) },
118 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_QUAD_COPPER) },
119 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_COPPER) },
120 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_FIBER) },
121 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES) },
122 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_DUAL) },
123 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_QUAD) },
124 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER) },
125 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571PT_QUAD_COPPER) },
126 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_FIBER) },
127 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER_LP) },
128 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_COPPER) },
129 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_FIBER) },
130 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_SERDES) },
131 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI) },
132 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82573L) },
133 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574L) },
134 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574LA) },
135 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82583V) },
136 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH2_LV_LM) },
137 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_LM) },
138 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_V) },
139 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_LM) },
140 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_V) },
141 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM2) },
142 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V2) },
143 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM3) },
144 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V3) },
145 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM) },
146 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V) },
147 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM2) },
148 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V2) },
149 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LBG_I219_LM3) },
150 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM4) },
151 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V4) },
152 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM5) },
153 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V5) },
154 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM6) },
155 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V6) },
156 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM7) },
157 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V7) },
158 { .vendor_id = 0, /* sentinel */ },
161 static const struct eth_dev_ops eth_em_ops = {
162 .dev_configure = eth_em_configure,
163 .dev_start = eth_em_start,
164 .dev_stop = eth_em_stop,
165 .dev_close = eth_em_close,
166 .promiscuous_enable = eth_em_promiscuous_enable,
167 .promiscuous_disable = eth_em_promiscuous_disable,
168 .allmulticast_enable = eth_em_allmulticast_enable,
169 .allmulticast_disable = eth_em_allmulticast_disable,
170 .link_update = eth_em_link_update,
171 .stats_get = eth_em_stats_get,
172 .stats_reset = eth_em_stats_reset,
173 .dev_infos_get = eth_em_infos_get,
174 .mtu_set = eth_em_mtu_set,
175 .vlan_filter_set = eth_em_vlan_filter_set,
176 .vlan_offload_set = eth_em_vlan_offload_set,
177 .rx_queue_setup = eth_em_rx_queue_setup,
178 .rx_queue_release = eth_em_rx_queue_release,
179 .tx_queue_setup = eth_em_tx_queue_setup,
180 .tx_queue_release = eth_em_tx_queue_release,
181 .rx_queue_intr_enable = eth_em_rx_queue_intr_enable,
182 .rx_queue_intr_disable = eth_em_rx_queue_intr_disable,
183 .dev_led_on = eth_em_led_on,
184 .dev_led_off = eth_em_led_off,
185 .flow_ctrl_get = eth_em_flow_ctrl_get,
186 .flow_ctrl_set = eth_em_flow_ctrl_set,
187 .mac_addr_set = eth_em_default_mac_addr_set,
188 .mac_addr_add = eth_em_rar_set,
189 .mac_addr_remove = eth_em_rar_clear,
190 .set_mc_addr_list = eth_em_set_mc_addr_list,
191 .rxq_info_get = em_rxq_info_get,
192 .txq_info_get = em_txq_info_get,
197 * eth_em_dev_is_ich8 - Check for ICH8 device
198 * @hw: pointer to the HW structure
200 * return TRUE for ICH8, otherwise FALSE
203 eth_em_dev_is_ich8(struct e1000_hw *hw)
205 DEBUGFUNC("eth_em_dev_is_ich8");
207 switch (hw->device_id) {
208 case E1000_DEV_ID_PCH2_LV_LM:
209 case E1000_DEV_ID_PCH_LPT_I217_LM:
210 case E1000_DEV_ID_PCH_LPT_I217_V:
211 case E1000_DEV_ID_PCH_LPTLP_I218_LM:
212 case E1000_DEV_ID_PCH_LPTLP_I218_V:
213 case E1000_DEV_ID_PCH_I218_V2:
214 case E1000_DEV_ID_PCH_I218_LM2:
215 case E1000_DEV_ID_PCH_I218_V3:
216 case E1000_DEV_ID_PCH_I218_LM3:
217 case E1000_DEV_ID_PCH_SPT_I219_LM:
218 case E1000_DEV_ID_PCH_SPT_I219_V:
219 case E1000_DEV_ID_PCH_SPT_I219_LM2:
220 case E1000_DEV_ID_PCH_SPT_I219_V2:
221 case E1000_DEV_ID_PCH_LBG_I219_LM3:
222 case E1000_DEV_ID_PCH_SPT_I219_LM4:
223 case E1000_DEV_ID_PCH_SPT_I219_V4:
224 case E1000_DEV_ID_PCH_SPT_I219_LM5:
225 case E1000_DEV_ID_PCH_SPT_I219_V5:
226 case E1000_DEV_ID_PCH_CNP_I219_LM6:
227 case E1000_DEV_ID_PCH_CNP_I219_V6:
228 case E1000_DEV_ID_PCH_CNP_I219_LM7:
229 case E1000_DEV_ID_PCH_CNP_I219_V7:
237 eth_em_dev_init(struct rte_eth_dev *eth_dev)
239 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
240 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
241 struct e1000_adapter *adapter =
242 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
243 struct e1000_hw *hw =
244 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
245 struct e1000_vfta * shadow_vfta =
246 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
248 eth_dev->dev_ops = ð_em_ops;
249 eth_dev->rx_queue_count = eth_em_rx_queue_count;
250 eth_dev->rx_descriptor_done = eth_em_rx_descriptor_done;
251 eth_dev->rx_descriptor_status = eth_em_rx_descriptor_status;
252 eth_dev->tx_descriptor_status = eth_em_tx_descriptor_status;
253 eth_dev->rx_pkt_burst = (eth_rx_burst_t)ð_em_recv_pkts;
254 eth_dev->tx_pkt_burst = (eth_tx_burst_t)ð_em_xmit_pkts;
255 eth_dev->tx_pkt_prepare = (eth_tx_prep_t)ð_em_prep_pkts;
257 /* for secondary processes, we don't initialise any further as primary
258 * has already done this work. Only check we don't need a different
260 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
261 if (eth_dev->data->scattered_rx)
262 eth_dev->rx_pkt_burst =
263 (eth_rx_burst_t)ð_em_recv_scattered_pkts;
267 rte_eth_copy_pci_info(eth_dev, pci_dev);
269 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
270 hw->device_id = pci_dev->id.device_id;
271 adapter->stopped = 0;
273 /* For ICH8 support we'll need to map the flash memory BAR */
274 if (eth_em_dev_is_ich8(hw))
275 hw->flash_address = (void *)pci_dev->mem_resource[1].addr;
277 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
278 em_hw_init(hw) != 0) {
279 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
281 eth_dev->data->port_id, pci_dev->id.vendor_id,
282 pci_dev->id.device_id);
286 /* Allocate memory for storing MAC addresses */
287 eth_dev->data->mac_addrs = rte_zmalloc("e1000", RTE_ETHER_ADDR_LEN *
288 hw->mac.rar_entry_count, 0);
289 if (eth_dev->data->mac_addrs == NULL) {
290 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
291 "store MAC addresses",
292 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
296 /* Copy the permanent MAC address */
297 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
298 eth_dev->data->mac_addrs);
300 /* initialize the vfta */
301 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
303 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
304 eth_dev->data->port_id, pci_dev->id.vendor_id,
305 pci_dev->id.device_id);
307 rte_intr_callback_register(intr_handle,
308 eth_em_interrupt_handler, eth_dev);
314 eth_em_dev_uninit(struct rte_eth_dev *eth_dev)
316 PMD_INIT_FUNC_TRACE();
318 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
321 eth_em_close(eth_dev);
326 static int eth_em_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
327 struct rte_pci_device *pci_dev)
329 return rte_eth_dev_pci_generic_probe(pci_dev,
330 sizeof(struct e1000_adapter), eth_em_dev_init);
333 static int eth_em_pci_remove(struct rte_pci_device *pci_dev)
335 return rte_eth_dev_pci_generic_remove(pci_dev, eth_em_dev_uninit);
338 static struct rte_pci_driver rte_em_pmd = {
339 .id_table = pci_id_em_map,
340 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
341 .probe = eth_em_pci_probe,
342 .remove = eth_em_pci_remove,
346 em_hw_init(struct e1000_hw *hw)
350 diag = hw->mac.ops.init_params(hw);
352 PMD_INIT_LOG(ERR, "MAC Initialization Error");
355 diag = hw->nvm.ops.init_params(hw);
357 PMD_INIT_LOG(ERR, "NVM Initialization Error");
360 diag = hw->phy.ops.init_params(hw);
362 PMD_INIT_LOG(ERR, "PHY Initialization Error");
365 (void) e1000_get_bus_info(hw);
368 hw->phy.autoneg_wait_to_complete = 0;
369 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
371 e1000_init_script_state_82541(hw, TRUE);
372 e1000_set_tbi_compatibility_82543(hw, TRUE);
375 if (hw->phy.media_type == e1000_media_type_copper) {
376 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
377 hw->phy.disable_polarity_correction = 0;
378 hw->phy.ms_type = e1000_ms_hw_default;
382 * Start from a known state, this is important in reading the nvm
387 /* Make sure we have a good EEPROM before we read from it */
388 if (e1000_validate_nvm_checksum(hw) < 0) {
390 * Some PCI-E parts fail the first check due to
391 * the link being in sleep state, call it again,
392 * if it fails a second time its a real issue.
394 diag = e1000_validate_nvm_checksum(hw);
396 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
401 /* Read the permanent MAC address out of the EEPROM */
402 diag = e1000_read_mac_addr(hw);
404 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
408 /* Now initialize the hardware */
409 diag = em_hardware_init(hw);
411 PMD_INIT_LOG(ERR, "Hardware initialization failed");
415 hw->mac.get_link_status = 1;
417 /* Indicate SOL/IDER usage */
418 diag = e1000_check_reset_block(hw);
420 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
426 em_hw_control_release(hw);
431 eth_em_configure(struct rte_eth_dev *dev)
433 struct e1000_interrupt *intr =
434 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
436 PMD_INIT_FUNC_TRACE();
437 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
439 PMD_INIT_FUNC_TRACE();
445 em_set_pba(struct e1000_hw *hw)
450 * Packet Buffer Allocation (PBA)
451 * Writing PBA sets the receive portion of the buffer
452 * the remainder is used for the transmit buffer.
453 * Devices before the 82547 had a Packet Buffer of 64K.
454 * After the 82547 the buffer was reduced to 40K.
456 switch (hw->mac.type) {
458 case e1000_82547_rev_2:
459 /* 82547: Total Packet Buffer is 40K */
460 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
464 case e1000_80003es2lan:
465 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
467 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
468 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
472 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
489 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
492 E1000_WRITE_REG(hw, E1000_PBA, pba);
496 eth_em_rxtx_control(struct rte_eth_dev *dev,
499 struct e1000_hw *hw =
500 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
503 tctl = E1000_READ_REG(hw, E1000_TCTL);
504 rctl = E1000_READ_REG(hw, E1000_RCTL);
507 tctl |= E1000_TCTL_EN;
508 rctl |= E1000_RCTL_EN;
511 tctl &= ~E1000_TCTL_EN;
512 rctl &= ~E1000_RCTL_EN;
514 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
515 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
516 E1000_WRITE_FLUSH(hw);
520 eth_em_start(struct rte_eth_dev *dev)
522 struct e1000_adapter *adapter =
523 E1000_DEV_PRIVATE(dev->data->dev_private);
524 struct e1000_hw *hw =
525 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
526 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
527 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
529 uint32_t intr_vector = 0;
534 PMD_INIT_FUNC_TRACE();
538 e1000_power_up_phy(hw);
540 /* Set default PBA value */
543 /* Put the address into the Receive Address Array */
544 e1000_rar_set(hw, hw->mac.addr, 0);
547 * With the 82571 adapter, RAR[0] may be overwritten
548 * when the other port is reset, we make a duplicate
549 * in RAR[14] for that eventuality, this assures
550 * the interface continues to function.
552 if (hw->mac.type == e1000_82571) {
553 e1000_set_laa_state_82571(hw, TRUE);
554 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
557 /* Initialize the hardware */
558 if (em_hardware_init(hw)) {
559 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
563 E1000_WRITE_REG(hw, E1000_VET, RTE_ETHER_TYPE_VLAN);
565 /* Configure for OS presence */
566 em_init_manageability(hw);
568 if (dev->data->dev_conf.intr_conf.rxq != 0) {
569 intr_vector = dev->data->nb_rx_queues;
570 if (rte_intr_efd_enable(intr_handle, intr_vector))
574 if (rte_intr_dp_is_en(intr_handle)) {
575 intr_handle->intr_vec =
576 rte_zmalloc("intr_vec",
577 dev->data->nb_rx_queues * sizeof(int), 0);
578 if (intr_handle->intr_vec == NULL) {
579 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
580 " intr_vec", dev->data->nb_rx_queues);
584 /* enable rx interrupt */
585 em_rxq_intr_enable(hw);
590 ret = eth_em_rx_init(dev);
592 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
593 em_dev_clear_queues(dev);
597 e1000_clear_hw_cntrs_base_generic(hw);
599 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
600 ETH_VLAN_EXTEND_MASK;
601 ret = eth_em_vlan_offload_set(dev, mask);
603 PMD_INIT_LOG(ERR, "Unable to update vlan offload");
604 em_dev_clear_queues(dev);
608 /* Set Interrupt Throttling Rate to maximum allowed value. */
609 E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
611 /* Setup link speed and duplex */
612 speeds = &dev->data->dev_conf.link_speeds;
613 if (*speeds == ETH_LINK_SPEED_AUTONEG) {
614 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
618 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
621 hw->phy.autoneg_advertised = 0;
623 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
624 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
625 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
627 goto error_invalid_config;
629 if (*speeds & ETH_LINK_SPEED_10M_HD) {
630 hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
633 if (*speeds & ETH_LINK_SPEED_10M) {
634 hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
637 if (*speeds & ETH_LINK_SPEED_100M_HD) {
638 hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
641 if (*speeds & ETH_LINK_SPEED_100M) {
642 hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
645 if (*speeds & ETH_LINK_SPEED_1G) {
646 hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
649 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
650 goto error_invalid_config;
652 /* Set/reset the mac.autoneg based on the link speed,
657 hw->mac.forced_speed_duplex =
658 hw->phy.autoneg_advertised;
664 e1000_setup_link(hw);
666 if (rte_intr_allow_others(intr_handle)) {
667 /* check if lsc interrupt is enabled */
668 if (dev->data->dev_conf.intr_conf.lsc != 0) {
669 ret = eth_em_interrupt_setup(dev);
671 PMD_INIT_LOG(ERR, "Unable to setup interrupts");
672 em_dev_clear_queues(dev);
677 rte_intr_callback_unregister(intr_handle,
678 eth_em_interrupt_handler,
680 if (dev->data->dev_conf.intr_conf.lsc != 0)
681 PMD_INIT_LOG(INFO, "lsc won't enable because of"
682 " no intr multiplexn");
684 /* check if rxq interrupt is enabled */
685 if (dev->data->dev_conf.intr_conf.rxq != 0)
686 eth_em_rxq_interrupt_setup(dev);
688 rte_intr_enable(intr_handle);
690 adapter->stopped = 0;
692 eth_em_rxtx_control(dev, true);
693 eth_em_link_update(dev, 0);
695 PMD_INIT_LOG(DEBUG, "<<");
699 error_invalid_config:
700 PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
701 dev->data->dev_conf.link_speeds, dev->data->port_id);
702 em_dev_clear_queues(dev);
706 /*********************************************************************
708 * This routine disables all traffic on the adapter by issuing a
709 * global reset on the MAC.
711 **********************************************************************/
713 eth_em_stop(struct rte_eth_dev *dev)
715 struct rte_eth_link link;
716 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
717 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
718 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
720 dev->data->dev_started = 0;
722 eth_em_rxtx_control(dev, false);
723 em_rxq_intr_disable(hw);
724 em_lsc_intr_disable(hw);
728 /* Flush desc rings for i219 */
729 if (hw->mac.type == e1000_pch_spt || hw->mac.type == e1000_pch_cnp)
730 em_flush_desc_rings(dev);
732 if (hw->mac.type >= e1000_82544)
733 E1000_WRITE_REG(hw, E1000_WUC, 0);
735 /* Power down the phy. Needed to make the link go down */
736 e1000_power_down_phy(hw);
738 em_dev_clear_queues(dev);
740 /* clear the recorded link status */
741 memset(&link, 0, sizeof(link));
742 rte_eth_linkstatus_set(dev, &link);
744 if (!rte_intr_allow_others(intr_handle))
745 /* resume to the default handler */
746 rte_intr_callback_register(intr_handle,
747 eth_em_interrupt_handler,
750 /* Clean datapath event and queue/vec mapping */
751 rte_intr_efd_disable(intr_handle);
752 if (intr_handle->intr_vec != NULL) {
753 rte_free(intr_handle->intr_vec);
754 intr_handle->intr_vec = NULL;
759 eth_em_close(struct rte_eth_dev *dev)
761 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
762 struct e1000_adapter *adapter =
763 E1000_DEV_PRIVATE(dev->data->dev_private);
764 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
765 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
767 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
771 adapter->stopped = 1;
772 em_dev_free_queues(dev);
773 e1000_phy_hw_reset(hw);
774 em_release_manageability(hw);
775 em_hw_control_release(hw);
777 /* disable uio intr before callback unregister */
778 rte_intr_disable(intr_handle);
779 rte_intr_callback_unregister(intr_handle,
780 eth_em_interrupt_handler, dev);
786 em_get_rx_buffer_size(struct e1000_hw *hw)
788 uint32_t rx_buf_size;
790 rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
794 /*********************************************************************
796 * Initialize the hardware
798 **********************************************************************/
800 em_hardware_init(struct e1000_hw *hw)
802 uint32_t rx_buf_size;
805 /* Issue a global reset */
808 /* Let the firmware know the OS is in control */
809 em_hw_control_acquire(hw);
812 * These parameters control the automatic generation (Tx) and
813 * response (Rx) to Ethernet PAUSE frames.
814 * - High water mark should allow for at least two standard size (1518)
815 * frames to be received after sending an XOFF.
816 * - Low water mark works best when it is very near the high water mark.
817 * This allows the receiver to restart by sending XON when it has
818 * drained a bit. Here we use an arbitrary value of 1500 which will
819 * restart after one full frame is pulled from the buffer. There
820 * could be several smaller frames in the buffer and if so they will
821 * not trigger the XON until their total number reduces the buffer
823 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
825 rx_buf_size = em_get_rx_buffer_size(hw);
827 hw->fc.high_water = rx_buf_size -
828 PMD_ROUNDUP(RTE_ETHER_MAX_LEN * 2, 1024);
829 hw->fc.low_water = hw->fc.high_water - 1500;
831 if (hw->mac.type == e1000_80003es2lan)
832 hw->fc.pause_time = UINT16_MAX;
834 hw->fc.pause_time = EM_FC_PAUSE_TIME;
838 /* Set Flow control, use the tunable location if sane */
839 if (em_fc_setting <= e1000_fc_full)
840 hw->fc.requested_mode = em_fc_setting;
842 hw->fc.requested_mode = e1000_fc_none;
844 /* Workaround: no TX flow ctrl for PCH */
845 if (hw->mac.type == e1000_pchlan)
846 hw->fc.requested_mode = e1000_fc_rx_pause;
848 /* Override - settings for PCH2LAN, ya its magic :) */
849 if (hw->mac.type == e1000_pch2lan) {
850 hw->fc.high_water = 0x5C20;
851 hw->fc.low_water = 0x5048;
852 hw->fc.pause_time = 0x0650;
853 hw->fc.refresh_time = 0x0400;
854 } else if (hw->mac.type == e1000_pch_lpt ||
855 hw->mac.type == e1000_pch_spt ||
856 hw->mac.type == e1000_pch_cnp) {
857 hw->fc.requested_mode = e1000_fc_full;
860 diag = e1000_init_hw(hw);
863 e1000_check_for_link(hw);
867 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
869 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
871 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
872 struct e1000_hw_stats *stats =
873 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
876 if(hw->phy.media_type == e1000_media_type_copper ||
877 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
878 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
879 stats->sec += E1000_READ_REG(hw, E1000_SEC);
882 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
883 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
884 stats->scc += E1000_READ_REG(hw, E1000_SCC);
885 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
887 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
888 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
889 stats->colc += E1000_READ_REG(hw, E1000_COLC);
890 stats->dc += E1000_READ_REG(hw, E1000_DC);
891 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
892 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
893 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
896 * For watchdog management we need to know if we have been
897 * paused during the last interval, so capture that here.
899 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
900 stats->xoffrxc += pause_frames;
901 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
902 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
903 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
904 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
905 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
906 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
907 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
908 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
909 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
910 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
911 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
912 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
915 * For the 64-bit byte counters the low dword must be read first.
916 * Both registers clear on the read of the high dword.
919 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
920 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
921 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
922 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
924 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
925 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
926 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
927 stats->roc += E1000_READ_REG(hw, E1000_ROC);
928 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
930 stats->tor += E1000_READ_REG(hw, E1000_TORH);
931 stats->tot += E1000_READ_REG(hw, E1000_TOTH);
933 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
934 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
935 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
936 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
937 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
938 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
939 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
940 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
941 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
942 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
944 /* Interrupt Counts */
946 if (hw->mac.type >= e1000_82571) {
947 stats->iac += E1000_READ_REG(hw, E1000_IAC);
948 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
949 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
950 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
951 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
952 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
953 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
954 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
955 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
958 if (hw->mac.type >= e1000_82543) {
959 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
960 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
961 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
962 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
963 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
964 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
967 if (rte_stats == NULL)
971 rte_stats->imissed = stats->mpc;
972 rte_stats->ierrors = stats->crcerrs +
973 stats->rlec + stats->ruc + stats->roc +
974 stats->rxerrc + stats->algnerrc + stats->cexterr;
977 rte_stats->oerrors = stats->ecol + stats->latecol;
979 rte_stats->ipackets = stats->gprc;
980 rte_stats->opackets = stats->gptc;
981 rte_stats->ibytes = stats->gorc;
982 rte_stats->obytes = stats->gotc;
987 eth_em_stats_reset(struct rte_eth_dev *dev)
989 struct e1000_hw_stats *hw_stats =
990 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
992 /* HW registers are cleared on read */
993 eth_em_stats_get(dev, NULL);
995 /* Reset software totals */
996 memset(hw_stats, 0, sizeof(*hw_stats));
1002 eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1004 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1005 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1006 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1008 em_rxq_intr_enable(hw);
1009 rte_intr_ack(intr_handle);
1015 eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1017 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1019 em_rxq_intr_disable(hw);
1025 em_get_max_pktlen(struct rte_eth_dev *dev)
1027 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1029 switch (hw->mac.type) {
1033 case e1000_ich10lan:
1039 case e1000_80003es2lan: /* 9K Jumbo Frame size */
1044 /* Adapters that do not support jumbo frames */
1046 return RTE_ETHER_MAX_LEN;
1048 return MAX_JUMBO_FRAME_SIZE;
1053 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1055 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1057 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1058 dev_info->max_rx_pktlen = em_get_max_pktlen(dev);
1059 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1062 * Starting with 631xESB hw supports 2 TX/RX queues per port.
1063 * Unfortunatelly, all these nics have just one TX context.
1064 * So we have few choises for TX:
1065 * - Use just one TX queue.
1066 * - Allow cksum offload only for one TX queue.
1067 * - Don't allow TX cksum offload at all.
1068 * For now, option #1 was chosen.
1069 * To use second RX queue we have to use extended RX descriptor
1070 * (Multiple Receive Queues are mutually exclusive with UDP
1071 * fragmentation and are not supported when a legacy receive
1072 * descriptor format is used).
1073 * Which means separate RX routinies - as legacy nics (82540, 82545)
1074 * don't support extended RXD.
1075 * To avoid it we support just one RX queue for now (no RSS).
1078 dev_info->max_rx_queues = 1;
1079 dev_info->max_tx_queues = 1;
1081 dev_info->rx_queue_offload_capa = em_get_rx_queue_offloads_capa(dev);
1082 dev_info->rx_offload_capa = em_get_rx_port_offloads_capa(dev) |
1083 dev_info->rx_queue_offload_capa;
1084 dev_info->tx_queue_offload_capa = em_get_tx_queue_offloads_capa(dev);
1085 dev_info->tx_offload_capa = em_get_tx_port_offloads_capa(dev) |
1086 dev_info->tx_queue_offload_capa;
1088 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1089 .nb_max = E1000_MAX_RING_DESC,
1090 .nb_min = E1000_MIN_RING_DESC,
1091 .nb_align = EM_RXD_ALIGN,
1094 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1095 .nb_max = E1000_MAX_RING_DESC,
1096 .nb_min = E1000_MIN_RING_DESC,
1097 .nb_align = EM_TXD_ALIGN,
1098 .nb_seg_max = EM_TX_MAX_SEG,
1099 .nb_mtu_seg_max = EM_TX_MAX_MTU_SEG,
1102 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1103 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1106 /* Preferred queue parameters */
1107 dev_info->default_rxportconf.nb_queues = 1;
1108 dev_info->default_txportconf.nb_queues = 1;
1109 dev_info->default_txportconf.ring_size = 256;
1110 dev_info->default_rxportconf.ring_size = 256;
1115 /* return 0 means link status changed, -1 means not changed */
1117 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1119 struct e1000_hw *hw =
1120 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1121 struct rte_eth_link link;
1125 hw->mac.get_link_status = 1;
1127 /* possible wait-to-complete in up to 9 seconds */
1128 for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1129 /* Read the real link status */
1130 switch (hw->phy.media_type) {
1131 case e1000_media_type_copper:
1132 /* Do the work to read phy */
1133 e1000_check_for_link(hw);
1134 link_up = !hw->mac.get_link_status;
1137 case e1000_media_type_fiber:
1138 e1000_check_for_link(hw);
1139 link_up = (E1000_READ_REG(hw, E1000_STATUS) &
1143 case e1000_media_type_internal_serdes:
1144 e1000_check_for_link(hw);
1145 link_up = hw->mac.serdes_has_link;
1151 if (link_up || wait_to_complete == 0)
1153 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
1155 memset(&link, 0, sizeof(link));
1157 /* Now we check if a transition has happened */
1159 uint16_t duplex, speed;
1160 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1161 link.link_duplex = (duplex == FULL_DUPLEX) ?
1162 ETH_LINK_FULL_DUPLEX :
1163 ETH_LINK_HALF_DUPLEX;
1164 link.link_speed = speed;
1165 link.link_status = ETH_LINK_UP;
1166 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
1167 ETH_LINK_SPEED_FIXED);
1169 link.link_speed = ETH_SPEED_NUM_NONE;
1170 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1171 link.link_status = ETH_LINK_DOWN;
1172 link.link_autoneg = ETH_LINK_FIXED;
1175 return rte_eth_linkstatus_set(dev, &link);
1179 * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
1180 * For ASF and Pass Through versions of f/w this means
1181 * that the driver is loaded. For AMT version type f/w
1182 * this means that the network i/f is open.
1185 em_hw_control_acquire(struct e1000_hw *hw)
1187 uint32_t ctrl_ext, swsm;
1189 /* Let firmware know the driver has taken over */
1190 if (hw->mac.type == e1000_82573) {
1191 swsm = E1000_READ_REG(hw, E1000_SWSM);
1192 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
1195 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1196 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1197 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1202 * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
1203 * For ASF and Pass Through versions of f/w this means that the
1204 * driver is no longer loaded. For AMT versions of the
1205 * f/w this means that the network i/f is closed.
1208 em_hw_control_release(struct e1000_hw *hw)
1210 uint32_t ctrl_ext, swsm;
1212 /* Let firmware taken over control of h/w */
1213 if (hw->mac.type == e1000_82573) {
1214 swsm = E1000_READ_REG(hw, E1000_SWSM);
1215 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
1217 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1218 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1219 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1224 * Bit of a misnomer, what this really means is
1225 * to enable OS management of the system... aka
1226 * to disable special hardware management features.
1229 em_init_manageability(struct e1000_hw *hw)
1231 if (e1000_enable_mng_pass_thru(hw)) {
1232 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1233 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1235 /* disable hardware interception of ARP */
1236 manc &= ~(E1000_MANC_ARP_EN);
1238 /* enable receiving management packets to the host */
1239 manc |= E1000_MANC_EN_MNG2HOST;
1240 manc2h |= 1 << 5; /* Mng Port 623 */
1241 manc2h |= 1 << 6; /* Mng Port 664 */
1242 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1243 E1000_WRITE_REG(hw, E1000_MANC, manc);
1248 * Give control back to hardware management
1249 * controller if there is one.
1252 em_release_manageability(struct e1000_hw *hw)
1256 if (e1000_enable_mng_pass_thru(hw)) {
1257 manc = E1000_READ_REG(hw, E1000_MANC);
1259 /* re-enable hardware interception of ARP */
1260 manc |= E1000_MANC_ARP_EN;
1261 manc &= ~E1000_MANC_EN_MNG2HOST;
1263 E1000_WRITE_REG(hw, E1000_MANC, manc);
1268 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1270 struct e1000_hw *hw =
1271 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1274 rctl = E1000_READ_REG(hw, E1000_RCTL);
1275 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1276 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1282 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1284 struct e1000_hw *hw =
1285 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1288 rctl = E1000_READ_REG(hw, E1000_RCTL);
1289 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1290 if (dev->data->all_multicast == 1)
1291 rctl |= E1000_RCTL_MPE;
1293 rctl &= (~E1000_RCTL_MPE);
1294 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1300 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1302 struct e1000_hw *hw =
1303 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1306 rctl = E1000_READ_REG(hw, E1000_RCTL);
1307 rctl |= E1000_RCTL_MPE;
1308 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1314 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1316 struct e1000_hw *hw =
1317 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1320 if (dev->data->promiscuous == 1)
1321 return 0; /* must remain in all_multicast mode */
1322 rctl = E1000_READ_REG(hw, E1000_RCTL);
1323 rctl &= (~E1000_RCTL_MPE);
1324 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1330 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1332 struct e1000_hw *hw =
1333 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1334 struct e1000_vfta * shadow_vfta =
1335 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1340 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1341 E1000_VFTA_ENTRY_MASK);
1342 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1343 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1348 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1350 /* update local VFTA copy */
1351 shadow_vfta->vfta[vid_idx] = vfta;
1357 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1359 struct e1000_hw *hw =
1360 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1363 /* Filter Table Disable */
1364 reg = E1000_READ_REG(hw, E1000_RCTL);
1365 reg &= ~E1000_RCTL_CFIEN;
1366 reg &= ~E1000_RCTL_VFE;
1367 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1371 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1373 struct e1000_hw *hw =
1374 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1375 struct e1000_vfta * shadow_vfta =
1376 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1380 /* Filter Table Enable, CFI not used for packet acceptance */
1381 reg = E1000_READ_REG(hw, E1000_RCTL);
1382 reg &= ~E1000_RCTL_CFIEN;
1383 reg |= E1000_RCTL_VFE;
1384 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1386 /* restore vfta from local copy */
1387 for (i = 0; i < IGB_VFTA_SIZE; i++)
1388 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1392 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1394 struct e1000_hw *hw =
1395 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1398 /* VLAN Mode Disable */
1399 reg = E1000_READ_REG(hw, E1000_CTRL);
1400 reg &= ~E1000_CTRL_VME;
1401 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1406 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1408 struct e1000_hw *hw =
1409 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1412 /* VLAN Mode Enable */
1413 reg = E1000_READ_REG(hw, E1000_CTRL);
1414 reg |= E1000_CTRL_VME;
1415 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1419 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1421 struct rte_eth_rxmode *rxmode;
1423 rxmode = &dev->data->dev_conf.rxmode;
1424 if(mask & ETH_VLAN_STRIP_MASK){
1425 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1426 em_vlan_hw_strip_enable(dev);
1428 em_vlan_hw_strip_disable(dev);
1431 if(mask & ETH_VLAN_FILTER_MASK){
1432 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1433 em_vlan_hw_filter_enable(dev);
1435 em_vlan_hw_filter_disable(dev);
1442 * It enables the interrupt mask and then enable the interrupt.
1445 * Pointer to struct rte_eth_dev.
1448 * - On success, zero.
1449 * - On failure, a negative value.
1452 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1455 struct e1000_hw *hw =
1456 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1458 /* clear interrupt */
1459 E1000_READ_REG(hw, E1000_ICR);
1460 regval = E1000_READ_REG(hw, E1000_IMS);
1461 E1000_WRITE_REG(hw, E1000_IMS,
1462 regval | E1000_ICR_LSC | E1000_ICR_OTHER);
1467 * It clears the interrupt causes and enables the interrupt.
1468 * It will be called once only during nic initialized.
1471 * Pointer to struct rte_eth_dev.
1474 * - On success, zero.
1475 * - On failure, a negative value.
1478 eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev)
1480 struct e1000_hw *hw =
1481 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1483 E1000_READ_REG(hw, E1000_ICR);
1484 em_rxq_intr_enable(hw);
1489 * It enable receive packet interrupt.
1491 * Pointer to struct e1000_hw
1496 em_rxq_intr_enable(struct e1000_hw *hw)
1498 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_RXT0);
1499 E1000_WRITE_FLUSH(hw);
1503 * It disabled lsc interrupt.
1505 * Pointer to struct e1000_hw
1510 em_lsc_intr_disable(struct e1000_hw *hw)
1512 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_LSC | E1000_IMS_OTHER);
1513 E1000_WRITE_FLUSH(hw);
1517 * It disabled receive packet interrupt.
1519 * Pointer to struct e1000_hw
1524 em_rxq_intr_disable(struct e1000_hw *hw)
1526 E1000_READ_REG(hw, E1000_ICR);
1527 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0);
1528 E1000_WRITE_FLUSH(hw);
1532 * It reads ICR and gets interrupt causes, check it and set a bit flag
1533 * to update link status.
1536 * Pointer to struct rte_eth_dev.
1539 * - On success, zero.
1540 * - On failure, a negative value.
1543 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1546 struct e1000_hw *hw =
1547 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1548 struct e1000_interrupt *intr =
1549 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1551 /* read-on-clear nic registers here */
1552 icr = E1000_READ_REG(hw, E1000_ICR);
1553 if (icr & E1000_ICR_LSC) {
1554 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1561 * It executes link_update after knowing an interrupt is prsent.
1564 * Pointer to struct rte_eth_dev.
1567 * - On success, zero.
1568 * - On failure, a negative value.
1571 eth_em_interrupt_action(struct rte_eth_dev *dev,
1572 struct rte_intr_handle *intr_handle)
1574 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1575 struct e1000_hw *hw =
1576 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1577 struct e1000_interrupt *intr =
1578 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1579 struct rte_eth_link link;
1582 if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1585 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1586 rte_intr_ack(intr_handle);
1588 /* set get_link_status to check register later */
1589 hw->mac.get_link_status = 1;
1590 ret = eth_em_link_update(dev, 0);
1592 /* check if link has changed */
1596 rte_eth_linkstatus_get(dev, &link);
1598 if (link.link_status) {
1599 PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s",
1600 dev->data->port_id, link.link_speed,
1601 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1602 "full-duplex" : "half-duplex");
1604 PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
1606 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
1607 pci_dev->addr.domain, pci_dev->addr.bus,
1608 pci_dev->addr.devid, pci_dev->addr.function);
1614 * Interrupt handler which shall be registered at first.
1617 * Pointer to interrupt handle.
1619 * The address of parameter (struct rte_eth_dev *) regsitered before.
1625 eth_em_interrupt_handler(void *param)
1627 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1629 eth_em_interrupt_get_status(dev);
1630 eth_em_interrupt_action(dev, dev->intr_handle);
1631 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1635 eth_em_led_on(struct rte_eth_dev *dev)
1637 struct e1000_hw *hw;
1639 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1640 return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1644 eth_em_led_off(struct rte_eth_dev *dev)
1646 struct e1000_hw *hw;
1648 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1649 return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1653 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1655 struct e1000_hw *hw;
1660 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1661 fc_conf->pause_time = hw->fc.pause_time;
1662 fc_conf->high_water = hw->fc.high_water;
1663 fc_conf->low_water = hw->fc.low_water;
1664 fc_conf->send_xon = hw->fc.send_xon;
1665 fc_conf->autoneg = hw->mac.autoneg;
1668 * Return rx_pause and tx_pause status according to actual setting of
1669 * the TFCE and RFCE bits in the CTRL register.
1671 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1672 if (ctrl & E1000_CTRL_TFCE)
1677 if (ctrl & E1000_CTRL_RFCE)
1682 if (rx_pause && tx_pause)
1683 fc_conf->mode = RTE_FC_FULL;
1685 fc_conf->mode = RTE_FC_RX_PAUSE;
1687 fc_conf->mode = RTE_FC_TX_PAUSE;
1689 fc_conf->mode = RTE_FC_NONE;
1695 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1697 struct e1000_hw *hw;
1699 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1705 uint32_t rx_buf_size;
1706 uint32_t max_high_water;
1709 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1710 if (fc_conf->autoneg != hw->mac.autoneg)
1712 rx_buf_size = em_get_rx_buffer_size(hw);
1713 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1715 /* At least reserve one Ethernet frame for watermark */
1716 max_high_water = rx_buf_size - RTE_ETHER_MAX_LEN;
1717 if ((fc_conf->high_water > max_high_water) ||
1718 (fc_conf->high_water < fc_conf->low_water)) {
1719 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1720 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
1724 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1725 hw->fc.pause_time = fc_conf->pause_time;
1726 hw->fc.high_water = fc_conf->high_water;
1727 hw->fc.low_water = fc_conf->low_water;
1728 hw->fc.send_xon = fc_conf->send_xon;
1730 err = e1000_setup_link_generic(hw);
1731 if (err == E1000_SUCCESS) {
1733 /* check if we want to forward MAC frames - driver doesn't have native
1734 * capability to do that, so we'll write the registers ourselves */
1736 rctl = E1000_READ_REG(hw, E1000_RCTL);
1738 /* set or clear MFLCN.PMCF bit depending on configuration */
1739 if (fc_conf->mac_ctrl_frame_fwd != 0)
1740 rctl |= E1000_RCTL_PMCF;
1742 rctl &= ~E1000_RCTL_PMCF;
1744 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1745 E1000_WRITE_FLUSH(hw);
1750 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1755 eth_em_rar_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1756 uint32_t index, __rte_unused uint32_t pool)
1758 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1760 return e1000_rar_set(hw, mac_addr->addr_bytes, index);
1764 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1766 uint8_t addr[RTE_ETHER_ADDR_LEN];
1767 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1769 memset(addr, 0, sizeof(addr));
1771 e1000_rar_set(hw, addr, index);
1775 eth_em_default_mac_addr_set(struct rte_eth_dev *dev,
1776 struct rte_ether_addr *addr)
1778 eth_em_rar_clear(dev, 0);
1780 return eth_em_rar_set(dev, (void *)addr, 0, 0);
1784 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1786 struct rte_eth_dev_info dev_info;
1787 struct e1000_hw *hw;
1788 uint32_t frame_size;
1792 ret = eth_em_infos_get(dev, &dev_info);
1796 frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
1799 /* check that mtu is within the allowed range */
1800 if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
1803 /* refuse mtu that requires the support of scattered packets when this
1804 * feature has not been enabled before. */
1805 if (!dev->data->scattered_rx &&
1806 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1809 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1810 rctl = E1000_READ_REG(hw, E1000_RCTL);
1812 /* switch to jumbo mode if needed */
1813 if (frame_size > RTE_ETHER_MAX_LEN) {
1814 dev->data->dev_conf.rxmode.offloads |=
1815 DEV_RX_OFFLOAD_JUMBO_FRAME;
1816 rctl |= E1000_RCTL_LPE;
1818 dev->data->dev_conf.rxmode.offloads &=
1819 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1820 rctl &= ~E1000_RCTL_LPE;
1822 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1824 /* update max frame size */
1825 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1830 eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
1831 struct rte_ether_addr *mc_addr_set,
1832 uint32_t nb_mc_addr)
1834 struct e1000_hw *hw;
1836 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1837 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
1841 RTE_PMD_REGISTER_PCI(net_e1000_em, rte_em_pmd);
1842 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_em, pci_id_em_map);
1843 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_em, "* igb_uio | uio_pci_generic | vfio-pci");
1845 /* see e1000_logs.c */
1846 RTE_INIT(igb_init_log)
1848 e1000_igb_init_log();