drivers/net/e1000/em_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_eal.h>
  51 #include <rte_atomic.h>
  52 #include <rte_malloc.h>
  53 #include <rte_dev.h>
  54
  55 #include "e1000_logs.h"
  56 #include "base/e1000_api.h"
  57 #include "e1000_ethdev.h"
  58
  59 #define EM_EIAC                 0x000DC
  60
  61 #define PMD_ROUNDUP(x,y)        (((x) + (y) - 1)/(y) * (y))
  62
  63
  64 static int eth_em_configure(struct rte_eth_dev *dev);
  65 static int eth_em_start(struct rte_eth_dev *dev);
  66 static void eth_em_stop(struct rte_eth_dev *dev);
  67 static void eth_em_close(struct rte_eth_dev *dev);
  68 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
  69 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
  70 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
  71 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
  72 static int eth_em_link_update(struct rte_eth_dev *dev,
  73                                 int wait_to_complete);
  74 static void eth_em_stats_get(struct rte_eth_dev *dev,
  75                                 struct rte_eth_stats *rte_stats);
  76 static void eth_em_stats_reset(struct rte_eth_dev *dev);
  77 static void eth_em_infos_get(struct rte_eth_dev *dev,
  78                                 struct rte_eth_dev_info *dev_info);
  79 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
  80                                 struct rte_eth_fc_conf *fc_conf);
  81 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
  82                                 struct rte_eth_fc_conf *fc_conf);
  83 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
  84 static int eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev);
  85 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
  86 static int eth_em_interrupt_action(struct rte_eth_dev *dev);
  87 static void eth_em_interrupt_handler(struct rte_intr_handle *handle,
  88                                                         void *param);
  89
  90 static int em_hw_init(struct e1000_hw *hw);
  91 static int em_hardware_init(struct e1000_hw *hw);
  92 static void em_hw_control_acquire(struct e1000_hw *hw);
  93 static void em_hw_control_release(struct e1000_hw *hw);
  94 static void em_init_manageability(struct e1000_hw *hw);
  95 static void em_release_manageability(struct e1000_hw *hw);
  96
  97 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  98
  99 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
 100                 uint16_t vlan_id, int on);
 101 static void eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 102 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 103 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 104 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 105 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 106
 107 /*
 108 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
 109                                         uint16_t vlan_id, int on);
 110 */
 111
 112 static int eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
 113 static int eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
 114 static void em_lsc_intr_disable(struct e1000_hw *hw);
 115 static void em_rxq_intr_enable(struct e1000_hw *hw);
 116 static void em_rxq_intr_disable(struct e1000_hw *hw);
 117
 118 static int eth_em_led_on(struct rte_eth_dev *dev);
 119 static int eth_em_led_off(struct rte_eth_dev *dev);
 120
 121 static int em_get_rx_buffer_size(struct e1000_hw *hw);
 122 static void eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 123                 uint32_t index, uint32_t pool);
 124 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 125
 126 static int eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
 127                                    struct ether_addr *mc_addr_set,
 128                                    uint32_t nb_mc_addr);
 129
 130 #define EM_FC_PAUSE_TIME 0x0680
 131 #define EM_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 132 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 133
 134 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
 135
 136 /*
 137  * The set of PCI devices this driver supports
 138  */
 139 static const struct rte_pci_id pci_id_em_map[] = {
 140
 141 #define RTE_PCI_DEV_ID_DECL_EM(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 142 #include "rte_pci_dev_ids.h"
 143
 144 {0},
 145 };
 146
 147 static const struct eth_dev_ops eth_em_ops = {
 148         .dev_configure        = eth_em_configure,
 149         .dev_start            = eth_em_start,
 150         .dev_stop             = eth_em_stop,
 151         .dev_close            = eth_em_close,
 152         .promiscuous_enable   = eth_em_promiscuous_enable,
 153         .promiscuous_disable  = eth_em_promiscuous_disable,
 154         .allmulticast_enable  = eth_em_allmulticast_enable,
 155         .allmulticast_disable = eth_em_allmulticast_disable,
 156         .link_update          = eth_em_link_update,
 157         .stats_get            = eth_em_stats_get,
 158         .stats_reset          = eth_em_stats_reset,
 159         .dev_infos_get        = eth_em_infos_get,
 160         .mtu_set              = eth_em_mtu_set,
 161         .vlan_filter_set      = eth_em_vlan_filter_set,
 162         .vlan_offload_set     = eth_em_vlan_offload_set,
 163         .rx_queue_setup       = eth_em_rx_queue_setup,
 164         .rx_queue_release     = eth_em_rx_queue_release,
 165         .rx_queue_count       = eth_em_rx_queue_count,
 166         .rx_descriptor_done   = eth_em_rx_descriptor_done,
 167         .tx_queue_setup       = eth_em_tx_queue_setup,
 168         .tx_queue_release     = eth_em_tx_queue_release,
 169         .rx_queue_intr_enable = eth_em_rx_queue_intr_enable,
 170         .rx_queue_intr_disable = eth_em_rx_queue_intr_disable,
 171         .dev_led_on           = eth_em_led_on,
 172         .dev_led_off          = eth_em_led_off,
 173         .flow_ctrl_get        = eth_em_flow_ctrl_get,
 174         .flow_ctrl_set        = eth_em_flow_ctrl_set,
 175         .mac_addr_add         = eth_em_rar_set,
 176         .mac_addr_remove      = eth_em_rar_clear,
 177         .set_mc_addr_list     = eth_em_set_mc_addr_list,
 178         .rxq_info_get         = em_rxq_info_get,
 179         .txq_info_get         = em_txq_info_get,
 180 };
 181
 182 /**
 183  * Atomically reads the link status information from global
 184  * structure rte_eth_dev.
 185  *
 186  * @param dev
 187  *   - Pointer to the structure rte_eth_dev to read from.
 188  *   - Pointer to the buffer to be saved with the link status.
 189  *
 190  * @return
 191  *   - On success, zero.
 192  *   - On failure, negative value.
 193  */
 194 static inline int
 195 rte_em_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 196                                 struct rte_eth_link *link)
 197 {
 198         struct rte_eth_link *dst = link;
 199         struct rte_eth_link *src = &(dev->data->dev_link);
 200
 201         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 202                                         *(uint64_t *)src) == 0)
 203                 return -1;
 204
 205         return 0;
 206 }
 207
 208 /**
 209  * Atomically writes the link status information into global
 210  * structure rte_eth_dev.
 211  *
 212  * @param dev
 213  *   - Pointer to the structure rte_eth_dev to read from.
 214  *   - Pointer to the buffer to be saved with the link status.
 215  *
 216  * @return
 217  *   - On success, zero.
 218  *   - On failure, negative value.
 219  */
 220 static inline int
 221 rte_em_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 222                                 struct rte_eth_link *link)
 223 {
 224         struct rte_eth_link *dst = &(dev->data->dev_link);
 225         struct rte_eth_link *src = link;
 226
 227         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 228                                         *(uint64_t *)src) == 0)
 229                 return -1;
 230
 231         return 0;
 232 }
 233
 234 static int
 235 eth_em_dev_init(struct rte_eth_dev *eth_dev)
 236 {
 237         struct rte_pci_device *pci_dev;
 238         struct e1000_adapter *adapter =
 239                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 240         struct e1000_hw *hw =
 241                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 242         struct e1000_vfta * shadow_vfta =
 243                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 244
 245         pci_dev = eth_dev->pci_dev;
 246
 247         rte_eth_copy_pci_info(eth_dev, pci_dev);
 248
 249         eth_dev->dev_ops = &eth_em_ops;
 250         eth_dev->rx_pkt_burst = (eth_rx_burst_t)&eth_em_recv_pkts;
 251         eth_dev->tx_pkt_burst = (eth_tx_burst_t)&eth_em_xmit_pkts;
 252
 253         /* for secondary processes, we don't initialise any further as primary
 254          * has already done this work. Only check we don't need a different
 255          * RX function */
 256         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 257                 if (eth_dev->data->scattered_rx)
 258                         eth_dev->rx_pkt_burst =
 259                                 (eth_rx_burst_t)&eth_em_recv_scattered_pkts;
 260                 return 0;
 261         }
 262
 263         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 264         hw->device_id = pci_dev->id.device_id;
 265         adapter->stopped = 0;
 266
 267         /* For ICH8 support we'll need to map the flash memory BAR */
 268
 269         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
 270                         em_hw_init(hw) != 0) {
 271                 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
 272                         "failed to init HW",
 273                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 274                         pci_dev->id.device_id);
 275                 return -(ENODEV);
 276         }
 277
 278         /* Allocate memory for storing MAC addresses */
 279         eth_dev->data->mac_addrs = rte_zmalloc("e1000", ETHER_ADDR_LEN *
 280                         hw->mac.rar_entry_count, 0);
 281         if (eth_dev->data->mac_addrs == NULL) {
 282                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 283                         "store MAC addresses",
 284                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 285                 return -(ENOMEM);
 286         }
 287
 288         /* Copy the permanent MAC address */
 289         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 290                 eth_dev->data->mac_addrs);
 291
 292         /* initialize the vfta */
 293         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 294
 295         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 296                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 297                      pci_dev->id.device_id);
 298
 299         rte_intr_callback_register(&(pci_dev->intr_handle),
 300                 eth_em_interrupt_handler, (void *)eth_dev);
 301
 302         return (0);
 303 }
 304
 305 static int
 306 eth_em_dev_uninit(struct rte_eth_dev *eth_dev)
 307 {
 308         struct rte_pci_device *pci_dev;
 309         struct e1000_adapter *adapter =
 310                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 311
 312         PMD_INIT_FUNC_TRACE();
 313
 314         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 315                 return -EPERM;
 316
 317         pci_dev = eth_dev->pci_dev;
 318
 319         if (adapter->stopped == 0)
 320                 eth_em_close(eth_dev);
 321
 322         eth_dev->dev_ops = NULL;
 323         eth_dev->rx_pkt_burst = NULL;
 324         eth_dev->tx_pkt_burst = NULL;
 325
 326         rte_free(eth_dev->data->mac_addrs);
 327         eth_dev->data->mac_addrs = NULL;
 328
 329         /* disable uio intr before callback unregister */
 330         rte_intr_disable(&(pci_dev->intr_handle));
 331         rte_intr_callback_unregister(&(pci_dev->intr_handle),
 332                 eth_em_interrupt_handler, (void *)eth_dev);
 333
 334         return 0;
 335 }
 336
 337 static struct eth_driver rte_em_pmd = {
 338         .pci_drv = {
 339                 .name = "rte_em_pmd",
 340                 .id_table = pci_id_em_map,
 341                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 342                         RTE_PCI_DRV_DETACHABLE,
 343         },
 344         .eth_dev_init = eth_em_dev_init,
 345         .eth_dev_uninit = eth_em_dev_uninit,
 346         .dev_private_size = sizeof(struct e1000_adapter),
 347 };
 348
 349 static int
 350 rte_em_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 351 {
 352         rte_eth_driver_register(&rte_em_pmd);
 353         return 0;
 354 }
 355
 356 static int
 357 em_hw_init(struct e1000_hw *hw)
 358 {
 359         int diag;
 360
 361         diag = hw->mac.ops.init_params(hw);
 362         if (diag != 0) {
 363                 PMD_INIT_LOG(ERR, "MAC Initialization Error");
 364                 return diag;
 365         }
 366         diag = hw->nvm.ops.init_params(hw);
 367         if (diag != 0) {
 368                 PMD_INIT_LOG(ERR, "NVM Initialization Error");
 369                 return diag;
 370         }
 371         diag = hw->phy.ops.init_params(hw);
 372         if (diag != 0) {
 373                 PMD_INIT_LOG(ERR, "PHY Initialization Error");
 374                 return diag;
 375         }
 376         (void) e1000_get_bus_info(hw);
 377
 378         hw->mac.autoneg = 1;
 379         hw->phy.autoneg_wait_to_complete = 0;
 380         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 381
 382         e1000_init_script_state_82541(hw, TRUE);
 383         e1000_set_tbi_compatibility_82543(hw, TRUE);
 384
 385         /* Copper options */
 386         if (hw->phy.media_type == e1000_media_type_copper) {
 387                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 388                 hw->phy.disable_polarity_correction = 0;
 389                 hw->phy.ms_type = e1000_ms_hw_default;
 390         }
 391
 392         /*
 393          * Start from a known state, this is important in reading the nvm
 394          * and mac from that.
 395          */
 396         e1000_reset_hw(hw);
 397
 398         /* Make sure we have a good EEPROM before we read from it */
 399         if (e1000_validate_nvm_checksum(hw) < 0) {
 400                 /*
 401                  * Some PCI-E parts fail the first check due to
 402                  * the link being in sleep state, call it again,
 403                  * if it fails a second time its a real issue.
 404                  */
 405                 diag = e1000_validate_nvm_checksum(hw);
 406                 if (diag < 0) {
 407                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 408                         goto error;
 409                 }
 410         }
 411
 412         /* Read the permanent MAC address out of the EEPROM */
 413         diag = e1000_read_mac_addr(hw);
 414         if (diag != 0) {
 415                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 416                 goto error;
 417         }
 418
 419         /* Now initialize the hardware */
 420         diag = em_hardware_init(hw);
 421         if (diag != 0) {
 422                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 423                 goto error;
 424         }
 425
 426         hw->mac.get_link_status = 1;
 427
 428         /* Indicate SOL/IDER usage */
 429         diag = e1000_check_reset_block(hw);
 430         if (diag < 0) {
 431                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
 432                         "SOL/IDER session");
 433         }
 434         return (0);
 435
 436 error:
 437         em_hw_control_release(hw);
 438         return (diag);
 439 }
 440
 441 static int
 442 eth_em_configure(struct rte_eth_dev *dev)
 443 {
 444         struct e1000_interrupt *intr =
 445                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 446
 447         PMD_INIT_FUNC_TRACE();
 448         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 449         PMD_INIT_FUNC_TRACE();
 450
 451         return (0);
 452 }
 453
 454 static void
 455 em_set_pba(struct e1000_hw *hw)
 456 {
 457         uint32_t pba;
 458
 459         /*
 460          * Packet Buffer Allocation (PBA)
 461          * Writing PBA sets the receive portion of the buffer
 462          * the remainder is used for the transmit buffer.
 463          * Devices before the 82547 had a Packet Buffer of 64K.
 464          * After the 82547 the buffer was reduced to 40K.
 465          */
 466         switch (hw->mac.type) {
 467                 case e1000_82547:
 468                 case e1000_82547_rev_2:
 469                 /* 82547: Total Packet Buffer is 40K */
 470                         pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
 471                         break;
 472                 case e1000_82571:
 473                 case e1000_82572:
 474                 case e1000_80003es2lan:
 475                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 476                         break;
 477                 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
 478                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
 479                         break;
 480                 case e1000_82574:
 481                 case e1000_82583:
 482                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
 483                         break;
 484                 case e1000_ich8lan:
 485                         pba = E1000_PBA_8K;
 486                         break;
 487                 case e1000_ich9lan:
 488                 case e1000_ich10lan:
 489                         pba = E1000_PBA_10K;
 490                         break;
 491                 case e1000_pchlan:
 492                 case e1000_pch2lan:
 493                         pba = E1000_PBA_26K;
 494                         break;
 495                 default:
 496                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
 497         }
 498
 499         E1000_WRITE_REG(hw, E1000_PBA, pba);
 500 }
 501
 502 static int
 503 eth_em_start(struct rte_eth_dev *dev)
 504 {
 505         struct e1000_adapter *adapter =
 506                 E1000_DEV_PRIVATE(dev->data->dev_private);
 507         struct e1000_hw *hw =
 508                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 509         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
 510         int ret, mask;
 511         uint32_t intr_vector = 0;
 512
 513         PMD_INIT_FUNC_TRACE();
 514
 515         eth_em_stop(dev);
 516
 517         e1000_power_up_phy(hw);
 518
 519         /* Set default PBA value */
 520         em_set_pba(hw);
 521
 522         /* Put the address into the Receive Address Array */
 523         e1000_rar_set(hw, hw->mac.addr, 0);
 524
 525         /*
 526          * With the 82571 adapter, RAR[0] may be overwritten
 527          * when the other port is reset, we make a duplicate
 528          * in RAR[14] for that eventuality, this assures
 529          * the interface continues to function.
 530          */
 531         if (hw->mac.type == e1000_82571) {
 532                 e1000_set_laa_state_82571(hw, TRUE);
 533                 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
 534         }
 535
 536         /* Initialize the hardware */
 537         if (em_hardware_init(hw)) {
 538                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 539                 return (-EIO);
 540         }
 541
 542         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 543
 544         /* Configure for OS presence */
 545         em_init_manageability(hw);
 546
 547         if (dev->data->dev_conf.intr_conf.rxq != 0) {
 548                 intr_vector = dev->data->nb_rx_queues;
 549                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 550                         return -1;
 551         }
 552
 553         if (rte_intr_dp_is_en(intr_handle)) {
 554                 intr_handle->intr_vec =
 555                         rte_zmalloc("intr_vec",
 556                                         dev->data->nb_rx_queues * sizeof(int), 0);
 557                 if (intr_handle->intr_vec == NULL) {
 558                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
 559                                                 " intr_vec\n", dev->data->nb_rx_queues);
 560                         return -ENOMEM;
 561                 }
 562
 563                 /* enable rx interrupt */
 564                 em_rxq_intr_enable(hw);
 565         }
 566
 567         eth_em_tx_init(dev);
 568
 569         ret = eth_em_rx_init(dev);
 570         if (ret) {
 571                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 572                 em_dev_clear_queues(dev);
 573                 return ret;
 574         }
 575
 576         e1000_clear_hw_cntrs_base_generic(hw);
 577
 578         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 579                         ETH_VLAN_EXTEND_MASK;
 580         eth_em_vlan_offload_set(dev, mask);
 581
 582         /* Set Interrupt Throttling Rate to maximum allowed value. */
 583         E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
 584
 585         /* Setup link speed and duplex */
 586         switch (dev->data->dev_conf.link_speed) {
 587         case ETH_LINK_SPEED_AUTONEG:
 588                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 589                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 590                 else if (dev->data->dev_conf.link_duplex ==
 591                                         ETH_LINK_HALF_DUPLEX)
 592                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
 593                 else if (dev->data->dev_conf.link_duplex ==
 594                                         ETH_LINK_FULL_DUPLEX)
 595                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
 596                 else
 597                         goto error_invalid_config;
 598                 break;
 599         case ETH_LINK_SPEED_10:
 600                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 601                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
 602                 else if (dev->data->dev_conf.link_duplex ==
 603                                         ETH_LINK_HALF_DUPLEX)
 604                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
 605                 else if (dev->data->dev_conf.link_duplex ==
 606                                         ETH_LINK_FULL_DUPLEX)
 607                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
 608                 else
 609                         goto error_invalid_config;
 610                 break;
 611         case ETH_LINK_SPEED_100:
 612                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 613                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
 614                 else if (dev->data->dev_conf.link_duplex ==
 615                                         ETH_LINK_HALF_DUPLEX)
 616                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
 617                 else if (dev->data->dev_conf.link_duplex ==
 618                                         ETH_LINK_FULL_DUPLEX)
 619                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
 620                 else
 621                         goto error_invalid_config;
 622                 break;
 623         case ETH_LINK_SPEED_1000:
 624                 if ((dev->data->dev_conf.link_duplex ==
 625                                 ETH_LINK_AUTONEG_DUPLEX) ||
 626                         (dev->data->dev_conf.link_duplex ==
 627                                         ETH_LINK_FULL_DUPLEX))
 628                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
 629                 else
 630                         goto error_invalid_config;
 631                 break;
 632         case ETH_LINK_SPEED_10000:
 633         default:
 634                 goto error_invalid_config;
 635         }
 636         e1000_setup_link(hw);
 637
 638         if (rte_intr_allow_others(intr_handle)) {
 639                 /* check if lsc interrupt is enabled */
 640                 if (dev->data->dev_conf.intr_conf.lsc != 0)
 641                         ret = eth_em_interrupt_setup(dev);
 642                         if (ret) {
 643                                 PMD_INIT_LOG(ERR, "Unable to setup interrupts");
 644                                 em_dev_clear_queues(dev);
 645                                 return ret;
 646                         }
 647         } else {
 648                 rte_intr_callback_unregister(intr_handle,
 649                                                 eth_em_interrupt_handler,
 650                                                 (void *)dev);
 651                 if (dev->data->dev_conf.intr_conf.lsc != 0)
 652                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
 653                                      " no intr multiplex\n");
 654         }
 655         /* check if rxq interrupt is enabled */
 656         if (dev->data->dev_conf.intr_conf.rxq != 0)
 657                 eth_em_rxq_interrupt_setup(dev);
 658
 659         rte_intr_enable(intr_handle);
 660
 661         adapter->stopped = 0;
 662
 663         PMD_INIT_LOG(DEBUG, "<<");
 664
 665         return (0);
 666
 667 error_invalid_config:
 668         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u",
 669                      dev->data->dev_conf.link_speed,
 670                      dev->data->dev_conf.link_duplex, dev->data->port_id);
 671         em_dev_clear_queues(dev);
 672         return (-EINVAL);
 673 }
 674
 675 /*********************************************************************
 676  *
 677  *  This routine disables all traffic on the adapter by issuing a
 678  *  global reset on the MAC.
 679  *
 680  **********************************************************************/
 681 static void
 682 eth_em_stop(struct rte_eth_dev *dev)
 683 {
 684         struct rte_eth_link link;
 685         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 686         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
 687
 688         em_rxq_intr_disable(hw);
 689         em_lsc_intr_disable(hw);
 690
 691         e1000_reset_hw(hw);
 692         if (hw->mac.type >= e1000_82544)
 693                 E1000_WRITE_REG(hw, E1000_WUC, 0);
 694
 695         /* Power down the phy. Needed to make the link go down */
 696         e1000_power_down_phy(hw);
 697
 698         em_dev_clear_queues(dev);
 699
 700         /* clear the recorded link status */
 701         memset(&link, 0, sizeof(link));
 702         rte_em_dev_atomic_write_link_status(dev, &link);
 703
 704         if (!rte_intr_allow_others(intr_handle))
 705                 /* resume to the default handler */
 706                 rte_intr_callback_register(intr_handle,
 707                                            eth_em_interrupt_handler,
 708                                            (void *)dev);
 709
 710         /* Clean datapath event and queue/vec mapping */
 711         rte_intr_efd_disable(intr_handle);
 712         if (intr_handle->intr_vec != NULL) {
 713                 rte_free(intr_handle->intr_vec);
 714                 intr_handle->intr_vec = NULL;
 715         }
 716 }
 717
 718 static void
 719 eth_em_close(struct rte_eth_dev *dev)
 720 {
 721         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 722         struct e1000_adapter *adapter =
 723                 E1000_DEV_PRIVATE(dev->data->dev_private);
 724
 725         eth_em_stop(dev);
 726         adapter->stopped = 1;
 727         em_dev_free_queues(dev);
 728         e1000_phy_hw_reset(hw);
 729         em_release_manageability(hw);
 730         em_hw_control_release(hw);
 731 }
 732
 733 static int
 734 em_get_rx_buffer_size(struct e1000_hw *hw)
 735 {
 736         uint32_t rx_buf_size;
 737
 738         rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
 739         return rx_buf_size;
 740 }
 741
 742 /*********************************************************************
 743  *
 744  *  Initialize the hardware
 745  *
 746  **********************************************************************/
 747 static int
 748 em_hardware_init(struct e1000_hw *hw)
 749 {
 750         uint32_t rx_buf_size;
 751         int diag;
 752
 753         /* Issue a global reset */
 754         e1000_reset_hw(hw);
 755
 756         /* Let the firmware know the OS is in control */
 757         em_hw_control_acquire(hw);
 758
 759         /*
 760          * These parameters control the automatic generation (Tx) and
 761          * response (Rx) to Ethernet PAUSE frames.
 762          * - High water mark should allow for at least two standard size (1518)
 763          *   frames to be received after sending an XOFF.
 764          * - Low water mark works best when it is very near the high water mark.
 765          *   This allows the receiver to restart by sending XON when it has
 766          *   drained a bit. Here we use an arbitrary value of 1500 which will
 767          *   restart after one full frame is pulled from the buffer. There
 768          *   could be several smaller frames in the buffer and if so they will
 769          *   not trigger the XON until their total number reduces the buffer
 770          *   by 1500.
 771          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
 772          */
 773         rx_buf_size = em_get_rx_buffer_size(hw);
 774
 775         hw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);
 776         hw->fc.low_water = hw->fc.high_water - 1500;
 777
 778         if (hw->mac.type == e1000_80003es2lan)
 779                 hw->fc.pause_time = UINT16_MAX;
 780         else
 781                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
 782
 783         hw->fc.send_xon = 1;
 784
 785         /* Set Flow control, use the tunable location if sane */
 786         if (em_fc_setting <= e1000_fc_full)
 787                 hw->fc.requested_mode = em_fc_setting;
 788         else
 789                 hw->fc.requested_mode = e1000_fc_none;
 790
 791         /* Workaround: no TX flow ctrl for PCH */
 792         if (hw->mac.type == e1000_pchlan)
 793                 hw->fc.requested_mode = e1000_fc_rx_pause;
 794
 795         /* Override - settings for PCH2LAN, ya its magic :) */
 796         if (hw->mac.type == e1000_pch2lan) {
 797                 hw->fc.high_water = 0x5C20;
 798                 hw->fc.low_water = 0x5048;
 799                 hw->fc.pause_time = 0x0650;
 800                 hw->fc.refresh_time = 0x0400;
 801         }
 802
 803         diag = e1000_init_hw(hw);
 804         if (diag < 0)
 805                 return (diag);
 806         e1000_check_for_link(hw);
 807         return (0);
 808 }
 809
 810 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
 811 static void
 812 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 813 {
 814         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 815         struct e1000_hw_stats *stats =
 816                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 817         int pause_frames;
 818
 819         if(hw->phy.media_type == e1000_media_type_copper ||
 820                         (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
 821                 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
 822                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
 823         }
 824
 825         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
 826         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
 827         stats->scc += E1000_READ_REG(hw, E1000_SCC);
 828         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
 829
 830         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
 831         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
 832         stats->colc += E1000_READ_REG(hw, E1000_COLC);
 833         stats->dc += E1000_READ_REG(hw, E1000_DC);
 834         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
 835         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
 836         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
 837
 838         /*
 839          * For watchdog management we need to know if we have been
 840          * paused during the last interval, so capture that here.
 841          */
 842         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
 843         stats->xoffrxc += pause_frames;
 844         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
 845         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
 846         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
 847         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
 848         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
 849         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
 850         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
 851         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
 852         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
 853         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
 854         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
 855         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
 856
 857         /*
 858          * For the 64-bit byte counters the low dword must be read first.
 859          * Both registers clear on the read of the high dword.
 860          */
 861
 862         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
 863         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
 864         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
 865         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
 866
 867         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
 868         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
 869         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
 870         stats->roc += E1000_READ_REG(hw, E1000_ROC);
 871         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
 872
 873         stats->tor += E1000_READ_REG(hw, E1000_TORH);
 874         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
 875
 876         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
 877         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
 878         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
 879         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
 880         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
 881         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
 882         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
 883         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
 884         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
 885         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
 886
 887         /* Interrupt Counts */
 888
 889         if (hw->mac.type >= e1000_82571) {
 890                 stats->iac += E1000_READ_REG(hw, E1000_IAC);
 891                 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
 892                 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
 893                 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
 894                 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
 895                 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
 896                 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
 897                 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
 898                 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
 899         }
 900
 901         if (hw->mac.type >= e1000_82543) {
 902                 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
 903                 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
 904                 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
 905                 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
 906                 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
 907                 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
 908         }
 909
 910         if (rte_stats == NULL)
 911                 return;
 912
 913         /* Rx Errors */
 914         rte_stats->ibadcrc = stats->crcerrs;
 915         rte_stats->ibadlen = stats->rlec + stats->ruc + stats->roc;
 916         rte_stats->imissed = stats->mpc;
 917         rte_stats->ierrors = rte_stats->ibadcrc +
 918                              rte_stats->ibadlen +
 919                              rte_stats->imissed +
 920                              stats->rxerrc + stats->algnerrc + stats->cexterr;
 921
 922         /* Tx Errors */
 923         rte_stats->oerrors = stats->ecol + stats->latecol;
 924
 925         rte_stats->ipackets = stats->gprc;
 926         rte_stats->opackets = stats->gptc;
 927         rte_stats->ibytes   = stats->gorc;
 928         rte_stats->obytes   = stats->gotc;
 929
 930         /* XON/XOFF pause frames stats registers */
 931         rte_stats->tx_pause_xon  = stats->xontxc;
 932         rte_stats->rx_pause_xon  = stats->xonrxc;
 933         rte_stats->tx_pause_xoff = stats->xofftxc;
 934         rte_stats->rx_pause_xoff = stats->xoffrxc;
 935 }
 936
 937 static void
 938 eth_em_stats_reset(struct rte_eth_dev *dev)
 939 {
 940         struct e1000_hw_stats *hw_stats =
 941                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 942
 943         /* HW registers are cleared on read */
 944         eth_em_stats_get(dev, NULL);
 945
 946         /* Reset software totals */
 947         memset(hw_stats, 0, sizeof(*hw_stats));
 948 }
 949
 950 static int
 951 eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
 952 {
 953         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 954
 955         em_rxq_intr_enable(hw);
 956         rte_intr_enable(&dev->pci_dev->intr_handle);
 957
 958         return 0;
 959 }
 960
 961 static int
 962 eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
 963 {
 964         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 965
 966         em_rxq_intr_disable(hw);
 967
 968         return 0;
 969 }
 970
 971 static uint32_t
 972 em_get_max_pktlen(const struct e1000_hw *hw)
 973 {
 974         switch (hw->mac.type) {
 975         case e1000_82571:
 976         case e1000_82572:
 977         case e1000_ich9lan:
 978         case e1000_ich10lan:
 979         case e1000_pch2lan:
 980         case e1000_82574:
 981         case e1000_80003es2lan: /* 9K Jumbo Frame size */
 982         case e1000_82583:
 983                 return (0x2412);
 984         case e1000_pchlan:
 985                 return (0x1000);
 986         /* Adapters that do not support jumbo frames */
 987         case e1000_ich8lan:
 988                 return (ETHER_MAX_LEN);
 989         default:
 990                 return (MAX_JUMBO_FRAME_SIZE);
 991         }
 992 }
 993
 994 static void
 995 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
 996 {
 997         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 998
 999         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1000         dev_info->max_rx_pktlen = em_get_max_pktlen(hw);
1001         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1002
1003         /*
1004          * Starting with 631xESB hw supports 2 TX/RX queues per port.
1005          * Unfortunatelly, all these nics have just one TX context.
1006          * So we have few choises for TX:
1007          * - Use just one TX queue.
1008          * - Allow cksum offload only for one TX queue.
1009          * - Don't allow TX cksum offload at all.
1010          * For now, option #1 was chosen.
1011          * To use second RX queue we have to use extended RX descriptor
1012          * (Multiple Receive Queues are mutually exclusive with UDP
1013          * fragmentation and are not supported when a legacy receive
1014          * descriptor format is used).
1015          * Which means separate RX routinies - as legacy nics (82540, 82545)
1016          * don't support extended RXD.
1017          * To avoid it we support just one RX queue for now (no RSS).
1018          */
1019
1020         dev_info->max_rx_queues = 1;
1021         dev_info->max_tx_queues = 1;
1022
1023         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1024                 .nb_max = E1000_MAX_RING_DESC,
1025                 .nb_min = E1000_MIN_RING_DESC,
1026                 .nb_align = EM_RXD_ALIGN,
1027         };
1028
1029         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1030                 .nb_max = E1000_MAX_RING_DESC,
1031                 .nb_min = E1000_MIN_RING_DESC,
1032                 .nb_align = EM_TXD_ALIGN,
1033         };
1034 }
1035
1036 /* return 0 means link status changed, -1 means not changed */
1037 static int
1038 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1039 {
1040         struct e1000_hw *hw =
1041                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1042         struct rte_eth_link link, old;
1043         int link_check, count;
1044
1045         link_check = 0;
1046         hw->mac.get_link_status = 1;
1047
1048         /* possible wait-to-complete in up to 9 seconds */
1049         for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1050                 /* Read the real link status */
1051                 switch (hw->phy.media_type) {
1052                 case e1000_media_type_copper:
1053                         /* Do the work to read phy */
1054                         e1000_check_for_link(hw);
1055                         link_check = !hw->mac.get_link_status;
1056                         break;
1057
1058                 case e1000_media_type_fiber:
1059                         e1000_check_for_link(hw);
1060                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1061                                         E1000_STATUS_LU);
1062                         break;
1063
1064                 case e1000_media_type_internal_serdes:
1065                         e1000_check_for_link(hw);
1066                         link_check = hw->mac.serdes_has_link;
1067                         break;
1068
1069                 default:
1070                         break;
1071                 }
1072                 if (link_check || wait_to_complete == 0)
1073                         break;
1074                 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
1075         }
1076         memset(&link, 0, sizeof(link));
1077         rte_em_dev_atomic_read_link_status(dev, &link);
1078         old = link;
1079
1080         /* Now we check if a transition has happened */
1081         if (link_check && (link.link_status == 0)) {
1082                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1083                         &link.link_duplex);
1084                 link.link_status = 1;
1085         } else if (!link_check && (link.link_status == 1)) {
1086                 link.link_speed = 0;
1087                 link.link_duplex = 0;
1088                 link.link_status = 0;
1089         }
1090         rte_em_dev_atomic_write_link_status(dev, &link);
1091
1092         /* not changed */
1093         if (old.link_status == link.link_status)
1094                 return -1;
1095
1096         /* changed */
1097         return 0;
1098 }
1099
1100 /*
1101  * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
1102  * For ASF and Pass Through versions of f/w this means
1103  * that the driver is loaded. For AMT version type f/w
1104  * this means that the network i/f is open.
1105  */
1106 static void
1107 em_hw_control_acquire(struct e1000_hw *hw)
1108 {
1109         uint32_t ctrl_ext, swsm;
1110
1111         /* Let firmware know the driver has taken over */
1112         if (hw->mac.type == e1000_82573) {
1113                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1114                 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
1115
1116         } else {
1117                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1118                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1119                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1120         }
1121 }
1122
1123 /*
1124  * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
1125  * For ASF and Pass Through versions of f/w this means that the
1126  * driver is no longer loaded. For AMT versions of the
1127  * f/w this means that the network i/f is closed.
1128  */
1129 static void
1130 em_hw_control_release(struct e1000_hw *hw)
1131 {
1132         uint32_t ctrl_ext, swsm;
1133
1134         /* Let firmware taken over control of h/w */
1135         if (hw->mac.type == e1000_82573) {
1136                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1137                 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
1138         } else {
1139                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1140                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1141                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1142         }
1143 }
1144
1145 /*
1146  * Bit of a misnomer, what this really means is
1147  * to enable OS management of the system... aka
1148  * to disable special hardware management features.
1149  */
1150 static void
1151 em_init_manageability(struct e1000_hw *hw)
1152 {
1153         if (e1000_enable_mng_pass_thru(hw)) {
1154                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1155                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1156
1157                 /* disable hardware interception of ARP */
1158                 manc &= ~(E1000_MANC_ARP_EN);
1159
1160                 /* enable receiving management packets to the host */
1161                 manc |= E1000_MANC_EN_MNG2HOST;
1162                 manc2h |= 1 << 5;  /* Mng Port 623 */
1163                 manc2h |= 1 << 6;  /* Mng Port 664 */
1164                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1165                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1166         }
1167 }
1168
1169 /*
1170  * Give control back to hardware management
1171  * controller if there is one.
1172  */
1173 static void
1174 em_release_manageability(struct e1000_hw *hw)
1175 {
1176         uint32_t manc;
1177
1178         if (e1000_enable_mng_pass_thru(hw)) {
1179                 manc = E1000_READ_REG(hw, E1000_MANC);
1180
1181                 /* re-enable hardware interception of ARP */
1182                 manc |= E1000_MANC_ARP_EN;
1183                 manc &= ~E1000_MANC_EN_MNG2HOST;
1184
1185                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1186         }
1187 }
1188
1189 static void
1190 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1191 {
1192         struct e1000_hw *hw =
1193                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1194         uint32_t rctl;
1195
1196         rctl = E1000_READ_REG(hw, E1000_RCTL);
1197         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1198         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1199 }
1200
1201 static void
1202 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1203 {
1204         struct e1000_hw *hw =
1205                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1206         uint32_t rctl;
1207
1208         rctl = E1000_READ_REG(hw, E1000_RCTL);
1209         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1210         if (dev->data->all_multicast == 1)
1211                 rctl |= E1000_RCTL_MPE;
1212         else
1213                 rctl &= (~E1000_RCTL_MPE);
1214         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1215 }
1216
1217 static void
1218 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1219 {
1220         struct e1000_hw *hw =
1221                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1222         uint32_t rctl;
1223
1224         rctl = E1000_READ_REG(hw, E1000_RCTL);
1225         rctl |= E1000_RCTL_MPE;
1226         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1227 }
1228
1229 static void
1230 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1231 {
1232         struct e1000_hw *hw =
1233                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1234         uint32_t rctl;
1235
1236         if (dev->data->promiscuous == 1)
1237                 return; /* must remain in all_multicast mode */
1238         rctl = E1000_READ_REG(hw, E1000_RCTL);
1239         rctl &= (~E1000_RCTL_MPE);
1240         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1241 }
1242
1243 static int
1244 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1245 {
1246         struct e1000_hw *hw =
1247                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1248         struct e1000_vfta * shadow_vfta =
1249                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1250         uint32_t vfta;
1251         uint32_t vid_idx;
1252         uint32_t vid_bit;
1253
1254         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1255                               E1000_VFTA_ENTRY_MASK);
1256         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1257         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1258         if (on)
1259                 vfta |= vid_bit;
1260         else
1261                 vfta &= ~vid_bit;
1262         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1263
1264         /* update local VFTA copy */
1265         shadow_vfta->vfta[vid_idx] = vfta;
1266
1267         return 0;
1268 }
1269
1270 static void
1271 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1272 {
1273         struct e1000_hw *hw =
1274                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1275         uint32_t reg;
1276
1277         /* Filter Table Disable */
1278         reg = E1000_READ_REG(hw, E1000_RCTL);
1279         reg &= ~E1000_RCTL_CFIEN;
1280         reg &= ~E1000_RCTL_VFE;
1281         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1282 }
1283
1284 static void
1285 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1286 {
1287         struct e1000_hw *hw =
1288                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1289         struct e1000_vfta * shadow_vfta =
1290                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1291         uint32_t reg;
1292         int i;
1293
1294         /* Filter Table Enable, CFI not used for packet acceptance */
1295         reg = E1000_READ_REG(hw, E1000_RCTL);
1296         reg &= ~E1000_RCTL_CFIEN;
1297         reg |= E1000_RCTL_VFE;
1298         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1299
1300         /* restore vfta from local copy */
1301         for (i = 0; i < IGB_VFTA_SIZE; i++)
1302                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1303 }
1304
1305 static void
1306 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1307 {
1308         struct e1000_hw *hw =
1309                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1310         uint32_t reg;
1311
1312         /* VLAN Mode Disable */
1313         reg = E1000_READ_REG(hw, E1000_CTRL);
1314         reg &= ~E1000_CTRL_VME;
1315         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1316
1317 }
1318
1319 static void
1320 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1321 {
1322         struct e1000_hw *hw =
1323                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1324         uint32_t reg;
1325
1326         /* VLAN Mode Enable */
1327         reg = E1000_READ_REG(hw, E1000_CTRL);
1328         reg |= E1000_CTRL_VME;
1329         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1330 }
1331
1332 static void
1333 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1334 {
1335         if(mask & ETH_VLAN_STRIP_MASK){
1336                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1337                         em_vlan_hw_strip_enable(dev);
1338                 else
1339                         em_vlan_hw_strip_disable(dev);
1340         }
1341
1342         if(mask & ETH_VLAN_FILTER_MASK){
1343                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1344                         em_vlan_hw_filter_enable(dev);
1345                 else
1346                         em_vlan_hw_filter_disable(dev);
1347         }
1348 }
1349
1350 /*
1351  * It enables the interrupt mask and then enable the interrupt.
1352  *
1353  * @param dev
1354  *  Pointer to struct rte_eth_dev.
1355  *
1356  * @return
1357  *  - On success, zero.
1358  *  - On failure, a negative value.
1359  */
1360 static int
1361 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1362 {
1363         uint32_t regval;
1364         struct e1000_hw *hw =
1365                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1366
1367         /* clear interrupt */
1368         E1000_READ_REG(hw, E1000_ICR);
1369         regval = E1000_READ_REG(hw, E1000_IMS);
1370         E1000_WRITE_REG(hw, E1000_IMS, regval | E1000_ICR_LSC);
1371         return (0);
1372 }
1373
1374 /*
1375  * It clears the interrupt causes and enables the interrupt.
1376  * It will be called once only during nic initialized.
1377  *
1378  * @param dev
1379  *  Pointer to struct rte_eth_dev.
1380  *
1381  * @return
1382  *  - On success, zero.
1383  *  - On failure, a negative value.
1384  */
1385 static int
1386 eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev)
1387 {
1388         struct e1000_hw *hw =
1389         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1390
1391         E1000_READ_REG(hw, E1000_ICR);
1392         em_rxq_intr_enable(hw);
1393         return 0;
1394 }
1395
1396 /*
1397  * It enable receive packet interrupt.
1398  * @param hw
1399  * Pointer to struct e1000_hw
1400  *
1401  * @return
1402  */
1403 static void
1404 em_rxq_intr_enable(struct e1000_hw *hw)
1405 {
1406         E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_RXT0);
1407         E1000_WRITE_FLUSH(hw);
1408 }
1409
1410 /*
1411  * It disabled lsc interrupt.
1412  * @param hw
1413  * Pointer to struct e1000_hw
1414  *
1415  * @return
1416  */
1417 static void
1418 em_lsc_intr_disable(struct e1000_hw *hw)
1419 {
1420         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_LSC);
1421         E1000_WRITE_FLUSH(hw);
1422 }
1423
1424 /*
1425  * It disabled receive packet interrupt.
1426  * @param hw
1427  * Pointer to struct e1000_hw
1428  *
1429  * @return
1430  */
1431 static void
1432 em_rxq_intr_disable(struct e1000_hw *hw)
1433 {
1434         E1000_READ_REG(hw, E1000_ICR);
1435         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0);
1436         E1000_WRITE_FLUSH(hw);
1437 }
1438
1439 /*
1440  * It reads ICR and gets interrupt causes, check it and set a bit flag
1441  * to update link status.
1442  *
1443  * @param dev
1444  *  Pointer to struct rte_eth_dev.
1445  *
1446  * @return
1447  *  - On success, zero.
1448  *  - On failure, a negative value.
1449  */
1450 static int
1451 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1452 {
1453         uint32_t icr;
1454         struct e1000_hw *hw =
1455                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1456         struct e1000_interrupt *intr =
1457                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1458
1459         /* read-on-clear nic registers here */
1460         icr = E1000_READ_REG(hw, E1000_ICR);
1461         if (icr & E1000_ICR_LSC) {
1462                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1463         }
1464
1465         return 0;
1466 }
1467
1468 /*
1469  * It executes link_update after knowing an interrupt is prsent.
1470  *
1471  * @param dev
1472  *  Pointer to struct rte_eth_dev.
1473  *
1474  * @return
1475  *  - On success, zero.
1476  *  - On failure, a negative value.
1477  */
1478 static int
1479 eth_em_interrupt_action(struct rte_eth_dev *dev)
1480 {
1481         struct e1000_hw *hw =
1482                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1483         struct e1000_interrupt *intr =
1484                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1485         uint32_t tctl, rctl;
1486         struct rte_eth_link link;
1487         int ret;
1488
1489         if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1490                 return -1;
1491
1492         intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1493         rte_intr_enable(&(dev->pci_dev->intr_handle));
1494
1495         /* set get_link_status to check register later */
1496         hw->mac.get_link_status = 1;
1497         ret = eth_em_link_update(dev, 0);
1498
1499         /* check if link has changed */
1500         if (ret < 0)
1501                 return 0;
1502
1503         memset(&link, 0, sizeof(link));
1504         rte_em_dev_atomic_read_link_status(dev, &link);
1505         if (link.link_status) {
1506                 PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s",
1507                              dev->data->port_id, (unsigned)link.link_speed,
1508                              link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1509                              "full-duplex" : "half-duplex");
1510         } else {
1511                 PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
1512         }
1513         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
1514                      dev->pci_dev->addr.domain, dev->pci_dev->addr.bus,
1515                      dev->pci_dev->addr.devid, dev->pci_dev->addr.function);
1516
1517         tctl = E1000_READ_REG(hw, E1000_TCTL);
1518         rctl = E1000_READ_REG(hw, E1000_RCTL);
1519         if (link.link_status) {
1520                 /* enable Tx/Rx */
1521                 tctl |= E1000_TCTL_EN;
1522                 rctl |= E1000_RCTL_EN;
1523         } else {
1524                 /* disable Tx/Rx */
1525                 tctl &= ~E1000_TCTL_EN;
1526                 rctl &= ~E1000_RCTL_EN;
1527         }
1528         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1529         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1530         E1000_WRITE_FLUSH(hw);
1531
1532         return 0;
1533 }
1534
1535 /**
1536  * Interrupt handler which shall be registered at first.
1537  *
1538  * @param handle
1539  *  Pointer to interrupt handle.
1540  * @param param
1541  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1542  *
1543  * @return
1544  *  void
1545  */
1546 static void
1547 eth_em_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1548                                                         void *param)
1549 {
1550         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1551
1552         eth_em_interrupt_get_status(dev);
1553         eth_em_interrupt_action(dev);
1554         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1555 }
1556
1557 static int
1558 eth_em_led_on(struct rte_eth_dev *dev)
1559 {
1560         struct e1000_hw *hw;
1561
1562         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1563         return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1564 }
1565
1566 static int
1567 eth_em_led_off(struct rte_eth_dev *dev)
1568 {
1569         struct e1000_hw *hw;
1570
1571         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1572         return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1573 }
1574
1575 static int
1576 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1577 {
1578         struct e1000_hw *hw;
1579         uint32_t ctrl;
1580         int tx_pause;
1581         int rx_pause;
1582
1583         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1584         fc_conf->pause_time = hw->fc.pause_time;
1585         fc_conf->high_water = hw->fc.high_water;
1586         fc_conf->low_water = hw->fc.low_water;
1587         fc_conf->send_xon = hw->fc.send_xon;
1588         fc_conf->autoneg = hw->mac.autoneg;
1589
1590         /*
1591          * Return rx_pause and tx_pause status according to actual setting of
1592          * the TFCE and RFCE bits in the CTRL register.
1593          */
1594         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1595         if (ctrl & E1000_CTRL_TFCE)
1596                 tx_pause = 1;
1597         else
1598                 tx_pause = 0;
1599
1600         if (ctrl & E1000_CTRL_RFCE)
1601                 rx_pause = 1;
1602         else
1603                 rx_pause = 0;
1604
1605         if (rx_pause && tx_pause)
1606                 fc_conf->mode = RTE_FC_FULL;
1607         else if (rx_pause)
1608                 fc_conf->mode = RTE_FC_RX_PAUSE;
1609         else if (tx_pause)
1610                 fc_conf->mode = RTE_FC_TX_PAUSE;
1611         else
1612                 fc_conf->mode = RTE_FC_NONE;
1613
1614         return 0;
1615 }
1616
1617 static int
1618 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1619 {
1620         struct e1000_hw *hw;
1621         int err;
1622         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1623                 e1000_fc_none,
1624                 e1000_fc_rx_pause,
1625                 e1000_fc_tx_pause,
1626                 e1000_fc_full
1627         };
1628         uint32_t rx_buf_size;
1629         uint32_t max_high_water;
1630         uint32_t rctl;
1631
1632         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1633         if (fc_conf->autoneg != hw->mac.autoneg)
1634                 return -ENOTSUP;
1635         rx_buf_size = em_get_rx_buffer_size(hw);
1636         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1637
1638         /* At least reserve one Ethernet frame for watermark */
1639         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1640         if ((fc_conf->high_water > max_high_water) ||
1641             (fc_conf->high_water < fc_conf->low_water)) {
1642                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1643                 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
1644                 return (-EINVAL);
1645         }
1646
1647         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1648         hw->fc.pause_time     = fc_conf->pause_time;
1649         hw->fc.high_water     = fc_conf->high_water;
1650         hw->fc.low_water      = fc_conf->low_water;
1651         hw->fc.send_xon       = fc_conf->send_xon;
1652
1653         err = e1000_setup_link_generic(hw);
1654         if (err == E1000_SUCCESS) {
1655
1656                 /* check if we want to forward MAC frames - driver doesn't have native
1657                  * capability to do that, so we'll write the registers ourselves */
1658
1659                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1660
1661                 /* set or clear MFLCN.PMCF bit depending on configuration */
1662                 if (fc_conf->mac_ctrl_frame_fwd != 0)
1663                         rctl |= E1000_RCTL_PMCF;
1664                 else
1665                         rctl &= ~E1000_RCTL_PMCF;
1666
1667                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1668                 E1000_WRITE_FLUSH(hw);
1669
1670                 return 0;
1671         }
1672
1673         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1674         return (-EIO);
1675 }
1676
1677 static void
1678 eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1679                 uint32_t index, __rte_unused uint32_t pool)
1680 {
1681         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1682
1683         e1000_rar_set(hw, mac_addr->addr_bytes, index);
1684 }
1685
1686 static void
1687 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1688 {
1689         uint8_t addr[ETHER_ADDR_LEN];
1690         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1691
1692         memset(addr, 0, sizeof(addr));
1693
1694         e1000_rar_set(hw, addr, index);
1695 }
1696
1697 static int
1698 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1699 {
1700         struct rte_eth_dev_info dev_info;
1701         struct e1000_hw *hw;
1702         uint32_t frame_size;
1703         uint32_t rctl;
1704
1705         eth_em_infos_get(dev, &dev_info);
1706         frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE;
1707
1708         /* check that mtu is within the allowed range */
1709         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1710                 return -EINVAL;
1711
1712         /* refuse mtu that requires the support of scattered packets when this
1713          * feature has not been enabled before. */
1714         if (!dev->data->scattered_rx &&
1715             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1716                 return -EINVAL;
1717
1718         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1719         rctl = E1000_READ_REG(hw, E1000_RCTL);
1720
1721         /* switch to jumbo mode if needed */
1722         if (frame_size > ETHER_MAX_LEN) {
1723                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1724                 rctl |= E1000_RCTL_LPE;
1725         } else {
1726                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1727                 rctl &= ~E1000_RCTL_LPE;
1728         }
1729         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1730
1731         /* update max frame size */
1732         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1733         return 0;
1734 }
1735
1736 static int
1737 eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
1738                         struct ether_addr *mc_addr_set,
1739                         uint32_t nb_mc_addr)
1740 {
1741         struct e1000_hw *hw;
1742
1743         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1744         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
1745         return 0;
1746 }
1747
1748 struct rte_driver em_pmd_drv = {
1749         .type = PMD_PDEV,
1750         .init = rte_em_pmd_init,
1751 };
1752
1753 PMD_REGISTER_DRIVER(em_pmd_drv);