4 * Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
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13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
40 #include <rte_common.h>
41 #include <rte_interrupts.h>
42 #include <rte_byteorder.h>
44 #include <rte_debug.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memory.h>
49 #include <rte_memzone.h>
51 #include <rte_atomic.h>
52 #include <rte_malloc.h>
55 #include "e1000_logs.h"
56 #include "base/e1000_api.h"
57 #include "e1000_ethdev.h"
59 #define EM_EIAC 0x000DC
61 #define PMD_ROUNDUP(x,y) (((x) + (y) - 1)/(y) * (y))
64 static int eth_em_configure(struct rte_eth_dev *dev);
65 static int eth_em_start(struct rte_eth_dev *dev);
66 static void eth_em_stop(struct rte_eth_dev *dev);
67 static void eth_em_close(struct rte_eth_dev *dev);
68 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
69 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
70 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
71 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
72 static int eth_em_link_update(struct rte_eth_dev *dev,
73 int wait_to_complete);
74 static void eth_em_stats_get(struct rte_eth_dev *dev,
75 struct rte_eth_stats *rte_stats);
76 static void eth_em_stats_reset(struct rte_eth_dev *dev);
77 static void eth_em_infos_get(struct rte_eth_dev *dev,
78 struct rte_eth_dev_info *dev_info);
79 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
80 struct rte_eth_fc_conf *fc_conf);
81 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
82 struct rte_eth_fc_conf *fc_conf);
83 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
84 static int eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev);
85 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
86 static int eth_em_interrupt_action(struct rte_eth_dev *dev,
87 struct rte_intr_handle *handle);
88 static void eth_em_interrupt_handler(struct rte_intr_handle *handle,
91 static int em_hw_init(struct e1000_hw *hw);
92 static int em_hardware_init(struct e1000_hw *hw);
93 static void em_hw_control_acquire(struct e1000_hw *hw);
94 static void em_hw_control_release(struct e1000_hw *hw);
95 static void em_init_manageability(struct e1000_hw *hw);
96 static void em_release_manageability(struct e1000_hw *hw);
98 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
100 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
101 uint16_t vlan_id, int on);
102 static void eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
103 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
104 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
105 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
106 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
109 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
110 uint16_t vlan_id, int on);
113 static int eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
114 static int eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
115 static void em_lsc_intr_disable(struct e1000_hw *hw);
116 static void em_rxq_intr_enable(struct e1000_hw *hw);
117 static void em_rxq_intr_disable(struct e1000_hw *hw);
119 static int eth_em_led_on(struct rte_eth_dev *dev);
120 static int eth_em_led_off(struct rte_eth_dev *dev);
122 static int em_get_rx_buffer_size(struct e1000_hw *hw);
123 static void eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
124 uint32_t index, uint32_t pool);
125 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
127 static int eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
128 struct ether_addr *mc_addr_set,
129 uint32_t nb_mc_addr);
131 #define EM_FC_PAUSE_TIME 0x0680
132 #define EM_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
133 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
135 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
138 * The set of PCI devices this driver supports
140 static const struct rte_pci_id pci_id_em_map[] = {
141 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82540EM) },
142 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_COPPER) },
143 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_FIBER) },
144 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_COPPER) },
145 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_FIBER) },
146 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_QUAD_COPPER) },
147 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_COPPER) },
148 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_FIBER) },
149 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES) },
150 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_DUAL) },
151 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_QUAD) },
152 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER) },
153 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571PT_QUAD_COPPER) },
154 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_FIBER) },
155 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER_LP) },
156 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_COPPER) },
157 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_FIBER) },
158 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_SERDES) },
159 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI) },
160 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82573L) },
161 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574L) },
162 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574LA) },
163 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82583V) },
164 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_LM) },
165 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_V) },
166 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_LM) },
167 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_V) },
168 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM2) },
169 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V2) },
170 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM3) },
171 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V3) },
172 { .vendor_id = 0, /* sentinel */ },
175 static const struct eth_dev_ops eth_em_ops = {
176 .dev_configure = eth_em_configure,
177 .dev_start = eth_em_start,
178 .dev_stop = eth_em_stop,
179 .dev_close = eth_em_close,
180 .promiscuous_enable = eth_em_promiscuous_enable,
181 .promiscuous_disable = eth_em_promiscuous_disable,
182 .allmulticast_enable = eth_em_allmulticast_enable,
183 .allmulticast_disable = eth_em_allmulticast_disable,
184 .link_update = eth_em_link_update,
185 .stats_get = eth_em_stats_get,
186 .stats_reset = eth_em_stats_reset,
187 .dev_infos_get = eth_em_infos_get,
188 .mtu_set = eth_em_mtu_set,
189 .vlan_filter_set = eth_em_vlan_filter_set,
190 .vlan_offload_set = eth_em_vlan_offload_set,
191 .rx_queue_setup = eth_em_rx_queue_setup,
192 .rx_queue_release = eth_em_rx_queue_release,
193 .rx_queue_count = eth_em_rx_queue_count,
194 .rx_descriptor_done = eth_em_rx_descriptor_done,
195 .tx_queue_setup = eth_em_tx_queue_setup,
196 .tx_queue_release = eth_em_tx_queue_release,
197 .rx_queue_intr_enable = eth_em_rx_queue_intr_enable,
198 .rx_queue_intr_disable = eth_em_rx_queue_intr_disable,
199 .dev_led_on = eth_em_led_on,
200 .dev_led_off = eth_em_led_off,
201 .flow_ctrl_get = eth_em_flow_ctrl_get,
202 .flow_ctrl_set = eth_em_flow_ctrl_set,
203 .mac_addr_add = eth_em_rar_set,
204 .mac_addr_remove = eth_em_rar_clear,
205 .set_mc_addr_list = eth_em_set_mc_addr_list,
206 .rxq_info_get = em_rxq_info_get,
207 .txq_info_get = em_txq_info_get,
211 * Atomically reads the link status information from global
212 * structure rte_eth_dev.
215 * - Pointer to the structure rte_eth_dev to read from.
216 * - Pointer to the buffer to be saved with the link status.
219 * - On success, zero.
220 * - On failure, negative value.
223 rte_em_dev_atomic_read_link_status(struct rte_eth_dev *dev,
224 struct rte_eth_link *link)
226 struct rte_eth_link *dst = link;
227 struct rte_eth_link *src = &(dev->data->dev_link);
229 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
230 *(uint64_t *)src) == 0)
237 * Atomically writes the link status information into global
238 * structure rte_eth_dev.
241 * - Pointer to the structure rte_eth_dev to read from.
242 * - Pointer to the buffer to be saved with the link status.
245 * - On success, zero.
246 * - On failure, negative value.
249 rte_em_dev_atomic_write_link_status(struct rte_eth_dev *dev,
250 struct rte_eth_link *link)
252 struct rte_eth_link *dst = &(dev->data->dev_link);
253 struct rte_eth_link *src = link;
255 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
256 *(uint64_t *)src) == 0)
263 * eth_em_dev_is_ich8 - Check for ICH8 device
264 * @hw: pointer to the HW structure
266 * return TRUE for ICH8, otherwise FALSE
269 eth_em_dev_is_ich8(struct e1000_hw *hw)
271 DEBUGFUNC("eth_em_dev_is_ich8");
273 switch (hw->device_id) {
274 case E1000_DEV_ID_PCH_LPT_I217_LM:
275 case E1000_DEV_ID_PCH_LPT_I217_V:
276 case E1000_DEV_ID_PCH_LPTLP_I218_LM:
277 case E1000_DEV_ID_PCH_LPTLP_I218_V:
278 case E1000_DEV_ID_PCH_I218_V2:
279 case E1000_DEV_ID_PCH_I218_LM2:
280 case E1000_DEV_ID_PCH_I218_V3:
281 case E1000_DEV_ID_PCH_I218_LM3:
289 eth_em_dev_init(struct rte_eth_dev *eth_dev)
291 struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(eth_dev);
292 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
293 struct e1000_adapter *adapter =
294 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
295 struct e1000_hw *hw =
296 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
297 struct e1000_vfta * shadow_vfta =
298 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
300 eth_dev->dev_ops = ð_em_ops;
301 eth_dev->rx_pkt_burst = (eth_rx_burst_t)ð_em_recv_pkts;
302 eth_dev->tx_pkt_burst = (eth_tx_burst_t)ð_em_xmit_pkts;
303 eth_dev->tx_pkt_prepare = (eth_tx_prep_t)ð_em_prep_pkts;
305 /* for secondary processes, we don't initialise any further as primary
306 * has already done this work. Only check we don't need a different
308 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
309 if (eth_dev->data->scattered_rx)
310 eth_dev->rx_pkt_burst =
311 (eth_rx_burst_t)ð_em_recv_scattered_pkts;
315 rte_eth_copy_pci_info(eth_dev, pci_dev);
317 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
318 hw->device_id = pci_dev->id.device_id;
319 adapter->stopped = 0;
321 /* For ICH8 support we'll need to map the flash memory BAR */
322 if (eth_em_dev_is_ich8(hw))
323 hw->flash_address = (void *)pci_dev->mem_resource[1].addr;
325 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
326 em_hw_init(hw) != 0) {
327 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
329 eth_dev->data->port_id, pci_dev->id.vendor_id,
330 pci_dev->id.device_id);
334 /* Allocate memory for storing MAC addresses */
335 eth_dev->data->mac_addrs = rte_zmalloc("e1000", ETHER_ADDR_LEN *
336 hw->mac.rar_entry_count, 0);
337 if (eth_dev->data->mac_addrs == NULL) {
338 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
339 "store MAC addresses",
340 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
344 /* Copy the permanent MAC address */
345 ether_addr_copy((struct ether_addr *) hw->mac.addr,
346 eth_dev->data->mac_addrs);
348 /* initialize the vfta */
349 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
351 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
352 eth_dev->data->port_id, pci_dev->id.vendor_id,
353 pci_dev->id.device_id);
355 rte_intr_callback_register(intr_handle,
356 eth_em_interrupt_handler, eth_dev);
362 eth_em_dev_uninit(struct rte_eth_dev *eth_dev)
364 struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(eth_dev);
365 struct e1000_adapter *adapter =
366 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
367 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
369 PMD_INIT_FUNC_TRACE();
371 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
374 if (adapter->stopped == 0)
375 eth_em_close(eth_dev);
377 eth_dev->dev_ops = NULL;
378 eth_dev->rx_pkt_burst = NULL;
379 eth_dev->tx_pkt_burst = NULL;
381 rte_free(eth_dev->data->mac_addrs);
382 eth_dev->data->mac_addrs = NULL;
384 /* disable uio intr before callback unregister */
385 rte_intr_disable(intr_handle);
386 rte_intr_callback_unregister(intr_handle,
387 eth_em_interrupt_handler, eth_dev);
392 static struct eth_driver rte_em_pmd = {
394 .id_table = pci_id_em_map,
395 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
396 RTE_PCI_DRV_DETACHABLE,
397 .probe = rte_eth_dev_pci_probe,
398 .remove = rte_eth_dev_pci_remove,
400 .eth_dev_init = eth_em_dev_init,
401 .eth_dev_uninit = eth_em_dev_uninit,
402 .dev_private_size = sizeof(struct e1000_adapter),
406 em_hw_init(struct e1000_hw *hw)
410 diag = hw->mac.ops.init_params(hw);
412 PMD_INIT_LOG(ERR, "MAC Initialization Error");
415 diag = hw->nvm.ops.init_params(hw);
417 PMD_INIT_LOG(ERR, "NVM Initialization Error");
420 diag = hw->phy.ops.init_params(hw);
422 PMD_INIT_LOG(ERR, "PHY Initialization Error");
425 (void) e1000_get_bus_info(hw);
428 hw->phy.autoneg_wait_to_complete = 0;
429 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
431 e1000_init_script_state_82541(hw, TRUE);
432 e1000_set_tbi_compatibility_82543(hw, TRUE);
435 if (hw->phy.media_type == e1000_media_type_copper) {
436 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
437 hw->phy.disable_polarity_correction = 0;
438 hw->phy.ms_type = e1000_ms_hw_default;
442 * Start from a known state, this is important in reading the nvm
447 /* Make sure we have a good EEPROM before we read from it */
448 if (e1000_validate_nvm_checksum(hw) < 0) {
450 * Some PCI-E parts fail the first check due to
451 * the link being in sleep state, call it again,
452 * if it fails a second time its a real issue.
454 diag = e1000_validate_nvm_checksum(hw);
456 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
461 /* Read the permanent MAC address out of the EEPROM */
462 diag = e1000_read_mac_addr(hw);
464 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
468 /* Now initialize the hardware */
469 diag = em_hardware_init(hw);
471 PMD_INIT_LOG(ERR, "Hardware initialization failed");
475 hw->mac.get_link_status = 1;
477 /* Indicate SOL/IDER usage */
478 diag = e1000_check_reset_block(hw);
480 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
486 em_hw_control_release(hw);
491 eth_em_configure(struct rte_eth_dev *dev)
493 struct e1000_interrupt *intr =
494 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
496 PMD_INIT_FUNC_TRACE();
497 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
498 PMD_INIT_FUNC_TRACE();
504 em_set_pba(struct e1000_hw *hw)
509 * Packet Buffer Allocation (PBA)
510 * Writing PBA sets the receive portion of the buffer
511 * the remainder is used for the transmit buffer.
512 * Devices before the 82547 had a Packet Buffer of 64K.
513 * After the 82547 the buffer was reduced to 40K.
515 switch (hw->mac.type) {
517 case e1000_82547_rev_2:
518 /* 82547: Total Packet Buffer is 40K */
519 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
523 case e1000_80003es2lan:
524 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
526 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
527 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
531 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
546 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
549 E1000_WRITE_REG(hw, E1000_PBA, pba);
553 eth_em_start(struct rte_eth_dev *dev)
555 struct e1000_adapter *adapter =
556 E1000_DEV_PRIVATE(dev->data->dev_private);
557 struct e1000_hw *hw =
558 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
559 struct rte_pci_device *pci_dev =
560 E1000_DEV_TO_PCI(dev);
561 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
563 uint32_t intr_vector = 0;
568 PMD_INIT_FUNC_TRACE();
572 e1000_power_up_phy(hw);
574 /* Set default PBA value */
577 /* Put the address into the Receive Address Array */
578 e1000_rar_set(hw, hw->mac.addr, 0);
581 * With the 82571 adapter, RAR[0] may be overwritten
582 * when the other port is reset, we make a duplicate
583 * in RAR[14] for that eventuality, this assures
584 * the interface continues to function.
586 if (hw->mac.type == e1000_82571) {
587 e1000_set_laa_state_82571(hw, TRUE);
588 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
591 /* Initialize the hardware */
592 if (em_hardware_init(hw)) {
593 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
597 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
599 /* Configure for OS presence */
600 em_init_manageability(hw);
602 if (dev->data->dev_conf.intr_conf.rxq != 0) {
603 intr_vector = dev->data->nb_rx_queues;
604 if (rte_intr_efd_enable(intr_handle, intr_vector))
608 if (rte_intr_dp_is_en(intr_handle)) {
609 intr_handle->intr_vec =
610 rte_zmalloc("intr_vec",
611 dev->data->nb_rx_queues * sizeof(int), 0);
612 if (intr_handle->intr_vec == NULL) {
613 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
614 " intr_vec\n", dev->data->nb_rx_queues);
618 /* enable rx interrupt */
619 em_rxq_intr_enable(hw);
624 ret = eth_em_rx_init(dev);
626 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
627 em_dev_clear_queues(dev);
631 e1000_clear_hw_cntrs_base_generic(hw);
633 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
634 ETH_VLAN_EXTEND_MASK;
635 eth_em_vlan_offload_set(dev, mask);
637 /* Set Interrupt Throttling Rate to maximum allowed value. */
638 E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
640 /* Setup link speed and duplex */
641 speeds = &dev->data->dev_conf.link_speeds;
642 if (*speeds == ETH_LINK_SPEED_AUTONEG) {
643 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
647 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
650 hw->phy.autoneg_advertised = 0;
652 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
653 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
654 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
656 goto error_invalid_config;
658 if (*speeds & ETH_LINK_SPEED_10M_HD) {
659 hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
662 if (*speeds & ETH_LINK_SPEED_10M) {
663 hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
666 if (*speeds & ETH_LINK_SPEED_100M_HD) {
667 hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
670 if (*speeds & ETH_LINK_SPEED_100M) {
671 hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
674 if (*speeds & ETH_LINK_SPEED_1G) {
675 hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
678 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
679 goto error_invalid_config;
681 /* Set/reset the mac.autoneg based on the link speed,
686 hw->mac.forced_speed_duplex =
687 hw->phy.autoneg_advertised;
693 e1000_setup_link(hw);
695 if (rte_intr_allow_others(intr_handle)) {
696 /* check if lsc interrupt is enabled */
697 if (dev->data->dev_conf.intr_conf.lsc != 0) {
698 ret = eth_em_interrupt_setup(dev);
700 PMD_INIT_LOG(ERR, "Unable to setup interrupts");
701 em_dev_clear_queues(dev);
706 rte_intr_callback_unregister(intr_handle,
707 eth_em_interrupt_handler,
709 if (dev->data->dev_conf.intr_conf.lsc != 0)
710 PMD_INIT_LOG(INFO, "lsc won't enable because of"
711 " no intr multiplex\n");
713 /* check if rxq interrupt is enabled */
714 if (dev->data->dev_conf.intr_conf.rxq != 0)
715 eth_em_rxq_interrupt_setup(dev);
717 rte_intr_enable(intr_handle);
719 adapter->stopped = 0;
721 PMD_INIT_LOG(DEBUG, "<<");
725 error_invalid_config:
726 PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
727 dev->data->dev_conf.link_speeds, dev->data->port_id);
728 em_dev_clear_queues(dev);
732 /*********************************************************************
734 * This routine disables all traffic on the adapter by issuing a
735 * global reset on the MAC.
737 **********************************************************************/
739 eth_em_stop(struct rte_eth_dev *dev)
741 struct rte_eth_link link;
742 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
743 struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
744 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
746 em_rxq_intr_disable(hw);
747 em_lsc_intr_disable(hw);
750 if (hw->mac.type >= e1000_82544)
751 E1000_WRITE_REG(hw, E1000_WUC, 0);
753 /* Power down the phy. Needed to make the link go down */
754 e1000_power_down_phy(hw);
756 em_dev_clear_queues(dev);
758 /* clear the recorded link status */
759 memset(&link, 0, sizeof(link));
760 rte_em_dev_atomic_write_link_status(dev, &link);
762 if (!rte_intr_allow_others(intr_handle))
763 /* resume to the default handler */
764 rte_intr_callback_register(intr_handle,
765 eth_em_interrupt_handler,
768 /* Clean datapath event and queue/vec mapping */
769 rte_intr_efd_disable(intr_handle);
770 if (intr_handle->intr_vec != NULL) {
771 rte_free(intr_handle->intr_vec);
772 intr_handle->intr_vec = NULL;
777 eth_em_close(struct rte_eth_dev *dev)
779 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
780 struct e1000_adapter *adapter =
781 E1000_DEV_PRIVATE(dev->data->dev_private);
784 adapter->stopped = 1;
785 em_dev_free_queues(dev);
786 e1000_phy_hw_reset(hw);
787 em_release_manageability(hw);
788 em_hw_control_release(hw);
792 em_get_rx_buffer_size(struct e1000_hw *hw)
794 uint32_t rx_buf_size;
796 rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
800 /*********************************************************************
802 * Initialize the hardware
804 **********************************************************************/
806 em_hardware_init(struct e1000_hw *hw)
808 uint32_t rx_buf_size;
811 /* Issue a global reset */
814 /* Let the firmware know the OS is in control */
815 em_hw_control_acquire(hw);
818 * These parameters control the automatic generation (Tx) and
819 * response (Rx) to Ethernet PAUSE frames.
820 * - High water mark should allow for at least two standard size (1518)
821 * frames to be received after sending an XOFF.
822 * - Low water mark works best when it is very near the high water mark.
823 * This allows the receiver to restart by sending XON when it has
824 * drained a bit. Here we use an arbitrary value of 1500 which will
825 * restart after one full frame is pulled from the buffer. There
826 * could be several smaller frames in the buffer and if so they will
827 * not trigger the XON until their total number reduces the buffer
829 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
831 rx_buf_size = em_get_rx_buffer_size(hw);
833 hw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);
834 hw->fc.low_water = hw->fc.high_water - 1500;
836 if (hw->mac.type == e1000_80003es2lan)
837 hw->fc.pause_time = UINT16_MAX;
839 hw->fc.pause_time = EM_FC_PAUSE_TIME;
843 /* Set Flow control, use the tunable location if sane */
844 if (em_fc_setting <= e1000_fc_full)
845 hw->fc.requested_mode = em_fc_setting;
847 hw->fc.requested_mode = e1000_fc_none;
849 /* Workaround: no TX flow ctrl for PCH */
850 if (hw->mac.type == e1000_pchlan)
851 hw->fc.requested_mode = e1000_fc_rx_pause;
853 /* Override - settings for PCH2LAN, ya its magic :) */
854 if (hw->mac.type == e1000_pch2lan) {
855 hw->fc.high_water = 0x5C20;
856 hw->fc.low_water = 0x5048;
857 hw->fc.pause_time = 0x0650;
858 hw->fc.refresh_time = 0x0400;
859 } else if (hw->mac.type == e1000_pch_lpt) {
860 hw->fc.requested_mode = e1000_fc_full;
863 diag = e1000_init_hw(hw);
866 e1000_check_for_link(hw);
870 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
872 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
874 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
875 struct e1000_hw_stats *stats =
876 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
879 if(hw->phy.media_type == e1000_media_type_copper ||
880 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
881 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
882 stats->sec += E1000_READ_REG(hw, E1000_SEC);
885 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
886 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
887 stats->scc += E1000_READ_REG(hw, E1000_SCC);
888 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
890 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
891 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
892 stats->colc += E1000_READ_REG(hw, E1000_COLC);
893 stats->dc += E1000_READ_REG(hw, E1000_DC);
894 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
895 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
896 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
899 * For watchdog management we need to know if we have been
900 * paused during the last interval, so capture that here.
902 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
903 stats->xoffrxc += pause_frames;
904 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
905 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
906 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
907 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
908 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
909 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
910 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
911 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
912 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
913 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
914 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
915 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
918 * For the 64-bit byte counters the low dword must be read first.
919 * Both registers clear on the read of the high dword.
922 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
923 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
924 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
925 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
927 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
928 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
929 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
930 stats->roc += E1000_READ_REG(hw, E1000_ROC);
931 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
933 stats->tor += E1000_READ_REG(hw, E1000_TORH);
934 stats->tot += E1000_READ_REG(hw, E1000_TOTH);
936 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
937 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
938 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
939 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
940 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
941 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
942 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
943 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
944 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
945 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
947 /* Interrupt Counts */
949 if (hw->mac.type >= e1000_82571) {
950 stats->iac += E1000_READ_REG(hw, E1000_IAC);
951 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
952 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
953 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
954 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
955 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
956 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
957 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
958 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
961 if (hw->mac.type >= e1000_82543) {
962 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
963 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
964 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
965 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
966 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
967 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
970 if (rte_stats == NULL)
974 rte_stats->imissed = stats->mpc;
975 rte_stats->ierrors = stats->crcerrs +
976 stats->rlec + stats->ruc + stats->roc +
977 stats->rxerrc + stats->algnerrc + stats->cexterr;
980 rte_stats->oerrors = stats->ecol + stats->latecol;
982 rte_stats->ipackets = stats->gprc;
983 rte_stats->opackets = stats->gptc;
984 rte_stats->ibytes = stats->gorc;
985 rte_stats->obytes = stats->gotc;
989 eth_em_stats_reset(struct rte_eth_dev *dev)
991 struct e1000_hw_stats *hw_stats =
992 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
994 /* HW registers are cleared on read */
995 eth_em_stats_get(dev, NULL);
997 /* Reset software totals */
998 memset(hw_stats, 0, sizeof(*hw_stats));
1002 eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1004 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1005 struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
1006 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1008 em_rxq_intr_enable(hw);
1009 rte_intr_enable(intr_handle);
1015 eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1017 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1019 em_rxq_intr_disable(hw);
1025 em_get_max_pktlen(const struct e1000_hw *hw)
1027 switch (hw->mac.type) {
1031 case e1000_ich10lan:
1035 case e1000_80003es2lan: /* 9K Jumbo Frame size */
1040 /* Adapters that do not support jumbo frames */
1042 return ETHER_MAX_LEN;
1044 return MAX_JUMBO_FRAME_SIZE;
1049 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1051 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1053 dev_info->pci_dev = RTE_DEV_TO_PCI(dev->device);
1054 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1055 dev_info->max_rx_pktlen = em_get_max_pktlen(hw);
1056 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1059 * Starting with 631xESB hw supports 2 TX/RX queues per port.
1060 * Unfortunatelly, all these nics have just one TX context.
1061 * So we have few choises for TX:
1062 * - Use just one TX queue.
1063 * - Allow cksum offload only for one TX queue.
1064 * - Don't allow TX cksum offload at all.
1065 * For now, option #1 was chosen.
1066 * To use second RX queue we have to use extended RX descriptor
1067 * (Multiple Receive Queues are mutually exclusive with UDP
1068 * fragmentation and are not supported when a legacy receive
1069 * descriptor format is used).
1070 * Which means separate RX routinies - as legacy nics (82540, 82545)
1071 * don't support extended RXD.
1072 * To avoid it we support just one RX queue for now (no RSS).
1075 dev_info->max_rx_queues = 1;
1076 dev_info->max_tx_queues = 1;
1078 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1079 .nb_max = E1000_MAX_RING_DESC,
1080 .nb_min = E1000_MIN_RING_DESC,
1081 .nb_align = EM_RXD_ALIGN,
1084 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1085 .nb_max = E1000_MAX_RING_DESC,
1086 .nb_min = E1000_MIN_RING_DESC,
1087 .nb_align = EM_TXD_ALIGN,
1088 .nb_seg_max = EM_TX_MAX_SEG,
1089 .nb_mtu_seg_max = EM_TX_MAX_MTU_SEG,
1092 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1093 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1097 /* return 0 means link status changed, -1 means not changed */
1099 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1101 struct e1000_hw *hw =
1102 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1103 struct rte_eth_link link, old;
1104 int link_check, count;
1107 hw->mac.get_link_status = 1;
1109 /* possible wait-to-complete in up to 9 seconds */
1110 for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1111 /* Read the real link status */
1112 switch (hw->phy.media_type) {
1113 case e1000_media_type_copper:
1114 /* Do the work to read phy */
1115 e1000_check_for_link(hw);
1116 link_check = !hw->mac.get_link_status;
1119 case e1000_media_type_fiber:
1120 e1000_check_for_link(hw);
1121 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1125 case e1000_media_type_internal_serdes:
1126 e1000_check_for_link(hw);
1127 link_check = hw->mac.serdes_has_link;
1133 if (link_check || wait_to_complete == 0)
1135 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
1137 memset(&link, 0, sizeof(link));
1138 rte_em_dev_atomic_read_link_status(dev, &link);
1141 /* Now we check if a transition has happened */
1142 if (link_check && (link.link_status == ETH_LINK_DOWN)) {
1143 uint16_t duplex, speed;
1144 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1145 link.link_duplex = (duplex == FULL_DUPLEX) ?
1146 ETH_LINK_FULL_DUPLEX :
1147 ETH_LINK_HALF_DUPLEX;
1148 link.link_speed = speed;
1149 link.link_status = ETH_LINK_UP;
1150 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
1151 ETH_LINK_SPEED_FIXED);
1152 } else if (!link_check && (link.link_status == ETH_LINK_UP)) {
1153 link.link_speed = 0;
1154 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1155 link.link_status = ETH_LINK_DOWN;
1156 link.link_autoneg = ETH_LINK_SPEED_FIXED;
1158 rte_em_dev_atomic_write_link_status(dev, &link);
1161 if (old.link_status == link.link_status)
1169 * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
1170 * For ASF and Pass Through versions of f/w this means
1171 * that the driver is loaded. For AMT version type f/w
1172 * this means that the network i/f is open.
1175 em_hw_control_acquire(struct e1000_hw *hw)
1177 uint32_t ctrl_ext, swsm;
1179 /* Let firmware know the driver has taken over */
1180 if (hw->mac.type == e1000_82573) {
1181 swsm = E1000_READ_REG(hw, E1000_SWSM);
1182 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
1185 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1186 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1187 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1192 * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
1193 * For ASF and Pass Through versions of f/w this means that the
1194 * driver is no longer loaded. For AMT versions of the
1195 * f/w this means that the network i/f is closed.
1198 em_hw_control_release(struct e1000_hw *hw)
1200 uint32_t ctrl_ext, swsm;
1202 /* Let firmware taken over control of h/w */
1203 if (hw->mac.type == e1000_82573) {
1204 swsm = E1000_READ_REG(hw, E1000_SWSM);
1205 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
1207 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1208 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1209 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1214 * Bit of a misnomer, what this really means is
1215 * to enable OS management of the system... aka
1216 * to disable special hardware management features.
1219 em_init_manageability(struct e1000_hw *hw)
1221 if (e1000_enable_mng_pass_thru(hw)) {
1222 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1223 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1225 /* disable hardware interception of ARP */
1226 manc &= ~(E1000_MANC_ARP_EN);
1228 /* enable receiving management packets to the host */
1229 manc |= E1000_MANC_EN_MNG2HOST;
1230 manc2h |= 1 << 5; /* Mng Port 623 */
1231 manc2h |= 1 << 6; /* Mng Port 664 */
1232 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1233 E1000_WRITE_REG(hw, E1000_MANC, manc);
1238 * Give control back to hardware management
1239 * controller if there is one.
1242 em_release_manageability(struct e1000_hw *hw)
1246 if (e1000_enable_mng_pass_thru(hw)) {
1247 manc = E1000_READ_REG(hw, E1000_MANC);
1249 /* re-enable hardware interception of ARP */
1250 manc |= E1000_MANC_ARP_EN;
1251 manc &= ~E1000_MANC_EN_MNG2HOST;
1253 E1000_WRITE_REG(hw, E1000_MANC, manc);
1258 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1260 struct e1000_hw *hw =
1261 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1264 rctl = E1000_READ_REG(hw, E1000_RCTL);
1265 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1266 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1270 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1272 struct e1000_hw *hw =
1273 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1276 rctl = E1000_READ_REG(hw, E1000_RCTL);
1277 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1278 if (dev->data->all_multicast == 1)
1279 rctl |= E1000_RCTL_MPE;
1281 rctl &= (~E1000_RCTL_MPE);
1282 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1286 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1288 struct e1000_hw *hw =
1289 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1292 rctl = E1000_READ_REG(hw, E1000_RCTL);
1293 rctl |= E1000_RCTL_MPE;
1294 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1298 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1300 struct e1000_hw *hw =
1301 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1304 if (dev->data->promiscuous == 1)
1305 return; /* must remain in all_multicast mode */
1306 rctl = E1000_READ_REG(hw, E1000_RCTL);
1307 rctl &= (~E1000_RCTL_MPE);
1308 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1312 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1314 struct e1000_hw *hw =
1315 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1316 struct e1000_vfta * shadow_vfta =
1317 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1322 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1323 E1000_VFTA_ENTRY_MASK);
1324 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1325 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1330 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1332 /* update local VFTA copy */
1333 shadow_vfta->vfta[vid_idx] = vfta;
1339 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1341 struct e1000_hw *hw =
1342 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1345 /* Filter Table Disable */
1346 reg = E1000_READ_REG(hw, E1000_RCTL);
1347 reg &= ~E1000_RCTL_CFIEN;
1348 reg &= ~E1000_RCTL_VFE;
1349 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1353 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1355 struct e1000_hw *hw =
1356 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1357 struct e1000_vfta * shadow_vfta =
1358 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1362 /* Filter Table Enable, CFI not used for packet acceptance */
1363 reg = E1000_READ_REG(hw, E1000_RCTL);
1364 reg &= ~E1000_RCTL_CFIEN;
1365 reg |= E1000_RCTL_VFE;
1366 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1368 /* restore vfta from local copy */
1369 for (i = 0; i < IGB_VFTA_SIZE; i++)
1370 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1374 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1376 struct e1000_hw *hw =
1377 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1380 /* VLAN Mode Disable */
1381 reg = E1000_READ_REG(hw, E1000_CTRL);
1382 reg &= ~E1000_CTRL_VME;
1383 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1388 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1390 struct e1000_hw *hw =
1391 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1394 /* VLAN Mode Enable */
1395 reg = E1000_READ_REG(hw, E1000_CTRL);
1396 reg |= E1000_CTRL_VME;
1397 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1401 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1403 if(mask & ETH_VLAN_STRIP_MASK){
1404 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1405 em_vlan_hw_strip_enable(dev);
1407 em_vlan_hw_strip_disable(dev);
1410 if(mask & ETH_VLAN_FILTER_MASK){
1411 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1412 em_vlan_hw_filter_enable(dev);
1414 em_vlan_hw_filter_disable(dev);
1419 * It enables the interrupt mask and then enable the interrupt.
1422 * Pointer to struct rte_eth_dev.
1425 * - On success, zero.
1426 * - On failure, a negative value.
1429 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1432 struct e1000_hw *hw =
1433 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1435 /* clear interrupt */
1436 E1000_READ_REG(hw, E1000_ICR);
1437 regval = E1000_READ_REG(hw, E1000_IMS);
1438 E1000_WRITE_REG(hw, E1000_IMS, regval | E1000_ICR_LSC);
1443 * It clears the interrupt causes and enables the interrupt.
1444 * It will be called once only during nic initialized.
1447 * Pointer to struct rte_eth_dev.
1450 * - On success, zero.
1451 * - On failure, a negative value.
1454 eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev)
1456 struct e1000_hw *hw =
1457 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1459 E1000_READ_REG(hw, E1000_ICR);
1460 em_rxq_intr_enable(hw);
1465 * It enable receive packet interrupt.
1467 * Pointer to struct e1000_hw
1472 em_rxq_intr_enable(struct e1000_hw *hw)
1474 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_RXT0);
1475 E1000_WRITE_FLUSH(hw);
1479 * It disabled lsc interrupt.
1481 * Pointer to struct e1000_hw
1486 em_lsc_intr_disable(struct e1000_hw *hw)
1488 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_LSC);
1489 E1000_WRITE_FLUSH(hw);
1493 * It disabled receive packet interrupt.
1495 * Pointer to struct e1000_hw
1500 em_rxq_intr_disable(struct e1000_hw *hw)
1502 E1000_READ_REG(hw, E1000_ICR);
1503 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0);
1504 E1000_WRITE_FLUSH(hw);
1508 * It reads ICR and gets interrupt causes, check it and set a bit flag
1509 * to update link status.
1512 * Pointer to struct rte_eth_dev.
1515 * - On success, zero.
1516 * - On failure, a negative value.
1519 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1522 struct e1000_hw *hw =
1523 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1524 struct e1000_interrupt *intr =
1525 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1527 /* read-on-clear nic registers here */
1528 icr = E1000_READ_REG(hw, E1000_ICR);
1529 if (icr & E1000_ICR_LSC) {
1530 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1537 * It executes link_update after knowing an interrupt is prsent.
1540 * Pointer to struct rte_eth_dev.
1543 * - On success, zero.
1544 * - On failure, a negative value.
1547 eth_em_interrupt_action(struct rte_eth_dev *dev,
1548 struct rte_intr_handle *intr_handle)
1550 struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
1551 struct e1000_hw *hw =
1552 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1553 struct e1000_interrupt *intr =
1554 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1555 uint32_t tctl, rctl;
1556 struct rte_eth_link link;
1559 if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1562 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1563 rte_intr_enable(intr_handle);
1565 /* set get_link_status to check register later */
1566 hw->mac.get_link_status = 1;
1567 ret = eth_em_link_update(dev, 0);
1569 /* check if link has changed */
1573 memset(&link, 0, sizeof(link));
1574 rte_em_dev_atomic_read_link_status(dev, &link);
1575 if (link.link_status) {
1576 PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s",
1577 dev->data->port_id, (unsigned)link.link_speed,
1578 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1579 "full-duplex" : "half-duplex");
1581 PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
1583 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
1584 pci_dev->addr.domain, pci_dev->addr.bus,
1585 pci_dev->addr.devid, pci_dev->addr.function);
1587 tctl = E1000_READ_REG(hw, E1000_TCTL);
1588 rctl = E1000_READ_REG(hw, E1000_RCTL);
1589 if (link.link_status) {
1591 tctl |= E1000_TCTL_EN;
1592 rctl |= E1000_RCTL_EN;
1595 tctl &= ~E1000_TCTL_EN;
1596 rctl &= ~E1000_RCTL_EN;
1598 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1599 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1600 E1000_WRITE_FLUSH(hw);
1606 * Interrupt handler which shall be registered at first.
1609 * Pointer to interrupt handle.
1611 * The address of parameter (struct rte_eth_dev *) regsitered before.
1617 eth_em_interrupt_handler(struct rte_intr_handle *handle,
1620 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1622 eth_em_interrupt_get_status(dev);
1623 eth_em_interrupt_action(dev, handle);
1624 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1628 eth_em_led_on(struct rte_eth_dev *dev)
1630 struct e1000_hw *hw;
1632 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1633 return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1637 eth_em_led_off(struct rte_eth_dev *dev)
1639 struct e1000_hw *hw;
1641 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1642 return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1646 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1648 struct e1000_hw *hw;
1653 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1654 fc_conf->pause_time = hw->fc.pause_time;
1655 fc_conf->high_water = hw->fc.high_water;
1656 fc_conf->low_water = hw->fc.low_water;
1657 fc_conf->send_xon = hw->fc.send_xon;
1658 fc_conf->autoneg = hw->mac.autoneg;
1661 * Return rx_pause and tx_pause status according to actual setting of
1662 * the TFCE and RFCE bits in the CTRL register.
1664 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1665 if (ctrl & E1000_CTRL_TFCE)
1670 if (ctrl & E1000_CTRL_RFCE)
1675 if (rx_pause && tx_pause)
1676 fc_conf->mode = RTE_FC_FULL;
1678 fc_conf->mode = RTE_FC_RX_PAUSE;
1680 fc_conf->mode = RTE_FC_TX_PAUSE;
1682 fc_conf->mode = RTE_FC_NONE;
1688 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1690 struct e1000_hw *hw;
1692 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1698 uint32_t rx_buf_size;
1699 uint32_t max_high_water;
1702 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1703 if (fc_conf->autoneg != hw->mac.autoneg)
1705 rx_buf_size = em_get_rx_buffer_size(hw);
1706 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1708 /* At least reserve one Ethernet frame for watermark */
1709 max_high_water = rx_buf_size - ETHER_MAX_LEN;
1710 if ((fc_conf->high_water > max_high_water) ||
1711 (fc_conf->high_water < fc_conf->low_water)) {
1712 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1713 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
1717 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1718 hw->fc.pause_time = fc_conf->pause_time;
1719 hw->fc.high_water = fc_conf->high_water;
1720 hw->fc.low_water = fc_conf->low_water;
1721 hw->fc.send_xon = fc_conf->send_xon;
1723 err = e1000_setup_link_generic(hw);
1724 if (err == E1000_SUCCESS) {
1726 /* check if we want to forward MAC frames - driver doesn't have native
1727 * capability to do that, so we'll write the registers ourselves */
1729 rctl = E1000_READ_REG(hw, E1000_RCTL);
1731 /* set or clear MFLCN.PMCF bit depending on configuration */
1732 if (fc_conf->mac_ctrl_frame_fwd != 0)
1733 rctl |= E1000_RCTL_PMCF;
1735 rctl &= ~E1000_RCTL_PMCF;
1737 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1738 E1000_WRITE_FLUSH(hw);
1743 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1748 eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1749 uint32_t index, __rte_unused uint32_t pool)
1751 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1753 e1000_rar_set(hw, mac_addr->addr_bytes, index);
1757 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1759 uint8_t addr[ETHER_ADDR_LEN];
1760 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1762 memset(addr, 0, sizeof(addr));
1764 e1000_rar_set(hw, addr, index);
1768 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1770 struct rte_eth_dev_info dev_info;
1771 struct e1000_hw *hw;
1772 uint32_t frame_size;
1775 eth_em_infos_get(dev, &dev_info);
1776 frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE;
1778 /* check that mtu is within the allowed range */
1779 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1782 /* refuse mtu that requires the support of scattered packets when this
1783 * feature has not been enabled before. */
1784 if (!dev->data->scattered_rx &&
1785 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1788 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1789 rctl = E1000_READ_REG(hw, E1000_RCTL);
1791 /* switch to jumbo mode if needed */
1792 if (frame_size > ETHER_MAX_LEN) {
1793 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1794 rctl |= E1000_RCTL_LPE;
1796 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1797 rctl &= ~E1000_RCTL_LPE;
1799 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1801 /* update max frame size */
1802 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1807 eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
1808 struct ether_addr *mc_addr_set,
1809 uint32_t nb_mc_addr)
1811 struct e1000_hw *hw;
1813 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1814 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
1818 RTE_PMD_REGISTER_PCI(net_e1000_em, rte_em_pmd.pci_drv);
1819 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_em, pci_id_em_map);
1820 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_em, "* igb_uio | uio_pci_generic | vfio");