drivers/net/e1000/em_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <stdarg.h>
  10
  11 #include <rte_common.h>
  12 #include <rte_interrupts.h>
  13 #include <rte_byteorder.h>
  14 #include <rte_debug.h>
  15 #include <rte_pci.h>
  16 #include <rte_bus_pci.h>
  17 #include <rte_ether.h>
  18 #include <rte_ethdev_driver.h>
  19 #include <rte_ethdev_pci.h>
  20 #include <rte_memory.h>
  21 #include <rte_eal.h>
  22 #include <rte_malloc.h>
  23 #include <rte_dev.h>
  24
  25 #include "e1000_logs.h"
  26 #include "base/e1000_api.h"
  27 #include "e1000_ethdev.h"
  28
  29 #define EM_EIAC                 0x000DC
  30
  31 #define PMD_ROUNDUP(x,y)        (((x) + (y) - 1)/(y) * (y))
  32
  33
  34 static int eth_em_configure(struct rte_eth_dev *dev);
  35 static int eth_em_start(struct rte_eth_dev *dev);
  36 static void eth_em_stop(struct rte_eth_dev *dev);
  37 static int eth_em_close(struct rte_eth_dev *dev);
  38 static int eth_em_promiscuous_enable(struct rte_eth_dev *dev);
  39 static int eth_em_promiscuous_disable(struct rte_eth_dev *dev);
  40 static int eth_em_allmulticast_enable(struct rte_eth_dev *dev);
  41 static int eth_em_allmulticast_disable(struct rte_eth_dev *dev);
  42 static int eth_em_link_update(struct rte_eth_dev *dev,
  43                                 int wait_to_complete);
  44 static int eth_em_stats_get(struct rte_eth_dev *dev,
  45                                 struct rte_eth_stats *rte_stats);
  46 static int eth_em_stats_reset(struct rte_eth_dev *dev);
  47 static int eth_em_infos_get(struct rte_eth_dev *dev,
  48                                 struct rte_eth_dev_info *dev_info);
  49 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
  50                                 struct rte_eth_fc_conf *fc_conf);
  51 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
  52                                 struct rte_eth_fc_conf *fc_conf);
  53 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
  54 static int eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev);
  55 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
  56 static int eth_em_interrupt_action(struct rte_eth_dev *dev,
  57                                    struct rte_intr_handle *handle);
  58 static void eth_em_interrupt_handler(void *param);
  59
  60 static int em_hw_init(struct e1000_hw *hw);
  61 static int em_hardware_init(struct e1000_hw *hw);
  62 static void em_hw_control_acquire(struct e1000_hw *hw);
  63 static void em_hw_control_release(struct e1000_hw *hw);
  64 static void em_init_manageability(struct e1000_hw *hw);
  65 static void em_release_manageability(struct e1000_hw *hw);
  66
  67 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  68
  69 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
  70                 uint16_t vlan_id, int on);
  71 static int eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  72 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
  73 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
  74 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
  75 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
  76
  77 /*
  78 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
  79                                         uint16_t vlan_id, int on);
  80 */
  81
  82 static int eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
  83 static int eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
  84 static void em_lsc_intr_disable(struct e1000_hw *hw);
  85 static void em_rxq_intr_enable(struct e1000_hw *hw);
  86 static void em_rxq_intr_disable(struct e1000_hw *hw);
  87
  88 static int eth_em_led_on(struct rte_eth_dev *dev);
  89 static int eth_em_led_off(struct rte_eth_dev *dev);
  90
  91 static int em_get_rx_buffer_size(struct e1000_hw *hw);
  92 static int eth_em_rar_set(struct rte_eth_dev *dev,
  93                         struct rte_ether_addr *mac_addr,
  94                         uint32_t index, uint32_t pool);
  95 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
  96 static int eth_em_default_mac_addr_set(struct rte_eth_dev *dev,
  97                                          struct rte_ether_addr *addr);
  98
  99 static int eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
 100                                    struct rte_ether_addr *mc_addr_set,
 101                                    uint32_t nb_mc_addr);
 102
 103 #define EM_FC_PAUSE_TIME 0x0680
 104 #define EM_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 105 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 106
 107 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
 108
 109 /*
 110  * The set of PCI devices this driver supports
 111  */
 112 static const struct rte_pci_id pci_id_em_map[] = {
 113         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82540EM) },
 114         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_COPPER) },
 115         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_FIBER) },
 116         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_COPPER) },
 117         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_FIBER) },
 118         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_QUAD_COPPER) },
 119         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_COPPER) },
 120         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_FIBER) },
 121         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES) },
 122         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_DUAL) },
 123         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_QUAD) },
 124         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER) },
 125         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571PT_QUAD_COPPER) },
 126         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_FIBER) },
 127         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER_LP) },
 128         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_COPPER) },
 129         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_FIBER) },
 130         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_SERDES) },
 131         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI) },
 132         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82573L) },
 133         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574L) },
 134         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574LA) },
 135         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82583V) },
 136         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH2_LV_LM) },
 137         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_LM) },
 138         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_V) },
 139         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_LM) },
 140         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_V) },
 141         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM2) },
 142         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V2) },
 143         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM3) },
 144         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V3) },
 145         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM) },
 146         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V) },
 147         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM2) },
 148         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V2) },
 149         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LBG_I219_LM3) },
 150         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM4) },
 151         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V4) },
 152         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM5) },
 153         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V5) },
 154         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM6) },
 155         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V6) },
 156         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM7) },
 157         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V7) },
 158         { .vendor_id = 0, /* sentinel */ },
 159 };
 160
 161 static const struct eth_dev_ops eth_em_ops = {
 162         .dev_configure        = eth_em_configure,
 163         .dev_start            = eth_em_start,
 164         .dev_stop             = eth_em_stop,
 165         .dev_close            = eth_em_close,
 166         .promiscuous_enable   = eth_em_promiscuous_enable,
 167         .promiscuous_disable  = eth_em_promiscuous_disable,
 168         .allmulticast_enable  = eth_em_allmulticast_enable,
 169         .allmulticast_disable = eth_em_allmulticast_disable,
 170         .link_update          = eth_em_link_update,
 171         .stats_get            = eth_em_stats_get,
 172         .stats_reset          = eth_em_stats_reset,
 173         .dev_infos_get        = eth_em_infos_get,
 174         .mtu_set              = eth_em_mtu_set,
 175         .vlan_filter_set      = eth_em_vlan_filter_set,
 176         .vlan_offload_set     = eth_em_vlan_offload_set,
 177         .rx_queue_setup       = eth_em_rx_queue_setup,
 178         .rx_queue_release     = eth_em_rx_queue_release,
 179         .tx_queue_setup       = eth_em_tx_queue_setup,
 180         .tx_queue_release     = eth_em_tx_queue_release,
 181         .rx_queue_intr_enable = eth_em_rx_queue_intr_enable,
 182         .rx_queue_intr_disable = eth_em_rx_queue_intr_disable,
 183         .dev_led_on           = eth_em_led_on,
 184         .dev_led_off          = eth_em_led_off,
 185         .flow_ctrl_get        = eth_em_flow_ctrl_get,
 186         .flow_ctrl_set        = eth_em_flow_ctrl_set,
 187         .mac_addr_set         = eth_em_default_mac_addr_set,
 188         .mac_addr_add         = eth_em_rar_set,
 189         .mac_addr_remove      = eth_em_rar_clear,
 190         .set_mc_addr_list     = eth_em_set_mc_addr_list,
 191         .rxq_info_get         = em_rxq_info_get,
 192         .txq_info_get         = em_txq_info_get,
 193 };
 194
 195
 196 /**
 197  *  eth_em_dev_is_ich8 - Check for ICH8 device
 198  *  @hw: pointer to the HW structure
 199  *
 200  *  return TRUE for ICH8, otherwise FALSE
 201  **/
 202 static bool
 203 eth_em_dev_is_ich8(struct e1000_hw *hw)
 204 {
 205         DEBUGFUNC("eth_em_dev_is_ich8");
 206
 207         switch (hw->device_id) {
 208         case E1000_DEV_ID_PCH2_LV_LM:
 209         case E1000_DEV_ID_PCH_LPT_I217_LM:
 210         case E1000_DEV_ID_PCH_LPT_I217_V:
 211         case E1000_DEV_ID_PCH_LPTLP_I218_LM:
 212         case E1000_DEV_ID_PCH_LPTLP_I218_V:
 213         case E1000_DEV_ID_PCH_I218_V2:
 214         case E1000_DEV_ID_PCH_I218_LM2:
 215         case E1000_DEV_ID_PCH_I218_V3:
 216         case E1000_DEV_ID_PCH_I218_LM3:
 217         case E1000_DEV_ID_PCH_SPT_I219_LM:
 218         case E1000_DEV_ID_PCH_SPT_I219_V:
 219         case E1000_DEV_ID_PCH_SPT_I219_LM2:
 220         case E1000_DEV_ID_PCH_SPT_I219_V2:
 221         case E1000_DEV_ID_PCH_LBG_I219_LM3:
 222         case E1000_DEV_ID_PCH_SPT_I219_LM4:
 223         case E1000_DEV_ID_PCH_SPT_I219_V4:
 224         case E1000_DEV_ID_PCH_SPT_I219_LM5:
 225         case E1000_DEV_ID_PCH_SPT_I219_V5:
 226         case E1000_DEV_ID_PCH_CNP_I219_LM6:
 227         case E1000_DEV_ID_PCH_CNP_I219_V6:
 228         case E1000_DEV_ID_PCH_CNP_I219_LM7:
 229         case E1000_DEV_ID_PCH_CNP_I219_V7:
 230                 return 1;
 231         default:
 232                 return 0;
 233         }
 234 }
 235
 236 static int
 237 eth_em_dev_init(struct rte_eth_dev *eth_dev)
 238 {
 239         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 240         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 241         struct e1000_adapter *adapter =
 242                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 243         struct e1000_hw *hw =
 244                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 245         struct e1000_vfta * shadow_vfta =
 246                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 247
 248         eth_dev->dev_ops = &eth_em_ops;
 249         eth_dev->rx_queue_count = eth_em_rx_queue_count;
 250         eth_dev->rx_descriptor_done   = eth_em_rx_descriptor_done;
 251         eth_dev->rx_descriptor_status = eth_em_rx_descriptor_status;
 252         eth_dev->tx_descriptor_status = eth_em_tx_descriptor_status;
 253         eth_dev->rx_pkt_burst = (eth_rx_burst_t)&eth_em_recv_pkts;
 254         eth_dev->tx_pkt_burst = (eth_tx_burst_t)&eth_em_xmit_pkts;
 255         eth_dev->tx_pkt_prepare = (eth_tx_prep_t)&eth_em_prep_pkts;
 256
 257         /* for secondary processes, we don't initialise any further as primary
 258          * has already done this work. Only check we don't need a different
 259          * RX function */
 260         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 261                 if (eth_dev->data->scattered_rx)
 262                         eth_dev->rx_pkt_burst =
 263                                 (eth_rx_burst_t)&eth_em_recv_scattered_pkts;
 264                 return 0;
 265         }
 266
 267         rte_eth_copy_pci_info(eth_dev, pci_dev);
 268
 269         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 270         hw->device_id = pci_dev->id.device_id;
 271         adapter->stopped = 0;
 272
 273         /* For ICH8 support we'll need to map the flash memory BAR */
 274         if (eth_em_dev_is_ich8(hw))
 275                 hw->flash_address = (void *)pci_dev->mem_resource[1].addr;
 276
 277         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
 278                         em_hw_init(hw) != 0) {
 279                 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
 280                         "failed to init HW",
 281                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 282                         pci_dev->id.device_id);
 283                 return -ENODEV;
 284         }
 285
 286         /* Allocate memory for storing MAC addresses */
 287         eth_dev->data->mac_addrs = rte_zmalloc("e1000", RTE_ETHER_ADDR_LEN *
 288                         hw->mac.rar_entry_count, 0);
 289         if (eth_dev->data->mac_addrs == NULL) {
 290                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 291                         "store MAC addresses",
 292                         RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 293                 return -ENOMEM;
 294         }
 295
 296         /* Copy the permanent MAC address */
 297         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
 298                 eth_dev->data->mac_addrs);
 299
 300         /* initialize the vfta */
 301         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 302
 303         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 304                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 305                      pci_dev->id.device_id);
 306
 307         rte_intr_callback_register(intr_handle,
 308                                    eth_em_interrupt_handler, eth_dev);
 309
 310         return 0;
 311 }
 312
 313 static int
 314 eth_em_dev_uninit(struct rte_eth_dev *eth_dev)
 315 {
 316         PMD_INIT_FUNC_TRACE();
 317
 318         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 319                 return 0;
 320
 321         eth_em_close(eth_dev);
 322
 323         return 0;
 324 }
 325
 326 static int eth_em_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 327         struct rte_pci_device *pci_dev)
 328 {
 329         return rte_eth_dev_pci_generic_probe(pci_dev,
 330                 sizeof(struct e1000_adapter), eth_em_dev_init);
 331 }
 332
 333 static int eth_em_pci_remove(struct rte_pci_device *pci_dev)
 334 {
 335         return rte_eth_dev_pci_generic_remove(pci_dev, eth_em_dev_uninit);
 336 }
 337
 338 static struct rte_pci_driver rte_em_pmd = {
 339         .id_table = pci_id_em_map,
 340         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 341         .probe = eth_em_pci_probe,
 342         .remove = eth_em_pci_remove,
 343 };
 344
 345 static int
 346 em_hw_init(struct e1000_hw *hw)
 347 {
 348         int diag;
 349
 350         diag = hw->mac.ops.init_params(hw);
 351         if (diag != 0) {
 352                 PMD_INIT_LOG(ERR, "MAC Initialization Error");
 353                 return diag;
 354         }
 355         diag = hw->nvm.ops.init_params(hw);
 356         if (diag != 0) {
 357                 PMD_INIT_LOG(ERR, "NVM Initialization Error");
 358                 return diag;
 359         }
 360         diag = hw->phy.ops.init_params(hw);
 361         if (diag != 0) {
 362                 PMD_INIT_LOG(ERR, "PHY Initialization Error");
 363                 return diag;
 364         }
 365         (void) e1000_get_bus_info(hw);
 366
 367         hw->mac.autoneg = 1;
 368         hw->phy.autoneg_wait_to_complete = 0;
 369         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 370
 371         e1000_init_script_state_82541(hw, TRUE);
 372         e1000_set_tbi_compatibility_82543(hw, TRUE);
 373
 374         /* Copper options */
 375         if (hw->phy.media_type == e1000_media_type_copper) {
 376                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 377                 hw->phy.disable_polarity_correction = 0;
 378                 hw->phy.ms_type = e1000_ms_hw_default;
 379         }
 380
 381         /*
 382          * Start from a known state, this is important in reading the nvm
 383          * and mac from that.
 384          */
 385         e1000_reset_hw(hw);
 386
 387         /* Make sure we have a good EEPROM before we read from it */
 388         if (e1000_validate_nvm_checksum(hw) < 0) {
 389                 /*
 390                  * Some PCI-E parts fail the first check due to
 391                  * the link being in sleep state, call it again,
 392                  * if it fails a second time its a real issue.
 393                  */
 394                 diag = e1000_validate_nvm_checksum(hw);
 395                 if (diag < 0) {
 396                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 397                         goto error;
 398                 }
 399         }
 400
 401         /* Read the permanent MAC address out of the EEPROM */
 402         diag = e1000_read_mac_addr(hw);
 403         if (diag != 0) {
 404                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 405                 goto error;
 406         }
 407
 408         /* Now initialize the hardware */
 409         diag = em_hardware_init(hw);
 410         if (diag != 0) {
 411                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 412                 goto error;
 413         }
 414
 415         hw->mac.get_link_status = 1;
 416
 417         /* Indicate SOL/IDER usage */
 418         diag = e1000_check_reset_block(hw);
 419         if (diag < 0) {
 420                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
 421                         "SOL/IDER session");
 422         }
 423         return 0;
 424
 425 error:
 426         em_hw_control_release(hw);
 427         return diag;
 428 }
 429
 430 static int
 431 eth_em_configure(struct rte_eth_dev *dev)
 432 {
 433         struct e1000_interrupt *intr =
 434                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 435
 436         PMD_INIT_FUNC_TRACE();
 437         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 438
 439         PMD_INIT_FUNC_TRACE();
 440
 441         return 0;
 442 }
 443
 444 static void
 445 em_set_pba(struct e1000_hw *hw)
 446 {
 447         uint32_t pba;
 448
 449         /*
 450          * Packet Buffer Allocation (PBA)
 451          * Writing PBA sets the receive portion of the buffer
 452          * the remainder is used for the transmit buffer.
 453          * Devices before the 82547 had a Packet Buffer of 64K.
 454          * After the 82547 the buffer was reduced to 40K.
 455          */
 456         switch (hw->mac.type) {
 457                 case e1000_82547:
 458                 case e1000_82547_rev_2:
 459                 /* 82547: Total Packet Buffer is 40K */
 460                         pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
 461                         break;
 462                 case e1000_82571:
 463                 case e1000_82572:
 464                 case e1000_80003es2lan:
 465                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 466                         break;
 467                 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
 468                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
 469                         break;
 470                 case e1000_82574:
 471                 case e1000_82583:
 472                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
 473                         break;
 474                 case e1000_ich8lan:
 475                         pba = E1000_PBA_8K;
 476                         break;
 477                 case e1000_ich9lan:
 478                 case e1000_ich10lan:
 479                         pba = E1000_PBA_10K;
 480                         break;
 481                 case e1000_pchlan:
 482                 case e1000_pch2lan:
 483                 case e1000_pch_lpt:
 484                 case e1000_pch_spt:
 485                 case e1000_pch_cnp:
 486                         pba = E1000_PBA_26K;
 487                         break;
 488                 default:
 489                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
 490         }
 491
 492         E1000_WRITE_REG(hw, E1000_PBA, pba);
 493 }
 494
 495 static void
 496 eth_em_rxtx_control(struct rte_eth_dev *dev,
 497                     bool enable)
 498 {
 499         struct e1000_hw *hw =
 500                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 501         uint32_t tctl, rctl;
 502
 503         tctl = E1000_READ_REG(hw, E1000_TCTL);
 504         rctl = E1000_READ_REG(hw, E1000_RCTL);
 505         if (enable) {
 506                 /* enable Tx/Rx */
 507                 tctl |= E1000_TCTL_EN;
 508                 rctl |= E1000_RCTL_EN;
 509         } else {
 510                 /* disable Tx/Rx */
 511                 tctl &= ~E1000_TCTL_EN;
 512                 rctl &= ~E1000_RCTL_EN;
 513         }
 514         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
 515         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
 516         E1000_WRITE_FLUSH(hw);
 517 }
 518
 519 static int
 520 eth_em_start(struct rte_eth_dev *dev)
 521 {
 522         struct e1000_adapter *adapter =
 523                 E1000_DEV_PRIVATE(dev->data->dev_private);
 524         struct e1000_hw *hw =
 525                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 526         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 527         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 528         int ret, mask;
 529         uint32_t intr_vector = 0;
 530         uint32_t *speeds;
 531         int num_speeds;
 532         bool autoneg;
 533
 534         PMD_INIT_FUNC_TRACE();
 535
 536         eth_em_stop(dev);
 537
 538         e1000_power_up_phy(hw);
 539
 540         /* Set default PBA value */
 541         em_set_pba(hw);
 542
 543         /* Put the address into the Receive Address Array */
 544         e1000_rar_set(hw, hw->mac.addr, 0);
 545
 546         /*
 547          * With the 82571 adapter, RAR[0] may be overwritten
 548          * when the other port is reset, we make a duplicate
 549          * in RAR[14] for that eventuality, this assures
 550          * the interface continues to function.
 551          */
 552         if (hw->mac.type == e1000_82571) {
 553                 e1000_set_laa_state_82571(hw, TRUE);
 554                 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
 555         }
 556
 557         /* Initialize the hardware */
 558         if (em_hardware_init(hw)) {
 559                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 560                 return -EIO;
 561         }
 562
 563         E1000_WRITE_REG(hw, E1000_VET, RTE_ETHER_TYPE_VLAN);
 564
 565         /* Configure for OS presence */
 566         em_init_manageability(hw);
 567
 568         if (dev->data->dev_conf.intr_conf.rxq != 0) {
 569                 intr_vector = dev->data->nb_rx_queues;
 570                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 571                         return -1;
 572         }
 573
 574         if (rte_intr_dp_is_en(intr_handle)) {
 575                 intr_handle->intr_vec =
 576                         rte_zmalloc("intr_vec",
 577                                         dev->data->nb_rx_queues * sizeof(int), 0);
 578                 if (intr_handle->intr_vec == NULL) {
 579                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
 580                                                 " intr_vec", dev->data->nb_rx_queues);
 581                         return -ENOMEM;
 582                 }
 583
 584                 /* enable rx interrupt */
 585                 em_rxq_intr_enable(hw);
 586         }
 587
 588         eth_em_tx_init(dev);
 589
 590         ret = eth_em_rx_init(dev);
 591         if (ret) {
 592                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 593                 em_dev_clear_queues(dev);
 594                 return ret;
 595         }
 596
 597         e1000_clear_hw_cntrs_base_generic(hw);
 598
 599         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 600                         ETH_VLAN_EXTEND_MASK;
 601         ret = eth_em_vlan_offload_set(dev, mask);
 602         if (ret) {
 603                 PMD_INIT_LOG(ERR, "Unable to update vlan offload");
 604                 em_dev_clear_queues(dev);
 605                 return ret;
 606         }
 607
 608         /* Set Interrupt Throttling Rate to maximum allowed value. */
 609         E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
 610
 611         /* Setup link speed and duplex */
 612         speeds = &dev->data->dev_conf.link_speeds;
 613         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
 614                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 615                 hw->mac.autoneg = 1;
 616         } else {
 617                 num_speeds = 0;
 618                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
 619
 620                 /* Reset */
 621                 hw->phy.autoneg_advertised = 0;
 622
 623                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
 624                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
 625                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
 626                         num_speeds = -1;
 627                         goto error_invalid_config;
 628                 }
 629                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
 630                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
 631                         num_speeds++;
 632                 }
 633                 if (*speeds & ETH_LINK_SPEED_10M) {
 634                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
 635                         num_speeds++;
 636                 }
 637                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
 638                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
 639                         num_speeds++;
 640                 }
 641                 if (*speeds & ETH_LINK_SPEED_100M) {
 642                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
 643                         num_speeds++;
 644                 }
 645                 if (*speeds & ETH_LINK_SPEED_1G) {
 646                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
 647                         num_speeds++;
 648                 }
 649                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
 650                         goto error_invalid_config;
 651
 652                 /* Set/reset the mac.autoneg based on the link speed,
 653                  * fixed or not
 654                  */
 655                 if (!autoneg) {
 656                         hw->mac.autoneg = 0;
 657                         hw->mac.forced_speed_duplex =
 658                                         hw->phy.autoneg_advertised;
 659                 } else {
 660                         hw->mac.autoneg = 1;
 661                 }
 662         }
 663
 664         e1000_setup_link(hw);
 665
 666         if (rte_intr_allow_others(intr_handle)) {
 667                 /* check if lsc interrupt is enabled */
 668                 if (dev->data->dev_conf.intr_conf.lsc != 0) {
 669                         ret = eth_em_interrupt_setup(dev);
 670                         if (ret) {
 671                                 PMD_INIT_LOG(ERR, "Unable to setup interrupts");
 672                                 em_dev_clear_queues(dev);
 673                                 return ret;
 674                         }
 675                 }
 676         } else {
 677                 rte_intr_callback_unregister(intr_handle,
 678                                                 eth_em_interrupt_handler,
 679                                                 (void *)dev);
 680                 if (dev->data->dev_conf.intr_conf.lsc != 0)
 681                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
 682                                      " no intr multiplexn");
 683         }
 684         /* check if rxq interrupt is enabled */
 685         if (dev->data->dev_conf.intr_conf.rxq != 0)
 686                 eth_em_rxq_interrupt_setup(dev);
 687
 688         rte_intr_enable(intr_handle);
 689
 690         adapter->stopped = 0;
 691
 692         eth_em_rxtx_control(dev, true);
 693         eth_em_link_update(dev, 0);
 694
 695         PMD_INIT_LOG(DEBUG, "<<");
 696
 697         return 0;
 698
 699 error_invalid_config:
 700         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
 701                      dev->data->dev_conf.link_speeds, dev->data->port_id);
 702         em_dev_clear_queues(dev);
 703         return -EINVAL;
 704 }
 705
 706 /*********************************************************************
 707  *
 708  *  This routine disables all traffic on the adapter by issuing a
 709  *  global reset on the MAC.
 710  *
 711  **********************************************************************/
 712 static void
 713 eth_em_stop(struct rte_eth_dev *dev)
 714 {
 715         struct rte_eth_link link;
 716         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 717         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 718         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 719
 720         eth_em_rxtx_control(dev, false);
 721         em_rxq_intr_disable(hw);
 722         em_lsc_intr_disable(hw);
 723
 724         e1000_reset_hw(hw);
 725
 726         /* Flush desc rings for i219 */
 727         if (hw->mac.type == e1000_pch_spt || hw->mac.type == e1000_pch_cnp)
 728                 em_flush_desc_rings(dev);
 729
 730         if (hw->mac.type >= e1000_82544)
 731                 E1000_WRITE_REG(hw, E1000_WUC, 0);
 732
 733         /* Power down the phy. Needed to make the link go down */
 734         e1000_power_down_phy(hw);
 735
 736         em_dev_clear_queues(dev);
 737
 738         /* clear the recorded link status */
 739         memset(&link, 0, sizeof(link));
 740         rte_eth_linkstatus_set(dev, &link);
 741
 742         if (!rte_intr_allow_others(intr_handle))
 743                 /* resume to the default handler */
 744                 rte_intr_callback_register(intr_handle,
 745                                            eth_em_interrupt_handler,
 746                                            (void *)dev);
 747
 748         /* Clean datapath event and queue/vec mapping */
 749         rte_intr_efd_disable(intr_handle);
 750         if (intr_handle->intr_vec != NULL) {
 751                 rte_free(intr_handle->intr_vec);
 752                 intr_handle->intr_vec = NULL;
 753         }
 754 }
 755
 756 static int
 757 eth_em_close(struct rte_eth_dev *dev)
 758 {
 759         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 760         struct e1000_adapter *adapter =
 761                 E1000_DEV_PRIVATE(dev->data->dev_private);
 762         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 763         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 764
 765         eth_em_stop(dev);
 766         adapter->stopped = 1;
 767         em_dev_free_queues(dev);
 768         e1000_phy_hw_reset(hw);
 769         em_release_manageability(hw);
 770         em_hw_control_release(hw);
 771
 772         dev->dev_ops = NULL;
 773         dev->rx_pkt_burst = NULL;
 774         dev->tx_pkt_burst = NULL;
 775
 776         /* disable uio intr before callback unregister */
 777         rte_intr_disable(intr_handle);
 778         rte_intr_callback_unregister(intr_handle,
 779                                      eth_em_interrupt_handler, dev);
 780
 781         return 0;
 782 }
 783
 784 static int
 785 em_get_rx_buffer_size(struct e1000_hw *hw)
 786 {
 787         uint32_t rx_buf_size;
 788
 789         rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
 790         return rx_buf_size;
 791 }
 792
 793 /*********************************************************************
 794  *
 795  *  Initialize the hardware
 796  *
 797  **********************************************************************/
 798 static int
 799 em_hardware_init(struct e1000_hw *hw)
 800 {
 801         uint32_t rx_buf_size;
 802         int diag;
 803
 804         /* Issue a global reset */
 805         e1000_reset_hw(hw);
 806
 807         /* Let the firmware know the OS is in control */
 808         em_hw_control_acquire(hw);
 809
 810         /*
 811          * These parameters control the automatic generation (Tx) and
 812          * response (Rx) to Ethernet PAUSE frames.
 813          * - High water mark should allow for at least two standard size (1518)
 814          *   frames to be received after sending an XOFF.
 815          * - Low water mark works best when it is very near the high water mark.
 816          *   This allows the receiver to restart by sending XON when it has
 817          *   drained a bit. Here we use an arbitrary value of 1500 which will
 818          *   restart after one full frame is pulled from the buffer. There
 819          *   could be several smaller frames in the buffer and if so they will
 820          *   not trigger the XON until their total number reduces the buffer
 821          *   by 1500.
 822          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
 823          */
 824         rx_buf_size = em_get_rx_buffer_size(hw);
 825
 826         hw->fc.high_water = rx_buf_size -
 827                 PMD_ROUNDUP(RTE_ETHER_MAX_LEN * 2, 1024);
 828         hw->fc.low_water = hw->fc.high_water - 1500;
 829
 830         if (hw->mac.type == e1000_80003es2lan)
 831                 hw->fc.pause_time = UINT16_MAX;
 832         else
 833                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
 834
 835         hw->fc.send_xon = 1;
 836
 837         /* Set Flow control, use the tunable location if sane */
 838         if (em_fc_setting <= e1000_fc_full)
 839                 hw->fc.requested_mode = em_fc_setting;
 840         else
 841                 hw->fc.requested_mode = e1000_fc_none;
 842
 843         /* Workaround: no TX flow ctrl for PCH */
 844         if (hw->mac.type == e1000_pchlan)
 845                 hw->fc.requested_mode = e1000_fc_rx_pause;
 846
 847         /* Override - settings for PCH2LAN, ya its magic :) */
 848         if (hw->mac.type == e1000_pch2lan) {
 849                 hw->fc.high_water = 0x5C20;
 850                 hw->fc.low_water = 0x5048;
 851                 hw->fc.pause_time = 0x0650;
 852                 hw->fc.refresh_time = 0x0400;
 853         } else if (hw->mac.type == e1000_pch_lpt ||
 854                    hw->mac.type == e1000_pch_spt ||
 855                    hw->mac.type == e1000_pch_cnp) {
 856                 hw->fc.requested_mode = e1000_fc_full;
 857         }
 858
 859         diag = e1000_init_hw(hw);
 860         if (diag < 0)
 861                 return diag;
 862         e1000_check_for_link(hw);
 863         return 0;
 864 }
 865
 866 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
 867 static int
 868 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 869 {
 870         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 871         struct e1000_hw_stats *stats =
 872                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 873         int pause_frames;
 874
 875         if(hw->phy.media_type == e1000_media_type_copper ||
 876                         (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
 877                 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
 878                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
 879         }
 880
 881         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
 882         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
 883         stats->scc += E1000_READ_REG(hw, E1000_SCC);
 884         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
 885
 886         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
 887         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
 888         stats->colc += E1000_READ_REG(hw, E1000_COLC);
 889         stats->dc += E1000_READ_REG(hw, E1000_DC);
 890         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
 891         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
 892         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
 893
 894         /*
 895          * For watchdog management we need to know if we have been
 896          * paused during the last interval, so capture that here.
 897          */
 898         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
 899         stats->xoffrxc += pause_frames;
 900         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
 901         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
 902         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
 903         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
 904         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
 905         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
 906         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
 907         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
 908         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
 909         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
 910         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
 911         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
 912
 913         /*
 914          * For the 64-bit byte counters the low dword must be read first.
 915          * Both registers clear on the read of the high dword.
 916          */
 917
 918         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
 919         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
 920         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
 921         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
 922
 923         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
 924         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
 925         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
 926         stats->roc += E1000_READ_REG(hw, E1000_ROC);
 927         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
 928
 929         stats->tor += E1000_READ_REG(hw, E1000_TORH);
 930         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
 931
 932         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
 933         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
 934         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
 935         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
 936         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
 937         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
 938         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
 939         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
 940         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
 941         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
 942
 943         /* Interrupt Counts */
 944
 945         if (hw->mac.type >= e1000_82571) {
 946                 stats->iac += E1000_READ_REG(hw, E1000_IAC);
 947                 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
 948                 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
 949                 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
 950                 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
 951                 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
 952                 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
 953                 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
 954                 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
 955         }
 956
 957         if (hw->mac.type >= e1000_82543) {
 958                 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
 959                 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
 960                 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
 961                 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
 962                 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
 963                 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
 964         }
 965
 966         if (rte_stats == NULL)
 967                 return -EINVAL;
 968
 969         /* Rx Errors */
 970         rte_stats->imissed = stats->mpc;
 971         rte_stats->ierrors = stats->crcerrs +
 972                              stats->rlec + stats->ruc + stats->roc +
 973                              stats->rxerrc + stats->algnerrc + stats->cexterr;
 974
 975         /* Tx Errors */
 976         rte_stats->oerrors = stats->ecol + stats->latecol;
 977
 978         rte_stats->ipackets = stats->gprc;
 979         rte_stats->opackets = stats->gptc;
 980         rte_stats->ibytes   = stats->gorc;
 981         rte_stats->obytes   = stats->gotc;
 982         return 0;
 983 }
 984
 985 static int
 986 eth_em_stats_reset(struct rte_eth_dev *dev)
 987 {
 988         struct e1000_hw_stats *hw_stats =
 989                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 990
 991         /* HW registers are cleared on read */
 992         eth_em_stats_get(dev, NULL);
 993
 994         /* Reset software totals */
 995         memset(hw_stats, 0, sizeof(*hw_stats));
 996
 997         return 0;
 998 }
 999
1000 static int
1001 eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1002 {
1003         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1004         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1005         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1006
1007         em_rxq_intr_enable(hw);
1008         rte_intr_ack(intr_handle);
1009
1010         return 0;
1011 }
1012
1013 static int
1014 eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1015 {
1016         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1017
1018         em_rxq_intr_disable(hw);
1019
1020         return 0;
1021 }
1022
1023 uint32_t
1024 em_get_max_pktlen(struct rte_eth_dev *dev)
1025 {
1026         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1027
1028         switch (hw->mac.type) {
1029         case e1000_82571:
1030         case e1000_82572:
1031         case e1000_ich9lan:
1032         case e1000_ich10lan:
1033         case e1000_pch2lan:
1034         case e1000_pch_lpt:
1035         case e1000_pch_spt:
1036         case e1000_pch_cnp:
1037         case e1000_82574:
1038         case e1000_80003es2lan: /* 9K Jumbo Frame size */
1039         case e1000_82583:
1040                 return 0x2412;
1041         case e1000_pchlan:
1042                 return 0x1000;
1043         /* Adapters that do not support jumbo frames */
1044         case e1000_ich8lan:
1045                 return RTE_ETHER_MAX_LEN;
1046         default:
1047                 return MAX_JUMBO_FRAME_SIZE;
1048         }
1049 }
1050
1051 static int
1052 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1053 {
1054         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1055
1056         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1057         dev_info->max_rx_pktlen = em_get_max_pktlen(dev);
1058         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1059
1060         /*
1061          * Starting with 631xESB hw supports 2 TX/RX queues per port.
1062          * Unfortunatelly, all these nics have just one TX context.
1063          * So we have few choises for TX:
1064          * - Use just one TX queue.
1065          * - Allow cksum offload only for one TX queue.
1066          * - Don't allow TX cksum offload at all.
1067          * For now, option #1 was chosen.
1068          * To use second RX queue we have to use extended RX descriptor
1069          * (Multiple Receive Queues are mutually exclusive with UDP
1070          * fragmentation and are not supported when a legacy receive
1071          * descriptor format is used).
1072          * Which means separate RX routinies - as legacy nics (82540, 82545)
1073          * don't support extended RXD.
1074          * To avoid it we support just one RX queue for now (no RSS).
1075          */
1076
1077         dev_info->max_rx_queues = 1;
1078         dev_info->max_tx_queues = 1;
1079
1080         dev_info->rx_queue_offload_capa = em_get_rx_queue_offloads_capa(dev);
1081         dev_info->rx_offload_capa = em_get_rx_port_offloads_capa(dev) |
1082                                     dev_info->rx_queue_offload_capa;
1083         dev_info->tx_queue_offload_capa = em_get_tx_queue_offloads_capa(dev);
1084         dev_info->tx_offload_capa = em_get_tx_port_offloads_capa(dev) |
1085                                     dev_info->tx_queue_offload_capa;
1086
1087         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1088                 .nb_max = E1000_MAX_RING_DESC,
1089                 .nb_min = E1000_MIN_RING_DESC,
1090                 .nb_align = EM_RXD_ALIGN,
1091         };
1092
1093         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1094                 .nb_max = E1000_MAX_RING_DESC,
1095                 .nb_min = E1000_MIN_RING_DESC,
1096                 .nb_align = EM_TXD_ALIGN,
1097                 .nb_seg_max = EM_TX_MAX_SEG,
1098                 .nb_mtu_seg_max = EM_TX_MAX_MTU_SEG,
1099         };
1100
1101         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1102                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1103                         ETH_LINK_SPEED_1G;
1104
1105         /* Preferred queue parameters */
1106         dev_info->default_rxportconf.nb_queues = 1;
1107         dev_info->default_txportconf.nb_queues = 1;
1108         dev_info->default_txportconf.ring_size = 256;
1109         dev_info->default_rxportconf.ring_size = 256;
1110
1111         return 0;
1112 }
1113
1114 /* return 0 means link status changed, -1 means not changed */
1115 static int
1116 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1117 {
1118         struct e1000_hw *hw =
1119                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1120         struct rte_eth_link link;
1121         int link_up, count;
1122
1123         link_up = 0;
1124         hw->mac.get_link_status = 1;
1125
1126         /* possible wait-to-complete in up to 9 seconds */
1127         for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1128                 /* Read the real link status */
1129                 switch (hw->phy.media_type) {
1130                 case e1000_media_type_copper:
1131                         /* Do the work to read phy */
1132                         e1000_check_for_link(hw);
1133                         link_up = !hw->mac.get_link_status;
1134                         break;
1135
1136                 case e1000_media_type_fiber:
1137                         e1000_check_for_link(hw);
1138                         link_up = (E1000_READ_REG(hw, E1000_STATUS) &
1139                                         E1000_STATUS_LU);
1140                         break;
1141
1142                 case e1000_media_type_internal_serdes:
1143                         e1000_check_for_link(hw);
1144                         link_up = hw->mac.serdes_has_link;
1145                         break;
1146
1147                 default:
1148                         break;
1149                 }
1150                 if (link_up || wait_to_complete == 0)
1151                         break;
1152                 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
1153         }
1154         memset(&link, 0, sizeof(link));
1155
1156         /* Now we check if a transition has happened */
1157         if (link_up) {
1158                 uint16_t duplex, speed;
1159                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1160                 link.link_duplex = (duplex == FULL_DUPLEX) ?
1161                                 ETH_LINK_FULL_DUPLEX :
1162                                 ETH_LINK_HALF_DUPLEX;
1163                 link.link_speed = speed;
1164                 link.link_status = ETH_LINK_UP;
1165                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
1166                                 ETH_LINK_SPEED_FIXED);
1167         } else {
1168                 link.link_speed = ETH_SPEED_NUM_NONE;
1169                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1170                 link.link_status = ETH_LINK_DOWN;
1171                 link.link_autoneg = ETH_LINK_FIXED;
1172         }
1173
1174         return rte_eth_linkstatus_set(dev, &link);
1175 }
1176
1177 /*
1178  * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
1179  * For ASF and Pass Through versions of f/w this means
1180  * that the driver is loaded. For AMT version type f/w
1181  * this means that the network i/f is open.
1182  */
1183 static void
1184 em_hw_control_acquire(struct e1000_hw *hw)
1185 {
1186         uint32_t ctrl_ext, swsm;
1187
1188         /* Let firmware know the driver has taken over */
1189         if (hw->mac.type == e1000_82573) {
1190                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1191                 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
1192
1193         } else {
1194                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1195                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1196                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1197         }
1198 }
1199
1200 /*
1201  * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
1202  * For ASF and Pass Through versions of f/w this means that the
1203  * driver is no longer loaded. For AMT versions of the
1204  * f/w this means that the network i/f is closed.
1205  */
1206 static void
1207 em_hw_control_release(struct e1000_hw *hw)
1208 {
1209         uint32_t ctrl_ext, swsm;
1210
1211         /* Let firmware taken over control of h/w */
1212         if (hw->mac.type == e1000_82573) {
1213                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1214                 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
1215         } else {
1216                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1217                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1218                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1219         }
1220 }
1221
1222 /*
1223  * Bit of a misnomer, what this really means is
1224  * to enable OS management of the system... aka
1225  * to disable special hardware management features.
1226  */
1227 static void
1228 em_init_manageability(struct e1000_hw *hw)
1229 {
1230         if (e1000_enable_mng_pass_thru(hw)) {
1231                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1232                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1233
1234                 /* disable hardware interception of ARP */
1235                 manc &= ~(E1000_MANC_ARP_EN);
1236
1237                 /* enable receiving management packets to the host */
1238                 manc |= E1000_MANC_EN_MNG2HOST;
1239                 manc2h |= 1 << 5;  /* Mng Port 623 */
1240                 manc2h |= 1 << 6;  /* Mng Port 664 */
1241                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1242                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1243         }
1244 }
1245
1246 /*
1247  * Give control back to hardware management
1248  * controller if there is one.
1249  */
1250 static void
1251 em_release_manageability(struct e1000_hw *hw)
1252 {
1253         uint32_t manc;
1254
1255         if (e1000_enable_mng_pass_thru(hw)) {
1256                 manc = E1000_READ_REG(hw, E1000_MANC);
1257
1258                 /* re-enable hardware interception of ARP */
1259                 manc |= E1000_MANC_ARP_EN;
1260                 manc &= ~E1000_MANC_EN_MNG2HOST;
1261
1262                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1263         }
1264 }
1265
1266 static int
1267 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1268 {
1269         struct e1000_hw *hw =
1270                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1271         uint32_t rctl;
1272
1273         rctl = E1000_READ_REG(hw, E1000_RCTL);
1274         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1275         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1276
1277         return 0;
1278 }
1279
1280 static int
1281 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1282 {
1283         struct e1000_hw *hw =
1284                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1285         uint32_t rctl;
1286
1287         rctl = E1000_READ_REG(hw, E1000_RCTL);
1288         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1289         if (dev->data->all_multicast == 1)
1290                 rctl |= E1000_RCTL_MPE;
1291         else
1292                 rctl &= (~E1000_RCTL_MPE);
1293         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1294
1295         return 0;
1296 }
1297
1298 static int
1299 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1300 {
1301         struct e1000_hw *hw =
1302                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1303         uint32_t rctl;
1304
1305         rctl = E1000_READ_REG(hw, E1000_RCTL);
1306         rctl |= E1000_RCTL_MPE;
1307         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1308
1309         return 0;
1310 }
1311
1312 static int
1313 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1314 {
1315         struct e1000_hw *hw =
1316                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1317         uint32_t rctl;
1318
1319         if (dev->data->promiscuous == 1)
1320                 return 0; /* must remain in all_multicast mode */
1321         rctl = E1000_READ_REG(hw, E1000_RCTL);
1322         rctl &= (~E1000_RCTL_MPE);
1323         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1324
1325         return 0;
1326 }
1327
1328 static int
1329 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1330 {
1331         struct e1000_hw *hw =
1332                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1333         struct e1000_vfta * shadow_vfta =
1334                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1335         uint32_t vfta;
1336         uint32_t vid_idx;
1337         uint32_t vid_bit;
1338
1339         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1340                               E1000_VFTA_ENTRY_MASK);
1341         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1342         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1343         if (on)
1344                 vfta |= vid_bit;
1345         else
1346                 vfta &= ~vid_bit;
1347         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1348
1349         /* update local VFTA copy */
1350         shadow_vfta->vfta[vid_idx] = vfta;
1351
1352         return 0;
1353 }
1354
1355 static void
1356 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1357 {
1358         struct e1000_hw *hw =
1359                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1360         uint32_t reg;
1361
1362         /* Filter Table Disable */
1363         reg = E1000_READ_REG(hw, E1000_RCTL);
1364         reg &= ~E1000_RCTL_CFIEN;
1365         reg &= ~E1000_RCTL_VFE;
1366         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1367 }
1368
1369 static void
1370 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1371 {
1372         struct e1000_hw *hw =
1373                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1374         struct e1000_vfta * shadow_vfta =
1375                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1376         uint32_t reg;
1377         int i;
1378
1379         /* Filter Table Enable, CFI not used for packet acceptance */
1380         reg = E1000_READ_REG(hw, E1000_RCTL);
1381         reg &= ~E1000_RCTL_CFIEN;
1382         reg |= E1000_RCTL_VFE;
1383         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1384
1385         /* restore vfta from local copy */
1386         for (i = 0; i < IGB_VFTA_SIZE; i++)
1387                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1388 }
1389
1390 static void
1391 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1392 {
1393         struct e1000_hw *hw =
1394                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1395         uint32_t reg;
1396
1397         /* VLAN Mode Disable */
1398         reg = E1000_READ_REG(hw, E1000_CTRL);
1399         reg &= ~E1000_CTRL_VME;
1400         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1401
1402 }
1403
1404 static void
1405 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1406 {
1407         struct e1000_hw *hw =
1408                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1409         uint32_t reg;
1410
1411         /* VLAN Mode Enable */
1412         reg = E1000_READ_REG(hw, E1000_CTRL);
1413         reg |= E1000_CTRL_VME;
1414         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1415 }
1416
1417 static int
1418 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1419 {
1420         struct rte_eth_rxmode *rxmode;
1421
1422         rxmode = &dev->data->dev_conf.rxmode;
1423         if(mask & ETH_VLAN_STRIP_MASK){
1424                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1425                         em_vlan_hw_strip_enable(dev);
1426                 else
1427                         em_vlan_hw_strip_disable(dev);
1428         }
1429
1430         if(mask & ETH_VLAN_FILTER_MASK){
1431                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1432                         em_vlan_hw_filter_enable(dev);
1433                 else
1434                         em_vlan_hw_filter_disable(dev);
1435         }
1436
1437         return 0;
1438 }
1439
1440 /*
1441  * It enables the interrupt mask and then enable the interrupt.
1442  *
1443  * @param dev
1444  *  Pointer to struct rte_eth_dev.
1445  *
1446  * @return
1447  *  - On success, zero.
1448  *  - On failure, a negative value.
1449  */
1450 static int
1451 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1452 {
1453         uint32_t regval;
1454         struct e1000_hw *hw =
1455                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1456
1457         /* clear interrupt */
1458         E1000_READ_REG(hw, E1000_ICR);
1459         regval = E1000_READ_REG(hw, E1000_IMS);
1460         E1000_WRITE_REG(hw, E1000_IMS,
1461                         regval | E1000_ICR_LSC | E1000_ICR_OTHER);
1462         return 0;
1463 }
1464
1465 /*
1466  * It clears the interrupt causes and enables the interrupt.
1467  * It will be called once only during nic initialized.
1468  *
1469  * @param dev
1470  *  Pointer to struct rte_eth_dev.
1471  *
1472  * @return
1473  *  - On success, zero.
1474  *  - On failure, a negative value.
1475  */
1476 static int
1477 eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev)
1478 {
1479         struct e1000_hw *hw =
1480         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1481
1482         E1000_READ_REG(hw, E1000_ICR);
1483         em_rxq_intr_enable(hw);
1484         return 0;
1485 }
1486
1487 /*
1488  * It enable receive packet interrupt.
1489  * @param hw
1490  * Pointer to struct e1000_hw
1491  *
1492  * @return
1493  */
1494 static void
1495 em_rxq_intr_enable(struct e1000_hw *hw)
1496 {
1497         E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_RXT0);
1498         E1000_WRITE_FLUSH(hw);
1499 }
1500
1501 /*
1502  * It disabled lsc interrupt.
1503  * @param hw
1504  * Pointer to struct e1000_hw
1505  *
1506  * @return
1507  */
1508 static void
1509 em_lsc_intr_disable(struct e1000_hw *hw)
1510 {
1511         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_LSC | E1000_IMS_OTHER);
1512         E1000_WRITE_FLUSH(hw);
1513 }
1514
1515 /*
1516  * It disabled receive packet interrupt.
1517  * @param hw
1518  * Pointer to struct e1000_hw
1519  *
1520  * @return
1521  */
1522 static void
1523 em_rxq_intr_disable(struct e1000_hw *hw)
1524 {
1525         E1000_READ_REG(hw, E1000_ICR);
1526         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0);
1527         E1000_WRITE_FLUSH(hw);
1528 }
1529
1530 /*
1531  * It reads ICR and gets interrupt causes, check it and set a bit flag
1532  * to update link status.
1533  *
1534  * @param dev
1535  *  Pointer to struct rte_eth_dev.
1536  *
1537  * @return
1538  *  - On success, zero.
1539  *  - On failure, a negative value.
1540  */
1541 static int
1542 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1543 {
1544         uint32_t icr;
1545         struct e1000_hw *hw =
1546                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1547         struct e1000_interrupt *intr =
1548                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1549
1550         /* read-on-clear nic registers here */
1551         icr = E1000_READ_REG(hw, E1000_ICR);
1552         if (icr & E1000_ICR_LSC) {
1553                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1554         }
1555
1556         return 0;
1557 }
1558
1559 /*
1560  * It executes link_update after knowing an interrupt is prsent.
1561  *
1562  * @param dev
1563  *  Pointer to struct rte_eth_dev.
1564  *
1565  * @return
1566  *  - On success, zero.
1567  *  - On failure, a negative value.
1568  */
1569 static int
1570 eth_em_interrupt_action(struct rte_eth_dev *dev,
1571                         struct rte_intr_handle *intr_handle)
1572 {
1573         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1574         struct e1000_hw *hw =
1575                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1576         struct e1000_interrupt *intr =
1577                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1578         struct rte_eth_link link;
1579         int ret;
1580
1581         if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1582                 return -1;
1583
1584         intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1585         rte_intr_ack(intr_handle);
1586
1587         /* set get_link_status to check register later */
1588         hw->mac.get_link_status = 1;
1589         ret = eth_em_link_update(dev, 0);
1590
1591         /* check if link has changed */
1592         if (ret < 0)
1593                 return 0;
1594
1595         rte_eth_linkstatus_get(dev, &link);
1596
1597         if (link.link_status) {
1598                 PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s",
1599                              dev->data->port_id, link.link_speed,
1600                              link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1601                              "full-duplex" : "half-duplex");
1602         } else {
1603                 PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
1604         }
1605         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
1606                      pci_dev->addr.domain, pci_dev->addr.bus,
1607                      pci_dev->addr.devid, pci_dev->addr.function);
1608
1609         return 0;
1610 }
1611
1612 /**
1613  * Interrupt handler which shall be registered at first.
1614  *
1615  * @param handle
1616  *  Pointer to interrupt handle.
1617  * @param param
1618  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1619  *
1620  * @return
1621  *  void
1622  */
1623 static void
1624 eth_em_interrupt_handler(void *param)
1625 {
1626         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1627
1628         eth_em_interrupt_get_status(dev);
1629         eth_em_interrupt_action(dev, dev->intr_handle);
1630         rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1631 }
1632
1633 static int
1634 eth_em_led_on(struct rte_eth_dev *dev)
1635 {
1636         struct e1000_hw *hw;
1637
1638         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1639         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1640 }
1641
1642 static int
1643 eth_em_led_off(struct rte_eth_dev *dev)
1644 {
1645         struct e1000_hw *hw;
1646
1647         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1648         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1649 }
1650
1651 static int
1652 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1653 {
1654         struct e1000_hw *hw;
1655         uint32_t ctrl;
1656         int tx_pause;
1657         int rx_pause;
1658
1659         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1660         fc_conf->pause_time = hw->fc.pause_time;
1661         fc_conf->high_water = hw->fc.high_water;
1662         fc_conf->low_water = hw->fc.low_water;
1663         fc_conf->send_xon = hw->fc.send_xon;
1664         fc_conf->autoneg = hw->mac.autoneg;
1665
1666         /*
1667          * Return rx_pause and tx_pause status according to actual setting of
1668          * the TFCE and RFCE bits in the CTRL register.
1669          */
1670         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1671         if (ctrl & E1000_CTRL_TFCE)
1672                 tx_pause = 1;
1673         else
1674                 tx_pause = 0;
1675
1676         if (ctrl & E1000_CTRL_RFCE)
1677                 rx_pause = 1;
1678         else
1679                 rx_pause = 0;
1680
1681         if (rx_pause && tx_pause)
1682                 fc_conf->mode = RTE_FC_FULL;
1683         else if (rx_pause)
1684                 fc_conf->mode = RTE_FC_RX_PAUSE;
1685         else if (tx_pause)
1686                 fc_conf->mode = RTE_FC_TX_PAUSE;
1687         else
1688                 fc_conf->mode = RTE_FC_NONE;
1689
1690         return 0;
1691 }
1692
1693 static int
1694 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1695 {
1696         struct e1000_hw *hw;
1697         int err;
1698         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1699                 e1000_fc_none,
1700                 e1000_fc_rx_pause,
1701                 e1000_fc_tx_pause,
1702                 e1000_fc_full
1703         };
1704         uint32_t rx_buf_size;
1705         uint32_t max_high_water;
1706         uint32_t rctl;
1707
1708         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1709         if (fc_conf->autoneg != hw->mac.autoneg)
1710                 return -ENOTSUP;
1711         rx_buf_size = em_get_rx_buffer_size(hw);
1712         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1713
1714         /* At least reserve one Ethernet frame for watermark */
1715         max_high_water = rx_buf_size - RTE_ETHER_MAX_LEN;
1716         if ((fc_conf->high_water > max_high_water) ||
1717             (fc_conf->high_water < fc_conf->low_water)) {
1718                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1719                 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
1720                 return -EINVAL;
1721         }
1722
1723         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1724         hw->fc.pause_time     = fc_conf->pause_time;
1725         hw->fc.high_water     = fc_conf->high_water;
1726         hw->fc.low_water      = fc_conf->low_water;
1727         hw->fc.send_xon       = fc_conf->send_xon;
1728
1729         err = e1000_setup_link_generic(hw);
1730         if (err == E1000_SUCCESS) {
1731
1732                 /* check if we want to forward MAC frames - driver doesn't have native
1733                  * capability to do that, so we'll write the registers ourselves */
1734
1735                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1736
1737                 /* set or clear MFLCN.PMCF bit depending on configuration */
1738                 if (fc_conf->mac_ctrl_frame_fwd != 0)
1739                         rctl |= E1000_RCTL_PMCF;
1740                 else
1741                         rctl &= ~E1000_RCTL_PMCF;
1742
1743                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1744                 E1000_WRITE_FLUSH(hw);
1745
1746                 return 0;
1747         }
1748
1749         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1750         return -EIO;
1751 }
1752
1753 static int
1754 eth_em_rar_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1755                 uint32_t index, __rte_unused uint32_t pool)
1756 {
1757         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1758
1759         return e1000_rar_set(hw, mac_addr->addr_bytes, index);
1760 }
1761
1762 static void
1763 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1764 {
1765         uint8_t addr[RTE_ETHER_ADDR_LEN];
1766         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1767
1768         memset(addr, 0, sizeof(addr));
1769
1770         e1000_rar_set(hw, addr, index);
1771 }
1772
1773 static int
1774 eth_em_default_mac_addr_set(struct rte_eth_dev *dev,
1775                             struct rte_ether_addr *addr)
1776 {
1777         eth_em_rar_clear(dev, 0);
1778
1779         return eth_em_rar_set(dev, (void *)addr, 0, 0);
1780 }
1781
1782 static int
1783 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1784 {
1785         struct rte_eth_dev_info dev_info;
1786         struct e1000_hw *hw;
1787         uint32_t frame_size;
1788         uint32_t rctl;
1789         int ret;
1790
1791         ret = eth_em_infos_get(dev, &dev_info);
1792         if (ret != 0)
1793                 return ret;
1794
1795         frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
1796                 VLAN_TAG_SIZE;
1797
1798         /* check that mtu is within the allowed range */
1799         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
1800                 return -EINVAL;
1801
1802         /* refuse mtu that requires the support of scattered packets when this
1803          * feature has not been enabled before. */
1804         if (!dev->data->scattered_rx &&
1805             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1806                 return -EINVAL;
1807
1808         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1809         rctl = E1000_READ_REG(hw, E1000_RCTL);
1810
1811         /* switch to jumbo mode if needed */
1812         if (frame_size > RTE_ETHER_MAX_LEN) {
1813                 dev->data->dev_conf.rxmode.offloads |=
1814                         DEV_RX_OFFLOAD_JUMBO_FRAME;
1815                 rctl |= E1000_RCTL_LPE;
1816         } else {
1817                 dev->data->dev_conf.rxmode.offloads &=
1818                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1819                 rctl &= ~E1000_RCTL_LPE;
1820         }
1821         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1822
1823         /* update max frame size */
1824         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1825         return 0;
1826 }
1827
1828 static int
1829 eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
1830                         struct rte_ether_addr *mc_addr_set,
1831                         uint32_t nb_mc_addr)
1832 {
1833         struct e1000_hw *hw;
1834
1835         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1836         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
1837         return 0;
1838 }
1839
1840 RTE_PMD_REGISTER_PCI(net_e1000_em, rte_em_pmd);
1841 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_em, pci_id_em_map);
1842 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_em, "* igb_uio | uio_pci_generic | vfio-pci");
1843
1844 /* see e1000_logs.c */
1845 RTE_INIT(igb_init_log)
1846 {
1847         e1000_igb_init_log();
1848 }