d28030edbd3898f1c4dbb2e55457b43778da8bc9
[dpdk.git] / drivers / net / e1000 / em_ethdev.c
1 /*-
2  *   BSD LICENSE
3  *
4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
5  *   All rights reserved.
6  *
7  *   Redistribution and use in source and binary forms, with or without
8  *   modification, are permitted provided that the following conditions
9  *   are met:
10  *
11  *     * Redistributions of source code must retain the above copyright
12  *       notice, this list of conditions and the following disclaimer.
13  *     * Redistributions in binary form must reproduce the above copyright
14  *       notice, this list of conditions and the following disclaimer in
15  *       the documentation and/or other materials provided with the
16  *       distribution.
17  *     * Neither the name of Intel Corporation nor the names of its
18  *       contributors may be used to endorse or promote products derived
19  *       from this software without specific prior written permission.
20  *
21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32  */
33
34 #include <sys/queue.h>
35 #include <stdio.h>
36 #include <errno.h>
37 #include <stdint.h>
38 #include <stdarg.h>
39
40 #include <rte_common.h>
41 #include <rte_interrupts.h>
42 #include <rte_byteorder.h>
43 #include <rte_log.h>
44 #include <rte_debug.h>
45 #include <rte_pci.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memory.h>
49 #include <rte_memzone.h>
50 #include <rte_eal.h>
51 #include <rte_atomic.h>
52 #include <rte_malloc.h>
53 #include <rte_dev.h>
54
55 #include "e1000_logs.h"
56 #include "base/e1000_api.h"
57 #include "e1000_ethdev.h"
58
59 #define EM_EIAC                 0x000DC
60
61 #define PMD_ROUNDUP(x,y)        (((x) + (y) - 1)/(y) * (y))
62
63
64 static int eth_em_configure(struct rte_eth_dev *dev);
65 static int eth_em_start(struct rte_eth_dev *dev);
66 static void eth_em_stop(struct rte_eth_dev *dev);
67 static void eth_em_close(struct rte_eth_dev *dev);
68 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
69 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
70 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
71 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
72 static int eth_em_link_update(struct rte_eth_dev *dev,
73                                 int wait_to_complete);
74 static void eth_em_stats_get(struct rte_eth_dev *dev,
75                                 struct rte_eth_stats *rte_stats);
76 static void eth_em_stats_reset(struct rte_eth_dev *dev);
77 static void eth_em_infos_get(struct rte_eth_dev *dev,
78                                 struct rte_eth_dev_info *dev_info);
79 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
80                                 struct rte_eth_fc_conf *fc_conf);
81 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
82                                 struct rte_eth_fc_conf *fc_conf);
83 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
84 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
85 static int eth_em_interrupt_action(struct rte_eth_dev *dev);
86 static void eth_em_interrupt_handler(struct rte_intr_handle *handle,
87                                                         void *param);
88
89 static int em_hw_init(struct e1000_hw *hw);
90 static int em_hardware_init(struct e1000_hw *hw);
91 static void em_hw_control_acquire(struct e1000_hw *hw);
92 static void em_hw_control_release(struct e1000_hw *hw);
93 static void em_init_manageability(struct e1000_hw *hw);
94 static void em_release_manageability(struct e1000_hw *hw);
95
96 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
97
98 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
99                 uint16_t vlan_id, int on);
100 static void eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
101 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
102 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
103 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
104 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
105
106 /*
107 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
108                                         uint16_t vlan_id, int on);
109 */
110 static int eth_em_led_on(struct rte_eth_dev *dev);
111 static int eth_em_led_off(struct rte_eth_dev *dev);
112
113 static void em_intr_disable(struct e1000_hw *hw);
114 static int em_get_rx_buffer_size(struct e1000_hw *hw);
115 static void eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
116                 uint32_t index, uint32_t pool);
117 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
118
119 #define EM_FC_PAUSE_TIME 0x0680
120 #define EM_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
121 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
122
123 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
124
125 /*
126  * The set of PCI devices this driver supports
127  */
128 static const struct rte_pci_id pci_id_em_map[] = {
129
130 #define RTE_PCI_DEV_ID_DECL_EM(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
131 #include "rte_pci_dev_ids.h"
132
133 {0},
134 };
135
136 static const struct eth_dev_ops eth_em_ops = {
137         .dev_configure        = eth_em_configure,
138         .dev_start            = eth_em_start,
139         .dev_stop             = eth_em_stop,
140         .dev_close            = eth_em_close,
141         .promiscuous_enable   = eth_em_promiscuous_enable,
142         .promiscuous_disable  = eth_em_promiscuous_disable,
143         .allmulticast_enable  = eth_em_allmulticast_enable,
144         .allmulticast_disable = eth_em_allmulticast_disable,
145         .link_update          = eth_em_link_update,
146         .stats_get            = eth_em_stats_get,
147         .stats_reset          = eth_em_stats_reset,
148         .dev_infos_get        = eth_em_infos_get,
149         .mtu_set              = eth_em_mtu_set,
150         .vlan_filter_set      = eth_em_vlan_filter_set,
151         .vlan_offload_set     = eth_em_vlan_offload_set,
152         .rx_queue_setup       = eth_em_rx_queue_setup,
153         .rx_queue_release     = eth_em_rx_queue_release,
154         .rx_queue_count       = eth_em_rx_queue_count,
155         .rx_descriptor_done   = eth_em_rx_descriptor_done,
156         .tx_queue_setup       = eth_em_tx_queue_setup,
157         .tx_queue_release     = eth_em_tx_queue_release,
158         .dev_led_on           = eth_em_led_on,
159         .dev_led_off          = eth_em_led_off,
160         .flow_ctrl_get        = eth_em_flow_ctrl_get,
161         .flow_ctrl_set        = eth_em_flow_ctrl_set,
162         .mac_addr_add         = eth_em_rar_set,
163         .mac_addr_remove      = eth_em_rar_clear,
164 };
165
166 /**
167  * Atomically reads the link status information from global
168  * structure rte_eth_dev.
169  *
170  * @param dev
171  *   - Pointer to the structure rte_eth_dev to read from.
172  *   - Pointer to the buffer to be saved with the link status.
173  *
174  * @return
175  *   - On success, zero.
176  *   - On failure, negative value.
177  */
178 static inline int
179 rte_em_dev_atomic_read_link_status(struct rte_eth_dev *dev,
180                                 struct rte_eth_link *link)
181 {
182         struct rte_eth_link *dst = link;
183         struct rte_eth_link *src = &(dev->data->dev_link);
184
185         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
186                                         *(uint64_t *)src) == 0)
187                 return -1;
188
189         return 0;
190 }
191
192 /**
193  * Atomically writes the link status information into global
194  * structure rte_eth_dev.
195  *
196  * @param dev
197  *   - Pointer to the structure rte_eth_dev to read from.
198  *   - Pointer to the buffer to be saved with the link status.
199  *
200  * @return
201  *   - On success, zero.
202  *   - On failure, negative value.
203  */
204 static inline int
205 rte_em_dev_atomic_write_link_status(struct rte_eth_dev *dev,
206                                 struct rte_eth_link *link)
207 {
208         struct rte_eth_link *dst = &(dev->data->dev_link);
209         struct rte_eth_link *src = link;
210
211         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
212                                         *(uint64_t *)src) == 0)
213                 return -1;
214
215         return 0;
216 }
217
218 static int
219 eth_em_dev_init(struct rte_eth_dev *eth_dev)
220 {
221         struct rte_pci_device *pci_dev;
222         struct e1000_hw *hw =
223                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
224         struct e1000_vfta * shadow_vfta =
225                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
226
227         pci_dev = eth_dev->pci_dev;
228         eth_dev->dev_ops = &eth_em_ops;
229         eth_dev->rx_pkt_burst = (eth_rx_burst_t)&eth_em_recv_pkts;
230         eth_dev->tx_pkt_burst = (eth_tx_burst_t)&eth_em_xmit_pkts;
231
232         /* for secondary processes, we don't initialise any further as primary
233          * has already done this work. Only check we don't need a different
234          * RX function */
235         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
236                 if (eth_dev->data->scattered_rx)
237                         eth_dev->rx_pkt_burst =
238                                 (eth_rx_burst_t)&eth_em_recv_scattered_pkts;
239                 return 0;
240         }
241
242         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
243         hw->device_id = pci_dev->id.device_id;
244
245         /* For ICH8 support we'll need to map the flash memory BAR */
246
247         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
248                         em_hw_init(hw) != 0) {
249                 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
250                         "failed to init HW",
251                         eth_dev->data->port_id, pci_dev->id.vendor_id,
252                         pci_dev->id.device_id);
253                 return -(ENODEV);
254         }
255
256         /* Allocate memory for storing MAC addresses */
257         eth_dev->data->mac_addrs = rte_zmalloc("e1000", ETHER_ADDR_LEN *
258                         hw->mac.rar_entry_count, 0);
259         if (eth_dev->data->mac_addrs == NULL) {
260                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
261                         "store MAC addresses",
262                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
263                 return -(ENOMEM);
264         }
265
266         /* Copy the permanent MAC address */
267         ether_addr_copy((struct ether_addr *) hw->mac.addr,
268                 eth_dev->data->mac_addrs);
269
270         /* initialize the vfta */
271         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
272
273         PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x",
274                      eth_dev->data->port_id, pci_dev->id.vendor_id,
275                      pci_dev->id.device_id);
276
277         rte_intr_callback_register(&(pci_dev->intr_handle),
278                 eth_em_interrupt_handler, (void *)eth_dev);
279
280         return (0);
281 }
282
283 static struct eth_driver rte_em_pmd = {
284         {
285                 .name = "rte_em_pmd",
286                 .id_table = pci_id_em_map,
287                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
288         },
289         .eth_dev_init = eth_em_dev_init,
290         .dev_private_size = sizeof(struct e1000_adapter),
291 };
292
293 static int
294 rte_em_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
295 {
296         rte_eth_driver_register(&rte_em_pmd);
297         return 0;
298 }
299
300 static int
301 em_hw_init(struct e1000_hw *hw)
302 {
303         int diag;
304
305         diag = hw->mac.ops.init_params(hw);
306         if (diag != 0) {
307                 PMD_INIT_LOG(ERR, "MAC Initialization Error");
308                 return diag;
309         }
310         diag = hw->nvm.ops.init_params(hw);
311         if (diag != 0) {
312                 PMD_INIT_LOG(ERR, "NVM Initialization Error");
313                 return diag;
314         }
315         diag = hw->phy.ops.init_params(hw);
316         if (diag != 0) {
317                 PMD_INIT_LOG(ERR, "PHY Initialization Error");
318                 return diag;
319         }
320         (void) e1000_get_bus_info(hw);
321
322         hw->mac.autoneg = 1;
323         hw->phy.autoneg_wait_to_complete = 0;
324         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
325
326         e1000_init_script_state_82541(hw, TRUE);
327         e1000_set_tbi_compatibility_82543(hw, TRUE);
328
329         /* Copper options */
330         if (hw->phy.media_type == e1000_media_type_copper) {
331                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
332                 hw->phy.disable_polarity_correction = 0;
333                 hw->phy.ms_type = e1000_ms_hw_default;
334         }
335
336         /*
337          * Start from a known state, this is important in reading the nvm
338          * and mac from that.
339          */
340         e1000_reset_hw(hw);
341
342         /* Make sure we have a good EEPROM before we read from it */
343         if (e1000_validate_nvm_checksum(hw) < 0) {
344                 /*
345                  * Some PCI-E parts fail the first check due to
346                  * the link being in sleep state, call it again,
347                  * if it fails a second time its a real issue.
348                  */
349                 diag = e1000_validate_nvm_checksum(hw);
350                 if (diag < 0) {
351                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
352                         goto error;
353                 }
354         }
355
356         /* Read the permanent MAC address out of the EEPROM */
357         diag = e1000_read_mac_addr(hw);
358         if (diag != 0) {
359                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
360                 goto error;
361         }
362
363         /* Now initialize the hardware */
364         diag = em_hardware_init(hw);
365         if (diag != 0) {
366                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
367                 goto error;
368         }
369
370         hw->mac.get_link_status = 1;
371
372         /* Indicate SOL/IDER usage */
373         diag = e1000_check_reset_block(hw);
374         if (diag < 0) {
375                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
376                         "SOL/IDER session");
377         }
378         return (0);
379
380 error:
381         em_hw_control_release(hw);
382         return (diag);
383 }
384
385 static int
386 eth_em_configure(struct rte_eth_dev *dev)
387 {
388         struct e1000_interrupt *intr =
389                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
390
391         PMD_INIT_FUNC_TRACE();
392         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
393         PMD_INIT_FUNC_TRACE();
394
395         return (0);
396 }
397
398 static void
399 em_set_pba(struct e1000_hw *hw)
400 {
401         uint32_t pba;
402
403         /*
404          * Packet Buffer Allocation (PBA)
405          * Writing PBA sets the receive portion of the buffer
406          * the remainder is used for the transmit buffer.
407          * Devices before the 82547 had a Packet Buffer of 64K.
408          * After the 82547 the buffer was reduced to 40K.
409          */
410         switch (hw->mac.type) {
411                 case e1000_82547:
412                 case e1000_82547_rev_2:
413                 /* 82547: Total Packet Buffer is 40K */
414                         pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
415                         break;
416                 case e1000_82571:
417                 case e1000_82572:
418                 case e1000_80003es2lan:
419                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
420                         break;
421                 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
422                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
423                         break;
424                 case e1000_82574:
425                 case e1000_82583:
426                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
427                         break;
428                 case e1000_ich8lan:
429                         pba = E1000_PBA_8K;
430                         break;
431                 case e1000_ich9lan:
432                 case e1000_ich10lan:
433                         pba = E1000_PBA_10K;
434                         break;
435                 case e1000_pchlan:
436                 case e1000_pch2lan:
437                         pba = E1000_PBA_26K;
438                         break;
439                 default:
440                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
441         }
442
443         E1000_WRITE_REG(hw, E1000_PBA, pba);
444 }
445
446 static int
447 eth_em_start(struct rte_eth_dev *dev)
448 {
449         struct e1000_hw *hw =
450                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
451         int ret, mask;
452
453         PMD_INIT_FUNC_TRACE();
454
455         eth_em_stop(dev);
456
457         e1000_power_up_phy(hw);
458
459         /* Set default PBA value */
460         em_set_pba(hw);
461
462         /* Put the address into the Receive Address Array */
463         e1000_rar_set(hw, hw->mac.addr, 0);
464
465         /*
466          * With the 82571 adapter, RAR[0] may be overwritten
467          * when the other port is reset, we make a duplicate
468          * in RAR[14] for that eventuality, this assures
469          * the interface continues to function.
470          */
471         if (hw->mac.type == e1000_82571) {
472                 e1000_set_laa_state_82571(hw, TRUE);
473                 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
474         }
475
476         /* Initialize the hardware */
477         if (em_hardware_init(hw)) {
478                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
479                 return (-EIO);
480         }
481
482         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
483
484         /* Configure for OS presence */
485         em_init_manageability(hw);
486
487         eth_em_tx_init(dev);
488
489         ret = eth_em_rx_init(dev);
490         if (ret) {
491                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
492                 em_dev_clear_queues(dev);
493                 return ret;
494         }
495
496         e1000_clear_hw_cntrs_base_generic(hw);
497
498         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
499                         ETH_VLAN_EXTEND_MASK;
500         eth_em_vlan_offload_set(dev, mask);
501
502         /* Set Interrupt Throttling Rate to maximum allowed value. */
503         E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
504
505         /* Setup link speed and duplex */
506         switch (dev->data->dev_conf.link_speed) {
507         case ETH_LINK_SPEED_AUTONEG:
508                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
509                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
510                 else if (dev->data->dev_conf.link_duplex ==
511                                         ETH_LINK_HALF_DUPLEX)
512                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
513                 else if (dev->data->dev_conf.link_duplex ==
514                                         ETH_LINK_FULL_DUPLEX)
515                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
516                 else
517                         goto error_invalid_config;
518                 break;
519         case ETH_LINK_SPEED_10:
520                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
521                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
522                 else if (dev->data->dev_conf.link_duplex ==
523                                         ETH_LINK_HALF_DUPLEX)
524                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
525                 else if (dev->data->dev_conf.link_duplex ==
526                                         ETH_LINK_FULL_DUPLEX)
527                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
528                 else
529                         goto error_invalid_config;
530                 break;
531         case ETH_LINK_SPEED_100:
532                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
533                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
534                 else if (dev->data->dev_conf.link_duplex ==
535                                         ETH_LINK_HALF_DUPLEX)
536                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
537                 else if (dev->data->dev_conf.link_duplex ==
538                                         ETH_LINK_FULL_DUPLEX)
539                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
540                 else
541                         goto error_invalid_config;
542                 break;
543         case ETH_LINK_SPEED_1000:
544                 if ((dev->data->dev_conf.link_duplex ==
545                                 ETH_LINK_AUTONEG_DUPLEX) ||
546                         (dev->data->dev_conf.link_duplex ==
547                                         ETH_LINK_FULL_DUPLEX))
548                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
549                 else
550                         goto error_invalid_config;
551                 break;
552         case ETH_LINK_SPEED_10000:
553         default:
554                 goto error_invalid_config;
555         }
556         e1000_setup_link(hw);
557
558         /* check if lsc interrupt feature is enabled */
559         if (dev->data->dev_conf.intr_conf.lsc != 0) {
560                 ret = eth_em_interrupt_setup(dev);
561                 if (ret) {
562                         PMD_INIT_LOG(ERR, "Unable to setup interrupts");
563                         em_dev_clear_queues(dev);
564                         return ret;
565                 }
566         }
567
568         PMD_INIT_LOG(DEBUG, "<<");
569
570         return (0);
571
572 error_invalid_config:
573         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u",
574                      dev->data->dev_conf.link_speed,
575                      dev->data->dev_conf.link_duplex, dev->data->port_id);
576         em_dev_clear_queues(dev);
577         return (-EINVAL);
578 }
579
580 /*********************************************************************
581  *
582  *  This routine disables all traffic on the adapter by issuing a
583  *  global reset on the MAC.
584  *
585  **********************************************************************/
586 static void
587 eth_em_stop(struct rte_eth_dev *dev)
588 {
589         struct rte_eth_link link;
590         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
591
592         em_intr_disable(hw);
593         e1000_reset_hw(hw);
594         if (hw->mac.type >= e1000_82544)
595                 E1000_WRITE_REG(hw, E1000_WUC, 0);
596
597         /* Power down the phy. Needed to make the link go down */
598         e1000_power_down_phy(hw);
599
600         em_dev_clear_queues(dev);
601
602         /* clear the recorded link status */
603         memset(&link, 0, sizeof(link));
604         rte_em_dev_atomic_write_link_status(dev, &link);
605 }
606
607 static void
608 eth_em_close(struct rte_eth_dev *dev)
609 {
610         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
611
612         eth_em_stop(dev);
613         e1000_phy_hw_reset(hw);
614         em_release_manageability(hw);
615         em_hw_control_release(hw);
616 }
617
618 static int
619 em_get_rx_buffer_size(struct e1000_hw *hw)
620 {
621         uint32_t rx_buf_size;
622
623         rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
624         return rx_buf_size;
625 }
626
627 /*********************************************************************
628  *
629  *  Initialize the hardware
630  *
631  **********************************************************************/
632 static int
633 em_hardware_init(struct e1000_hw *hw)
634 {
635         uint32_t rx_buf_size;
636         int diag;
637
638         /* Issue a global reset */
639         e1000_reset_hw(hw);
640
641         /* Let the firmware know the OS is in control */
642         em_hw_control_acquire(hw);
643
644         /*
645          * These parameters control the automatic generation (Tx) and
646          * response (Rx) to Ethernet PAUSE frames.
647          * - High water mark should allow for at least two standard size (1518)
648          *   frames to be received after sending an XOFF.
649          * - Low water mark works best when it is very near the high water mark.
650          *   This allows the receiver to restart by sending XON when it has
651          *   drained a bit. Here we use an arbitrary value of 1500 which will
652          *   restart after one full frame is pulled from the buffer. There
653          *   could be several smaller frames in the buffer and if so they will
654          *   not trigger the XON until their total number reduces the buffer
655          *   by 1500.
656          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
657          */
658         rx_buf_size = em_get_rx_buffer_size(hw);
659
660         hw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);
661         hw->fc.low_water = hw->fc.high_water - 1500;
662
663         if (hw->mac.type == e1000_80003es2lan)
664                 hw->fc.pause_time = UINT16_MAX;
665         else
666                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
667
668         hw->fc.send_xon = 1;
669
670         /* Set Flow control, use the tunable location if sane */
671         if (em_fc_setting <= e1000_fc_full)
672                 hw->fc.requested_mode = em_fc_setting;
673         else
674                 hw->fc.requested_mode = e1000_fc_none;
675
676         /* Workaround: no TX flow ctrl for PCH */
677         if (hw->mac.type == e1000_pchlan)
678                 hw->fc.requested_mode = e1000_fc_rx_pause;
679
680         /* Override - settings for PCH2LAN, ya its magic :) */
681         if (hw->mac.type == e1000_pch2lan) {
682                 hw->fc.high_water = 0x5C20;
683                 hw->fc.low_water = 0x5048;
684                 hw->fc.pause_time = 0x0650;
685                 hw->fc.refresh_time = 0x0400;
686         }
687
688         diag = e1000_init_hw(hw);
689         if (diag < 0)
690                 return (diag);
691         e1000_check_for_link(hw);
692         return (0);
693 }
694
695 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
696 static void
697 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
698 {
699         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
700         struct e1000_hw_stats *stats =
701                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
702         int pause_frames;
703
704         if(hw->phy.media_type == e1000_media_type_copper ||
705                         (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
706                 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
707                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
708         }
709
710         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
711         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
712         stats->scc += E1000_READ_REG(hw, E1000_SCC);
713         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
714
715         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
716         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
717         stats->colc += E1000_READ_REG(hw, E1000_COLC);
718         stats->dc += E1000_READ_REG(hw, E1000_DC);
719         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
720         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
721         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
722
723         /*
724          * For watchdog management we need to know if we have been
725          * paused during the last interval, so capture that here.
726          */
727         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
728         stats->xoffrxc += pause_frames;
729         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
730         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
731         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
732         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
733         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
734         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
735         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
736         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
737         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
738         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
739         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
740         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
741
742         /*
743          * For the 64-bit byte counters the low dword must be read first.
744          * Both registers clear on the read of the high dword.
745          */
746
747         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
748         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
749         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
750         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
751
752         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
753         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
754         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
755         stats->roc += E1000_READ_REG(hw, E1000_ROC);
756         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
757
758         stats->tor += E1000_READ_REG(hw, E1000_TORH);
759         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
760
761         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
762         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
763         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
764         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
765         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
766         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
767         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
768         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
769         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
770         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
771
772         /* Interrupt Counts */
773
774         if (hw->mac.type >= e1000_82571) {
775                 stats->iac += E1000_READ_REG(hw, E1000_IAC);
776                 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
777                 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
778                 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
779                 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
780                 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
781                 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
782                 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
783                 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
784         }
785
786         if (hw->mac.type >= e1000_82543) {
787                 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
788                 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
789                 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
790                 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
791                 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
792                 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
793         }
794
795         if (rte_stats == NULL)
796                 return;
797
798         /* Rx Errors */
799         rte_stats->ibadcrc = stats->crcerrs;
800         rte_stats->ibadlen = stats->rlec + stats->ruc + stats->roc;
801         rte_stats->imissed = stats->mpc;
802         rte_stats->ierrors = rte_stats->ibadcrc +
803                              rte_stats->ibadlen +
804                              rte_stats->imissed +
805                              stats->rxerrc + stats->algnerrc + stats->cexterr;
806
807         /* Tx Errors */
808         rte_stats->oerrors = stats->ecol + stats->latecol;
809
810         rte_stats->ipackets = stats->gprc;
811         rte_stats->opackets = stats->gptc;
812         rte_stats->ibytes   = stats->gorc;
813         rte_stats->obytes   = stats->gotc;
814
815         /* XON/XOFF pause frames stats registers */
816         rte_stats->tx_pause_xon  = stats->xontxc;
817         rte_stats->rx_pause_xon  = stats->xonrxc;
818         rte_stats->tx_pause_xoff = stats->xofftxc;
819         rte_stats->rx_pause_xoff = stats->xoffrxc;
820 }
821
822 static void
823 eth_em_stats_reset(struct rte_eth_dev *dev)
824 {
825         struct e1000_hw_stats *hw_stats =
826                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
827
828         /* HW registers are cleared on read */
829         eth_em_stats_get(dev, NULL);
830
831         /* Reset software totals */
832         memset(hw_stats, 0, sizeof(*hw_stats));
833 }
834
835 static uint32_t
836 em_get_max_pktlen(const struct e1000_hw *hw)
837 {
838         switch (hw->mac.type) {
839         case e1000_82571:
840         case e1000_82572:
841         case e1000_ich9lan:
842         case e1000_ich10lan:
843         case e1000_pch2lan:
844         case e1000_82574:
845         case e1000_80003es2lan: /* 9K Jumbo Frame size */
846                 return (0x2412);
847         case e1000_pchlan:
848                 return (0x1000);
849         /* Adapters that do not support jumbo frames */
850         case e1000_82583:
851         case e1000_ich8lan:
852                 return (ETHER_MAX_LEN);
853         default:
854                 return (MAX_JUMBO_FRAME_SIZE);
855         }
856 }
857
858 static void
859 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
860 {
861         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
862
863         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
864         dev_info->max_rx_pktlen = em_get_max_pktlen(hw);
865         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
866
867         /*
868          * Starting with 631xESB hw supports 2 TX/RX queues per port.
869          * Unfortunatelly, all these nics have just one TX context.
870          * So we have few choises for TX:
871          * - Use just one TX queue.
872          * - Allow cksum offload only for one TX queue.
873          * - Don't allow TX cksum offload at all.
874          * For now, option #1 was chosen.
875          * To use second RX queue we have to use extended RX descriptor
876          * (Multiple Receive Queues are mutually exclusive with UDP
877          * fragmentation and are not supported when a legacy receive
878          * descriptor format is used).
879          * Which means separate RX routinies - as legacy nics (82540, 82545)
880          * don't support extended RXD.
881          * To avoid it we support just one RX queue for now (no RSS).
882          */
883
884         dev_info->max_rx_queues = 1;
885         dev_info->max_tx_queues = 1;
886 }
887
888 /* return 0 means link status changed, -1 means not changed */
889 static int
890 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
891 {
892         struct e1000_hw *hw =
893                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
894         struct rte_eth_link link, old;
895         int link_check, count;
896
897         link_check = 0;
898         hw->mac.get_link_status = 1;
899
900         /* possible wait-to-complete in up to 9 seconds */
901         for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
902                 /* Read the real link status */
903                 switch (hw->phy.media_type) {
904                 case e1000_media_type_copper:
905                         /* Do the work to read phy */
906                         e1000_check_for_link(hw);
907                         link_check = !hw->mac.get_link_status;
908                         break;
909
910                 case e1000_media_type_fiber:
911                         e1000_check_for_link(hw);
912                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
913                                         E1000_STATUS_LU);
914                         break;
915
916                 case e1000_media_type_internal_serdes:
917                         e1000_check_for_link(hw);
918                         link_check = hw->mac.serdes_has_link;
919                         break;
920
921                 default:
922                         break;
923                 }
924                 if (link_check || wait_to_complete == 0)
925                         break;
926                 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
927         }
928         memset(&link, 0, sizeof(link));
929         rte_em_dev_atomic_read_link_status(dev, &link);
930         old = link;
931
932         /* Now we check if a transition has happened */
933         if (link_check && (link.link_status == 0)) {
934                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
935                         &link.link_duplex);
936                 link.link_status = 1;
937         } else if (!link_check && (link.link_status == 1)) {
938                 link.link_speed = 0;
939                 link.link_duplex = 0;
940                 link.link_status = 0;
941         }
942         rte_em_dev_atomic_write_link_status(dev, &link);
943
944         /* not changed */
945         if (old.link_status == link.link_status)
946                 return -1;
947
948         /* changed */
949         return 0;
950 }
951
952 /*
953  * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
954  * For ASF and Pass Through versions of f/w this means
955  * that the driver is loaded. For AMT version type f/w
956  * this means that the network i/f is open.
957  */
958 static void
959 em_hw_control_acquire(struct e1000_hw *hw)
960 {
961         uint32_t ctrl_ext, swsm;
962
963         /* Let firmware know the driver has taken over */
964         if (hw->mac.type == e1000_82573) {
965                 swsm = E1000_READ_REG(hw, E1000_SWSM);
966                 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
967
968         } else {
969                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
970                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
971                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
972         }
973 }
974
975 /*
976  * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
977  * For ASF and Pass Through versions of f/w this means that the
978  * driver is no longer loaded. For AMT versions of the
979  * f/w this means that the network i/f is closed.
980  */
981 static void
982 em_hw_control_release(struct e1000_hw *hw)
983 {
984         uint32_t ctrl_ext, swsm;
985
986         /* Let firmware taken over control of h/w */
987         if (hw->mac.type == e1000_82573) {
988                 swsm = E1000_READ_REG(hw, E1000_SWSM);
989                 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
990         } else {
991                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
992                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
993                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
994         }
995 }
996
997 /*
998  * Bit of a misnomer, what this really means is
999  * to enable OS management of the system... aka
1000  * to disable special hardware management features.
1001  */
1002 static void
1003 em_init_manageability(struct e1000_hw *hw)
1004 {
1005         if (e1000_enable_mng_pass_thru(hw)) {
1006                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1007                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1008
1009                 /* disable hardware interception of ARP */
1010                 manc &= ~(E1000_MANC_ARP_EN);
1011
1012                 /* enable receiving management packets to the host */
1013                 manc |= E1000_MANC_EN_MNG2HOST;
1014                 manc2h |= 1 << 5;  /* Mng Port 623 */
1015                 manc2h |= 1 << 6;  /* Mng Port 664 */
1016                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1017                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1018         }
1019 }
1020
1021 /*
1022  * Give control back to hardware management
1023  * controller if there is one.
1024  */
1025 static void
1026 em_release_manageability(struct e1000_hw *hw)
1027 {
1028         uint32_t manc;
1029
1030         if (e1000_enable_mng_pass_thru(hw)) {
1031                 manc = E1000_READ_REG(hw, E1000_MANC);
1032
1033                 /* re-enable hardware interception of ARP */
1034                 manc |= E1000_MANC_ARP_EN;
1035                 manc &= ~E1000_MANC_EN_MNG2HOST;
1036
1037                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1038         }
1039 }
1040
1041 static void
1042 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1043 {
1044         struct e1000_hw *hw =
1045                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1046         uint32_t rctl;
1047
1048         rctl = E1000_READ_REG(hw, E1000_RCTL);
1049         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1050         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1051 }
1052
1053 static void
1054 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1055 {
1056         struct e1000_hw *hw =
1057                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1058         uint32_t rctl;
1059
1060         rctl = E1000_READ_REG(hw, E1000_RCTL);
1061         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1062         if (dev->data->all_multicast == 1)
1063                 rctl |= E1000_RCTL_MPE;
1064         else
1065                 rctl &= (~E1000_RCTL_MPE);
1066         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1067 }
1068
1069 static void
1070 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1071 {
1072         struct e1000_hw *hw =
1073                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1074         uint32_t rctl;
1075
1076         rctl = E1000_READ_REG(hw, E1000_RCTL);
1077         rctl |= E1000_RCTL_MPE;
1078         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1079 }
1080
1081 static void
1082 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1083 {
1084         struct e1000_hw *hw =
1085                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1086         uint32_t rctl;
1087
1088         if (dev->data->promiscuous == 1)
1089                 return; /* must remain in all_multicast mode */
1090         rctl = E1000_READ_REG(hw, E1000_RCTL);
1091         rctl &= (~E1000_RCTL_MPE);
1092         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1093 }
1094
1095 static int
1096 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1097 {
1098         struct e1000_hw *hw =
1099                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1100         struct e1000_vfta * shadow_vfta =
1101                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1102         uint32_t vfta;
1103         uint32_t vid_idx;
1104         uint32_t vid_bit;
1105
1106         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1107                               E1000_VFTA_ENTRY_MASK);
1108         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1109         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1110         if (on)
1111                 vfta |= vid_bit;
1112         else
1113                 vfta &= ~vid_bit;
1114         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1115
1116         /* update local VFTA copy */
1117         shadow_vfta->vfta[vid_idx] = vfta;
1118
1119         return 0;
1120 }
1121
1122 static void
1123 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1124 {
1125         struct e1000_hw *hw =
1126                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1127         uint32_t reg;
1128
1129         /* Filter Table Disable */
1130         reg = E1000_READ_REG(hw, E1000_RCTL);
1131         reg &= ~E1000_RCTL_CFIEN;
1132         reg &= ~E1000_RCTL_VFE;
1133         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1134 }
1135
1136 static void
1137 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1138 {
1139         struct e1000_hw *hw =
1140                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1141         struct e1000_vfta * shadow_vfta =
1142                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1143         uint32_t reg;
1144         int i;
1145
1146         /* Filter Table Enable, CFI not used for packet acceptance */
1147         reg = E1000_READ_REG(hw, E1000_RCTL);
1148         reg &= ~E1000_RCTL_CFIEN;
1149         reg |= E1000_RCTL_VFE;
1150         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1151
1152         /* restore vfta from local copy */
1153         for (i = 0; i < IGB_VFTA_SIZE; i++)
1154                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1155 }
1156
1157 static void
1158 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1159 {
1160         struct e1000_hw *hw =
1161                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1162         uint32_t reg;
1163
1164         /* VLAN Mode Disable */
1165         reg = E1000_READ_REG(hw, E1000_CTRL);
1166         reg &= ~E1000_CTRL_VME;
1167         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1168
1169 }
1170
1171 static void
1172 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1173 {
1174         struct e1000_hw *hw =
1175                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1176         uint32_t reg;
1177
1178         /* VLAN Mode Enable */
1179         reg = E1000_READ_REG(hw, E1000_CTRL);
1180         reg |= E1000_CTRL_VME;
1181         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1182 }
1183
1184 static void
1185 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1186 {
1187         if(mask & ETH_VLAN_STRIP_MASK){
1188                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1189                         em_vlan_hw_strip_enable(dev);
1190                 else
1191                         em_vlan_hw_strip_disable(dev);
1192         }
1193
1194         if(mask & ETH_VLAN_FILTER_MASK){
1195                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1196                         em_vlan_hw_filter_enable(dev);
1197                 else
1198                         em_vlan_hw_filter_disable(dev);
1199         }
1200 }
1201
1202 static void
1203 em_intr_disable(struct e1000_hw *hw)
1204 {
1205         E1000_WRITE_REG(hw, E1000_IMC, ~0);
1206 }
1207
1208 /**
1209  * It enables the interrupt mask and then enable the interrupt.
1210  *
1211  * @param dev
1212  *  Pointer to struct rte_eth_dev.
1213  *
1214  * @return
1215  *  - On success, zero.
1216  *  - On failure, a negative value.
1217  */
1218 static int
1219 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1220 {
1221         struct e1000_hw *hw =
1222                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1223
1224         E1000_WRITE_REG(hw, E1000_IMS, E1000_ICR_LSC);
1225         rte_intr_enable(&(dev->pci_dev->intr_handle));
1226         return (0);
1227 }
1228
1229 /*
1230  * It reads ICR and gets interrupt causes, check it and set a bit flag
1231  * to update link status.
1232  *
1233  * @param dev
1234  *  Pointer to struct rte_eth_dev.
1235  *
1236  * @return
1237  *  - On success, zero.
1238  *  - On failure, a negative value.
1239  */
1240 static int
1241 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1242 {
1243         uint32_t icr;
1244         struct e1000_hw *hw =
1245                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1246         struct e1000_interrupt *intr =
1247                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1248
1249         /* read-on-clear nic registers here */
1250         icr = E1000_READ_REG(hw, E1000_ICR);
1251         if (icr & E1000_ICR_LSC) {
1252                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1253         }
1254
1255         return 0;
1256 }
1257
1258 /*
1259  * It executes link_update after knowing an interrupt is prsent.
1260  *
1261  * @param dev
1262  *  Pointer to struct rte_eth_dev.
1263  *
1264  * @return
1265  *  - On success, zero.
1266  *  - On failure, a negative value.
1267  */
1268 static int
1269 eth_em_interrupt_action(struct rte_eth_dev *dev)
1270 {
1271         struct e1000_hw *hw =
1272                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1273         struct e1000_interrupt *intr =
1274                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1275         uint32_t tctl, rctl;
1276         struct rte_eth_link link;
1277         int ret;
1278
1279         if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1280                 return -1;
1281
1282         intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1283         rte_intr_enable(&(dev->pci_dev->intr_handle));
1284
1285         /* set get_link_status to check register later */
1286         hw->mac.get_link_status = 1;
1287         ret = eth_em_link_update(dev, 0);
1288
1289         /* check if link has changed */
1290         if (ret < 0)
1291                 return 0;
1292
1293         memset(&link, 0, sizeof(link));
1294         rte_em_dev_atomic_read_link_status(dev, &link);
1295         if (link.link_status) {
1296                 PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s",
1297                              dev->data->port_id, (unsigned)link.link_speed,
1298                              link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1299                              "full-duplex" : "half-duplex");
1300         } else {
1301                 PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
1302         }
1303         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1304                      dev->pci_dev->addr.domain, dev->pci_dev->addr.bus,
1305                      dev->pci_dev->addr.devid, dev->pci_dev->addr.function);
1306         tctl = E1000_READ_REG(hw, E1000_TCTL);
1307         rctl = E1000_READ_REG(hw, E1000_RCTL);
1308         if (link.link_status) {
1309                 /* enable Tx/Rx */
1310                 tctl |= E1000_TCTL_EN;
1311                 rctl |= E1000_RCTL_EN;
1312         } else {
1313                 /* disable Tx/Rx */
1314                 tctl &= ~E1000_TCTL_EN;
1315                 rctl &= ~E1000_RCTL_EN;
1316         }
1317         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1318         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1319         E1000_WRITE_FLUSH(hw);
1320
1321         return 0;
1322 }
1323
1324 /**
1325  * Interrupt handler which shall be registered at first.
1326  *
1327  * @param handle
1328  *  Pointer to interrupt handle.
1329  * @param param
1330  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1331  *
1332  * @return
1333  *  void
1334  */
1335 static void
1336 eth_em_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1337                                                         void *param)
1338 {
1339         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1340
1341         eth_em_interrupt_get_status(dev);
1342         eth_em_interrupt_action(dev);
1343         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1344 }
1345
1346 static int
1347 eth_em_led_on(struct rte_eth_dev *dev)
1348 {
1349         struct e1000_hw *hw;
1350
1351         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1352         return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1353 }
1354
1355 static int
1356 eth_em_led_off(struct rte_eth_dev *dev)
1357 {
1358         struct e1000_hw *hw;
1359
1360         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1361         return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1362 }
1363
1364 static int
1365 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1366 {
1367         struct e1000_hw *hw;
1368         uint32_t ctrl;
1369         int tx_pause;
1370         int rx_pause;
1371
1372         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1373         fc_conf->pause_time = hw->fc.pause_time;
1374         fc_conf->high_water = hw->fc.high_water;
1375         fc_conf->low_water = hw->fc.low_water;
1376         fc_conf->send_xon = hw->fc.send_xon;
1377         fc_conf->autoneg = hw->mac.autoneg;
1378
1379         /*
1380          * Return rx_pause and tx_pause status according to actual setting of
1381          * the TFCE and RFCE bits in the CTRL register.
1382          */
1383         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1384         if (ctrl & E1000_CTRL_TFCE)
1385                 tx_pause = 1;
1386         else
1387                 tx_pause = 0;
1388
1389         if (ctrl & E1000_CTRL_RFCE)
1390                 rx_pause = 1;
1391         else
1392                 rx_pause = 0;
1393
1394         if (rx_pause && tx_pause)
1395                 fc_conf->mode = RTE_FC_FULL;
1396         else if (rx_pause)
1397                 fc_conf->mode = RTE_FC_RX_PAUSE;
1398         else if (tx_pause)
1399                 fc_conf->mode = RTE_FC_TX_PAUSE;
1400         else
1401                 fc_conf->mode = RTE_FC_NONE;
1402
1403         return 0;
1404 }
1405
1406 static int
1407 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1408 {
1409         struct e1000_hw *hw;
1410         int err;
1411         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1412                 e1000_fc_none,
1413                 e1000_fc_rx_pause,
1414                 e1000_fc_tx_pause,
1415                 e1000_fc_full
1416         };
1417         uint32_t rx_buf_size;
1418         uint32_t max_high_water;
1419         uint32_t rctl;
1420
1421         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1422         if (fc_conf->autoneg != hw->mac.autoneg)
1423                 return -ENOTSUP;
1424         rx_buf_size = em_get_rx_buffer_size(hw);
1425         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1426
1427         /* At least reserve one Ethernet frame for watermark */
1428         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1429         if ((fc_conf->high_water > max_high_water) ||
1430             (fc_conf->high_water < fc_conf->low_water)) {
1431                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1432                 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
1433                 return (-EINVAL);
1434         }
1435
1436         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1437         hw->fc.pause_time     = fc_conf->pause_time;
1438         hw->fc.high_water     = fc_conf->high_water;
1439         hw->fc.low_water      = fc_conf->low_water;
1440         hw->fc.send_xon       = fc_conf->send_xon;
1441
1442         err = e1000_setup_link_generic(hw);
1443         if (err == E1000_SUCCESS) {
1444
1445                 /* check if we want to forward MAC frames - driver doesn't have native
1446                  * capability to do that, so we'll write the registers ourselves */
1447
1448                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1449
1450                 /* set or clear MFLCN.PMCF bit depending on configuration */
1451                 if (fc_conf->mac_ctrl_frame_fwd != 0)
1452                         rctl |= E1000_RCTL_PMCF;
1453                 else
1454                         rctl &= ~E1000_RCTL_PMCF;
1455
1456                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1457                 E1000_WRITE_FLUSH(hw);
1458
1459                 return 0;
1460         }
1461
1462         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1463         return (-EIO);
1464 }
1465
1466 static void
1467 eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1468                 uint32_t index, __rte_unused uint32_t pool)
1469 {
1470         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1471
1472         e1000_rar_set(hw, mac_addr->addr_bytes, index);
1473 }
1474
1475 static void
1476 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1477 {
1478         uint8_t addr[ETHER_ADDR_LEN];
1479         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1480
1481         memset(addr, 0, sizeof(addr));
1482
1483         e1000_rar_set(hw, addr, index);
1484 }
1485
1486 static int
1487 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1488 {
1489         struct rte_eth_dev_info dev_info;
1490         struct e1000_hw *hw;
1491         uint32_t frame_size;
1492         uint32_t rctl;
1493
1494         eth_em_infos_get(dev, &dev_info);
1495         frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE;
1496
1497         /* check that mtu is within the allowed range */
1498         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1499                 return -EINVAL;
1500
1501         /* refuse mtu that requires the support of scattered packets when this
1502          * feature has not been enabled before. */
1503         if (!dev->data->scattered_rx &&
1504             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1505                 return -EINVAL;
1506
1507         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1508         rctl = E1000_READ_REG(hw, E1000_RCTL);
1509
1510         /* switch to jumbo mode if needed */
1511         if (frame_size > ETHER_MAX_LEN) {
1512                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1513                 rctl |= E1000_RCTL_LPE;
1514         } else {
1515                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1516                 rctl &= ~E1000_RCTL_LPE;
1517         }
1518         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1519
1520         /* update max frame size */
1521         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1522         return 0;
1523 }
1524
1525 struct rte_driver em_pmd_drv = {
1526         .type = PMD_PDEV,
1527         .init = rte_em_pmd_init,
1528 };
1529
1530 PMD_REGISTER_DRIVER(em_pmd_drv);