4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
40 #include <rte_common.h>
41 #include <rte_interrupts.h>
42 #include <rte_byteorder.h>
44 #include <rte_debug.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memory.h>
49 #include <rte_memzone.h>
51 #include <rte_atomic.h>
52 #include <rte_malloc.h>
55 #include "e1000_logs.h"
56 #include "base/e1000_api.h"
57 #include "e1000_ethdev.h"
59 #define EM_EIAC 0x000DC
61 #define PMD_ROUNDUP(x,y) (((x) + (y) - 1)/(y) * (y))
64 static int eth_em_configure(struct rte_eth_dev *dev);
65 static int eth_em_start(struct rte_eth_dev *dev);
66 static void eth_em_stop(struct rte_eth_dev *dev);
67 static void eth_em_close(struct rte_eth_dev *dev);
68 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
69 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
70 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
71 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
72 static int eth_em_link_update(struct rte_eth_dev *dev,
73 int wait_to_complete);
74 static void eth_em_stats_get(struct rte_eth_dev *dev,
75 struct rte_eth_stats *rte_stats);
76 static void eth_em_stats_reset(struct rte_eth_dev *dev);
77 static void eth_em_infos_get(struct rte_eth_dev *dev,
78 struct rte_eth_dev_info *dev_info);
79 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
80 struct rte_eth_fc_conf *fc_conf);
81 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
82 struct rte_eth_fc_conf *fc_conf);
83 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
84 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
85 static int eth_em_interrupt_action(struct rte_eth_dev *dev);
86 static void eth_em_interrupt_handler(struct rte_intr_handle *handle,
89 static int em_hw_init(struct e1000_hw *hw);
90 static int em_hardware_init(struct e1000_hw *hw);
91 static void em_hw_control_acquire(struct e1000_hw *hw);
92 static void em_hw_control_release(struct e1000_hw *hw);
93 static void em_init_manageability(struct e1000_hw *hw);
94 static void em_release_manageability(struct e1000_hw *hw);
96 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
98 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
99 uint16_t vlan_id, int on);
100 static void eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
101 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
102 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
103 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
104 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
107 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
108 uint16_t vlan_id, int on);
110 static int eth_em_led_on(struct rte_eth_dev *dev);
111 static int eth_em_led_off(struct rte_eth_dev *dev);
113 static void em_intr_disable(struct e1000_hw *hw);
114 static int em_get_rx_buffer_size(struct e1000_hw *hw);
115 static void eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
116 uint32_t index, uint32_t pool);
117 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
119 #define EM_FC_PAUSE_TIME 0x0680
120 #define EM_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
121 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
123 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
126 * The set of PCI devices this driver supports
128 static const struct rte_pci_id pci_id_em_map[] = {
130 #define RTE_PCI_DEV_ID_DECL_EM(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
131 #include "rte_pci_dev_ids.h"
136 static const struct eth_dev_ops eth_em_ops = {
137 .dev_configure = eth_em_configure,
138 .dev_start = eth_em_start,
139 .dev_stop = eth_em_stop,
140 .dev_close = eth_em_close,
141 .promiscuous_enable = eth_em_promiscuous_enable,
142 .promiscuous_disable = eth_em_promiscuous_disable,
143 .allmulticast_enable = eth_em_allmulticast_enable,
144 .allmulticast_disable = eth_em_allmulticast_disable,
145 .link_update = eth_em_link_update,
146 .stats_get = eth_em_stats_get,
147 .stats_reset = eth_em_stats_reset,
148 .dev_infos_get = eth_em_infos_get,
149 .mtu_set = eth_em_mtu_set,
150 .vlan_filter_set = eth_em_vlan_filter_set,
151 .vlan_offload_set = eth_em_vlan_offload_set,
152 .rx_queue_setup = eth_em_rx_queue_setup,
153 .rx_queue_release = eth_em_rx_queue_release,
154 .rx_queue_count = eth_em_rx_queue_count,
155 .rx_descriptor_done = eth_em_rx_descriptor_done,
156 .tx_queue_setup = eth_em_tx_queue_setup,
157 .tx_queue_release = eth_em_tx_queue_release,
158 .dev_led_on = eth_em_led_on,
159 .dev_led_off = eth_em_led_off,
160 .flow_ctrl_get = eth_em_flow_ctrl_get,
161 .flow_ctrl_set = eth_em_flow_ctrl_set,
162 .mac_addr_add = eth_em_rar_set,
163 .mac_addr_remove = eth_em_rar_clear,
167 * Atomically reads the link status information from global
168 * structure rte_eth_dev.
171 * - Pointer to the structure rte_eth_dev to read from.
172 * - Pointer to the buffer to be saved with the link status.
175 * - On success, zero.
176 * - On failure, negative value.
179 rte_em_dev_atomic_read_link_status(struct rte_eth_dev *dev,
180 struct rte_eth_link *link)
182 struct rte_eth_link *dst = link;
183 struct rte_eth_link *src = &(dev->data->dev_link);
185 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
186 *(uint64_t *)src) == 0)
193 * Atomically writes the link status information into global
194 * structure rte_eth_dev.
197 * - Pointer to the structure rte_eth_dev to read from.
198 * - Pointer to the buffer to be saved with the link status.
201 * - On success, zero.
202 * - On failure, negative value.
205 rte_em_dev_atomic_write_link_status(struct rte_eth_dev *dev,
206 struct rte_eth_link *link)
208 struct rte_eth_link *dst = &(dev->data->dev_link);
209 struct rte_eth_link *src = link;
211 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
212 *(uint64_t *)src) == 0)
219 eth_em_dev_init(struct rte_eth_dev *eth_dev)
221 struct rte_pci_device *pci_dev;
222 struct e1000_hw *hw =
223 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
224 struct e1000_vfta * shadow_vfta =
225 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
227 pci_dev = eth_dev->pci_dev;
228 eth_dev->dev_ops = ð_em_ops;
229 eth_dev->rx_pkt_burst = (eth_rx_burst_t)ð_em_recv_pkts;
230 eth_dev->tx_pkt_burst = (eth_tx_burst_t)ð_em_xmit_pkts;
232 /* for secondary processes, we don't initialise any further as primary
233 * has already done this work. Only check we don't need a different
235 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
236 if (eth_dev->data->scattered_rx)
237 eth_dev->rx_pkt_burst =
238 (eth_rx_burst_t)ð_em_recv_scattered_pkts;
242 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
243 hw->device_id = pci_dev->id.device_id;
245 /* For ICH8 support we'll need to map the flash memory BAR */
247 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
248 em_hw_init(hw) != 0) {
249 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
251 eth_dev->data->port_id, pci_dev->id.vendor_id,
252 pci_dev->id.device_id);
256 /* Allocate memory for storing MAC addresses */
257 eth_dev->data->mac_addrs = rte_zmalloc("e1000", ETHER_ADDR_LEN *
258 hw->mac.rar_entry_count, 0);
259 if (eth_dev->data->mac_addrs == NULL) {
260 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
261 "store MAC addresses",
262 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
266 /* Copy the permanent MAC address */
267 ether_addr_copy((struct ether_addr *) hw->mac.addr,
268 eth_dev->data->mac_addrs);
270 /* initialize the vfta */
271 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
273 PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x",
274 eth_dev->data->port_id, pci_dev->id.vendor_id,
275 pci_dev->id.device_id);
277 rte_intr_callback_register(&(pci_dev->intr_handle),
278 eth_em_interrupt_handler, (void *)eth_dev);
283 static struct eth_driver rte_em_pmd = {
285 .name = "rte_em_pmd",
286 .id_table = pci_id_em_map,
287 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
289 .eth_dev_init = eth_em_dev_init,
290 .dev_private_size = sizeof(struct e1000_adapter),
294 rte_em_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
296 rte_eth_driver_register(&rte_em_pmd);
301 em_hw_init(struct e1000_hw *hw)
305 diag = hw->mac.ops.init_params(hw);
307 PMD_INIT_LOG(ERR, "MAC Initialization Error");
310 diag = hw->nvm.ops.init_params(hw);
312 PMD_INIT_LOG(ERR, "NVM Initialization Error");
315 diag = hw->phy.ops.init_params(hw);
317 PMD_INIT_LOG(ERR, "PHY Initialization Error");
320 (void) e1000_get_bus_info(hw);
323 hw->phy.autoneg_wait_to_complete = 0;
324 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
326 e1000_init_script_state_82541(hw, TRUE);
327 e1000_set_tbi_compatibility_82543(hw, TRUE);
330 if (hw->phy.media_type == e1000_media_type_copper) {
331 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
332 hw->phy.disable_polarity_correction = 0;
333 hw->phy.ms_type = e1000_ms_hw_default;
337 * Start from a known state, this is important in reading the nvm
342 /* Make sure we have a good EEPROM before we read from it */
343 if (e1000_validate_nvm_checksum(hw) < 0) {
345 * Some PCI-E parts fail the first check due to
346 * the link being in sleep state, call it again,
347 * if it fails a second time its a real issue.
349 diag = e1000_validate_nvm_checksum(hw);
351 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
356 /* Read the permanent MAC address out of the EEPROM */
357 diag = e1000_read_mac_addr(hw);
359 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
363 /* Now initialize the hardware */
364 diag = em_hardware_init(hw);
366 PMD_INIT_LOG(ERR, "Hardware initialization failed");
370 hw->mac.get_link_status = 1;
372 /* Indicate SOL/IDER usage */
373 diag = e1000_check_reset_block(hw);
375 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
381 em_hw_control_release(hw);
386 eth_em_configure(struct rte_eth_dev *dev)
388 struct e1000_interrupt *intr =
389 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
391 PMD_INIT_FUNC_TRACE();
392 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
393 PMD_INIT_FUNC_TRACE();
399 em_set_pba(struct e1000_hw *hw)
404 * Packet Buffer Allocation (PBA)
405 * Writing PBA sets the receive portion of the buffer
406 * the remainder is used for the transmit buffer.
407 * Devices before the 82547 had a Packet Buffer of 64K.
408 * After the 82547 the buffer was reduced to 40K.
410 switch (hw->mac.type) {
412 case e1000_82547_rev_2:
413 /* 82547: Total Packet Buffer is 40K */
414 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
418 case e1000_80003es2lan:
419 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
421 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
422 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
426 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
440 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
443 E1000_WRITE_REG(hw, E1000_PBA, pba);
447 eth_em_start(struct rte_eth_dev *dev)
449 struct e1000_hw *hw =
450 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
453 PMD_INIT_FUNC_TRACE();
457 e1000_power_up_phy(hw);
459 /* Set default PBA value */
462 /* Put the address into the Receive Address Array */
463 e1000_rar_set(hw, hw->mac.addr, 0);
466 * With the 82571 adapter, RAR[0] may be overwritten
467 * when the other port is reset, we make a duplicate
468 * in RAR[14] for that eventuality, this assures
469 * the interface continues to function.
471 if (hw->mac.type == e1000_82571) {
472 e1000_set_laa_state_82571(hw, TRUE);
473 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
476 /* Initialize the hardware */
477 if (em_hardware_init(hw)) {
478 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
482 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
484 /* Configure for OS presence */
485 em_init_manageability(hw);
489 ret = eth_em_rx_init(dev);
491 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
492 em_dev_clear_queues(dev);
496 e1000_clear_hw_cntrs_base_generic(hw);
498 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
499 ETH_VLAN_EXTEND_MASK;
500 eth_em_vlan_offload_set(dev, mask);
502 /* Set Interrupt Throttling Rate to maximum allowed value. */
503 E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
505 /* Setup link speed and duplex */
506 switch (dev->data->dev_conf.link_speed) {
507 case ETH_LINK_SPEED_AUTONEG:
508 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
509 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
510 else if (dev->data->dev_conf.link_duplex ==
511 ETH_LINK_HALF_DUPLEX)
512 hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
513 else if (dev->data->dev_conf.link_duplex ==
514 ETH_LINK_FULL_DUPLEX)
515 hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
517 goto error_invalid_config;
519 case ETH_LINK_SPEED_10:
520 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
521 hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
522 else if (dev->data->dev_conf.link_duplex ==
523 ETH_LINK_HALF_DUPLEX)
524 hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
525 else if (dev->data->dev_conf.link_duplex ==
526 ETH_LINK_FULL_DUPLEX)
527 hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
529 goto error_invalid_config;
531 case ETH_LINK_SPEED_100:
532 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
533 hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
534 else if (dev->data->dev_conf.link_duplex ==
535 ETH_LINK_HALF_DUPLEX)
536 hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
537 else if (dev->data->dev_conf.link_duplex ==
538 ETH_LINK_FULL_DUPLEX)
539 hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
541 goto error_invalid_config;
543 case ETH_LINK_SPEED_1000:
544 if ((dev->data->dev_conf.link_duplex ==
545 ETH_LINK_AUTONEG_DUPLEX) ||
546 (dev->data->dev_conf.link_duplex ==
547 ETH_LINK_FULL_DUPLEX))
548 hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
550 goto error_invalid_config;
552 case ETH_LINK_SPEED_10000:
554 goto error_invalid_config;
556 e1000_setup_link(hw);
558 /* check if lsc interrupt feature is enabled */
559 if (dev->data->dev_conf.intr_conf.lsc != 0) {
560 ret = eth_em_interrupt_setup(dev);
562 PMD_INIT_LOG(ERR, "Unable to setup interrupts");
563 em_dev_clear_queues(dev);
568 PMD_INIT_LOG(DEBUG, "<<");
572 error_invalid_config:
573 PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u",
574 dev->data->dev_conf.link_speed,
575 dev->data->dev_conf.link_duplex, dev->data->port_id);
576 em_dev_clear_queues(dev);
580 /*********************************************************************
582 * This routine disables all traffic on the adapter by issuing a
583 * global reset on the MAC.
585 **********************************************************************/
587 eth_em_stop(struct rte_eth_dev *dev)
589 struct rte_eth_link link;
590 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
594 if (hw->mac.type >= e1000_82544)
595 E1000_WRITE_REG(hw, E1000_WUC, 0);
597 /* Power down the phy. Needed to make the link go down */
598 e1000_power_down_phy(hw);
600 em_dev_clear_queues(dev);
602 /* clear the recorded link status */
603 memset(&link, 0, sizeof(link));
604 rte_em_dev_atomic_write_link_status(dev, &link);
608 eth_em_close(struct rte_eth_dev *dev)
610 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
613 e1000_phy_hw_reset(hw);
614 em_release_manageability(hw);
615 em_hw_control_release(hw);
619 em_get_rx_buffer_size(struct e1000_hw *hw)
621 uint32_t rx_buf_size;
623 rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
627 /*********************************************************************
629 * Initialize the hardware
631 **********************************************************************/
633 em_hardware_init(struct e1000_hw *hw)
635 uint32_t rx_buf_size;
638 /* Issue a global reset */
641 /* Let the firmware know the OS is in control */
642 em_hw_control_acquire(hw);
645 * These parameters control the automatic generation (Tx) and
646 * response (Rx) to Ethernet PAUSE frames.
647 * - High water mark should allow for at least two standard size (1518)
648 * frames to be received after sending an XOFF.
649 * - Low water mark works best when it is very near the high water mark.
650 * This allows the receiver to restart by sending XON when it has
651 * drained a bit. Here we use an arbitrary value of 1500 which will
652 * restart after one full frame is pulled from the buffer. There
653 * could be several smaller frames in the buffer and if so they will
654 * not trigger the XON until their total number reduces the buffer
656 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
658 rx_buf_size = em_get_rx_buffer_size(hw);
660 hw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);
661 hw->fc.low_water = hw->fc.high_water - 1500;
663 if (hw->mac.type == e1000_80003es2lan)
664 hw->fc.pause_time = UINT16_MAX;
666 hw->fc.pause_time = EM_FC_PAUSE_TIME;
670 /* Set Flow control, use the tunable location if sane */
671 if (em_fc_setting <= e1000_fc_full)
672 hw->fc.requested_mode = em_fc_setting;
674 hw->fc.requested_mode = e1000_fc_none;
676 /* Workaround: no TX flow ctrl for PCH */
677 if (hw->mac.type == e1000_pchlan)
678 hw->fc.requested_mode = e1000_fc_rx_pause;
680 /* Override - settings for PCH2LAN, ya its magic :) */
681 if (hw->mac.type == e1000_pch2lan) {
682 hw->fc.high_water = 0x5C20;
683 hw->fc.low_water = 0x5048;
684 hw->fc.pause_time = 0x0650;
685 hw->fc.refresh_time = 0x0400;
688 diag = e1000_init_hw(hw);
691 e1000_check_for_link(hw);
695 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
697 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
699 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
700 struct e1000_hw_stats *stats =
701 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
704 if(hw->phy.media_type == e1000_media_type_copper ||
705 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
706 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
707 stats->sec += E1000_READ_REG(hw, E1000_SEC);
710 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
711 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
712 stats->scc += E1000_READ_REG(hw, E1000_SCC);
713 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
715 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
716 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
717 stats->colc += E1000_READ_REG(hw, E1000_COLC);
718 stats->dc += E1000_READ_REG(hw, E1000_DC);
719 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
720 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
721 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
724 * For watchdog management we need to know if we have been
725 * paused during the last interval, so capture that here.
727 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
728 stats->xoffrxc += pause_frames;
729 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
730 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
731 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
732 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
733 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
734 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
735 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
736 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
737 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
738 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
739 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
740 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
743 * For the 64-bit byte counters the low dword must be read first.
744 * Both registers clear on the read of the high dword.
747 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
748 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
749 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
750 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
752 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
753 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
754 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
755 stats->roc += E1000_READ_REG(hw, E1000_ROC);
756 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
758 stats->tor += E1000_READ_REG(hw, E1000_TORH);
759 stats->tot += E1000_READ_REG(hw, E1000_TOTH);
761 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
762 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
763 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
764 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
765 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
766 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
767 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
768 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
769 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
770 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
772 /* Interrupt Counts */
774 if (hw->mac.type >= e1000_82571) {
775 stats->iac += E1000_READ_REG(hw, E1000_IAC);
776 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
777 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
778 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
779 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
780 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
781 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
782 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
783 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
786 if (hw->mac.type >= e1000_82543) {
787 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
788 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
789 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
790 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
791 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
792 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
795 if (rte_stats == NULL)
799 rte_stats->ibadcrc = stats->crcerrs;
800 rte_stats->ibadlen = stats->rlec + stats->ruc + stats->roc;
801 rte_stats->imissed = stats->mpc;
802 rte_stats->ierrors = rte_stats->ibadcrc +
805 stats->rxerrc + stats->algnerrc + stats->cexterr;
808 rte_stats->oerrors = stats->ecol + stats->latecol;
810 rte_stats->ipackets = stats->gprc;
811 rte_stats->opackets = stats->gptc;
812 rte_stats->ibytes = stats->gorc;
813 rte_stats->obytes = stats->gotc;
815 /* XON/XOFF pause frames stats registers */
816 rte_stats->tx_pause_xon = stats->xontxc;
817 rte_stats->rx_pause_xon = stats->xonrxc;
818 rte_stats->tx_pause_xoff = stats->xofftxc;
819 rte_stats->rx_pause_xoff = stats->xoffrxc;
823 eth_em_stats_reset(struct rte_eth_dev *dev)
825 struct e1000_hw_stats *hw_stats =
826 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
828 /* HW registers are cleared on read */
829 eth_em_stats_get(dev, NULL);
831 /* Reset software totals */
832 memset(hw_stats, 0, sizeof(*hw_stats));
836 em_get_max_pktlen(const struct e1000_hw *hw)
838 switch (hw->mac.type) {
845 case e1000_80003es2lan: /* 9K Jumbo Frame size */
849 /* Adapters that do not support jumbo frames */
852 return (ETHER_MAX_LEN);
854 return (MAX_JUMBO_FRAME_SIZE);
859 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
861 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
863 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
864 dev_info->max_rx_pktlen = em_get_max_pktlen(hw);
865 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
868 * Starting with 631xESB hw supports 2 TX/RX queues per port.
869 * Unfortunatelly, all these nics have just one TX context.
870 * So we have few choises for TX:
871 * - Use just one TX queue.
872 * - Allow cksum offload only for one TX queue.
873 * - Don't allow TX cksum offload at all.
874 * For now, option #1 was chosen.
875 * To use second RX queue we have to use extended RX descriptor
876 * (Multiple Receive Queues are mutually exclusive with UDP
877 * fragmentation and are not supported when a legacy receive
878 * descriptor format is used).
879 * Which means separate RX routinies - as legacy nics (82540, 82545)
880 * don't support extended RXD.
881 * To avoid it we support just one RX queue for now (no RSS).
884 dev_info->max_rx_queues = 1;
885 dev_info->max_tx_queues = 1;
888 /* return 0 means link status changed, -1 means not changed */
890 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
892 struct e1000_hw *hw =
893 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
894 struct rte_eth_link link, old;
895 int link_check, count;
898 hw->mac.get_link_status = 1;
900 /* possible wait-to-complete in up to 9 seconds */
901 for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
902 /* Read the real link status */
903 switch (hw->phy.media_type) {
904 case e1000_media_type_copper:
905 /* Do the work to read phy */
906 e1000_check_for_link(hw);
907 link_check = !hw->mac.get_link_status;
910 case e1000_media_type_fiber:
911 e1000_check_for_link(hw);
912 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
916 case e1000_media_type_internal_serdes:
917 e1000_check_for_link(hw);
918 link_check = hw->mac.serdes_has_link;
924 if (link_check || wait_to_complete == 0)
926 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
928 memset(&link, 0, sizeof(link));
929 rte_em_dev_atomic_read_link_status(dev, &link);
932 /* Now we check if a transition has happened */
933 if (link_check && (link.link_status == 0)) {
934 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
936 link.link_status = 1;
937 } else if (!link_check && (link.link_status == 1)) {
939 link.link_duplex = 0;
940 link.link_status = 0;
942 rte_em_dev_atomic_write_link_status(dev, &link);
945 if (old.link_status == link.link_status)
953 * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
954 * For ASF and Pass Through versions of f/w this means
955 * that the driver is loaded. For AMT version type f/w
956 * this means that the network i/f is open.
959 em_hw_control_acquire(struct e1000_hw *hw)
961 uint32_t ctrl_ext, swsm;
963 /* Let firmware know the driver has taken over */
964 if (hw->mac.type == e1000_82573) {
965 swsm = E1000_READ_REG(hw, E1000_SWSM);
966 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
969 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
970 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
971 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
976 * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
977 * For ASF and Pass Through versions of f/w this means that the
978 * driver is no longer loaded. For AMT versions of the
979 * f/w this means that the network i/f is closed.
982 em_hw_control_release(struct e1000_hw *hw)
984 uint32_t ctrl_ext, swsm;
986 /* Let firmware taken over control of h/w */
987 if (hw->mac.type == e1000_82573) {
988 swsm = E1000_READ_REG(hw, E1000_SWSM);
989 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
991 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
992 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
993 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
998 * Bit of a misnomer, what this really means is
999 * to enable OS management of the system... aka
1000 * to disable special hardware management features.
1003 em_init_manageability(struct e1000_hw *hw)
1005 if (e1000_enable_mng_pass_thru(hw)) {
1006 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1007 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1009 /* disable hardware interception of ARP */
1010 manc &= ~(E1000_MANC_ARP_EN);
1012 /* enable receiving management packets to the host */
1013 manc |= E1000_MANC_EN_MNG2HOST;
1014 manc2h |= 1 << 5; /* Mng Port 623 */
1015 manc2h |= 1 << 6; /* Mng Port 664 */
1016 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1017 E1000_WRITE_REG(hw, E1000_MANC, manc);
1022 * Give control back to hardware management
1023 * controller if there is one.
1026 em_release_manageability(struct e1000_hw *hw)
1030 if (e1000_enable_mng_pass_thru(hw)) {
1031 manc = E1000_READ_REG(hw, E1000_MANC);
1033 /* re-enable hardware interception of ARP */
1034 manc |= E1000_MANC_ARP_EN;
1035 manc &= ~E1000_MANC_EN_MNG2HOST;
1037 E1000_WRITE_REG(hw, E1000_MANC, manc);
1042 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1044 struct e1000_hw *hw =
1045 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1048 rctl = E1000_READ_REG(hw, E1000_RCTL);
1049 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1050 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1054 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1056 struct e1000_hw *hw =
1057 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1060 rctl = E1000_READ_REG(hw, E1000_RCTL);
1061 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1062 if (dev->data->all_multicast == 1)
1063 rctl |= E1000_RCTL_MPE;
1065 rctl &= (~E1000_RCTL_MPE);
1066 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1070 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1072 struct e1000_hw *hw =
1073 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1076 rctl = E1000_READ_REG(hw, E1000_RCTL);
1077 rctl |= E1000_RCTL_MPE;
1078 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1082 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1084 struct e1000_hw *hw =
1085 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1088 if (dev->data->promiscuous == 1)
1089 return; /* must remain in all_multicast mode */
1090 rctl = E1000_READ_REG(hw, E1000_RCTL);
1091 rctl &= (~E1000_RCTL_MPE);
1092 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1096 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1098 struct e1000_hw *hw =
1099 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1100 struct e1000_vfta * shadow_vfta =
1101 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1106 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1107 E1000_VFTA_ENTRY_MASK);
1108 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1109 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1114 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1116 /* update local VFTA copy */
1117 shadow_vfta->vfta[vid_idx] = vfta;
1123 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1125 struct e1000_hw *hw =
1126 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1129 /* Filter Table Disable */
1130 reg = E1000_READ_REG(hw, E1000_RCTL);
1131 reg &= ~E1000_RCTL_CFIEN;
1132 reg &= ~E1000_RCTL_VFE;
1133 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1137 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1139 struct e1000_hw *hw =
1140 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1141 struct e1000_vfta * shadow_vfta =
1142 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1146 /* Filter Table Enable, CFI not used for packet acceptance */
1147 reg = E1000_READ_REG(hw, E1000_RCTL);
1148 reg &= ~E1000_RCTL_CFIEN;
1149 reg |= E1000_RCTL_VFE;
1150 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1152 /* restore vfta from local copy */
1153 for (i = 0; i < IGB_VFTA_SIZE; i++)
1154 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1158 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1160 struct e1000_hw *hw =
1161 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1164 /* VLAN Mode Disable */
1165 reg = E1000_READ_REG(hw, E1000_CTRL);
1166 reg &= ~E1000_CTRL_VME;
1167 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1172 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1174 struct e1000_hw *hw =
1175 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1178 /* VLAN Mode Enable */
1179 reg = E1000_READ_REG(hw, E1000_CTRL);
1180 reg |= E1000_CTRL_VME;
1181 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1185 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1187 if(mask & ETH_VLAN_STRIP_MASK){
1188 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1189 em_vlan_hw_strip_enable(dev);
1191 em_vlan_hw_strip_disable(dev);
1194 if(mask & ETH_VLAN_FILTER_MASK){
1195 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1196 em_vlan_hw_filter_enable(dev);
1198 em_vlan_hw_filter_disable(dev);
1203 em_intr_disable(struct e1000_hw *hw)
1205 E1000_WRITE_REG(hw, E1000_IMC, ~0);
1209 * It enables the interrupt mask and then enable the interrupt.
1212 * Pointer to struct rte_eth_dev.
1215 * - On success, zero.
1216 * - On failure, a negative value.
1219 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1221 struct e1000_hw *hw =
1222 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1224 E1000_WRITE_REG(hw, E1000_IMS, E1000_ICR_LSC);
1225 rte_intr_enable(&(dev->pci_dev->intr_handle));
1230 * It reads ICR and gets interrupt causes, check it and set a bit flag
1231 * to update link status.
1234 * Pointer to struct rte_eth_dev.
1237 * - On success, zero.
1238 * - On failure, a negative value.
1241 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1244 struct e1000_hw *hw =
1245 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1246 struct e1000_interrupt *intr =
1247 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1249 /* read-on-clear nic registers here */
1250 icr = E1000_READ_REG(hw, E1000_ICR);
1251 if (icr & E1000_ICR_LSC) {
1252 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1259 * It executes link_update after knowing an interrupt is prsent.
1262 * Pointer to struct rte_eth_dev.
1265 * - On success, zero.
1266 * - On failure, a negative value.
1269 eth_em_interrupt_action(struct rte_eth_dev *dev)
1271 struct e1000_hw *hw =
1272 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1273 struct e1000_interrupt *intr =
1274 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1275 uint32_t tctl, rctl;
1276 struct rte_eth_link link;
1279 if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1282 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1283 rte_intr_enable(&(dev->pci_dev->intr_handle));
1285 /* set get_link_status to check register later */
1286 hw->mac.get_link_status = 1;
1287 ret = eth_em_link_update(dev, 0);
1289 /* check if link has changed */
1293 memset(&link, 0, sizeof(link));
1294 rte_em_dev_atomic_read_link_status(dev, &link);
1295 if (link.link_status) {
1296 PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s",
1297 dev->data->port_id, (unsigned)link.link_speed,
1298 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1299 "full-duplex" : "half-duplex");
1301 PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
1303 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1304 dev->pci_dev->addr.domain, dev->pci_dev->addr.bus,
1305 dev->pci_dev->addr.devid, dev->pci_dev->addr.function);
1306 tctl = E1000_READ_REG(hw, E1000_TCTL);
1307 rctl = E1000_READ_REG(hw, E1000_RCTL);
1308 if (link.link_status) {
1310 tctl |= E1000_TCTL_EN;
1311 rctl |= E1000_RCTL_EN;
1314 tctl &= ~E1000_TCTL_EN;
1315 rctl &= ~E1000_RCTL_EN;
1317 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1318 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1319 E1000_WRITE_FLUSH(hw);
1325 * Interrupt handler which shall be registered at first.
1328 * Pointer to interrupt handle.
1330 * The address of parameter (struct rte_eth_dev *) regsitered before.
1336 eth_em_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1339 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1341 eth_em_interrupt_get_status(dev);
1342 eth_em_interrupt_action(dev);
1343 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1347 eth_em_led_on(struct rte_eth_dev *dev)
1349 struct e1000_hw *hw;
1351 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1352 return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1356 eth_em_led_off(struct rte_eth_dev *dev)
1358 struct e1000_hw *hw;
1360 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1361 return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1365 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1367 struct e1000_hw *hw;
1372 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1373 fc_conf->pause_time = hw->fc.pause_time;
1374 fc_conf->high_water = hw->fc.high_water;
1375 fc_conf->low_water = hw->fc.low_water;
1376 fc_conf->send_xon = hw->fc.send_xon;
1377 fc_conf->autoneg = hw->mac.autoneg;
1380 * Return rx_pause and tx_pause status according to actual setting of
1381 * the TFCE and RFCE bits in the CTRL register.
1383 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1384 if (ctrl & E1000_CTRL_TFCE)
1389 if (ctrl & E1000_CTRL_RFCE)
1394 if (rx_pause && tx_pause)
1395 fc_conf->mode = RTE_FC_FULL;
1397 fc_conf->mode = RTE_FC_RX_PAUSE;
1399 fc_conf->mode = RTE_FC_TX_PAUSE;
1401 fc_conf->mode = RTE_FC_NONE;
1407 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1409 struct e1000_hw *hw;
1411 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1417 uint32_t rx_buf_size;
1418 uint32_t max_high_water;
1421 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1422 if (fc_conf->autoneg != hw->mac.autoneg)
1424 rx_buf_size = em_get_rx_buffer_size(hw);
1425 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1427 /* At least reserve one Ethernet frame for watermark */
1428 max_high_water = rx_buf_size - ETHER_MAX_LEN;
1429 if ((fc_conf->high_water > max_high_water) ||
1430 (fc_conf->high_water < fc_conf->low_water)) {
1431 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1432 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
1436 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1437 hw->fc.pause_time = fc_conf->pause_time;
1438 hw->fc.high_water = fc_conf->high_water;
1439 hw->fc.low_water = fc_conf->low_water;
1440 hw->fc.send_xon = fc_conf->send_xon;
1442 err = e1000_setup_link_generic(hw);
1443 if (err == E1000_SUCCESS) {
1445 /* check if we want to forward MAC frames - driver doesn't have native
1446 * capability to do that, so we'll write the registers ourselves */
1448 rctl = E1000_READ_REG(hw, E1000_RCTL);
1450 /* set or clear MFLCN.PMCF bit depending on configuration */
1451 if (fc_conf->mac_ctrl_frame_fwd != 0)
1452 rctl |= E1000_RCTL_PMCF;
1454 rctl &= ~E1000_RCTL_PMCF;
1456 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1457 E1000_WRITE_FLUSH(hw);
1462 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1467 eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1468 uint32_t index, __rte_unused uint32_t pool)
1470 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1472 e1000_rar_set(hw, mac_addr->addr_bytes, index);
1476 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1478 uint8_t addr[ETHER_ADDR_LEN];
1479 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1481 memset(addr, 0, sizeof(addr));
1483 e1000_rar_set(hw, addr, index);
1487 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1489 struct rte_eth_dev_info dev_info;
1490 struct e1000_hw *hw;
1491 uint32_t frame_size;
1494 eth_em_infos_get(dev, &dev_info);
1495 frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE;
1497 /* check that mtu is within the allowed range */
1498 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1501 /* refuse mtu that requires the support of scattered packets when this
1502 * feature has not been enabled before. */
1503 if (!dev->data->scattered_rx &&
1504 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1507 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1508 rctl = E1000_READ_REG(hw, E1000_RCTL);
1510 /* switch to jumbo mode if needed */
1511 if (frame_size > ETHER_MAX_LEN) {
1512 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1513 rctl |= E1000_RCTL_LPE;
1515 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1516 rctl &= ~E1000_RCTL_LPE;
1518 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1520 /* update max frame size */
1521 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1525 struct rte_driver em_pmd_drv = {
1527 .init = rte_em_pmd_init,
1530 PMD_REGISTER_DRIVER(em_pmd_drv);