drivers/net/e1000/em_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <stdarg.h>
  10
  11 #include <rte_common.h>
  12 #include <rte_interrupts.h>
  13 #include <rte_byteorder.h>
  14 #include <rte_debug.h>
  15 #include <rte_pci.h>
  16 #include <rte_bus_pci.h>
  17 #include <rte_ether.h>
  18 #include <rte_ethdev_driver.h>
  19 #include <rte_ethdev_pci.h>
  20 #include <rte_memory.h>
  21 #include <rte_eal.h>
  22 #include <rte_malloc.h>
  23 #include <rte_dev.h>
  24
  25 #include "e1000_logs.h"
  26 #include "base/e1000_api.h"
  27 #include "e1000_ethdev.h"
  28
  29 #define EM_EIAC                 0x000DC
  30
  31 #define PMD_ROUNDUP(x,y)        (((x) + (y) - 1)/(y) * (y))
  32
  33
  34 static int eth_em_configure(struct rte_eth_dev *dev);
  35 static int eth_em_start(struct rte_eth_dev *dev);
  36 static void eth_em_stop(struct rte_eth_dev *dev);
  37 static int eth_em_close(struct rte_eth_dev *dev);
  38 static int eth_em_promiscuous_enable(struct rte_eth_dev *dev);
  39 static int eth_em_promiscuous_disable(struct rte_eth_dev *dev);
  40 static int eth_em_allmulticast_enable(struct rte_eth_dev *dev);
  41 static int eth_em_allmulticast_disable(struct rte_eth_dev *dev);
  42 static int eth_em_link_update(struct rte_eth_dev *dev,
  43                                 int wait_to_complete);
  44 static int eth_em_stats_get(struct rte_eth_dev *dev,
  45                                 struct rte_eth_stats *rte_stats);
  46 static int eth_em_stats_reset(struct rte_eth_dev *dev);
  47 static int eth_em_infos_get(struct rte_eth_dev *dev,
  48                                 struct rte_eth_dev_info *dev_info);
  49 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
  50                                 struct rte_eth_fc_conf *fc_conf);
  51 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
  52                                 struct rte_eth_fc_conf *fc_conf);
  53 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
  54 static int eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev);
  55 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
  56 static int eth_em_interrupt_action(struct rte_eth_dev *dev,
  57                                    struct rte_intr_handle *handle);
  58 static void eth_em_interrupt_handler(void *param);
  59
  60 static int em_hw_init(struct e1000_hw *hw);
  61 static int em_hardware_init(struct e1000_hw *hw);
  62 static void em_hw_control_acquire(struct e1000_hw *hw);
  63 static void em_hw_control_release(struct e1000_hw *hw);
  64 static void em_init_manageability(struct e1000_hw *hw);
  65 static void em_release_manageability(struct e1000_hw *hw);
  66
  67 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  68
  69 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
  70                 uint16_t vlan_id, int on);
  71 static int eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  72 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
  73 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
  74 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
  75 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
  76
  77 /*
  78 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
  79                                         uint16_t vlan_id, int on);
  80 */
  81
  82 static int eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
  83 static int eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
  84 static void em_lsc_intr_disable(struct e1000_hw *hw);
  85 static void em_rxq_intr_enable(struct e1000_hw *hw);
  86 static void em_rxq_intr_disable(struct e1000_hw *hw);
  87
  88 static int eth_em_led_on(struct rte_eth_dev *dev);
  89 static int eth_em_led_off(struct rte_eth_dev *dev);
  90
  91 static int em_get_rx_buffer_size(struct e1000_hw *hw);
  92 static int eth_em_rar_set(struct rte_eth_dev *dev,
  93                         struct rte_ether_addr *mac_addr,
  94                         uint32_t index, uint32_t pool);
  95 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
  96 static int eth_em_default_mac_addr_set(struct rte_eth_dev *dev,
  97                                          struct rte_ether_addr *addr);
  98
  99 static int eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
 100                                    struct rte_ether_addr *mc_addr_set,
 101                                    uint32_t nb_mc_addr);
 102
 103 #define EM_FC_PAUSE_TIME 0x0680
 104 #define EM_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 105 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 106
 107 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
 108
 109 /*
 110  * The set of PCI devices this driver supports
 111  */
 112 static const struct rte_pci_id pci_id_em_map[] = {
 113         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82540EM) },
 114         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_COPPER) },
 115         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_FIBER) },
 116         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_COPPER) },
 117         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_FIBER) },
 118         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_QUAD_COPPER) },
 119         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_COPPER) },
 120         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_FIBER) },
 121         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES) },
 122         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_DUAL) },
 123         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_QUAD) },
 124         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER) },
 125         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571PT_QUAD_COPPER) },
 126         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_FIBER) },
 127         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER_LP) },
 128         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_COPPER) },
 129         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_FIBER) },
 130         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_SERDES) },
 131         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI) },
 132         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82573L) },
 133         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574L) },
 134         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574LA) },
 135         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82583V) },
 136         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH2_LV_LM) },
 137         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_LM) },
 138         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_V) },
 139         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_LM) },
 140         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_V) },
 141         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM2) },
 142         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V2) },
 143         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM3) },
 144         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V3) },
 145         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM) },
 146         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V) },
 147         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM2) },
 148         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V2) },
 149         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LBG_I219_LM3) },
 150         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM4) },
 151         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V4) },
 152         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM5) },
 153         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V5) },
 154         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM6) },
 155         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V6) },
 156         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM7) },
 157         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V7) },
 158         { .vendor_id = 0, /* sentinel */ },
 159 };
 160
 161 static const struct eth_dev_ops eth_em_ops = {
 162         .dev_configure        = eth_em_configure,
 163         .dev_start            = eth_em_start,
 164         .dev_stop             = eth_em_stop,
 165         .dev_close            = eth_em_close,
 166         .promiscuous_enable   = eth_em_promiscuous_enable,
 167         .promiscuous_disable  = eth_em_promiscuous_disable,
 168         .allmulticast_enable  = eth_em_allmulticast_enable,
 169         .allmulticast_disable = eth_em_allmulticast_disable,
 170         .link_update          = eth_em_link_update,
 171         .stats_get            = eth_em_stats_get,
 172         .stats_reset          = eth_em_stats_reset,
 173         .dev_infos_get        = eth_em_infos_get,
 174         .mtu_set              = eth_em_mtu_set,
 175         .vlan_filter_set      = eth_em_vlan_filter_set,
 176         .vlan_offload_set     = eth_em_vlan_offload_set,
 177         .rx_queue_setup       = eth_em_rx_queue_setup,
 178         .rx_queue_release     = eth_em_rx_queue_release,
 179         .tx_queue_setup       = eth_em_tx_queue_setup,
 180         .tx_queue_release     = eth_em_tx_queue_release,
 181         .rx_queue_intr_enable = eth_em_rx_queue_intr_enable,
 182         .rx_queue_intr_disable = eth_em_rx_queue_intr_disable,
 183         .dev_led_on           = eth_em_led_on,
 184         .dev_led_off          = eth_em_led_off,
 185         .flow_ctrl_get        = eth_em_flow_ctrl_get,
 186         .flow_ctrl_set        = eth_em_flow_ctrl_set,
 187         .mac_addr_set         = eth_em_default_mac_addr_set,
 188         .mac_addr_add         = eth_em_rar_set,
 189         .mac_addr_remove      = eth_em_rar_clear,
 190         .set_mc_addr_list     = eth_em_set_mc_addr_list,
 191         .rxq_info_get         = em_rxq_info_get,
 192         .txq_info_get         = em_txq_info_get,
 193 };
 194
 195
 196 /**
 197  *  eth_em_dev_is_ich8 - Check for ICH8 device
 198  *  @hw: pointer to the HW structure
 199  *
 200  *  return TRUE for ICH8, otherwise FALSE
 201  **/
 202 static bool
 203 eth_em_dev_is_ich8(struct e1000_hw *hw)
 204 {
 205         DEBUGFUNC("eth_em_dev_is_ich8");
 206
 207         switch (hw->device_id) {
 208         case E1000_DEV_ID_PCH2_LV_LM:
 209         case E1000_DEV_ID_PCH_LPT_I217_LM:
 210         case E1000_DEV_ID_PCH_LPT_I217_V:
 211         case E1000_DEV_ID_PCH_LPTLP_I218_LM:
 212         case E1000_DEV_ID_PCH_LPTLP_I218_V:
 213         case E1000_DEV_ID_PCH_I218_V2:
 214         case E1000_DEV_ID_PCH_I218_LM2:
 215         case E1000_DEV_ID_PCH_I218_V3:
 216         case E1000_DEV_ID_PCH_I218_LM3:
 217         case E1000_DEV_ID_PCH_SPT_I219_LM:
 218         case E1000_DEV_ID_PCH_SPT_I219_V:
 219         case E1000_DEV_ID_PCH_SPT_I219_LM2:
 220         case E1000_DEV_ID_PCH_SPT_I219_V2:
 221         case E1000_DEV_ID_PCH_LBG_I219_LM3:
 222         case E1000_DEV_ID_PCH_SPT_I219_LM4:
 223         case E1000_DEV_ID_PCH_SPT_I219_V4:
 224         case E1000_DEV_ID_PCH_SPT_I219_LM5:
 225         case E1000_DEV_ID_PCH_SPT_I219_V5:
 226         case E1000_DEV_ID_PCH_CNP_I219_LM6:
 227         case E1000_DEV_ID_PCH_CNP_I219_V6:
 228         case E1000_DEV_ID_PCH_CNP_I219_LM7:
 229         case E1000_DEV_ID_PCH_CNP_I219_V7:
 230                 return 1;
 231         default:
 232                 return 0;
 233         }
 234 }
 235
 236 static int
 237 eth_em_dev_init(struct rte_eth_dev *eth_dev)
 238 {
 239         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 240         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 241         struct e1000_adapter *adapter =
 242                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 243         struct e1000_hw *hw =
 244                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 245         struct e1000_vfta * shadow_vfta =
 246                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 247
 248         eth_dev->dev_ops = &eth_em_ops;
 249         eth_dev->rx_queue_count = eth_em_rx_queue_count;
 250         eth_dev->rx_descriptor_done   = eth_em_rx_descriptor_done;
 251         eth_dev->rx_descriptor_status = eth_em_rx_descriptor_status;
 252         eth_dev->tx_descriptor_status = eth_em_tx_descriptor_status;
 253         eth_dev->rx_pkt_burst = (eth_rx_burst_t)&eth_em_recv_pkts;
 254         eth_dev->tx_pkt_burst = (eth_tx_burst_t)&eth_em_xmit_pkts;
 255         eth_dev->tx_pkt_prepare = (eth_tx_prep_t)&eth_em_prep_pkts;
 256
 257         /* for secondary processes, we don't initialise any further as primary
 258          * has already done this work. Only check we don't need a different
 259          * RX function */
 260         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 261                 if (eth_dev->data->scattered_rx)
 262                         eth_dev->rx_pkt_burst =
 263                                 (eth_rx_burst_t)&eth_em_recv_scattered_pkts;
 264                 return 0;
 265         }
 266
 267         rte_eth_copy_pci_info(eth_dev, pci_dev);
 268
 269         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 270         hw->device_id = pci_dev->id.device_id;
 271         adapter->stopped = 0;
 272
 273         /* For ICH8 support we'll need to map the flash memory BAR */
 274         if (eth_em_dev_is_ich8(hw))
 275                 hw->flash_address = (void *)pci_dev->mem_resource[1].addr;
 276
 277         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
 278                         em_hw_init(hw) != 0) {
 279                 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
 280                         "failed to init HW",
 281                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 282                         pci_dev->id.device_id);
 283                 return -ENODEV;
 284         }
 285
 286         /* Allocate memory for storing MAC addresses */
 287         eth_dev->data->mac_addrs = rte_zmalloc("e1000", RTE_ETHER_ADDR_LEN *
 288                         hw->mac.rar_entry_count, 0);
 289         if (eth_dev->data->mac_addrs == NULL) {
 290                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 291                         "store MAC addresses",
 292                         RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 293                 return -ENOMEM;
 294         }
 295
 296         /* Copy the permanent MAC address */
 297         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
 298                 eth_dev->data->mac_addrs);
 299
 300         /* initialize the vfta */
 301         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 302
 303         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 304                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 305                      pci_dev->id.device_id);
 306
 307         rte_intr_callback_register(intr_handle,
 308                                    eth_em_interrupt_handler, eth_dev);
 309
 310         return 0;
 311 }
 312
 313 static int
 314 eth_em_dev_uninit(struct rte_eth_dev *eth_dev)
 315 {
 316         PMD_INIT_FUNC_TRACE();
 317
 318         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 319                 return 0;
 320
 321         eth_em_close(eth_dev);
 322
 323         return 0;
 324 }
 325
 326 static int eth_em_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 327         struct rte_pci_device *pci_dev)
 328 {
 329         return rte_eth_dev_pci_generic_probe(pci_dev,
 330                 sizeof(struct e1000_adapter), eth_em_dev_init);
 331 }
 332
 333 static int eth_em_pci_remove(struct rte_pci_device *pci_dev)
 334 {
 335         return rte_eth_dev_pci_generic_remove(pci_dev, eth_em_dev_uninit);
 336 }
 337
 338 static struct rte_pci_driver rte_em_pmd = {
 339         .id_table = pci_id_em_map,
 340         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 341         .probe = eth_em_pci_probe,
 342         .remove = eth_em_pci_remove,
 343 };
 344
 345 static int
 346 em_hw_init(struct e1000_hw *hw)
 347 {
 348         int diag;
 349
 350         diag = hw->mac.ops.init_params(hw);
 351         if (diag != 0) {
 352                 PMD_INIT_LOG(ERR, "MAC Initialization Error");
 353                 return diag;
 354         }
 355         diag = hw->nvm.ops.init_params(hw);
 356         if (diag != 0) {
 357                 PMD_INIT_LOG(ERR, "NVM Initialization Error");
 358                 return diag;
 359         }
 360         diag = hw->phy.ops.init_params(hw);
 361         if (diag != 0) {
 362                 PMD_INIT_LOG(ERR, "PHY Initialization Error");
 363                 return diag;
 364         }
 365         (void) e1000_get_bus_info(hw);
 366
 367         hw->mac.autoneg = 1;
 368         hw->phy.autoneg_wait_to_complete = 0;
 369         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 370
 371         e1000_init_script_state_82541(hw, TRUE);
 372         e1000_set_tbi_compatibility_82543(hw, TRUE);
 373
 374         /* Copper options */
 375         if (hw->phy.media_type == e1000_media_type_copper) {
 376                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 377                 hw->phy.disable_polarity_correction = 0;
 378                 hw->phy.ms_type = e1000_ms_hw_default;
 379         }
 380
 381         /*
 382          * Start from a known state, this is important in reading the nvm
 383          * and mac from that.
 384          */
 385         e1000_reset_hw(hw);
 386
 387         /* Make sure we have a good EEPROM before we read from it */
 388         if (e1000_validate_nvm_checksum(hw) < 0) {
 389                 /*
 390                  * Some PCI-E parts fail the first check due to
 391                  * the link being in sleep state, call it again,
 392                  * if it fails a second time its a real issue.
 393                  */
 394                 diag = e1000_validate_nvm_checksum(hw);
 395                 if (diag < 0) {
 396                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 397                         goto error;
 398                 }
 399         }
 400
 401         /* Read the permanent MAC address out of the EEPROM */
 402         diag = e1000_read_mac_addr(hw);
 403         if (diag != 0) {
 404                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 405                 goto error;
 406         }
 407
 408         /* Now initialize the hardware */
 409         diag = em_hardware_init(hw);
 410         if (diag != 0) {
 411                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 412                 goto error;
 413         }
 414
 415         hw->mac.get_link_status = 1;
 416
 417         /* Indicate SOL/IDER usage */
 418         diag = e1000_check_reset_block(hw);
 419         if (diag < 0) {
 420                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
 421                         "SOL/IDER session");
 422         }
 423         return 0;
 424
 425 error:
 426         em_hw_control_release(hw);
 427         return diag;
 428 }
 429
 430 static int
 431 eth_em_configure(struct rte_eth_dev *dev)
 432 {
 433         struct e1000_interrupt *intr =
 434                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 435
 436         PMD_INIT_FUNC_TRACE();
 437         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 438
 439         PMD_INIT_FUNC_TRACE();
 440
 441         return 0;
 442 }
 443
 444 static void
 445 em_set_pba(struct e1000_hw *hw)
 446 {
 447         uint32_t pba;
 448
 449         /*
 450          * Packet Buffer Allocation (PBA)
 451          * Writing PBA sets the receive portion of the buffer
 452          * the remainder is used for the transmit buffer.
 453          * Devices before the 82547 had a Packet Buffer of 64K.
 454          * After the 82547 the buffer was reduced to 40K.
 455          */
 456         switch (hw->mac.type) {
 457                 case e1000_82547:
 458                 case e1000_82547_rev_2:
 459                 /* 82547: Total Packet Buffer is 40K */
 460                         pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
 461                         break;
 462                 case e1000_82571:
 463                 case e1000_82572:
 464                 case e1000_80003es2lan:
 465                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 466                         break;
 467                 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
 468                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
 469                         break;
 470                 case e1000_82574:
 471                 case e1000_82583:
 472                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
 473                         break;
 474                 case e1000_ich8lan:
 475                         pba = E1000_PBA_8K;
 476                         break;
 477                 case e1000_ich9lan:
 478                 case e1000_ich10lan:
 479                         pba = E1000_PBA_10K;
 480                         break;
 481                 case e1000_pchlan:
 482                 case e1000_pch2lan:
 483                 case e1000_pch_lpt:
 484                 case e1000_pch_spt:
 485                 case e1000_pch_cnp:
 486                         pba = E1000_PBA_26K;
 487                         break;
 488                 default:
 489                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
 490         }
 491
 492         E1000_WRITE_REG(hw, E1000_PBA, pba);
 493 }
 494
 495 static void
 496 eth_em_rxtx_control(struct rte_eth_dev *dev,
 497                     bool enable)
 498 {
 499         struct e1000_hw *hw =
 500                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 501         uint32_t tctl, rctl;
 502
 503         tctl = E1000_READ_REG(hw, E1000_TCTL);
 504         rctl = E1000_READ_REG(hw, E1000_RCTL);
 505         if (enable) {
 506                 /* enable Tx/Rx */
 507                 tctl |= E1000_TCTL_EN;
 508                 rctl |= E1000_RCTL_EN;
 509         } else {
 510                 /* disable Tx/Rx */
 511                 tctl &= ~E1000_TCTL_EN;
 512                 rctl &= ~E1000_RCTL_EN;
 513         }
 514         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
 515         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
 516         E1000_WRITE_FLUSH(hw);
 517 }
 518
 519 static int
 520 eth_em_start(struct rte_eth_dev *dev)
 521 {
 522         struct e1000_adapter *adapter =
 523                 E1000_DEV_PRIVATE(dev->data->dev_private);
 524         struct e1000_hw *hw =
 525                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 526         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 527         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 528         int ret, mask;
 529         uint32_t intr_vector = 0;
 530         uint32_t *speeds;
 531         int num_speeds;
 532         bool autoneg;
 533
 534         PMD_INIT_FUNC_TRACE();
 535
 536         eth_em_stop(dev);
 537
 538         e1000_power_up_phy(hw);
 539
 540         /* Set default PBA value */
 541         em_set_pba(hw);
 542
 543         /* Put the address into the Receive Address Array */
 544         e1000_rar_set(hw, hw->mac.addr, 0);
 545
 546         /*
 547          * With the 82571 adapter, RAR[0] may be overwritten
 548          * when the other port is reset, we make a duplicate
 549          * in RAR[14] for that eventuality, this assures
 550          * the interface continues to function.
 551          */
 552         if (hw->mac.type == e1000_82571) {
 553                 e1000_set_laa_state_82571(hw, TRUE);
 554                 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
 555         }
 556
 557         /* Initialize the hardware */
 558         if (em_hardware_init(hw)) {
 559                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 560                 return -EIO;
 561         }
 562
 563         E1000_WRITE_REG(hw, E1000_VET, RTE_ETHER_TYPE_VLAN);
 564
 565         /* Configure for OS presence */
 566         em_init_manageability(hw);
 567
 568         if (dev->data->dev_conf.intr_conf.rxq != 0) {
 569                 intr_vector = dev->data->nb_rx_queues;
 570                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 571                         return -1;
 572         }
 573
 574         if (rte_intr_dp_is_en(intr_handle)) {
 575                 intr_handle->intr_vec =
 576                         rte_zmalloc("intr_vec",
 577                                         dev->data->nb_rx_queues * sizeof(int), 0);
 578                 if (intr_handle->intr_vec == NULL) {
 579                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
 580                                                 " intr_vec", dev->data->nb_rx_queues);
 581                         return -ENOMEM;
 582                 }
 583
 584                 /* enable rx interrupt */
 585                 em_rxq_intr_enable(hw);
 586         }
 587
 588         eth_em_tx_init(dev);
 589
 590         ret = eth_em_rx_init(dev);
 591         if (ret) {
 592                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 593                 em_dev_clear_queues(dev);
 594                 return ret;
 595         }
 596
 597         e1000_clear_hw_cntrs_base_generic(hw);
 598
 599         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 600                         ETH_VLAN_EXTEND_MASK;
 601         ret = eth_em_vlan_offload_set(dev, mask);
 602         if (ret) {
 603                 PMD_INIT_LOG(ERR, "Unable to update vlan offload");
 604                 em_dev_clear_queues(dev);
 605                 return ret;
 606         }
 607
 608         /* Set Interrupt Throttling Rate to maximum allowed value. */
 609         E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
 610
 611         /* Setup link speed and duplex */
 612         speeds = &dev->data->dev_conf.link_speeds;
 613         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
 614                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 615                 hw->mac.autoneg = 1;
 616         } else {
 617                 num_speeds = 0;
 618                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
 619
 620                 /* Reset */
 621                 hw->phy.autoneg_advertised = 0;
 622
 623                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
 624                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
 625                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
 626                         num_speeds = -1;
 627                         goto error_invalid_config;
 628                 }
 629                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
 630                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
 631                         num_speeds++;
 632                 }
 633                 if (*speeds & ETH_LINK_SPEED_10M) {
 634                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
 635                         num_speeds++;
 636                 }
 637                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
 638                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
 639                         num_speeds++;
 640                 }
 641                 if (*speeds & ETH_LINK_SPEED_100M) {
 642                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
 643                         num_speeds++;
 644                 }
 645                 if (*speeds & ETH_LINK_SPEED_1G) {
 646                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
 647                         num_speeds++;
 648                 }
 649                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
 650                         goto error_invalid_config;
 651
 652                 /* Set/reset the mac.autoneg based on the link speed,
 653                  * fixed or not
 654                  */
 655                 if (!autoneg) {
 656                         hw->mac.autoneg = 0;
 657                         hw->mac.forced_speed_duplex =
 658                                         hw->phy.autoneg_advertised;
 659                 } else {
 660                         hw->mac.autoneg = 1;
 661                 }
 662         }
 663
 664         e1000_setup_link(hw);
 665
 666         if (rte_intr_allow_others(intr_handle)) {
 667                 /* check if lsc interrupt is enabled */
 668                 if (dev->data->dev_conf.intr_conf.lsc != 0) {
 669                         ret = eth_em_interrupt_setup(dev);
 670                         if (ret) {
 671                                 PMD_INIT_LOG(ERR, "Unable to setup interrupts");
 672                                 em_dev_clear_queues(dev);
 673                                 return ret;
 674                         }
 675                 }
 676         } else {
 677                 rte_intr_callback_unregister(intr_handle,
 678                                                 eth_em_interrupt_handler,
 679                                                 (void *)dev);
 680                 if (dev->data->dev_conf.intr_conf.lsc != 0)
 681                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
 682                                      " no intr multiplexn");
 683         }
 684         /* check if rxq interrupt is enabled */
 685         if (dev->data->dev_conf.intr_conf.rxq != 0)
 686                 eth_em_rxq_interrupt_setup(dev);
 687
 688         rte_intr_enable(intr_handle);
 689
 690         adapter->stopped = 0;
 691
 692         eth_em_rxtx_control(dev, true);
 693         eth_em_link_update(dev, 0);
 694
 695         PMD_INIT_LOG(DEBUG, "<<");
 696
 697         return 0;
 698
 699 error_invalid_config:
 700         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
 701                      dev->data->dev_conf.link_speeds, dev->data->port_id);
 702         em_dev_clear_queues(dev);
 703         return -EINVAL;
 704 }
 705
 706 /*********************************************************************
 707  *
 708  *  This routine disables all traffic on the adapter by issuing a
 709  *  global reset on the MAC.
 710  *
 711  **********************************************************************/
 712 static void
 713 eth_em_stop(struct rte_eth_dev *dev)
 714 {
 715         struct rte_eth_link link;
 716         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 717         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 718         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 719
 720         dev->data->dev_started = 0;
 721
 722         eth_em_rxtx_control(dev, false);
 723         em_rxq_intr_disable(hw);
 724         em_lsc_intr_disable(hw);
 725
 726         e1000_reset_hw(hw);
 727
 728         /* Flush desc rings for i219 */
 729         if (hw->mac.type == e1000_pch_spt || hw->mac.type == e1000_pch_cnp)
 730                 em_flush_desc_rings(dev);
 731
 732         if (hw->mac.type >= e1000_82544)
 733                 E1000_WRITE_REG(hw, E1000_WUC, 0);
 734
 735         /* Power down the phy. Needed to make the link go down */
 736         e1000_power_down_phy(hw);
 737
 738         em_dev_clear_queues(dev);
 739
 740         /* clear the recorded link status */
 741         memset(&link, 0, sizeof(link));
 742         rte_eth_linkstatus_set(dev, &link);
 743
 744         if (!rte_intr_allow_others(intr_handle))
 745                 /* resume to the default handler */
 746                 rte_intr_callback_register(intr_handle,
 747                                            eth_em_interrupt_handler,
 748                                            (void *)dev);
 749
 750         /* Clean datapath event and queue/vec mapping */
 751         rte_intr_efd_disable(intr_handle);
 752         if (intr_handle->intr_vec != NULL) {
 753                 rte_free(intr_handle->intr_vec);
 754                 intr_handle->intr_vec = NULL;
 755         }
 756 }
 757
 758 static int
 759 eth_em_close(struct rte_eth_dev *dev)
 760 {
 761         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 762         struct e1000_adapter *adapter =
 763                 E1000_DEV_PRIVATE(dev->data->dev_private);
 764         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 765         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 766
 767         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 768                 return 0;
 769
 770         eth_em_stop(dev);
 771         adapter->stopped = 1;
 772         em_dev_free_queues(dev);
 773         e1000_phy_hw_reset(hw);
 774         em_release_manageability(hw);
 775         em_hw_control_release(hw);
 776
 777         dev->dev_ops = NULL;
 778         dev->rx_pkt_burst = NULL;
 779         dev->tx_pkt_burst = NULL;
 780
 781         /* disable uio intr before callback unregister */
 782         rte_intr_disable(intr_handle);
 783         rte_intr_callback_unregister(intr_handle,
 784                                      eth_em_interrupt_handler, dev);
 785
 786         return 0;
 787 }
 788
 789 static int
 790 em_get_rx_buffer_size(struct e1000_hw *hw)
 791 {
 792         uint32_t rx_buf_size;
 793
 794         rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
 795         return rx_buf_size;
 796 }
 797
 798 /*********************************************************************
 799  *
 800  *  Initialize the hardware
 801  *
 802  **********************************************************************/
 803 static int
 804 em_hardware_init(struct e1000_hw *hw)
 805 {
 806         uint32_t rx_buf_size;
 807         int diag;
 808
 809         /* Issue a global reset */
 810         e1000_reset_hw(hw);
 811
 812         /* Let the firmware know the OS is in control */
 813         em_hw_control_acquire(hw);
 814
 815         /*
 816          * These parameters control the automatic generation (Tx) and
 817          * response (Rx) to Ethernet PAUSE frames.
 818          * - High water mark should allow for at least two standard size (1518)
 819          *   frames to be received after sending an XOFF.
 820          * - Low water mark works best when it is very near the high water mark.
 821          *   This allows the receiver to restart by sending XON when it has
 822          *   drained a bit. Here we use an arbitrary value of 1500 which will
 823          *   restart after one full frame is pulled from the buffer. There
 824          *   could be several smaller frames in the buffer and if so they will
 825          *   not trigger the XON until their total number reduces the buffer
 826          *   by 1500.
 827          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
 828          */
 829         rx_buf_size = em_get_rx_buffer_size(hw);
 830
 831         hw->fc.high_water = rx_buf_size -
 832                 PMD_ROUNDUP(RTE_ETHER_MAX_LEN * 2, 1024);
 833         hw->fc.low_water = hw->fc.high_water - 1500;
 834
 835         if (hw->mac.type == e1000_80003es2lan)
 836                 hw->fc.pause_time = UINT16_MAX;
 837         else
 838                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
 839
 840         hw->fc.send_xon = 1;
 841
 842         /* Set Flow control, use the tunable location if sane */
 843         if (em_fc_setting <= e1000_fc_full)
 844                 hw->fc.requested_mode = em_fc_setting;
 845         else
 846                 hw->fc.requested_mode = e1000_fc_none;
 847
 848         /* Workaround: no TX flow ctrl for PCH */
 849         if (hw->mac.type == e1000_pchlan)
 850                 hw->fc.requested_mode = e1000_fc_rx_pause;
 851
 852         /* Override - settings for PCH2LAN, ya its magic :) */
 853         if (hw->mac.type == e1000_pch2lan) {
 854                 hw->fc.high_water = 0x5C20;
 855                 hw->fc.low_water = 0x5048;
 856                 hw->fc.pause_time = 0x0650;
 857                 hw->fc.refresh_time = 0x0400;
 858         } else if (hw->mac.type == e1000_pch_lpt ||
 859                    hw->mac.type == e1000_pch_spt ||
 860                    hw->mac.type == e1000_pch_cnp) {
 861                 hw->fc.requested_mode = e1000_fc_full;
 862         }
 863
 864         diag = e1000_init_hw(hw);
 865         if (diag < 0)
 866                 return diag;
 867         e1000_check_for_link(hw);
 868         return 0;
 869 }
 870
 871 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
 872 static int
 873 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 874 {
 875         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 876         struct e1000_hw_stats *stats =
 877                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 878         int pause_frames;
 879
 880         if(hw->phy.media_type == e1000_media_type_copper ||
 881                         (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
 882                 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
 883                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
 884         }
 885
 886         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
 887         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
 888         stats->scc += E1000_READ_REG(hw, E1000_SCC);
 889         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
 890
 891         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
 892         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
 893         stats->colc += E1000_READ_REG(hw, E1000_COLC);
 894         stats->dc += E1000_READ_REG(hw, E1000_DC);
 895         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
 896         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
 897         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
 898
 899         /*
 900          * For watchdog management we need to know if we have been
 901          * paused during the last interval, so capture that here.
 902          */
 903         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
 904         stats->xoffrxc += pause_frames;
 905         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
 906         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
 907         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
 908         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
 909         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
 910         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
 911         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
 912         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
 913         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
 914         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
 915         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
 916         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
 917
 918         /*
 919          * For the 64-bit byte counters the low dword must be read first.
 920          * Both registers clear on the read of the high dword.
 921          */
 922
 923         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
 924         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
 925         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
 926         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
 927
 928         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
 929         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
 930         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
 931         stats->roc += E1000_READ_REG(hw, E1000_ROC);
 932         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
 933
 934         stats->tor += E1000_READ_REG(hw, E1000_TORH);
 935         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
 936
 937         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
 938         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
 939         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
 940         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
 941         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
 942         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
 943         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
 944         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
 945         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
 946         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
 947
 948         /* Interrupt Counts */
 949
 950         if (hw->mac.type >= e1000_82571) {
 951                 stats->iac += E1000_READ_REG(hw, E1000_IAC);
 952                 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
 953                 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
 954                 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
 955                 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
 956                 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
 957                 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
 958                 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
 959                 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
 960         }
 961
 962         if (hw->mac.type >= e1000_82543) {
 963                 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
 964                 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
 965                 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
 966                 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
 967                 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
 968                 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
 969         }
 970
 971         if (rte_stats == NULL)
 972                 return -EINVAL;
 973
 974         /* Rx Errors */
 975         rte_stats->imissed = stats->mpc;
 976         rte_stats->ierrors = stats->crcerrs +
 977                              stats->rlec + stats->ruc + stats->roc +
 978                              stats->rxerrc + stats->algnerrc + stats->cexterr;
 979
 980         /* Tx Errors */
 981         rte_stats->oerrors = stats->ecol + stats->latecol;
 982
 983         rte_stats->ipackets = stats->gprc;
 984         rte_stats->opackets = stats->gptc;
 985         rte_stats->ibytes   = stats->gorc;
 986         rte_stats->obytes   = stats->gotc;
 987         return 0;
 988 }
 989
 990 static int
 991 eth_em_stats_reset(struct rte_eth_dev *dev)
 992 {
 993         struct e1000_hw_stats *hw_stats =
 994                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 995
 996         /* HW registers are cleared on read */
 997         eth_em_stats_get(dev, NULL);
 998
 999         /* Reset software totals */
1000         memset(hw_stats, 0, sizeof(*hw_stats));
1001
1002         return 0;
1003 }
1004
1005 static int
1006 eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1007 {
1008         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1009         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1010         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1011
1012         em_rxq_intr_enable(hw);
1013         rte_intr_ack(intr_handle);
1014
1015         return 0;
1016 }
1017
1018 static int
1019 eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1020 {
1021         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1022
1023         em_rxq_intr_disable(hw);
1024
1025         return 0;
1026 }
1027
1028 uint32_t
1029 em_get_max_pktlen(struct rte_eth_dev *dev)
1030 {
1031         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1032
1033         switch (hw->mac.type) {
1034         case e1000_82571:
1035         case e1000_82572:
1036         case e1000_ich9lan:
1037         case e1000_ich10lan:
1038         case e1000_pch2lan:
1039         case e1000_pch_lpt:
1040         case e1000_pch_spt:
1041         case e1000_pch_cnp:
1042         case e1000_82574:
1043         case e1000_80003es2lan: /* 9K Jumbo Frame size */
1044         case e1000_82583:
1045                 return 0x2412;
1046         case e1000_pchlan:
1047                 return 0x1000;
1048         /* Adapters that do not support jumbo frames */
1049         case e1000_ich8lan:
1050                 return RTE_ETHER_MAX_LEN;
1051         default:
1052                 return MAX_JUMBO_FRAME_SIZE;
1053         }
1054 }
1055
1056 static int
1057 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1058 {
1059         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1060
1061         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1062         dev_info->max_rx_pktlen = em_get_max_pktlen(dev);
1063         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1064
1065         /*
1066          * Starting with 631xESB hw supports 2 TX/RX queues per port.
1067          * Unfortunatelly, all these nics have just one TX context.
1068          * So we have few choises for TX:
1069          * - Use just one TX queue.
1070          * - Allow cksum offload only for one TX queue.
1071          * - Don't allow TX cksum offload at all.
1072          * For now, option #1 was chosen.
1073          * To use second RX queue we have to use extended RX descriptor
1074          * (Multiple Receive Queues are mutually exclusive with UDP
1075          * fragmentation and are not supported when a legacy receive
1076          * descriptor format is used).
1077          * Which means separate RX routinies - as legacy nics (82540, 82545)
1078          * don't support extended RXD.
1079          * To avoid it we support just one RX queue for now (no RSS).
1080          */
1081
1082         dev_info->max_rx_queues = 1;
1083         dev_info->max_tx_queues = 1;
1084
1085         dev_info->rx_queue_offload_capa = em_get_rx_queue_offloads_capa(dev);
1086         dev_info->rx_offload_capa = em_get_rx_port_offloads_capa(dev) |
1087                                     dev_info->rx_queue_offload_capa;
1088         dev_info->tx_queue_offload_capa = em_get_tx_queue_offloads_capa(dev);
1089         dev_info->tx_offload_capa = em_get_tx_port_offloads_capa(dev) |
1090                                     dev_info->tx_queue_offload_capa;
1091
1092         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1093                 .nb_max = E1000_MAX_RING_DESC,
1094                 .nb_min = E1000_MIN_RING_DESC,
1095                 .nb_align = EM_RXD_ALIGN,
1096         };
1097
1098         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1099                 .nb_max = E1000_MAX_RING_DESC,
1100                 .nb_min = E1000_MIN_RING_DESC,
1101                 .nb_align = EM_TXD_ALIGN,
1102                 .nb_seg_max = EM_TX_MAX_SEG,
1103                 .nb_mtu_seg_max = EM_TX_MAX_MTU_SEG,
1104         };
1105
1106         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1107                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1108                         ETH_LINK_SPEED_1G;
1109
1110         /* Preferred queue parameters */
1111         dev_info->default_rxportconf.nb_queues = 1;
1112         dev_info->default_txportconf.nb_queues = 1;
1113         dev_info->default_txportconf.ring_size = 256;
1114         dev_info->default_rxportconf.ring_size = 256;
1115
1116         return 0;
1117 }
1118
1119 /* return 0 means link status changed, -1 means not changed */
1120 static int
1121 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1122 {
1123         struct e1000_hw *hw =
1124                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1125         struct rte_eth_link link;
1126         int link_up, count;
1127
1128         link_up = 0;
1129         hw->mac.get_link_status = 1;
1130
1131         /* possible wait-to-complete in up to 9 seconds */
1132         for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1133                 /* Read the real link status */
1134                 switch (hw->phy.media_type) {
1135                 case e1000_media_type_copper:
1136                         /* Do the work to read phy */
1137                         e1000_check_for_link(hw);
1138                         link_up = !hw->mac.get_link_status;
1139                         break;
1140
1141                 case e1000_media_type_fiber:
1142                         e1000_check_for_link(hw);
1143                         link_up = (E1000_READ_REG(hw, E1000_STATUS) &
1144                                         E1000_STATUS_LU);
1145                         break;
1146
1147                 case e1000_media_type_internal_serdes:
1148                         e1000_check_for_link(hw);
1149                         link_up = hw->mac.serdes_has_link;
1150                         break;
1151
1152                 default:
1153                         break;
1154                 }
1155                 if (link_up || wait_to_complete == 0)
1156                         break;
1157                 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
1158         }
1159         memset(&link, 0, sizeof(link));
1160
1161         /* Now we check if a transition has happened */
1162         if (link_up) {
1163                 uint16_t duplex, speed;
1164                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1165                 link.link_duplex = (duplex == FULL_DUPLEX) ?
1166                                 ETH_LINK_FULL_DUPLEX :
1167                                 ETH_LINK_HALF_DUPLEX;
1168                 link.link_speed = speed;
1169                 link.link_status = ETH_LINK_UP;
1170                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
1171                                 ETH_LINK_SPEED_FIXED);
1172         } else {
1173                 link.link_speed = ETH_SPEED_NUM_NONE;
1174                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1175                 link.link_status = ETH_LINK_DOWN;
1176                 link.link_autoneg = ETH_LINK_FIXED;
1177         }
1178
1179         return rte_eth_linkstatus_set(dev, &link);
1180 }
1181
1182 /*
1183  * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
1184  * For ASF and Pass Through versions of f/w this means
1185  * that the driver is loaded. For AMT version type f/w
1186  * this means that the network i/f is open.
1187  */
1188 static void
1189 em_hw_control_acquire(struct e1000_hw *hw)
1190 {
1191         uint32_t ctrl_ext, swsm;
1192
1193         /* Let firmware know the driver has taken over */
1194         if (hw->mac.type == e1000_82573) {
1195                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1196                 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
1197
1198         } else {
1199                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1200                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1201                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1202         }
1203 }
1204
1205 /*
1206  * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
1207  * For ASF and Pass Through versions of f/w this means that the
1208  * driver is no longer loaded. For AMT versions of the
1209  * f/w this means that the network i/f is closed.
1210  */
1211 static void
1212 em_hw_control_release(struct e1000_hw *hw)
1213 {
1214         uint32_t ctrl_ext, swsm;
1215
1216         /* Let firmware taken over control of h/w */
1217         if (hw->mac.type == e1000_82573) {
1218                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1219                 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
1220         } else {
1221                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1222                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1223                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1224         }
1225 }
1226
1227 /*
1228  * Bit of a misnomer, what this really means is
1229  * to enable OS management of the system... aka
1230  * to disable special hardware management features.
1231  */
1232 static void
1233 em_init_manageability(struct e1000_hw *hw)
1234 {
1235         if (e1000_enable_mng_pass_thru(hw)) {
1236                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1237                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1238
1239                 /* disable hardware interception of ARP */
1240                 manc &= ~(E1000_MANC_ARP_EN);
1241
1242                 /* enable receiving management packets to the host */
1243                 manc |= E1000_MANC_EN_MNG2HOST;
1244                 manc2h |= 1 << 5;  /* Mng Port 623 */
1245                 manc2h |= 1 << 6;  /* Mng Port 664 */
1246                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1247                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1248         }
1249 }
1250
1251 /*
1252  * Give control back to hardware management
1253  * controller if there is one.
1254  */
1255 static void
1256 em_release_manageability(struct e1000_hw *hw)
1257 {
1258         uint32_t manc;
1259
1260         if (e1000_enable_mng_pass_thru(hw)) {
1261                 manc = E1000_READ_REG(hw, E1000_MANC);
1262
1263                 /* re-enable hardware interception of ARP */
1264                 manc |= E1000_MANC_ARP_EN;
1265                 manc &= ~E1000_MANC_EN_MNG2HOST;
1266
1267                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1268         }
1269 }
1270
1271 static int
1272 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1273 {
1274         struct e1000_hw *hw =
1275                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1276         uint32_t rctl;
1277
1278         rctl = E1000_READ_REG(hw, E1000_RCTL);
1279         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1280         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1281
1282         return 0;
1283 }
1284
1285 static int
1286 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1287 {
1288         struct e1000_hw *hw =
1289                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1290         uint32_t rctl;
1291
1292         rctl = E1000_READ_REG(hw, E1000_RCTL);
1293         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1294         if (dev->data->all_multicast == 1)
1295                 rctl |= E1000_RCTL_MPE;
1296         else
1297                 rctl &= (~E1000_RCTL_MPE);
1298         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1299
1300         return 0;
1301 }
1302
1303 static int
1304 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1305 {
1306         struct e1000_hw *hw =
1307                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1308         uint32_t rctl;
1309
1310         rctl = E1000_READ_REG(hw, E1000_RCTL);
1311         rctl |= E1000_RCTL_MPE;
1312         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1313
1314         return 0;
1315 }
1316
1317 static int
1318 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1319 {
1320         struct e1000_hw *hw =
1321                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1322         uint32_t rctl;
1323
1324         if (dev->data->promiscuous == 1)
1325                 return 0; /* must remain in all_multicast mode */
1326         rctl = E1000_READ_REG(hw, E1000_RCTL);
1327         rctl &= (~E1000_RCTL_MPE);
1328         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1329
1330         return 0;
1331 }
1332
1333 static int
1334 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1335 {
1336         struct e1000_hw *hw =
1337                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1338         struct e1000_vfta * shadow_vfta =
1339                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1340         uint32_t vfta;
1341         uint32_t vid_idx;
1342         uint32_t vid_bit;
1343
1344         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1345                               E1000_VFTA_ENTRY_MASK);
1346         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1347         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1348         if (on)
1349                 vfta |= vid_bit;
1350         else
1351                 vfta &= ~vid_bit;
1352         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1353
1354         /* update local VFTA copy */
1355         shadow_vfta->vfta[vid_idx] = vfta;
1356
1357         return 0;
1358 }
1359
1360 static void
1361 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1362 {
1363         struct e1000_hw *hw =
1364                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1365         uint32_t reg;
1366
1367         /* Filter Table Disable */
1368         reg = E1000_READ_REG(hw, E1000_RCTL);
1369         reg &= ~E1000_RCTL_CFIEN;
1370         reg &= ~E1000_RCTL_VFE;
1371         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1372 }
1373
1374 static void
1375 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1376 {
1377         struct e1000_hw *hw =
1378                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1379         struct e1000_vfta * shadow_vfta =
1380                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1381         uint32_t reg;
1382         int i;
1383
1384         /* Filter Table Enable, CFI not used for packet acceptance */
1385         reg = E1000_READ_REG(hw, E1000_RCTL);
1386         reg &= ~E1000_RCTL_CFIEN;
1387         reg |= E1000_RCTL_VFE;
1388         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1389
1390         /* restore vfta from local copy */
1391         for (i = 0; i < IGB_VFTA_SIZE; i++)
1392                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1393 }
1394
1395 static void
1396 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1397 {
1398         struct e1000_hw *hw =
1399                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1400         uint32_t reg;
1401
1402         /* VLAN Mode Disable */
1403         reg = E1000_READ_REG(hw, E1000_CTRL);
1404         reg &= ~E1000_CTRL_VME;
1405         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1406
1407 }
1408
1409 static void
1410 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1411 {
1412         struct e1000_hw *hw =
1413                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1414         uint32_t reg;
1415
1416         /* VLAN Mode Enable */
1417         reg = E1000_READ_REG(hw, E1000_CTRL);
1418         reg |= E1000_CTRL_VME;
1419         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1420 }
1421
1422 static int
1423 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1424 {
1425         struct rte_eth_rxmode *rxmode;
1426
1427         rxmode = &dev->data->dev_conf.rxmode;
1428         if(mask & ETH_VLAN_STRIP_MASK){
1429                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1430                         em_vlan_hw_strip_enable(dev);
1431                 else
1432                         em_vlan_hw_strip_disable(dev);
1433         }
1434
1435         if(mask & ETH_VLAN_FILTER_MASK){
1436                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1437                         em_vlan_hw_filter_enable(dev);
1438                 else
1439                         em_vlan_hw_filter_disable(dev);
1440         }
1441
1442         return 0;
1443 }
1444
1445 /*
1446  * It enables the interrupt mask and then enable the interrupt.
1447  *
1448  * @param dev
1449  *  Pointer to struct rte_eth_dev.
1450  *
1451  * @return
1452  *  - On success, zero.
1453  *  - On failure, a negative value.
1454  */
1455 static int
1456 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1457 {
1458         uint32_t regval;
1459         struct e1000_hw *hw =
1460                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1461
1462         /* clear interrupt */
1463         E1000_READ_REG(hw, E1000_ICR);
1464         regval = E1000_READ_REG(hw, E1000_IMS);
1465         E1000_WRITE_REG(hw, E1000_IMS,
1466                         regval | E1000_ICR_LSC | E1000_ICR_OTHER);
1467         return 0;
1468 }
1469
1470 /*
1471  * It clears the interrupt causes and enables the interrupt.
1472  * It will be called once only during nic initialized.
1473  *
1474  * @param dev
1475  *  Pointer to struct rte_eth_dev.
1476  *
1477  * @return
1478  *  - On success, zero.
1479  *  - On failure, a negative value.
1480  */
1481 static int
1482 eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev)
1483 {
1484         struct e1000_hw *hw =
1485         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1486
1487         E1000_READ_REG(hw, E1000_ICR);
1488         em_rxq_intr_enable(hw);
1489         return 0;
1490 }
1491
1492 /*
1493  * It enable receive packet interrupt.
1494  * @param hw
1495  * Pointer to struct e1000_hw
1496  *
1497  * @return
1498  */
1499 static void
1500 em_rxq_intr_enable(struct e1000_hw *hw)
1501 {
1502         E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_RXT0);
1503         E1000_WRITE_FLUSH(hw);
1504 }
1505
1506 /*
1507  * It disabled lsc interrupt.
1508  * @param hw
1509  * Pointer to struct e1000_hw
1510  *
1511  * @return
1512  */
1513 static void
1514 em_lsc_intr_disable(struct e1000_hw *hw)
1515 {
1516         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_LSC | E1000_IMS_OTHER);
1517         E1000_WRITE_FLUSH(hw);
1518 }
1519
1520 /*
1521  * It disabled receive packet interrupt.
1522  * @param hw
1523  * Pointer to struct e1000_hw
1524  *
1525  * @return
1526  */
1527 static void
1528 em_rxq_intr_disable(struct e1000_hw *hw)
1529 {
1530         E1000_READ_REG(hw, E1000_ICR);
1531         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0);
1532         E1000_WRITE_FLUSH(hw);
1533 }
1534
1535 /*
1536  * It reads ICR and gets interrupt causes, check it and set a bit flag
1537  * to update link status.
1538  *
1539  * @param dev
1540  *  Pointer to struct rte_eth_dev.
1541  *
1542  * @return
1543  *  - On success, zero.
1544  *  - On failure, a negative value.
1545  */
1546 static int
1547 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1548 {
1549         uint32_t icr;
1550         struct e1000_hw *hw =
1551                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1552         struct e1000_interrupt *intr =
1553                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1554
1555         /* read-on-clear nic registers here */
1556         icr = E1000_READ_REG(hw, E1000_ICR);
1557         if (icr & E1000_ICR_LSC) {
1558                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1559         }
1560
1561         return 0;
1562 }
1563
1564 /*
1565  * It executes link_update after knowing an interrupt is prsent.
1566  *
1567  * @param dev
1568  *  Pointer to struct rte_eth_dev.
1569  *
1570  * @return
1571  *  - On success, zero.
1572  *  - On failure, a negative value.
1573  */
1574 static int
1575 eth_em_interrupt_action(struct rte_eth_dev *dev,
1576                         struct rte_intr_handle *intr_handle)
1577 {
1578         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1579         struct e1000_hw *hw =
1580                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1581         struct e1000_interrupt *intr =
1582                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1583         struct rte_eth_link link;
1584         int ret;
1585
1586         if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1587                 return -1;
1588
1589         intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1590         rte_intr_ack(intr_handle);
1591
1592         /* set get_link_status to check register later */
1593         hw->mac.get_link_status = 1;
1594         ret = eth_em_link_update(dev, 0);
1595
1596         /* check if link has changed */
1597         if (ret < 0)
1598                 return 0;
1599
1600         rte_eth_linkstatus_get(dev, &link);
1601
1602         if (link.link_status) {
1603                 PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s",
1604                              dev->data->port_id, link.link_speed,
1605                              link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1606                              "full-duplex" : "half-duplex");
1607         } else {
1608                 PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
1609         }
1610         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
1611                      pci_dev->addr.domain, pci_dev->addr.bus,
1612                      pci_dev->addr.devid, pci_dev->addr.function);
1613
1614         return 0;
1615 }
1616
1617 /**
1618  * Interrupt handler which shall be registered at first.
1619  *
1620  * @param handle
1621  *  Pointer to interrupt handle.
1622  * @param param
1623  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1624  *
1625  * @return
1626  *  void
1627  */
1628 static void
1629 eth_em_interrupt_handler(void *param)
1630 {
1631         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1632
1633         eth_em_interrupt_get_status(dev);
1634         eth_em_interrupt_action(dev, dev->intr_handle);
1635         rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1636 }
1637
1638 static int
1639 eth_em_led_on(struct rte_eth_dev *dev)
1640 {
1641         struct e1000_hw *hw;
1642
1643         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1644         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1645 }
1646
1647 static int
1648 eth_em_led_off(struct rte_eth_dev *dev)
1649 {
1650         struct e1000_hw *hw;
1651
1652         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1653         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1654 }
1655
1656 static int
1657 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1658 {
1659         struct e1000_hw *hw;
1660         uint32_t ctrl;
1661         int tx_pause;
1662         int rx_pause;
1663
1664         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1665         fc_conf->pause_time = hw->fc.pause_time;
1666         fc_conf->high_water = hw->fc.high_water;
1667         fc_conf->low_water = hw->fc.low_water;
1668         fc_conf->send_xon = hw->fc.send_xon;
1669         fc_conf->autoneg = hw->mac.autoneg;
1670
1671         /*
1672          * Return rx_pause and tx_pause status according to actual setting of
1673          * the TFCE and RFCE bits in the CTRL register.
1674          */
1675         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1676         if (ctrl & E1000_CTRL_TFCE)
1677                 tx_pause = 1;
1678         else
1679                 tx_pause = 0;
1680
1681         if (ctrl & E1000_CTRL_RFCE)
1682                 rx_pause = 1;
1683         else
1684                 rx_pause = 0;
1685
1686         if (rx_pause && tx_pause)
1687                 fc_conf->mode = RTE_FC_FULL;
1688         else if (rx_pause)
1689                 fc_conf->mode = RTE_FC_RX_PAUSE;
1690         else if (tx_pause)
1691                 fc_conf->mode = RTE_FC_TX_PAUSE;
1692         else
1693                 fc_conf->mode = RTE_FC_NONE;
1694
1695         return 0;
1696 }
1697
1698 static int
1699 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1700 {
1701         struct e1000_hw *hw;
1702         int err;
1703         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1704                 e1000_fc_none,
1705                 e1000_fc_rx_pause,
1706                 e1000_fc_tx_pause,
1707                 e1000_fc_full
1708         };
1709         uint32_t rx_buf_size;
1710         uint32_t max_high_water;
1711         uint32_t rctl;
1712
1713         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1714         if (fc_conf->autoneg != hw->mac.autoneg)
1715                 return -ENOTSUP;
1716         rx_buf_size = em_get_rx_buffer_size(hw);
1717         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1718
1719         /* At least reserve one Ethernet frame for watermark */
1720         max_high_water = rx_buf_size - RTE_ETHER_MAX_LEN;
1721         if ((fc_conf->high_water > max_high_water) ||
1722             (fc_conf->high_water < fc_conf->low_water)) {
1723                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1724                 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
1725                 return -EINVAL;
1726         }
1727
1728         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1729         hw->fc.pause_time     = fc_conf->pause_time;
1730         hw->fc.high_water     = fc_conf->high_water;
1731         hw->fc.low_water      = fc_conf->low_water;
1732         hw->fc.send_xon       = fc_conf->send_xon;
1733
1734         err = e1000_setup_link_generic(hw);
1735         if (err == E1000_SUCCESS) {
1736
1737                 /* check if we want to forward MAC frames - driver doesn't have native
1738                  * capability to do that, so we'll write the registers ourselves */
1739
1740                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1741
1742                 /* set or clear MFLCN.PMCF bit depending on configuration */
1743                 if (fc_conf->mac_ctrl_frame_fwd != 0)
1744                         rctl |= E1000_RCTL_PMCF;
1745                 else
1746                         rctl &= ~E1000_RCTL_PMCF;
1747
1748                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1749                 E1000_WRITE_FLUSH(hw);
1750
1751                 return 0;
1752         }
1753
1754         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1755         return -EIO;
1756 }
1757
1758 static int
1759 eth_em_rar_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1760                 uint32_t index, __rte_unused uint32_t pool)
1761 {
1762         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1763
1764         return e1000_rar_set(hw, mac_addr->addr_bytes, index);
1765 }
1766
1767 static void
1768 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1769 {
1770         uint8_t addr[RTE_ETHER_ADDR_LEN];
1771         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1772
1773         memset(addr, 0, sizeof(addr));
1774
1775         e1000_rar_set(hw, addr, index);
1776 }
1777
1778 static int
1779 eth_em_default_mac_addr_set(struct rte_eth_dev *dev,
1780                             struct rte_ether_addr *addr)
1781 {
1782         eth_em_rar_clear(dev, 0);
1783
1784         return eth_em_rar_set(dev, (void *)addr, 0, 0);
1785 }
1786
1787 static int
1788 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1789 {
1790         struct rte_eth_dev_info dev_info;
1791         struct e1000_hw *hw;
1792         uint32_t frame_size;
1793         uint32_t rctl;
1794         int ret;
1795
1796         ret = eth_em_infos_get(dev, &dev_info);
1797         if (ret != 0)
1798                 return ret;
1799
1800         frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
1801                 VLAN_TAG_SIZE;
1802
1803         /* check that mtu is within the allowed range */
1804         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
1805                 return -EINVAL;
1806
1807         /* refuse mtu that requires the support of scattered packets when this
1808          * feature has not been enabled before. */
1809         if (!dev->data->scattered_rx &&
1810             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1811                 return -EINVAL;
1812
1813         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1814         rctl = E1000_READ_REG(hw, E1000_RCTL);
1815
1816         /* switch to jumbo mode if needed */
1817         if (frame_size > RTE_ETHER_MAX_LEN) {
1818                 dev->data->dev_conf.rxmode.offloads |=
1819                         DEV_RX_OFFLOAD_JUMBO_FRAME;
1820                 rctl |= E1000_RCTL_LPE;
1821         } else {
1822                 dev->data->dev_conf.rxmode.offloads &=
1823                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1824                 rctl &= ~E1000_RCTL_LPE;
1825         }
1826         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1827
1828         /* update max frame size */
1829         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1830         return 0;
1831 }
1832
1833 static int
1834 eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
1835                         struct rte_ether_addr *mc_addr_set,
1836                         uint32_t nb_mc_addr)
1837 {
1838         struct e1000_hw *hw;
1839
1840         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1841         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
1842         return 0;
1843 }
1844
1845 RTE_PMD_REGISTER_PCI(net_e1000_em, rte_em_pmd);
1846 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_em, pci_id_em_map);
1847 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_em, "* igb_uio | uio_pci_generic | vfio-pci");
1848
1849 /* see e1000_logs.c */
1850 RTE_INIT(igb_init_log)
1851 {
1852         e1000_igb_init_log();
1853 }