4 * Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
40 #include <rte_common.h>
41 #include <rte_interrupts.h>
42 #include <rte_byteorder.h>
44 #include <rte_debug.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memory.h>
49 #include <rte_memzone.h>
51 #include <rte_atomic.h>
52 #include <rte_malloc.h>
55 #include "e1000_logs.h"
56 #include "base/e1000_api.h"
57 #include "e1000_ethdev.h"
59 #define EM_EIAC 0x000DC
61 #define PMD_ROUNDUP(x,y) (((x) + (y) - 1)/(y) * (y))
64 static int eth_em_configure(struct rte_eth_dev *dev);
65 static int eth_em_start(struct rte_eth_dev *dev);
66 static void eth_em_stop(struct rte_eth_dev *dev);
67 static void eth_em_close(struct rte_eth_dev *dev);
68 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
69 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
70 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
71 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
72 static int eth_em_link_update(struct rte_eth_dev *dev,
73 int wait_to_complete);
74 static void eth_em_stats_get(struct rte_eth_dev *dev,
75 struct rte_eth_stats *rte_stats);
76 static void eth_em_stats_reset(struct rte_eth_dev *dev);
77 static void eth_em_infos_get(struct rte_eth_dev *dev,
78 struct rte_eth_dev_info *dev_info);
79 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
80 struct rte_eth_fc_conf *fc_conf);
81 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
82 struct rte_eth_fc_conf *fc_conf);
83 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
84 static int eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev);
85 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
86 static int eth_em_interrupt_action(struct rte_eth_dev *dev,
87 struct rte_intr_handle *handle);
88 static void eth_em_interrupt_handler(void *param);
90 static int em_hw_init(struct e1000_hw *hw);
91 static int em_hardware_init(struct e1000_hw *hw);
92 static void em_hw_control_acquire(struct e1000_hw *hw);
93 static void em_hw_control_release(struct e1000_hw *hw);
94 static void em_init_manageability(struct e1000_hw *hw);
95 static void em_release_manageability(struct e1000_hw *hw);
97 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
99 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
100 uint16_t vlan_id, int on);
101 static void eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
102 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
103 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
104 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
105 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
108 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
109 uint16_t vlan_id, int on);
112 static int eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
113 static int eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
114 static void em_lsc_intr_disable(struct e1000_hw *hw);
115 static void em_rxq_intr_enable(struct e1000_hw *hw);
116 static void em_rxq_intr_disable(struct e1000_hw *hw);
118 static int eth_em_led_on(struct rte_eth_dev *dev);
119 static int eth_em_led_off(struct rte_eth_dev *dev);
121 static int em_get_rx_buffer_size(struct e1000_hw *hw);
122 static void eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
123 uint32_t index, uint32_t pool);
124 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
126 static int eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
127 struct ether_addr *mc_addr_set,
128 uint32_t nb_mc_addr);
130 #define EM_FC_PAUSE_TIME 0x0680
131 #define EM_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
132 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
134 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
137 * The set of PCI devices this driver supports
139 static const struct rte_pci_id pci_id_em_map[] = {
140 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82540EM) },
141 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_COPPER) },
142 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_FIBER) },
143 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_COPPER) },
144 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_FIBER) },
145 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_QUAD_COPPER) },
146 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_COPPER) },
147 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_FIBER) },
148 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES) },
149 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_DUAL) },
150 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_QUAD) },
151 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER) },
152 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571PT_QUAD_COPPER) },
153 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_FIBER) },
154 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER_LP) },
155 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_COPPER) },
156 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_FIBER) },
157 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_SERDES) },
158 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI) },
159 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82573L) },
160 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574L) },
161 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574LA) },
162 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82583V) },
163 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_LM) },
164 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_V) },
165 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_LM) },
166 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_V) },
167 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM2) },
168 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V2) },
169 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM3) },
170 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V3) },
171 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM) },
172 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V) },
173 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM2) },
174 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V2) },
175 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LBG_I219_LM3) },
176 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM4) },
177 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V4) },
178 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM5) },
179 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V5) },
180 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM6) },
181 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V6) },
182 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM7) },
183 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V7) },
184 { .vendor_id = 0, /* sentinel */ },
187 static const struct eth_dev_ops eth_em_ops = {
188 .dev_configure = eth_em_configure,
189 .dev_start = eth_em_start,
190 .dev_stop = eth_em_stop,
191 .dev_close = eth_em_close,
192 .promiscuous_enable = eth_em_promiscuous_enable,
193 .promiscuous_disable = eth_em_promiscuous_disable,
194 .allmulticast_enable = eth_em_allmulticast_enable,
195 .allmulticast_disable = eth_em_allmulticast_disable,
196 .link_update = eth_em_link_update,
197 .stats_get = eth_em_stats_get,
198 .stats_reset = eth_em_stats_reset,
199 .dev_infos_get = eth_em_infos_get,
200 .mtu_set = eth_em_mtu_set,
201 .vlan_filter_set = eth_em_vlan_filter_set,
202 .vlan_offload_set = eth_em_vlan_offload_set,
203 .rx_queue_setup = eth_em_rx_queue_setup,
204 .rx_queue_release = eth_em_rx_queue_release,
205 .rx_queue_count = eth_em_rx_queue_count,
206 .rx_descriptor_done = eth_em_rx_descriptor_done,
207 .rx_descriptor_status = eth_em_rx_descriptor_status,
208 .tx_descriptor_status = eth_em_tx_descriptor_status,
209 .tx_queue_setup = eth_em_tx_queue_setup,
210 .tx_queue_release = eth_em_tx_queue_release,
211 .rx_queue_intr_enable = eth_em_rx_queue_intr_enable,
212 .rx_queue_intr_disable = eth_em_rx_queue_intr_disable,
213 .dev_led_on = eth_em_led_on,
214 .dev_led_off = eth_em_led_off,
215 .flow_ctrl_get = eth_em_flow_ctrl_get,
216 .flow_ctrl_set = eth_em_flow_ctrl_set,
217 .mac_addr_add = eth_em_rar_set,
218 .mac_addr_remove = eth_em_rar_clear,
219 .set_mc_addr_list = eth_em_set_mc_addr_list,
220 .rxq_info_get = em_rxq_info_get,
221 .txq_info_get = em_txq_info_get,
225 * Atomically reads the link status information from global
226 * structure rte_eth_dev.
229 * - Pointer to the structure rte_eth_dev to read from.
230 * - Pointer to the buffer to be saved with the link status.
233 * - On success, zero.
234 * - On failure, negative value.
237 rte_em_dev_atomic_read_link_status(struct rte_eth_dev *dev,
238 struct rte_eth_link *link)
240 struct rte_eth_link *dst = link;
241 struct rte_eth_link *src = &(dev->data->dev_link);
243 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
244 *(uint64_t *)src) == 0)
251 * Atomically writes the link status information into global
252 * structure rte_eth_dev.
255 * - Pointer to the structure rte_eth_dev to read from.
256 * - Pointer to the buffer to be saved with the link status.
259 * - On success, zero.
260 * - On failure, negative value.
263 rte_em_dev_atomic_write_link_status(struct rte_eth_dev *dev,
264 struct rte_eth_link *link)
266 struct rte_eth_link *dst = &(dev->data->dev_link);
267 struct rte_eth_link *src = link;
269 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
270 *(uint64_t *)src) == 0)
277 * eth_em_dev_is_ich8 - Check for ICH8 device
278 * @hw: pointer to the HW structure
280 * return TRUE for ICH8, otherwise FALSE
283 eth_em_dev_is_ich8(struct e1000_hw *hw)
285 DEBUGFUNC("eth_em_dev_is_ich8");
287 switch (hw->device_id) {
288 case E1000_DEV_ID_PCH_LPT_I217_LM:
289 case E1000_DEV_ID_PCH_LPT_I217_V:
290 case E1000_DEV_ID_PCH_LPTLP_I218_LM:
291 case E1000_DEV_ID_PCH_LPTLP_I218_V:
292 case E1000_DEV_ID_PCH_I218_V2:
293 case E1000_DEV_ID_PCH_I218_LM2:
294 case E1000_DEV_ID_PCH_I218_V3:
295 case E1000_DEV_ID_PCH_I218_LM3:
296 case E1000_DEV_ID_PCH_SPT_I219_LM:
297 case E1000_DEV_ID_PCH_SPT_I219_V:
298 case E1000_DEV_ID_PCH_SPT_I219_LM2:
299 case E1000_DEV_ID_PCH_SPT_I219_V2:
300 case E1000_DEV_ID_PCH_LBG_I219_LM3:
301 case E1000_DEV_ID_PCH_SPT_I219_LM4:
302 case E1000_DEV_ID_PCH_SPT_I219_V4:
303 case E1000_DEV_ID_PCH_SPT_I219_LM5:
304 case E1000_DEV_ID_PCH_SPT_I219_V5:
305 case E1000_DEV_ID_PCH_CNP_I219_LM6:
306 case E1000_DEV_ID_PCH_CNP_I219_V6:
307 case E1000_DEV_ID_PCH_CNP_I219_LM7:
308 case E1000_DEV_ID_PCH_CNP_I219_V7:
316 eth_em_dev_init(struct rte_eth_dev *eth_dev)
318 struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(eth_dev);
319 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
320 struct e1000_adapter *adapter =
321 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
322 struct e1000_hw *hw =
323 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
324 struct e1000_vfta * shadow_vfta =
325 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
327 eth_dev->dev_ops = ð_em_ops;
328 eth_dev->rx_pkt_burst = (eth_rx_burst_t)ð_em_recv_pkts;
329 eth_dev->tx_pkt_burst = (eth_tx_burst_t)ð_em_xmit_pkts;
330 eth_dev->tx_pkt_prepare = (eth_tx_prep_t)ð_em_prep_pkts;
332 /* for secondary processes, we don't initialise any further as primary
333 * has already done this work. Only check we don't need a different
335 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
336 if (eth_dev->data->scattered_rx)
337 eth_dev->rx_pkt_burst =
338 (eth_rx_burst_t)ð_em_recv_scattered_pkts;
342 rte_eth_copy_pci_info(eth_dev, pci_dev);
343 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
345 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
346 hw->device_id = pci_dev->id.device_id;
347 adapter->stopped = 0;
349 /* For ICH8 support we'll need to map the flash memory BAR */
350 if (eth_em_dev_is_ich8(hw))
351 hw->flash_address = (void *)pci_dev->mem_resource[1].addr;
353 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
354 em_hw_init(hw) != 0) {
355 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
357 eth_dev->data->port_id, pci_dev->id.vendor_id,
358 pci_dev->id.device_id);
362 /* Allocate memory for storing MAC addresses */
363 eth_dev->data->mac_addrs = rte_zmalloc("e1000", ETHER_ADDR_LEN *
364 hw->mac.rar_entry_count, 0);
365 if (eth_dev->data->mac_addrs == NULL) {
366 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
367 "store MAC addresses",
368 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
372 /* Copy the permanent MAC address */
373 ether_addr_copy((struct ether_addr *) hw->mac.addr,
374 eth_dev->data->mac_addrs);
376 /* initialize the vfta */
377 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
379 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
380 eth_dev->data->port_id, pci_dev->id.vendor_id,
381 pci_dev->id.device_id);
383 rte_intr_callback_register(intr_handle,
384 eth_em_interrupt_handler, eth_dev);
390 eth_em_dev_uninit(struct rte_eth_dev *eth_dev)
392 struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(eth_dev);
393 struct e1000_adapter *adapter =
394 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
395 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
397 PMD_INIT_FUNC_TRACE();
399 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
402 if (adapter->stopped == 0)
403 eth_em_close(eth_dev);
405 eth_dev->dev_ops = NULL;
406 eth_dev->rx_pkt_burst = NULL;
407 eth_dev->tx_pkt_burst = NULL;
409 rte_free(eth_dev->data->mac_addrs);
410 eth_dev->data->mac_addrs = NULL;
412 /* disable uio intr before callback unregister */
413 rte_intr_disable(intr_handle);
414 rte_intr_callback_unregister(intr_handle,
415 eth_em_interrupt_handler, eth_dev);
420 static struct eth_driver rte_em_pmd = {
422 .id_table = pci_id_em_map,
423 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
424 .probe = rte_eth_dev_pci_probe,
425 .remove = rte_eth_dev_pci_remove,
427 .eth_dev_init = eth_em_dev_init,
428 .eth_dev_uninit = eth_em_dev_uninit,
429 .dev_private_size = sizeof(struct e1000_adapter),
433 em_hw_init(struct e1000_hw *hw)
437 diag = hw->mac.ops.init_params(hw);
439 PMD_INIT_LOG(ERR, "MAC Initialization Error");
442 diag = hw->nvm.ops.init_params(hw);
444 PMD_INIT_LOG(ERR, "NVM Initialization Error");
447 diag = hw->phy.ops.init_params(hw);
449 PMD_INIT_LOG(ERR, "PHY Initialization Error");
452 (void) e1000_get_bus_info(hw);
455 hw->phy.autoneg_wait_to_complete = 0;
456 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
458 e1000_init_script_state_82541(hw, TRUE);
459 e1000_set_tbi_compatibility_82543(hw, TRUE);
462 if (hw->phy.media_type == e1000_media_type_copper) {
463 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
464 hw->phy.disable_polarity_correction = 0;
465 hw->phy.ms_type = e1000_ms_hw_default;
469 * Start from a known state, this is important in reading the nvm
474 /* Make sure we have a good EEPROM before we read from it */
475 if (e1000_validate_nvm_checksum(hw) < 0) {
477 * Some PCI-E parts fail the first check due to
478 * the link being in sleep state, call it again,
479 * if it fails a second time its a real issue.
481 diag = e1000_validate_nvm_checksum(hw);
483 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
488 /* Read the permanent MAC address out of the EEPROM */
489 diag = e1000_read_mac_addr(hw);
491 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
495 /* Now initialize the hardware */
496 diag = em_hardware_init(hw);
498 PMD_INIT_LOG(ERR, "Hardware initialization failed");
502 hw->mac.get_link_status = 1;
504 /* Indicate SOL/IDER usage */
505 diag = e1000_check_reset_block(hw);
507 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
513 em_hw_control_release(hw);
518 eth_em_configure(struct rte_eth_dev *dev)
520 struct e1000_interrupt *intr =
521 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
523 PMD_INIT_FUNC_TRACE();
524 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
525 PMD_INIT_FUNC_TRACE();
531 em_set_pba(struct e1000_hw *hw)
536 * Packet Buffer Allocation (PBA)
537 * Writing PBA sets the receive portion of the buffer
538 * the remainder is used for the transmit buffer.
539 * Devices before the 82547 had a Packet Buffer of 64K.
540 * After the 82547 the buffer was reduced to 40K.
542 switch (hw->mac.type) {
544 case e1000_82547_rev_2:
545 /* 82547: Total Packet Buffer is 40K */
546 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
550 case e1000_80003es2lan:
551 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
553 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
554 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
558 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
575 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
578 E1000_WRITE_REG(hw, E1000_PBA, pba);
582 eth_em_start(struct rte_eth_dev *dev)
584 struct e1000_adapter *adapter =
585 E1000_DEV_PRIVATE(dev->data->dev_private);
586 struct e1000_hw *hw =
587 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
588 struct rte_pci_device *pci_dev =
589 E1000_DEV_TO_PCI(dev);
590 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
592 uint32_t intr_vector = 0;
597 PMD_INIT_FUNC_TRACE();
601 e1000_power_up_phy(hw);
603 /* Set default PBA value */
606 /* Put the address into the Receive Address Array */
607 e1000_rar_set(hw, hw->mac.addr, 0);
610 * With the 82571 adapter, RAR[0] may be overwritten
611 * when the other port is reset, we make a duplicate
612 * in RAR[14] for that eventuality, this assures
613 * the interface continues to function.
615 if (hw->mac.type == e1000_82571) {
616 e1000_set_laa_state_82571(hw, TRUE);
617 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
620 /* Initialize the hardware */
621 if (em_hardware_init(hw)) {
622 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
626 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
628 /* Configure for OS presence */
629 em_init_manageability(hw);
631 if (dev->data->dev_conf.intr_conf.rxq != 0) {
632 intr_vector = dev->data->nb_rx_queues;
633 if (rte_intr_efd_enable(intr_handle, intr_vector))
637 if (rte_intr_dp_is_en(intr_handle)) {
638 intr_handle->intr_vec =
639 rte_zmalloc("intr_vec",
640 dev->data->nb_rx_queues * sizeof(int), 0);
641 if (intr_handle->intr_vec == NULL) {
642 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
643 " intr_vec", dev->data->nb_rx_queues);
647 /* enable rx interrupt */
648 em_rxq_intr_enable(hw);
653 ret = eth_em_rx_init(dev);
655 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
656 em_dev_clear_queues(dev);
660 e1000_clear_hw_cntrs_base_generic(hw);
662 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
663 ETH_VLAN_EXTEND_MASK;
664 eth_em_vlan_offload_set(dev, mask);
666 /* Set Interrupt Throttling Rate to maximum allowed value. */
667 E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
669 /* Setup link speed and duplex */
670 speeds = &dev->data->dev_conf.link_speeds;
671 if (*speeds == ETH_LINK_SPEED_AUTONEG) {
672 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
676 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
679 hw->phy.autoneg_advertised = 0;
681 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
682 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
683 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
685 goto error_invalid_config;
687 if (*speeds & ETH_LINK_SPEED_10M_HD) {
688 hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
691 if (*speeds & ETH_LINK_SPEED_10M) {
692 hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
695 if (*speeds & ETH_LINK_SPEED_100M_HD) {
696 hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
699 if (*speeds & ETH_LINK_SPEED_100M) {
700 hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
703 if (*speeds & ETH_LINK_SPEED_1G) {
704 hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
707 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
708 goto error_invalid_config;
710 /* Set/reset the mac.autoneg based on the link speed,
715 hw->mac.forced_speed_duplex =
716 hw->phy.autoneg_advertised;
722 e1000_setup_link(hw);
724 if (rte_intr_allow_others(intr_handle)) {
725 /* check if lsc interrupt is enabled */
726 if (dev->data->dev_conf.intr_conf.lsc != 0) {
727 ret = eth_em_interrupt_setup(dev);
729 PMD_INIT_LOG(ERR, "Unable to setup interrupts");
730 em_dev_clear_queues(dev);
735 rte_intr_callback_unregister(intr_handle,
736 eth_em_interrupt_handler,
738 if (dev->data->dev_conf.intr_conf.lsc != 0)
739 PMD_INIT_LOG(INFO, "lsc won't enable because of"
740 " no intr multiplexn");
742 /* check if rxq interrupt is enabled */
743 if (dev->data->dev_conf.intr_conf.rxq != 0)
744 eth_em_rxq_interrupt_setup(dev);
746 rte_intr_enable(intr_handle);
748 adapter->stopped = 0;
750 PMD_INIT_LOG(DEBUG, "<<");
754 error_invalid_config:
755 PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
756 dev->data->dev_conf.link_speeds, dev->data->port_id);
757 em_dev_clear_queues(dev);
761 /*********************************************************************
763 * This routine disables all traffic on the adapter by issuing a
764 * global reset on the MAC.
766 **********************************************************************/
768 eth_em_stop(struct rte_eth_dev *dev)
770 struct rte_eth_link link;
771 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
772 struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
773 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
775 em_rxq_intr_disable(hw);
776 em_lsc_intr_disable(hw);
779 if (hw->mac.type >= e1000_82544)
780 E1000_WRITE_REG(hw, E1000_WUC, 0);
782 /* Power down the phy. Needed to make the link go down */
783 e1000_power_down_phy(hw);
785 em_dev_clear_queues(dev);
787 /* clear the recorded link status */
788 memset(&link, 0, sizeof(link));
789 rte_em_dev_atomic_write_link_status(dev, &link);
791 if (!rte_intr_allow_others(intr_handle))
792 /* resume to the default handler */
793 rte_intr_callback_register(intr_handle,
794 eth_em_interrupt_handler,
797 /* Clean datapath event and queue/vec mapping */
798 rte_intr_efd_disable(intr_handle);
799 if (intr_handle->intr_vec != NULL) {
800 rte_free(intr_handle->intr_vec);
801 intr_handle->intr_vec = NULL;
806 eth_em_close(struct rte_eth_dev *dev)
808 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
809 struct e1000_adapter *adapter =
810 E1000_DEV_PRIVATE(dev->data->dev_private);
813 adapter->stopped = 1;
814 em_dev_free_queues(dev);
815 e1000_phy_hw_reset(hw);
816 em_release_manageability(hw);
817 em_hw_control_release(hw);
821 em_get_rx_buffer_size(struct e1000_hw *hw)
823 uint32_t rx_buf_size;
825 rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
829 /*********************************************************************
831 * Initialize the hardware
833 **********************************************************************/
835 em_hardware_init(struct e1000_hw *hw)
837 uint32_t rx_buf_size;
840 /* Issue a global reset */
843 /* Let the firmware know the OS is in control */
844 em_hw_control_acquire(hw);
847 * These parameters control the automatic generation (Tx) and
848 * response (Rx) to Ethernet PAUSE frames.
849 * - High water mark should allow for at least two standard size (1518)
850 * frames to be received after sending an XOFF.
851 * - Low water mark works best when it is very near the high water mark.
852 * This allows the receiver to restart by sending XON when it has
853 * drained a bit. Here we use an arbitrary value of 1500 which will
854 * restart after one full frame is pulled from the buffer. There
855 * could be several smaller frames in the buffer and if so they will
856 * not trigger the XON until their total number reduces the buffer
858 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
860 rx_buf_size = em_get_rx_buffer_size(hw);
862 hw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);
863 hw->fc.low_water = hw->fc.high_water - 1500;
865 if (hw->mac.type == e1000_80003es2lan)
866 hw->fc.pause_time = UINT16_MAX;
868 hw->fc.pause_time = EM_FC_PAUSE_TIME;
872 /* Set Flow control, use the tunable location if sane */
873 if (em_fc_setting <= e1000_fc_full)
874 hw->fc.requested_mode = em_fc_setting;
876 hw->fc.requested_mode = e1000_fc_none;
878 /* Workaround: no TX flow ctrl for PCH */
879 if (hw->mac.type == e1000_pchlan)
880 hw->fc.requested_mode = e1000_fc_rx_pause;
882 /* Override - settings for PCH2LAN, ya its magic :) */
883 if (hw->mac.type == e1000_pch2lan) {
884 hw->fc.high_water = 0x5C20;
885 hw->fc.low_water = 0x5048;
886 hw->fc.pause_time = 0x0650;
887 hw->fc.refresh_time = 0x0400;
888 } else if (hw->mac.type == e1000_pch_lpt ||
889 hw->mac.type == e1000_pch_spt ||
890 hw->mac.type == e1000_pch_cnp) {
891 hw->fc.requested_mode = e1000_fc_full;
894 diag = e1000_init_hw(hw);
897 e1000_check_for_link(hw);
901 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
903 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
905 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
906 struct e1000_hw_stats *stats =
907 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
910 if(hw->phy.media_type == e1000_media_type_copper ||
911 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
912 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
913 stats->sec += E1000_READ_REG(hw, E1000_SEC);
916 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
917 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
918 stats->scc += E1000_READ_REG(hw, E1000_SCC);
919 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
921 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
922 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
923 stats->colc += E1000_READ_REG(hw, E1000_COLC);
924 stats->dc += E1000_READ_REG(hw, E1000_DC);
925 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
926 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
927 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
930 * For watchdog management we need to know if we have been
931 * paused during the last interval, so capture that here.
933 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
934 stats->xoffrxc += pause_frames;
935 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
936 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
937 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
938 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
939 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
940 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
941 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
942 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
943 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
944 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
945 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
946 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
949 * For the 64-bit byte counters the low dword must be read first.
950 * Both registers clear on the read of the high dword.
953 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
954 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
955 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
956 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
958 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
959 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
960 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
961 stats->roc += E1000_READ_REG(hw, E1000_ROC);
962 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
964 stats->tor += E1000_READ_REG(hw, E1000_TORH);
965 stats->tot += E1000_READ_REG(hw, E1000_TOTH);
967 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
968 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
969 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
970 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
971 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
972 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
973 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
974 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
975 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
976 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
978 /* Interrupt Counts */
980 if (hw->mac.type >= e1000_82571) {
981 stats->iac += E1000_READ_REG(hw, E1000_IAC);
982 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
983 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
984 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
985 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
986 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
987 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
988 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
989 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
992 if (hw->mac.type >= e1000_82543) {
993 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
994 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
995 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
996 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
997 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
998 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1001 if (rte_stats == NULL)
1005 rte_stats->imissed = stats->mpc;
1006 rte_stats->ierrors = stats->crcerrs +
1007 stats->rlec + stats->ruc + stats->roc +
1008 stats->rxerrc + stats->algnerrc + stats->cexterr;
1011 rte_stats->oerrors = stats->ecol + stats->latecol;
1013 rte_stats->ipackets = stats->gprc;
1014 rte_stats->opackets = stats->gptc;
1015 rte_stats->ibytes = stats->gorc;
1016 rte_stats->obytes = stats->gotc;
1020 eth_em_stats_reset(struct rte_eth_dev *dev)
1022 struct e1000_hw_stats *hw_stats =
1023 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1025 /* HW registers are cleared on read */
1026 eth_em_stats_get(dev, NULL);
1028 /* Reset software totals */
1029 memset(hw_stats, 0, sizeof(*hw_stats));
1033 eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1035 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1036 struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
1037 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1039 em_rxq_intr_enable(hw);
1040 rte_intr_enable(intr_handle);
1046 eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1048 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1050 em_rxq_intr_disable(hw);
1056 em_get_max_pktlen(const struct e1000_hw *hw)
1058 switch (hw->mac.type) {
1062 case e1000_ich10lan:
1068 case e1000_80003es2lan: /* 9K Jumbo Frame size */
1073 /* Adapters that do not support jumbo frames */
1075 return ETHER_MAX_LEN;
1077 return MAX_JUMBO_FRAME_SIZE;
1082 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1084 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1086 dev_info->pci_dev = RTE_DEV_TO_PCI(dev->device);
1087 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1088 dev_info->max_rx_pktlen = em_get_max_pktlen(hw);
1089 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1090 dev_info->rx_offload_capa =
1091 DEV_RX_OFFLOAD_VLAN_STRIP |
1092 DEV_RX_OFFLOAD_IPV4_CKSUM |
1093 DEV_RX_OFFLOAD_UDP_CKSUM |
1094 DEV_RX_OFFLOAD_TCP_CKSUM;
1095 dev_info->tx_offload_capa =
1096 DEV_TX_OFFLOAD_VLAN_INSERT |
1097 DEV_TX_OFFLOAD_IPV4_CKSUM |
1098 DEV_TX_OFFLOAD_UDP_CKSUM |
1099 DEV_TX_OFFLOAD_TCP_CKSUM;
1102 * Starting with 631xESB hw supports 2 TX/RX queues per port.
1103 * Unfortunatelly, all these nics have just one TX context.
1104 * So we have few choises for TX:
1105 * - Use just one TX queue.
1106 * - Allow cksum offload only for one TX queue.
1107 * - Don't allow TX cksum offload at all.
1108 * For now, option #1 was chosen.
1109 * To use second RX queue we have to use extended RX descriptor
1110 * (Multiple Receive Queues are mutually exclusive with UDP
1111 * fragmentation and are not supported when a legacy receive
1112 * descriptor format is used).
1113 * Which means separate RX routinies - as legacy nics (82540, 82545)
1114 * don't support extended RXD.
1115 * To avoid it we support just one RX queue for now (no RSS).
1118 dev_info->max_rx_queues = 1;
1119 dev_info->max_tx_queues = 1;
1121 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1122 .nb_max = E1000_MAX_RING_DESC,
1123 .nb_min = E1000_MIN_RING_DESC,
1124 .nb_align = EM_RXD_ALIGN,
1127 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1128 .nb_max = E1000_MAX_RING_DESC,
1129 .nb_min = E1000_MIN_RING_DESC,
1130 .nb_align = EM_TXD_ALIGN,
1131 .nb_seg_max = EM_TX_MAX_SEG,
1132 .nb_mtu_seg_max = EM_TX_MAX_MTU_SEG,
1135 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1136 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1140 /* return 0 means link status changed, -1 means not changed */
1142 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1144 struct e1000_hw *hw =
1145 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1146 struct rte_eth_link link, old;
1147 int link_check, count;
1150 hw->mac.get_link_status = 1;
1152 /* possible wait-to-complete in up to 9 seconds */
1153 for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1154 /* Read the real link status */
1155 switch (hw->phy.media_type) {
1156 case e1000_media_type_copper:
1157 /* Do the work to read phy */
1158 e1000_check_for_link(hw);
1159 link_check = !hw->mac.get_link_status;
1162 case e1000_media_type_fiber:
1163 e1000_check_for_link(hw);
1164 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1168 case e1000_media_type_internal_serdes:
1169 e1000_check_for_link(hw);
1170 link_check = hw->mac.serdes_has_link;
1176 if (link_check || wait_to_complete == 0)
1178 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
1180 memset(&link, 0, sizeof(link));
1181 rte_em_dev_atomic_read_link_status(dev, &link);
1184 /* Now we check if a transition has happened */
1185 if (link_check && (link.link_status == ETH_LINK_DOWN)) {
1186 uint16_t duplex, speed;
1187 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1188 link.link_duplex = (duplex == FULL_DUPLEX) ?
1189 ETH_LINK_FULL_DUPLEX :
1190 ETH_LINK_HALF_DUPLEX;
1191 link.link_speed = speed;
1192 link.link_status = ETH_LINK_UP;
1193 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
1194 ETH_LINK_SPEED_FIXED);
1195 } else if (!link_check && (link.link_status == ETH_LINK_UP)) {
1196 link.link_speed = 0;
1197 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1198 link.link_status = ETH_LINK_DOWN;
1199 link.link_autoneg = ETH_LINK_SPEED_FIXED;
1201 rte_em_dev_atomic_write_link_status(dev, &link);
1204 if (old.link_status == link.link_status)
1212 * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
1213 * For ASF and Pass Through versions of f/w this means
1214 * that the driver is loaded. For AMT version type f/w
1215 * this means that the network i/f is open.
1218 em_hw_control_acquire(struct e1000_hw *hw)
1220 uint32_t ctrl_ext, swsm;
1222 /* Let firmware know the driver has taken over */
1223 if (hw->mac.type == e1000_82573) {
1224 swsm = E1000_READ_REG(hw, E1000_SWSM);
1225 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
1228 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1229 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1230 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1235 * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
1236 * For ASF and Pass Through versions of f/w this means that the
1237 * driver is no longer loaded. For AMT versions of the
1238 * f/w this means that the network i/f is closed.
1241 em_hw_control_release(struct e1000_hw *hw)
1243 uint32_t ctrl_ext, swsm;
1245 /* Let firmware taken over control of h/w */
1246 if (hw->mac.type == e1000_82573) {
1247 swsm = E1000_READ_REG(hw, E1000_SWSM);
1248 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
1250 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1251 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1252 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1257 * Bit of a misnomer, what this really means is
1258 * to enable OS management of the system... aka
1259 * to disable special hardware management features.
1262 em_init_manageability(struct e1000_hw *hw)
1264 if (e1000_enable_mng_pass_thru(hw)) {
1265 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1266 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1268 /* disable hardware interception of ARP */
1269 manc &= ~(E1000_MANC_ARP_EN);
1271 /* enable receiving management packets to the host */
1272 manc |= E1000_MANC_EN_MNG2HOST;
1273 manc2h |= 1 << 5; /* Mng Port 623 */
1274 manc2h |= 1 << 6; /* Mng Port 664 */
1275 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1276 E1000_WRITE_REG(hw, E1000_MANC, manc);
1281 * Give control back to hardware management
1282 * controller if there is one.
1285 em_release_manageability(struct e1000_hw *hw)
1289 if (e1000_enable_mng_pass_thru(hw)) {
1290 manc = E1000_READ_REG(hw, E1000_MANC);
1292 /* re-enable hardware interception of ARP */
1293 manc |= E1000_MANC_ARP_EN;
1294 manc &= ~E1000_MANC_EN_MNG2HOST;
1296 E1000_WRITE_REG(hw, E1000_MANC, manc);
1301 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1303 struct e1000_hw *hw =
1304 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1307 rctl = E1000_READ_REG(hw, E1000_RCTL);
1308 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1309 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1313 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1315 struct e1000_hw *hw =
1316 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1319 rctl = E1000_READ_REG(hw, E1000_RCTL);
1320 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1321 if (dev->data->all_multicast == 1)
1322 rctl |= E1000_RCTL_MPE;
1324 rctl &= (~E1000_RCTL_MPE);
1325 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1329 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1331 struct e1000_hw *hw =
1332 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1335 rctl = E1000_READ_REG(hw, E1000_RCTL);
1336 rctl |= E1000_RCTL_MPE;
1337 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1341 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1343 struct e1000_hw *hw =
1344 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1347 if (dev->data->promiscuous == 1)
1348 return; /* must remain in all_multicast mode */
1349 rctl = E1000_READ_REG(hw, E1000_RCTL);
1350 rctl &= (~E1000_RCTL_MPE);
1351 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1355 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1357 struct e1000_hw *hw =
1358 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1359 struct e1000_vfta * shadow_vfta =
1360 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1365 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1366 E1000_VFTA_ENTRY_MASK);
1367 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1368 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1373 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1375 /* update local VFTA copy */
1376 shadow_vfta->vfta[vid_idx] = vfta;
1382 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1384 struct e1000_hw *hw =
1385 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1388 /* Filter Table Disable */
1389 reg = E1000_READ_REG(hw, E1000_RCTL);
1390 reg &= ~E1000_RCTL_CFIEN;
1391 reg &= ~E1000_RCTL_VFE;
1392 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1396 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1398 struct e1000_hw *hw =
1399 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1400 struct e1000_vfta * shadow_vfta =
1401 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1405 /* Filter Table Enable, CFI not used for packet acceptance */
1406 reg = E1000_READ_REG(hw, E1000_RCTL);
1407 reg &= ~E1000_RCTL_CFIEN;
1408 reg |= E1000_RCTL_VFE;
1409 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1411 /* restore vfta from local copy */
1412 for (i = 0; i < IGB_VFTA_SIZE; i++)
1413 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1417 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1419 struct e1000_hw *hw =
1420 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1423 /* VLAN Mode Disable */
1424 reg = E1000_READ_REG(hw, E1000_CTRL);
1425 reg &= ~E1000_CTRL_VME;
1426 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1431 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1433 struct e1000_hw *hw =
1434 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1437 /* VLAN Mode Enable */
1438 reg = E1000_READ_REG(hw, E1000_CTRL);
1439 reg |= E1000_CTRL_VME;
1440 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1444 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1446 if(mask & ETH_VLAN_STRIP_MASK){
1447 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1448 em_vlan_hw_strip_enable(dev);
1450 em_vlan_hw_strip_disable(dev);
1453 if(mask & ETH_VLAN_FILTER_MASK){
1454 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1455 em_vlan_hw_filter_enable(dev);
1457 em_vlan_hw_filter_disable(dev);
1462 * It enables the interrupt mask and then enable the interrupt.
1465 * Pointer to struct rte_eth_dev.
1468 * - On success, zero.
1469 * - On failure, a negative value.
1472 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1475 struct e1000_hw *hw =
1476 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1478 /* clear interrupt */
1479 E1000_READ_REG(hw, E1000_ICR);
1480 regval = E1000_READ_REG(hw, E1000_IMS);
1481 E1000_WRITE_REG(hw, E1000_IMS, regval | E1000_ICR_LSC);
1486 * It clears the interrupt causes and enables the interrupt.
1487 * It will be called once only during nic initialized.
1490 * Pointer to struct rte_eth_dev.
1493 * - On success, zero.
1494 * - On failure, a negative value.
1497 eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev)
1499 struct e1000_hw *hw =
1500 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1502 E1000_READ_REG(hw, E1000_ICR);
1503 em_rxq_intr_enable(hw);
1508 * It enable receive packet interrupt.
1510 * Pointer to struct e1000_hw
1515 em_rxq_intr_enable(struct e1000_hw *hw)
1517 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_RXT0);
1518 E1000_WRITE_FLUSH(hw);
1522 * It disabled lsc interrupt.
1524 * Pointer to struct e1000_hw
1529 em_lsc_intr_disable(struct e1000_hw *hw)
1531 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_LSC);
1532 E1000_WRITE_FLUSH(hw);
1536 * It disabled receive packet interrupt.
1538 * Pointer to struct e1000_hw
1543 em_rxq_intr_disable(struct e1000_hw *hw)
1545 E1000_READ_REG(hw, E1000_ICR);
1546 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0);
1547 E1000_WRITE_FLUSH(hw);
1551 * It reads ICR and gets interrupt causes, check it and set a bit flag
1552 * to update link status.
1555 * Pointer to struct rte_eth_dev.
1558 * - On success, zero.
1559 * - On failure, a negative value.
1562 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1565 struct e1000_hw *hw =
1566 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1567 struct e1000_interrupt *intr =
1568 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1570 /* read-on-clear nic registers here */
1571 icr = E1000_READ_REG(hw, E1000_ICR);
1572 if (icr & E1000_ICR_LSC) {
1573 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1580 * It executes link_update after knowing an interrupt is prsent.
1583 * Pointer to struct rte_eth_dev.
1586 * - On success, zero.
1587 * - On failure, a negative value.
1590 eth_em_interrupt_action(struct rte_eth_dev *dev,
1591 struct rte_intr_handle *intr_handle)
1593 struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
1594 struct e1000_hw *hw =
1595 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1596 struct e1000_interrupt *intr =
1597 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1598 uint32_t tctl, rctl;
1599 struct rte_eth_link link;
1602 if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1605 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1606 rte_intr_enable(intr_handle);
1608 /* set get_link_status to check register later */
1609 hw->mac.get_link_status = 1;
1610 ret = eth_em_link_update(dev, 0);
1612 /* check if link has changed */
1616 memset(&link, 0, sizeof(link));
1617 rte_em_dev_atomic_read_link_status(dev, &link);
1618 if (link.link_status) {
1619 PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s",
1620 dev->data->port_id, (unsigned)link.link_speed,
1621 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1622 "full-duplex" : "half-duplex");
1624 PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
1626 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
1627 pci_dev->addr.domain, pci_dev->addr.bus,
1628 pci_dev->addr.devid, pci_dev->addr.function);
1630 tctl = E1000_READ_REG(hw, E1000_TCTL);
1631 rctl = E1000_READ_REG(hw, E1000_RCTL);
1632 if (link.link_status) {
1634 tctl |= E1000_TCTL_EN;
1635 rctl |= E1000_RCTL_EN;
1638 tctl &= ~E1000_TCTL_EN;
1639 rctl &= ~E1000_RCTL_EN;
1641 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1642 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1643 E1000_WRITE_FLUSH(hw);
1649 * Interrupt handler which shall be registered at first.
1652 * Pointer to interrupt handle.
1654 * The address of parameter (struct rte_eth_dev *) regsitered before.
1660 eth_em_interrupt_handler(void *param)
1662 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1664 eth_em_interrupt_get_status(dev);
1665 eth_em_interrupt_action(dev, dev->intr_handle);
1666 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1670 eth_em_led_on(struct rte_eth_dev *dev)
1672 struct e1000_hw *hw;
1674 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1675 return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1679 eth_em_led_off(struct rte_eth_dev *dev)
1681 struct e1000_hw *hw;
1683 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1684 return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1688 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1690 struct e1000_hw *hw;
1695 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1696 fc_conf->pause_time = hw->fc.pause_time;
1697 fc_conf->high_water = hw->fc.high_water;
1698 fc_conf->low_water = hw->fc.low_water;
1699 fc_conf->send_xon = hw->fc.send_xon;
1700 fc_conf->autoneg = hw->mac.autoneg;
1703 * Return rx_pause and tx_pause status according to actual setting of
1704 * the TFCE and RFCE bits in the CTRL register.
1706 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1707 if (ctrl & E1000_CTRL_TFCE)
1712 if (ctrl & E1000_CTRL_RFCE)
1717 if (rx_pause && tx_pause)
1718 fc_conf->mode = RTE_FC_FULL;
1720 fc_conf->mode = RTE_FC_RX_PAUSE;
1722 fc_conf->mode = RTE_FC_TX_PAUSE;
1724 fc_conf->mode = RTE_FC_NONE;
1730 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1732 struct e1000_hw *hw;
1734 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1740 uint32_t rx_buf_size;
1741 uint32_t max_high_water;
1744 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1745 if (fc_conf->autoneg != hw->mac.autoneg)
1747 rx_buf_size = em_get_rx_buffer_size(hw);
1748 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1750 /* At least reserve one Ethernet frame for watermark */
1751 max_high_water = rx_buf_size - ETHER_MAX_LEN;
1752 if ((fc_conf->high_water > max_high_water) ||
1753 (fc_conf->high_water < fc_conf->low_water)) {
1754 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1755 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
1759 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1760 hw->fc.pause_time = fc_conf->pause_time;
1761 hw->fc.high_water = fc_conf->high_water;
1762 hw->fc.low_water = fc_conf->low_water;
1763 hw->fc.send_xon = fc_conf->send_xon;
1765 err = e1000_setup_link_generic(hw);
1766 if (err == E1000_SUCCESS) {
1768 /* check if we want to forward MAC frames - driver doesn't have native
1769 * capability to do that, so we'll write the registers ourselves */
1771 rctl = E1000_READ_REG(hw, E1000_RCTL);
1773 /* set or clear MFLCN.PMCF bit depending on configuration */
1774 if (fc_conf->mac_ctrl_frame_fwd != 0)
1775 rctl |= E1000_RCTL_PMCF;
1777 rctl &= ~E1000_RCTL_PMCF;
1779 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1780 E1000_WRITE_FLUSH(hw);
1785 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1790 eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1791 uint32_t index, __rte_unused uint32_t pool)
1793 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1795 e1000_rar_set(hw, mac_addr->addr_bytes, index);
1799 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1801 uint8_t addr[ETHER_ADDR_LEN];
1802 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1804 memset(addr, 0, sizeof(addr));
1806 e1000_rar_set(hw, addr, index);
1810 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1812 struct rte_eth_dev_info dev_info;
1813 struct e1000_hw *hw;
1814 uint32_t frame_size;
1817 eth_em_infos_get(dev, &dev_info);
1818 frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE;
1820 /* check that mtu is within the allowed range */
1821 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1824 /* refuse mtu that requires the support of scattered packets when this
1825 * feature has not been enabled before. */
1826 if (!dev->data->scattered_rx &&
1827 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1830 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1831 rctl = E1000_READ_REG(hw, E1000_RCTL);
1833 /* switch to jumbo mode if needed */
1834 if (frame_size > ETHER_MAX_LEN) {
1835 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1836 rctl |= E1000_RCTL_LPE;
1838 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1839 rctl &= ~E1000_RCTL_LPE;
1841 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1843 /* update max frame size */
1844 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1849 eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
1850 struct ether_addr *mc_addr_set,
1851 uint32_t nb_mc_addr)
1853 struct e1000_hw *hw;
1855 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1856 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
1860 RTE_PMD_REGISTER_PCI(net_e1000_em, rte_em_pmd.pci_drv);
1861 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_em, pci_id_em_map);
1862 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_em, "* igb_uio | uio_pci_generic | vfio");