drivers/net/e1000/em_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <stdarg.h>
  10
  11 #include <rte_common.h>
  12 #include <rte_interrupts.h>
  13 #include <rte_byteorder.h>
  14 #include <rte_debug.h>
  15 #include <rte_pci.h>
  16 #include <rte_bus_pci.h>
  17 #include <rte_ether.h>
  18 #include <rte_ethdev_driver.h>
  19 #include <rte_ethdev_pci.h>
  20 #include <rte_memory.h>
  21 #include <rte_eal.h>
  22 #include <rte_malloc.h>
  23 #include <rte_dev.h>
  24
  25 #include "e1000_logs.h"
  26 #include "base/e1000_api.h"
  27 #include "e1000_ethdev.h"
  28
  29 #define EM_EIAC                 0x000DC
  30
  31 #define PMD_ROUNDUP(x,y)        (((x) + (y) - 1)/(y) * (y))
  32
  33
  34 static int eth_em_configure(struct rte_eth_dev *dev);
  35 static int eth_em_start(struct rte_eth_dev *dev);
  36 static void eth_em_stop(struct rte_eth_dev *dev);
  37 static void eth_em_close(struct rte_eth_dev *dev);
  38 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
  39 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
  40 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
  41 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
  42 static int eth_em_link_update(struct rte_eth_dev *dev,
  43                                 int wait_to_complete);
  44 static int eth_em_stats_get(struct rte_eth_dev *dev,
  45                                 struct rte_eth_stats *rte_stats);
  46 static void eth_em_stats_reset(struct rte_eth_dev *dev);
  47 static void eth_em_infos_get(struct rte_eth_dev *dev,
  48                                 struct rte_eth_dev_info *dev_info);
  49 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
  50                                 struct rte_eth_fc_conf *fc_conf);
  51 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
  52                                 struct rte_eth_fc_conf *fc_conf);
  53 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
  54 static int eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev);
  55 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
  56 static int eth_em_interrupt_action(struct rte_eth_dev *dev,
  57                                    struct rte_intr_handle *handle);
  58 static void eth_em_interrupt_handler(void *param);
  59
  60 static int em_hw_init(struct e1000_hw *hw);
  61 static int em_hardware_init(struct e1000_hw *hw);
  62 static void em_hw_control_acquire(struct e1000_hw *hw);
  63 static void em_hw_control_release(struct e1000_hw *hw);
  64 static void em_init_manageability(struct e1000_hw *hw);
  65 static void em_release_manageability(struct e1000_hw *hw);
  66
  67 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  68
  69 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
  70                 uint16_t vlan_id, int on);
  71 static int eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  72 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
  73 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
  74 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
  75 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
  76
  77 /*
  78 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
  79                                         uint16_t vlan_id, int on);
  80 */
  81
  82 static int eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
  83 static int eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
  84 static void em_lsc_intr_disable(struct e1000_hw *hw);
  85 static void em_rxq_intr_enable(struct e1000_hw *hw);
  86 static void em_rxq_intr_disable(struct e1000_hw *hw);
  87
  88 static int eth_em_led_on(struct rte_eth_dev *dev);
  89 static int eth_em_led_off(struct rte_eth_dev *dev);
  90
  91 static int em_get_rx_buffer_size(struct e1000_hw *hw);
  92 static int eth_em_rar_set(struct rte_eth_dev *dev,
  93                         struct rte_ether_addr *mac_addr,
  94                         uint32_t index, uint32_t pool);
  95 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
  96 static int eth_em_default_mac_addr_set(struct rte_eth_dev *dev,
  97                                          struct rte_ether_addr *addr);
  98
  99 static int eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
 100                                    struct rte_ether_addr *mc_addr_set,
 101                                    uint32_t nb_mc_addr);
 102
 103 #define EM_FC_PAUSE_TIME 0x0680
 104 #define EM_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 105 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 106
 107 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
 108
 109 /*
 110  * The set of PCI devices this driver supports
 111  */
 112 static const struct rte_pci_id pci_id_em_map[] = {
 113         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82540EM) },
 114         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_COPPER) },
 115         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_FIBER) },
 116         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_COPPER) },
 117         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_FIBER) },
 118         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_QUAD_COPPER) },
 119         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_COPPER) },
 120         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_FIBER) },
 121         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES) },
 122         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_DUAL) },
 123         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_QUAD) },
 124         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER) },
 125         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571PT_QUAD_COPPER) },
 126         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_FIBER) },
 127         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER_LP) },
 128         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_COPPER) },
 129         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_FIBER) },
 130         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_SERDES) },
 131         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI) },
 132         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82573L) },
 133         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574L) },
 134         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574LA) },
 135         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82583V) },
 136         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH2_LV_LM) },
 137         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_LM) },
 138         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_V) },
 139         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_LM) },
 140         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_V) },
 141         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM2) },
 142         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V2) },
 143         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM3) },
 144         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V3) },
 145         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM) },
 146         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V) },
 147         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM2) },
 148         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V2) },
 149         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LBG_I219_LM3) },
 150         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM4) },
 151         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V4) },
 152         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM5) },
 153         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V5) },
 154         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM6) },
 155         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V6) },
 156         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM7) },
 157         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V7) },
 158         { .vendor_id = 0, /* sentinel */ },
 159 };
 160
 161 static const struct eth_dev_ops eth_em_ops = {
 162         .dev_configure        = eth_em_configure,
 163         .dev_start            = eth_em_start,
 164         .dev_stop             = eth_em_stop,
 165         .dev_close            = eth_em_close,
 166         .promiscuous_enable   = eth_em_promiscuous_enable,
 167         .promiscuous_disable  = eth_em_promiscuous_disable,
 168         .allmulticast_enable  = eth_em_allmulticast_enable,
 169         .allmulticast_disable = eth_em_allmulticast_disable,
 170         .link_update          = eth_em_link_update,
 171         .stats_get            = eth_em_stats_get,
 172         .stats_reset          = eth_em_stats_reset,
 173         .dev_infos_get        = eth_em_infos_get,
 174         .mtu_set              = eth_em_mtu_set,
 175         .vlan_filter_set      = eth_em_vlan_filter_set,
 176         .vlan_offload_set     = eth_em_vlan_offload_set,
 177         .rx_queue_setup       = eth_em_rx_queue_setup,
 178         .rx_queue_release     = eth_em_rx_queue_release,
 179         .rx_queue_count       = eth_em_rx_queue_count,
 180         .rx_descriptor_done   = eth_em_rx_descriptor_done,
 181         .rx_descriptor_status = eth_em_rx_descriptor_status,
 182         .tx_descriptor_status = eth_em_tx_descriptor_status,
 183         .tx_queue_setup       = eth_em_tx_queue_setup,
 184         .tx_queue_release     = eth_em_tx_queue_release,
 185         .rx_queue_intr_enable = eth_em_rx_queue_intr_enable,
 186         .rx_queue_intr_disable = eth_em_rx_queue_intr_disable,
 187         .dev_led_on           = eth_em_led_on,
 188         .dev_led_off          = eth_em_led_off,
 189         .flow_ctrl_get        = eth_em_flow_ctrl_get,
 190         .flow_ctrl_set        = eth_em_flow_ctrl_set,
 191         .mac_addr_set         = eth_em_default_mac_addr_set,
 192         .mac_addr_add         = eth_em_rar_set,
 193         .mac_addr_remove      = eth_em_rar_clear,
 194         .set_mc_addr_list     = eth_em_set_mc_addr_list,
 195         .rxq_info_get         = em_rxq_info_get,
 196         .txq_info_get         = em_txq_info_get,
 197 };
 198
 199
 200 /**
 201  *  eth_em_dev_is_ich8 - Check for ICH8 device
 202  *  @hw: pointer to the HW structure
 203  *
 204  *  return TRUE for ICH8, otherwise FALSE
 205  **/
 206 static bool
 207 eth_em_dev_is_ich8(struct e1000_hw *hw)
 208 {
 209         DEBUGFUNC("eth_em_dev_is_ich8");
 210
 211         switch (hw->device_id) {
 212         case E1000_DEV_ID_PCH2_LV_LM:
 213         case E1000_DEV_ID_PCH_LPT_I217_LM:
 214         case E1000_DEV_ID_PCH_LPT_I217_V:
 215         case E1000_DEV_ID_PCH_LPTLP_I218_LM:
 216         case E1000_DEV_ID_PCH_LPTLP_I218_V:
 217         case E1000_DEV_ID_PCH_I218_V2:
 218         case E1000_DEV_ID_PCH_I218_LM2:
 219         case E1000_DEV_ID_PCH_I218_V3:
 220         case E1000_DEV_ID_PCH_I218_LM3:
 221         case E1000_DEV_ID_PCH_SPT_I219_LM:
 222         case E1000_DEV_ID_PCH_SPT_I219_V:
 223         case E1000_DEV_ID_PCH_SPT_I219_LM2:
 224         case E1000_DEV_ID_PCH_SPT_I219_V2:
 225         case E1000_DEV_ID_PCH_LBG_I219_LM3:
 226         case E1000_DEV_ID_PCH_SPT_I219_LM4:
 227         case E1000_DEV_ID_PCH_SPT_I219_V4:
 228         case E1000_DEV_ID_PCH_SPT_I219_LM5:
 229         case E1000_DEV_ID_PCH_SPT_I219_V5:
 230         case E1000_DEV_ID_PCH_CNP_I219_LM6:
 231         case E1000_DEV_ID_PCH_CNP_I219_V6:
 232         case E1000_DEV_ID_PCH_CNP_I219_LM7:
 233         case E1000_DEV_ID_PCH_CNP_I219_V7:
 234                 return 1;
 235         default:
 236                 return 0;
 237         }
 238 }
 239
 240 static int
 241 eth_em_dev_init(struct rte_eth_dev *eth_dev)
 242 {
 243         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 244         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 245         struct e1000_adapter *adapter =
 246                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 247         struct e1000_hw *hw =
 248                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 249         struct e1000_vfta * shadow_vfta =
 250                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 251
 252         eth_dev->dev_ops = &eth_em_ops;
 253         eth_dev->rx_pkt_burst = (eth_rx_burst_t)&eth_em_recv_pkts;
 254         eth_dev->tx_pkt_burst = (eth_tx_burst_t)&eth_em_xmit_pkts;
 255         eth_dev->tx_pkt_prepare = (eth_tx_prep_t)&eth_em_prep_pkts;
 256
 257         /* for secondary processes, we don't initialise any further as primary
 258          * has already done this work. Only check we don't need a different
 259          * RX function */
 260         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 261                 if (eth_dev->data->scattered_rx)
 262                         eth_dev->rx_pkt_burst =
 263                                 (eth_rx_burst_t)&eth_em_recv_scattered_pkts;
 264                 return 0;
 265         }
 266
 267         rte_eth_copy_pci_info(eth_dev, pci_dev);
 268
 269         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 270         hw->device_id = pci_dev->id.device_id;
 271         adapter->stopped = 0;
 272
 273         /* For ICH8 support we'll need to map the flash memory BAR */
 274         if (eth_em_dev_is_ich8(hw))
 275                 hw->flash_address = (void *)pci_dev->mem_resource[1].addr;
 276
 277         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
 278                         em_hw_init(hw) != 0) {
 279                 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
 280                         "failed to init HW",
 281                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 282                         pci_dev->id.device_id);
 283                 return -ENODEV;
 284         }
 285
 286         /* Allocate memory for storing MAC addresses */
 287         eth_dev->data->mac_addrs = rte_zmalloc("e1000", RTE_ETHER_ADDR_LEN *
 288                         hw->mac.rar_entry_count, 0);
 289         if (eth_dev->data->mac_addrs == NULL) {
 290                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 291                         "store MAC addresses",
 292                         RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 293                 return -ENOMEM;
 294         }
 295
 296         /* Copy the permanent MAC address */
 297         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
 298                 eth_dev->data->mac_addrs);
 299
 300         /* initialize the vfta */
 301         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 302
 303         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 304                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 305                      pci_dev->id.device_id);
 306
 307         rte_intr_callback_register(intr_handle,
 308                                    eth_em_interrupt_handler, eth_dev);
 309
 310         return 0;
 311 }
 312
 313 static int
 314 eth_em_dev_uninit(struct rte_eth_dev *eth_dev)
 315 {
 316         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 317         struct e1000_adapter *adapter =
 318                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 319         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 320
 321         PMD_INIT_FUNC_TRACE();
 322
 323         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 324                 return -EPERM;
 325
 326         if (adapter->stopped == 0)
 327                 eth_em_close(eth_dev);
 328
 329         eth_dev->dev_ops = NULL;
 330         eth_dev->rx_pkt_burst = NULL;
 331         eth_dev->tx_pkt_burst = NULL;
 332
 333         /* disable uio intr before callback unregister */
 334         rte_intr_disable(intr_handle);
 335         rte_intr_callback_unregister(intr_handle,
 336                                      eth_em_interrupt_handler, eth_dev);
 337
 338         return 0;
 339 }
 340
 341 static int eth_em_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 342         struct rte_pci_device *pci_dev)
 343 {
 344         return rte_eth_dev_pci_generic_probe(pci_dev,
 345                 sizeof(struct e1000_adapter), eth_em_dev_init);
 346 }
 347
 348 static int eth_em_pci_remove(struct rte_pci_device *pci_dev)
 349 {
 350         return rte_eth_dev_pci_generic_remove(pci_dev, eth_em_dev_uninit);
 351 }
 352
 353 static struct rte_pci_driver rte_em_pmd = {
 354         .id_table = pci_id_em_map,
 355         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 356         .probe = eth_em_pci_probe,
 357         .remove = eth_em_pci_remove,
 358 };
 359
 360 static int
 361 em_hw_init(struct e1000_hw *hw)
 362 {
 363         int diag;
 364
 365         diag = hw->mac.ops.init_params(hw);
 366         if (diag != 0) {
 367                 PMD_INIT_LOG(ERR, "MAC Initialization Error");
 368                 return diag;
 369         }
 370         diag = hw->nvm.ops.init_params(hw);
 371         if (diag != 0) {
 372                 PMD_INIT_LOG(ERR, "NVM Initialization Error");
 373                 return diag;
 374         }
 375         diag = hw->phy.ops.init_params(hw);
 376         if (diag != 0) {
 377                 PMD_INIT_LOG(ERR, "PHY Initialization Error");
 378                 return diag;
 379         }
 380         (void) e1000_get_bus_info(hw);
 381
 382         hw->mac.autoneg = 1;
 383         hw->phy.autoneg_wait_to_complete = 0;
 384         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 385
 386         e1000_init_script_state_82541(hw, TRUE);
 387         e1000_set_tbi_compatibility_82543(hw, TRUE);
 388
 389         /* Copper options */
 390         if (hw->phy.media_type == e1000_media_type_copper) {
 391                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 392                 hw->phy.disable_polarity_correction = 0;
 393                 hw->phy.ms_type = e1000_ms_hw_default;
 394         }
 395
 396         /*
 397          * Start from a known state, this is important in reading the nvm
 398          * and mac from that.
 399          */
 400         e1000_reset_hw(hw);
 401
 402         /* Make sure we have a good EEPROM before we read from it */
 403         if (e1000_validate_nvm_checksum(hw) < 0) {
 404                 /*
 405                  * Some PCI-E parts fail the first check due to
 406                  * the link being in sleep state, call it again,
 407                  * if it fails a second time its a real issue.
 408                  */
 409                 diag = e1000_validate_nvm_checksum(hw);
 410                 if (diag < 0) {
 411                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 412                         goto error;
 413                 }
 414         }
 415
 416         /* Read the permanent MAC address out of the EEPROM */
 417         diag = e1000_read_mac_addr(hw);
 418         if (diag != 0) {
 419                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 420                 goto error;
 421         }
 422
 423         /* Now initialize the hardware */
 424         diag = em_hardware_init(hw);
 425         if (diag != 0) {
 426                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 427                 goto error;
 428         }
 429
 430         hw->mac.get_link_status = 1;
 431
 432         /* Indicate SOL/IDER usage */
 433         diag = e1000_check_reset_block(hw);
 434         if (diag < 0) {
 435                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
 436                         "SOL/IDER session");
 437         }
 438         return 0;
 439
 440 error:
 441         em_hw_control_release(hw);
 442         return diag;
 443 }
 444
 445 static int
 446 eth_em_configure(struct rte_eth_dev *dev)
 447 {
 448         struct e1000_interrupt *intr =
 449                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 450
 451         PMD_INIT_FUNC_TRACE();
 452         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 453
 454         PMD_INIT_FUNC_TRACE();
 455
 456         return 0;
 457 }
 458
 459 static void
 460 em_set_pba(struct e1000_hw *hw)
 461 {
 462         uint32_t pba;
 463
 464         /*
 465          * Packet Buffer Allocation (PBA)
 466          * Writing PBA sets the receive portion of the buffer
 467          * the remainder is used for the transmit buffer.
 468          * Devices before the 82547 had a Packet Buffer of 64K.
 469          * After the 82547 the buffer was reduced to 40K.
 470          */
 471         switch (hw->mac.type) {
 472                 case e1000_82547:
 473                 case e1000_82547_rev_2:
 474                 /* 82547: Total Packet Buffer is 40K */
 475                         pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
 476                         break;
 477                 case e1000_82571:
 478                 case e1000_82572:
 479                 case e1000_80003es2lan:
 480                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 481                         break;
 482                 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
 483                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
 484                         break;
 485                 case e1000_82574:
 486                 case e1000_82583:
 487                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
 488                         break;
 489                 case e1000_ich8lan:
 490                         pba = E1000_PBA_8K;
 491                         break;
 492                 case e1000_ich9lan:
 493                 case e1000_ich10lan:
 494                         pba = E1000_PBA_10K;
 495                         break;
 496                 case e1000_pchlan:
 497                 case e1000_pch2lan:
 498                 case e1000_pch_lpt:
 499                 case e1000_pch_spt:
 500                 case e1000_pch_cnp:
 501                         pba = E1000_PBA_26K;
 502                         break;
 503                 default:
 504                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
 505         }
 506
 507         E1000_WRITE_REG(hw, E1000_PBA, pba);
 508 }
 509
 510 static void
 511 eth_em_rxtx_control(struct rte_eth_dev *dev,
 512                     bool enable)
 513 {
 514         struct e1000_hw *hw =
 515                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 516         uint32_t tctl, rctl;
 517
 518         tctl = E1000_READ_REG(hw, E1000_TCTL);
 519         rctl = E1000_READ_REG(hw, E1000_RCTL);
 520         if (enable) {
 521                 /* enable Tx/Rx */
 522                 tctl |= E1000_TCTL_EN;
 523                 rctl |= E1000_RCTL_EN;
 524         } else {
 525                 /* disable Tx/Rx */
 526                 tctl &= ~E1000_TCTL_EN;
 527                 rctl &= ~E1000_RCTL_EN;
 528         }
 529         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
 530         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
 531         E1000_WRITE_FLUSH(hw);
 532 }
 533
 534 static int
 535 eth_em_start(struct rte_eth_dev *dev)
 536 {
 537         struct e1000_adapter *adapter =
 538                 E1000_DEV_PRIVATE(dev->data->dev_private);
 539         struct e1000_hw *hw =
 540                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 541         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 542         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 543         int ret, mask;
 544         uint32_t intr_vector = 0;
 545         uint32_t *speeds;
 546         int num_speeds;
 547         bool autoneg;
 548
 549         PMD_INIT_FUNC_TRACE();
 550
 551         eth_em_stop(dev);
 552
 553         e1000_power_up_phy(hw);
 554
 555         /* Set default PBA value */
 556         em_set_pba(hw);
 557
 558         /* Put the address into the Receive Address Array */
 559         e1000_rar_set(hw, hw->mac.addr, 0);
 560
 561         /*
 562          * With the 82571 adapter, RAR[0] may be overwritten
 563          * when the other port is reset, we make a duplicate
 564          * in RAR[14] for that eventuality, this assures
 565          * the interface continues to function.
 566          */
 567         if (hw->mac.type == e1000_82571) {
 568                 e1000_set_laa_state_82571(hw, TRUE);
 569                 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
 570         }
 571
 572         /* Initialize the hardware */
 573         if (em_hardware_init(hw)) {
 574                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 575                 return -EIO;
 576         }
 577
 578         E1000_WRITE_REG(hw, E1000_VET, RTE_ETHER_TYPE_VLAN);
 579
 580         /* Configure for OS presence */
 581         em_init_manageability(hw);
 582
 583         if (dev->data->dev_conf.intr_conf.rxq != 0) {
 584                 intr_vector = dev->data->nb_rx_queues;
 585                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 586                         return -1;
 587         }
 588
 589         if (rte_intr_dp_is_en(intr_handle)) {
 590                 intr_handle->intr_vec =
 591                         rte_zmalloc("intr_vec",
 592                                         dev->data->nb_rx_queues * sizeof(int), 0);
 593                 if (intr_handle->intr_vec == NULL) {
 594                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
 595                                                 " intr_vec", dev->data->nb_rx_queues);
 596                         return -ENOMEM;
 597                 }
 598
 599                 /* enable rx interrupt */
 600                 em_rxq_intr_enable(hw);
 601         }
 602
 603         eth_em_tx_init(dev);
 604
 605         ret = eth_em_rx_init(dev);
 606         if (ret) {
 607                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 608                 em_dev_clear_queues(dev);
 609                 return ret;
 610         }
 611
 612         e1000_clear_hw_cntrs_base_generic(hw);
 613
 614         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 615                         ETH_VLAN_EXTEND_MASK;
 616         ret = eth_em_vlan_offload_set(dev, mask);
 617         if (ret) {
 618                 PMD_INIT_LOG(ERR, "Unable to update vlan offload");
 619                 em_dev_clear_queues(dev);
 620                 return ret;
 621         }
 622
 623         /* Set Interrupt Throttling Rate to maximum allowed value. */
 624         E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
 625
 626         /* Setup link speed and duplex */
 627         speeds = &dev->data->dev_conf.link_speeds;
 628         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
 629                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 630                 hw->mac.autoneg = 1;
 631         } else {
 632                 num_speeds = 0;
 633                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
 634
 635                 /* Reset */
 636                 hw->phy.autoneg_advertised = 0;
 637
 638                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
 639                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
 640                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
 641                         num_speeds = -1;
 642                         goto error_invalid_config;
 643                 }
 644                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
 645                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
 646                         num_speeds++;
 647                 }
 648                 if (*speeds & ETH_LINK_SPEED_10M) {
 649                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
 650                         num_speeds++;
 651                 }
 652                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
 653                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
 654                         num_speeds++;
 655                 }
 656                 if (*speeds & ETH_LINK_SPEED_100M) {
 657                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
 658                         num_speeds++;
 659                 }
 660                 if (*speeds & ETH_LINK_SPEED_1G) {
 661                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
 662                         num_speeds++;
 663                 }
 664                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
 665                         goto error_invalid_config;
 666
 667                 /* Set/reset the mac.autoneg based on the link speed,
 668                  * fixed or not
 669                  */
 670                 if (!autoneg) {
 671                         hw->mac.autoneg = 0;
 672                         hw->mac.forced_speed_duplex =
 673                                         hw->phy.autoneg_advertised;
 674                 } else {
 675                         hw->mac.autoneg = 1;
 676                 }
 677         }
 678
 679         e1000_setup_link(hw);
 680
 681         if (rte_intr_allow_others(intr_handle)) {
 682                 /* check if lsc interrupt is enabled */
 683                 if (dev->data->dev_conf.intr_conf.lsc != 0) {
 684                         ret = eth_em_interrupt_setup(dev);
 685                         if (ret) {
 686                                 PMD_INIT_LOG(ERR, "Unable to setup interrupts");
 687                                 em_dev_clear_queues(dev);
 688                                 return ret;
 689                         }
 690                 }
 691         } else {
 692                 rte_intr_callback_unregister(intr_handle,
 693                                                 eth_em_interrupt_handler,
 694                                                 (void *)dev);
 695                 if (dev->data->dev_conf.intr_conf.lsc != 0)
 696                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
 697                                      " no intr multiplexn");
 698         }
 699         /* check if rxq interrupt is enabled */
 700         if (dev->data->dev_conf.intr_conf.rxq != 0)
 701                 eth_em_rxq_interrupt_setup(dev);
 702
 703         rte_intr_enable(intr_handle);
 704
 705         adapter->stopped = 0;
 706
 707         eth_em_rxtx_control(dev, true);
 708         eth_em_link_update(dev, 0);
 709
 710         PMD_INIT_LOG(DEBUG, "<<");
 711
 712         return 0;
 713
 714 error_invalid_config:
 715         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
 716                      dev->data->dev_conf.link_speeds, dev->data->port_id);
 717         em_dev_clear_queues(dev);
 718         return -EINVAL;
 719 }
 720
 721 /*********************************************************************
 722  *
 723  *  This routine disables all traffic on the adapter by issuing a
 724  *  global reset on the MAC.
 725  *
 726  **********************************************************************/
 727 static void
 728 eth_em_stop(struct rte_eth_dev *dev)
 729 {
 730         struct rte_eth_link link;
 731         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 732         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 733         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 734
 735         eth_em_rxtx_control(dev, false);
 736         em_rxq_intr_disable(hw);
 737         em_lsc_intr_disable(hw);
 738
 739         e1000_reset_hw(hw);
 740         if (hw->mac.type >= e1000_82544)
 741                 E1000_WRITE_REG(hw, E1000_WUC, 0);
 742
 743         /* Power down the phy. Needed to make the link go down */
 744         e1000_power_down_phy(hw);
 745
 746         em_dev_clear_queues(dev);
 747
 748         /* clear the recorded link status */
 749         memset(&link, 0, sizeof(link));
 750         rte_eth_linkstatus_set(dev, &link);
 751
 752         if (!rte_intr_allow_others(intr_handle))
 753                 /* resume to the default handler */
 754                 rte_intr_callback_register(intr_handle,
 755                                            eth_em_interrupt_handler,
 756                                            (void *)dev);
 757
 758         /* Clean datapath event and queue/vec mapping */
 759         rte_intr_efd_disable(intr_handle);
 760         if (intr_handle->intr_vec != NULL) {
 761                 rte_free(intr_handle->intr_vec);
 762                 intr_handle->intr_vec = NULL;
 763         }
 764 }
 765
 766 static void
 767 eth_em_close(struct rte_eth_dev *dev)
 768 {
 769         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 770         struct e1000_adapter *adapter =
 771                 E1000_DEV_PRIVATE(dev->data->dev_private);
 772
 773         eth_em_stop(dev);
 774         adapter->stopped = 1;
 775         em_dev_free_queues(dev);
 776         e1000_phy_hw_reset(hw);
 777         em_release_manageability(hw);
 778         em_hw_control_release(hw);
 779 }
 780
 781 static int
 782 em_get_rx_buffer_size(struct e1000_hw *hw)
 783 {
 784         uint32_t rx_buf_size;
 785
 786         rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
 787         return rx_buf_size;
 788 }
 789
 790 /*********************************************************************
 791  *
 792  *  Initialize the hardware
 793  *
 794  **********************************************************************/
 795 static int
 796 em_hardware_init(struct e1000_hw *hw)
 797 {
 798         uint32_t rx_buf_size;
 799         int diag;
 800
 801         /* Issue a global reset */
 802         e1000_reset_hw(hw);
 803
 804         /* Let the firmware know the OS is in control */
 805         em_hw_control_acquire(hw);
 806
 807         /*
 808          * These parameters control the automatic generation (Tx) and
 809          * response (Rx) to Ethernet PAUSE frames.
 810          * - High water mark should allow for at least two standard size (1518)
 811          *   frames to be received after sending an XOFF.
 812          * - Low water mark works best when it is very near the high water mark.
 813          *   This allows the receiver to restart by sending XON when it has
 814          *   drained a bit. Here we use an arbitrary value of 1500 which will
 815          *   restart after one full frame is pulled from the buffer. There
 816          *   could be several smaller frames in the buffer and if so they will
 817          *   not trigger the XON until their total number reduces the buffer
 818          *   by 1500.
 819          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
 820          */
 821         rx_buf_size = em_get_rx_buffer_size(hw);
 822
 823         hw->fc.high_water = rx_buf_size -
 824                 PMD_ROUNDUP(RTE_ETHER_MAX_LEN * 2, 1024);
 825         hw->fc.low_water = hw->fc.high_water - 1500;
 826
 827         if (hw->mac.type == e1000_80003es2lan)
 828                 hw->fc.pause_time = UINT16_MAX;
 829         else
 830                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
 831
 832         hw->fc.send_xon = 1;
 833
 834         /* Set Flow control, use the tunable location if sane */
 835         if (em_fc_setting <= e1000_fc_full)
 836                 hw->fc.requested_mode = em_fc_setting;
 837         else
 838                 hw->fc.requested_mode = e1000_fc_none;
 839
 840         /* Workaround: no TX flow ctrl for PCH */
 841         if (hw->mac.type == e1000_pchlan)
 842                 hw->fc.requested_mode = e1000_fc_rx_pause;
 843
 844         /* Override - settings for PCH2LAN, ya its magic :) */
 845         if (hw->mac.type == e1000_pch2lan) {
 846                 hw->fc.high_water = 0x5C20;
 847                 hw->fc.low_water = 0x5048;
 848                 hw->fc.pause_time = 0x0650;
 849                 hw->fc.refresh_time = 0x0400;
 850         } else if (hw->mac.type == e1000_pch_lpt ||
 851                    hw->mac.type == e1000_pch_spt ||
 852                    hw->mac.type == e1000_pch_cnp) {
 853                 hw->fc.requested_mode = e1000_fc_full;
 854         }
 855
 856         diag = e1000_init_hw(hw);
 857         if (diag < 0)
 858                 return diag;
 859         e1000_check_for_link(hw);
 860         return 0;
 861 }
 862
 863 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
 864 static int
 865 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 866 {
 867         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 868         struct e1000_hw_stats *stats =
 869                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 870         int pause_frames;
 871
 872         if(hw->phy.media_type == e1000_media_type_copper ||
 873                         (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
 874                 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
 875                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
 876         }
 877
 878         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
 879         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
 880         stats->scc += E1000_READ_REG(hw, E1000_SCC);
 881         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
 882
 883         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
 884         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
 885         stats->colc += E1000_READ_REG(hw, E1000_COLC);
 886         stats->dc += E1000_READ_REG(hw, E1000_DC);
 887         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
 888         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
 889         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
 890
 891         /*
 892          * For watchdog management we need to know if we have been
 893          * paused during the last interval, so capture that here.
 894          */
 895         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
 896         stats->xoffrxc += pause_frames;
 897         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
 898         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
 899         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
 900         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
 901         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
 902         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
 903         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
 904         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
 905         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
 906         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
 907         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
 908         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
 909
 910         /*
 911          * For the 64-bit byte counters the low dword must be read first.
 912          * Both registers clear on the read of the high dword.
 913          */
 914
 915         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
 916         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
 917         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
 918         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
 919
 920         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
 921         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
 922         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
 923         stats->roc += E1000_READ_REG(hw, E1000_ROC);
 924         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
 925
 926         stats->tor += E1000_READ_REG(hw, E1000_TORH);
 927         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
 928
 929         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
 930         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
 931         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
 932         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
 933         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
 934         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
 935         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
 936         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
 937         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
 938         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
 939
 940         /* Interrupt Counts */
 941
 942         if (hw->mac.type >= e1000_82571) {
 943                 stats->iac += E1000_READ_REG(hw, E1000_IAC);
 944                 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
 945                 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
 946                 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
 947                 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
 948                 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
 949                 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
 950                 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
 951                 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
 952         }
 953
 954         if (hw->mac.type >= e1000_82543) {
 955                 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
 956                 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
 957                 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
 958                 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
 959                 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
 960                 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
 961         }
 962
 963         if (rte_stats == NULL)
 964                 return -EINVAL;
 965
 966         /* Rx Errors */
 967         rte_stats->imissed = stats->mpc;
 968         rte_stats->ierrors = stats->crcerrs +
 969                              stats->rlec + stats->ruc + stats->roc +
 970                              stats->rxerrc + stats->algnerrc + stats->cexterr;
 971
 972         /* Tx Errors */
 973         rte_stats->oerrors = stats->ecol + stats->latecol;
 974
 975         rte_stats->ipackets = stats->gprc;
 976         rte_stats->opackets = stats->gptc;
 977         rte_stats->ibytes   = stats->gorc;
 978         rte_stats->obytes   = stats->gotc;
 979         return 0;
 980 }
 981
 982 static void
 983 eth_em_stats_reset(struct rte_eth_dev *dev)
 984 {
 985         struct e1000_hw_stats *hw_stats =
 986                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 987
 988         /* HW registers are cleared on read */
 989         eth_em_stats_get(dev, NULL);
 990
 991         /* Reset software totals */
 992         memset(hw_stats, 0, sizeof(*hw_stats));
 993 }
 994
 995 static int
 996 eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
 997 {
 998         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 999         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1000         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1001
1002         em_rxq_intr_enable(hw);
1003         rte_intr_ack(intr_handle);
1004
1005         return 0;
1006 }
1007
1008 static int
1009 eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1010 {
1011         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1012
1013         em_rxq_intr_disable(hw);
1014
1015         return 0;
1016 }
1017
1018 uint32_t
1019 em_get_max_pktlen(struct rte_eth_dev *dev)
1020 {
1021         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1022
1023         switch (hw->mac.type) {
1024         case e1000_82571:
1025         case e1000_82572:
1026         case e1000_ich9lan:
1027         case e1000_ich10lan:
1028         case e1000_pch2lan:
1029         case e1000_pch_lpt:
1030         case e1000_pch_spt:
1031         case e1000_pch_cnp:
1032         case e1000_82574:
1033         case e1000_80003es2lan: /* 9K Jumbo Frame size */
1034         case e1000_82583:
1035                 return 0x2412;
1036         case e1000_pchlan:
1037                 return 0x1000;
1038         /* Adapters that do not support jumbo frames */
1039         case e1000_ich8lan:
1040                 return RTE_ETHER_MAX_LEN;
1041         default:
1042                 return MAX_JUMBO_FRAME_SIZE;
1043         }
1044 }
1045
1046 static void
1047 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1048 {
1049         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1050
1051         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1052         dev_info->max_rx_pktlen = em_get_max_pktlen(dev);
1053         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1054
1055         /*
1056          * Starting with 631xESB hw supports 2 TX/RX queues per port.
1057          * Unfortunatelly, all these nics have just one TX context.
1058          * So we have few choises for TX:
1059          * - Use just one TX queue.
1060          * - Allow cksum offload only for one TX queue.
1061          * - Don't allow TX cksum offload at all.
1062          * For now, option #1 was chosen.
1063          * To use second RX queue we have to use extended RX descriptor
1064          * (Multiple Receive Queues are mutually exclusive with UDP
1065          * fragmentation and are not supported when a legacy receive
1066          * descriptor format is used).
1067          * Which means separate RX routinies - as legacy nics (82540, 82545)
1068          * don't support extended RXD.
1069          * To avoid it we support just one RX queue for now (no RSS).
1070          */
1071
1072         dev_info->max_rx_queues = 1;
1073         dev_info->max_tx_queues = 1;
1074
1075         dev_info->rx_queue_offload_capa = em_get_rx_queue_offloads_capa(dev);
1076         dev_info->rx_offload_capa = em_get_rx_port_offloads_capa(dev) |
1077                                     dev_info->rx_queue_offload_capa;
1078         dev_info->tx_queue_offload_capa = em_get_tx_queue_offloads_capa(dev);
1079         dev_info->tx_offload_capa = em_get_tx_port_offloads_capa(dev) |
1080                                     dev_info->tx_queue_offload_capa;
1081
1082         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1083                 .nb_max = E1000_MAX_RING_DESC,
1084                 .nb_min = E1000_MIN_RING_DESC,
1085                 .nb_align = EM_RXD_ALIGN,
1086         };
1087
1088         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1089                 .nb_max = E1000_MAX_RING_DESC,
1090                 .nb_min = E1000_MIN_RING_DESC,
1091                 .nb_align = EM_TXD_ALIGN,
1092                 .nb_seg_max = EM_TX_MAX_SEG,
1093                 .nb_mtu_seg_max = EM_TX_MAX_MTU_SEG,
1094         };
1095
1096         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1097                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1098                         ETH_LINK_SPEED_1G;
1099
1100         /* Preferred queue parameters */
1101         dev_info->default_rxportconf.nb_queues = 1;
1102         dev_info->default_txportconf.nb_queues = 1;
1103         dev_info->default_txportconf.ring_size = 256;
1104         dev_info->default_rxportconf.ring_size = 256;
1105 }
1106
1107 /* return 0 means link status changed, -1 means not changed */
1108 static int
1109 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1110 {
1111         struct e1000_hw *hw =
1112                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1113         struct rte_eth_link link;
1114         int link_check, count;
1115
1116         link_check = 0;
1117         hw->mac.get_link_status = 1;
1118
1119         /* possible wait-to-complete in up to 9 seconds */
1120         for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1121                 /* Read the real link status */
1122                 switch (hw->phy.media_type) {
1123                 case e1000_media_type_copper:
1124                         /* Do the work to read phy */
1125                         e1000_check_for_link(hw);
1126                         link_check = !hw->mac.get_link_status;
1127                         break;
1128
1129                 case e1000_media_type_fiber:
1130                         e1000_check_for_link(hw);
1131                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1132                                         E1000_STATUS_LU);
1133                         break;
1134
1135                 case e1000_media_type_internal_serdes:
1136                         e1000_check_for_link(hw);
1137                         link_check = hw->mac.serdes_has_link;
1138                         break;
1139
1140                 default:
1141                         break;
1142                 }
1143                 if (link_check || wait_to_complete == 0)
1144                         break;
1145                 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
1146         }
1147         memset(&link, 0, sizeof(link));
1148
1149         /* Now we check if a transition has happened */
1150         if (link_check && (link.link_status == ETH_LINK_DOWN)) {
1151                 uint16_t duplex, speed;
1152                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1153                 link.link_duplex = (duplex == FULL_DUPLEX) ?
1154                                 ETH_LINK_FULL_DUPLEX :
1155                                 ETH_LINK_HALF_DUPLEX;
1156                 link.link_speed = speed;
1157                 link.link_status = ETH_LINK_UP;
1158                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
1159                                 ETH_LINK_SPEED_FIXED);
1160         } else if (!link_check && (link.link_status == ETH_LINK_UP)) {
1161                 link.link_speed = ETH_SPEED_NUM_NONE;
1162                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1163                 link.link_status = ETH_LINK_DOWN;
1164                 link.link_autoneg = ETH_LINK_FIXED;
1165         }
1166
1167         return rte_eth_linkstatus_set(dev, &link);
1168 }
1169
1170 /*
1171  * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
1172  * For ASF and Pass Through versions of f/w this means
1173  * that the driver is loaded. For AMT version type f/w
1174  * this means that the network i/f is open.
1175  */
1176 static void
1177 em_hw_control_acquire(struct e1000_hw *hw)
1178 {
1179         uint32_t ctrl_ext, swsm;
1180
1181         /* Let firmware know the driver has taken over */
1182         if (hw->mac.type == e1000_82573) {
1183                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1184                 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
1185
1186         } else {
1187                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1188                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1189                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1190         }
1191 }
1192
1193 /*
1194  * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
1195  * For ASF and Pass Through versions of f/w this means that the
1196  * driver is no longer loaded. For AMT versions of the
1197  * f/w this means that the network i/f is closed.
1198  */
1199 static void
1200 em_hw_control_release(struct e1000_hw *hw)
1201 {
1202         uint32_t ctrl_ext, swsm;
1203
1204         /* Let firmware taken over control of h/w */
1205         if (hw->mac.type == e1000_82573) {
1206                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1207                 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
1208         } else {
1209                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1210                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1211                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1212         }
1213 }
1214
1215 /*
1216  * Bit of a misnomer, what this really means is
1217  * to enable OS management of the system... aka
1218  * to disable special hardware management features.
1219  */
1220 static void
1221 em_init_manageability(struct e1000_hw *hw)
1222 {
1223         if (e1000_enable_mng_pass_thru(hw)) {
1224                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1225                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1226
1227                 /* disable hardware interception of ARP */
1228                 manc &= ~(E1000_MANC_ARP_EN);
1229
1230                 /* enable receiving management packets to the host */
1231                 manc |= E1000_MANC_EN_MNG2HOST;
1232                 manc2h |= 1 << 5;  /* Mng Port 623 */
1233                 manc2h |= 1 << 6;  /* Mng Port 664 */
1234                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1235                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1236         }
1237 }
1238
1239 /*
1240  * Give control back to hardware management
1241  * controller if there is one.
1242  */
1243 static void
1244 em_release_manageability(struct e1000_hw *hw)
1245 {
1246         uint32_t manc;
1247
1248         if (e1000_enable_mng_pass_thru(hw)) {
1249                 manc = E1000_READ_REG(hw, E1000_MANC);
1250
1251                 /* re-enable hardware interception of ARP */
1252                 manc |= E1000_MANC_ARP_EN;
1253                 manc &= ~E1000_MANC_EN_MNG2HOST;
1254
1255                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1256         }
1257 }
1258
1259 static void
1260 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1261 {
1262         struct e1000_hw *hw =
1263                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1264         uint32_t rctl;
1265
1266         rctl = E1000_READ_REG(hw, E1000_RCTL);
1267         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1268         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1269 }
1270
1271 static void
1272 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1273 {
1274         struct e1000_hw *hw =
1275                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1276         uint32_t rctl;
1277
1278         rctl = E1000_READ_REG(hw, E1000_RCTL);
1279         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1280         if (dev->data->all_multicast == 1)
1281                 rctl |= E1000_RCTL_MPE;
1282         else
1283                 rctl &= (~E1000_RCTL_MPE);
1284         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1285 }
1286
1287 static void
1288 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1289 {
1290         struct e1000_hw *hw =
1291                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1292         uint32_t rctl;
1293
1294         rctl = E1000_READ_REG(hw, E1000_RCTL);
1295         rctl |= E1000_RCTL_MPE;
1296         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1297 }
1298
1299 static void
1300 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1301 {
1302         struct e1000_hw *hw =
1303                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1304         uint32_t rctl;
1305
1306         if (dev->data->promiscuous == 1)
1307                 return; /* must remain in all_multicast mode */
1308         rctl = E1000_READ_REG(hw, E1000_RCTL);
1309         rctl &= (~E1000_RCTL_MPE);
1310         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1311 }
1312
1313 static int
1314 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1315 {
1316         struct e1000_hw *hw =
1317                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1318         struct e1000_vfta * shadow_vfta =
1319                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1320         uint32_t vfta;
1321         uint32_t vid_idx;
1322         uint32_t vid_bit;
1323
1324         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1325                               E1000_VFTA_ENTRY_MASK);
1326         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1327         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1328         if (on)
1329                 vfta |= vid_bit;
1330         else
1331                 vfta &= ~vid_bit;
1332         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1333
1334         /* update local VFTA copy */
1335         shadow_vfta->vfta[vid_idx] = vfta;
1336
1337         return 0;
1338 }
1339
1340 static void
1341 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1342 {
1343         struct e1000_hw *hw =
1344                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1345         uint32_t reg;
1346
1347         /* Filter Table Disable */
1348         reg = E1000_READ_REG(hw, E1000_RCTL);
1349         reg &= ~E1000_RCTL_CFIEN;
1350         reg &= ~E1000_RCTL_VFE;
1351         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1352 }
1353
1354 static void
1355 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1356 {
1357         struct e1000_hw *hw =
1358                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1359         struct e1000_vfta * shadow_vfta =
1360                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1361         uint32_t reg;
1362         int i;
1363
1364         /* Filter Table Enable, CFI not used for packet acceptance */
1365         reg = E1000_READ_REG(hw, E1000_RCTL);
1366         reg &= ~E1000_RCTL_CFIEN;
1367         reg |= E1000_RCTL_VFE;
1368         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1369
1370         /* restore vfta from local copy */
1371         for (i = 0; i < IGB_VFTA_SIZE; i++)
1372                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1373 }
1374
1375 static void
1376 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1377 {
1378         struct e1000_hw *hw =
1379                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1380         uint32_t reg;
1381
1382         /* VLAN Mode Disable */
1383         reg = E1000_READ_REG(hw, E1000_CTRL);
1384         reg &= ~E1000_CTRL_VME;
1385         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1386
1387 }
1388
1389 static void
1390 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1391 {
1392         struct e1000_hw *hw =
1393                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1394         uint32_t reg;
1395
1396         /* VLAN Mode Enable */
1397         reg = E1000_READ_REG(hw, E1000_CTRL);
1398         reg |= E1000_CTRL_VME;
1399         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1400 }
1401
1402 static int
1403 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1404 {
1405         struct rte_eth_rxmode *rxmode;
1406
1407         rxmode = &dev->data->dev_conf.rxmode;
1408         if(mask & ETH_VLAN_STRIP_MASK){
1409                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1410                         em_vlan_hw_strip_enable(dev);
1411                 else
1412                         em_vlan_hw_strip_disable(dev);
1413         }
1414
1415         if(mask & ETH_VLAN_FILTER_MASK){
1416                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1417                         em_vlan_hw_filter_enable(dev);
1418                 else
1419                         em_vlan_hw_filter_disable(dev);
1420         }
1421
1422         return 0;
1423 }
1424
1425 /*
1426  * It enables the interrupt mask and then enable the interrupt.
1427  *
1428  * @param dev
1429  *  Pointer to struct rte_eth_dev.
1430  *
1431  * @return
1432  *  - On success, zero.
1433  *  - On failure, a negative value.
1434  */
1435 static int
1436 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1437 {
1438         uint32_t regval;
1439         struct e1000_hw *hw =
1440                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1441
1442         /* clear interrupt */
1443         E1000_READ_REG(hw, E1000_ICR);
1444         regval = E1000_READ_REG(hw, E1000_IMS);
1445         E1000_WRITE_REG(hw, E1000_IMS,
1446                         regval | E1000_ICR_LSC | E1000_ICR_OTHER);
1447         return 0;
1448 }
1449
1450 /*
1451  * It clears the interrupt causes and enables the interrupt.
1452  * It will be called once only during nic initialized.
1453  *
1454  * @param dev
1455  *  Pointer to struct rte_eth_dev.
1456  *
1457  * @return
1458  *  - On success, zero.
1459  *  - On failure, a negative value.
1460  */
1461 static int
1462 eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev)
1463 {
1464         struct e1000_hw *hw =
1465         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1466
1467         E1000_READ_REG(hw, E1000_ICR);
1468         em_rxq_intr_enable(hw);
1469         return 0;
1470 }
1471
1472 /*
1473  * It enable receive packet interrupt.
1474  * @param hw
1475  * Pointer to struct e1000_hw
1476  *
1477  * @return
1478  */
1479 static void
1480 em_rxq_intr_enable(struct e1000_hw *hw)
1481 {
1482         E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_RXT0);
1483         E1000_WRITE_FLUSH(hw);
1484 }
1485
1486 /*
1487  * It disabled lsc interrupt.
1488  * @param hw
1489  * Pointer to struct e1000_hw
1490  *
1491  * @return
1492  */
1493 static void
1494 em_lsc_intr_disable(struct e1000_hw *hw)
1495 {
1496         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_LSC | E1000_IMS_OTHER);
1497         E1000_WRITE_FLUSH(hw);
1498 }
1499
1500 /*
1501  * It disabled receive packet interrupt.
1502  * @param hw
1503  * Pointer to struct e1000_hw
1504  *
1505  * @return
1506  */
1507 static void
1508 em_rxq_intr_disable(struct e1000_hw *hw)
1509 {
1510         E1000_READ_REG(hw, E1000_ICR);
1511         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0);
1512         E1000_WRITE_FLUSH(hw);
1513 }
1514
1515 /*
1516  * It reads ICR and gets interrupt causes, check it and set a bit flag
1517  * to update link status.
1518  *
1519  * @param dev
1520  *  Pointer to struct rte_eth_dev.
1521  *
1522  * @return
1523  *  - On success, zero.
1524  *  - On failure, a negative value.
1525  */
1526 static int
1527 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1528 {
1529         uint32_t icr;
1530         struct e1000_hw *hw =
1531                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1532         struct e1000_interrupt *intr =
1533                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1534
1535         /* read-on-clear nic registers here */
1536         icr = E1000_READ_REG(hw, E1000_ICR);
1537         if (icr & E1000_ICR_LSC) {
1538                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1539         }
1540
1541         return 0;
1542 }
1543
1544 /*
1545  * It executes link_update after knowing an interrupt is prsent.
1546  *
1547  * @param dev
1548  *  Pointer to struct rte_eth_dev.
1549  *
1550  * @return
1551  *  - On success, zero.
1552  *  - On failure, a negative value.
1553  */
1554 static int
1555 eth_em_interrupt_action(struct rte_eth_dev *dev,
1556                         struct rte_intr_handle *intr_handle)
1557 {
1558         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1559         struct e1000_hw *hw =
1560                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1561         struct e1000_interrupt *intr =
1562                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1563         struct rte_eth_link link;
1564         int ret;
1565
1566         if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1567                 return -1;
1568
1569         intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1570         rte_intr_ack(intr_handle);
1571
1572         /* set get_link_status to check register later */
1573         hw->mac.get_link_status = 1;
1574         ret = eth_em_link_update(dev, 0);
1575
1576         /* check if link has changed */
1577         if (ret < 0)
1578                 return 0;
1579
1580         rte_eth_linkstatus_get(dev, &link);
1581
1582         if (link.link_status) {
1583                 PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s",
1584                              dev->data->port_id, link.link_speed,
1585                              link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1586                              "full-duplex" : "half-duplex");
1587         } else {
1588                 PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
1589         }
1590         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
1591                      pci_dev->addr.domain, pci_dev->addr.bus,
1592                      pci_dev->addr.devid, pci_dev->addr.function);
1593
1594         return 0;
1595 }
1596
1597 /**
1598  * Interrupt handler which shall be registered at first.
1599  *
1600  * @param handle
1601  *  Pointer to interrupt handle.
1602  * @param param
1603  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1604  *
1605  * @return
1606  *  void
1607  */
1608 static void
1609 eth_em_interrupt_handler(void *param)
1610 {
1611         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1612
1613         eth_em_interrupt_get_status(dev);
1614         eth_em_interrupt_action(dev, dev->intr_handle);
1615         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1616 }
1617
1618 static int
1619 eth_em_led_on(struct rte_eth_dev *dev)
1620 {
1621         struct e1000_hw *hw;
1622
1623         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1624         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1625 }
1626
1627 static int
1628 eth_em_led_off(struct rte_eth_dev *dev)
1629 {
1630         struct e1000_hw *hw;
1631
1632         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1633         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1634 }
1635
1636 static int
1637 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1638 {
1639         struct e1000_hw *hw;
1640         uint32_t ctrl;
1641         int tx_pause;
1642         int rx_pause;
1643
1644         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1645         fc_conf->pause_time = hw->fc.pause_time;
1646         fc_conf->high_water = hw->fc.high_water;
1647         fc_conf->low_water = hw->fc.low_water;
1648         fc_conf->send_xon = hw->fc.send_xon;
1649         fc_conf->autoneg = hw->mac.autoneg;
1650
1651         /*
1652          * Return rx_pause and tx_pause status according to actual setting of
1653          * the TFCE and RFCE bits in the CTRL register.
1654          */
1655         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1656         if (ctrl & E1000_CTRL_TFCE)
1657                 tx_pause = 1;
1658         else
1659                 tx_pause = 0;
1660
1661         if (ctrl & E1000_CTRL_RFCE)
1662                 rx_pause = 1;
1663         else
1664                 rx_pause = 0;
1665
1666         if (rx_pause && tx_pause)
1667                 fc_conf->mode = RTE_FC_FULL;
1668         else if (rx_pause)
1669                 fc_conf->mode = RTE_FC_RX_PAUSE;
1670         else if (tx_pause)
1671                 fc_conf->mode = RTE_FC_TX_PAUSE;
1672         else
1673                 fc_conf->mode = RTE_FC_NONE;
1674
1675         return 0;
1676 }
1677
1678 static int
1679 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1680 {
1681         struct e1000_hw *hw;
1682         int err;
1683         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1684                 e1000_fc_none,
1685                 e1000_fc_rx_pause,
1686                 e1000_fc_tx_pause,
1687                 e1000_fc_full
1688         };
1689         uint32_t rx_buf_size;
1690         uint32_t max_high_water;
1691         uint32_t rctl;
1692
1693         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1694         if (fc_conf->autoneg != hw->mac.autoneg)
1695                 return -ENOTSUP;
1696         rx_buf_size = em_get_rx_buffer_size(hw);
1697         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1698
1699         /* At least reserve one Ethernet frame for watermark */
1700         max_high_water = rx_buf_size - RTE_ETHER_MAX_LEN;
1701         if ((fc_conf->high_water > max_high_water) ||
1702             (fc_conf->high_water < fc_conf->low_water)) {
1703                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1704                 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
1705                 return -EINVAL;
1706         }
1707
1708         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1709         hw->fc.pause_time     = fc_conf->pause_time;
1710         hw->fc.high_water     = fc_conf->high_water;
1711         hw->fc.low_water      = fc_conf->low_water;
1712         hw->fc.send_xon       = fc_conf->send_xon;
1713
1714         err = e1000_setup_link_generic(hw);
1715         if (err == E1000_SUCCESS) {
1716
1717                 /* check if we want to forward MAC frames - driver doesn't have native
1718                  * capability to do that, so we'll write the registers ourselves */
1719
1720                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1721
1722                 /* set or clear MFLCN.PMCF bit depending on configuration */
1723                 if (fc_conf->mac_ctrl_frame_fwd != 0)
1724                         rctl |= E1000_RCTL_PMCF;
1725                 else
1726                         rctl &= ~E1000_RCTL_PMCF;
1727
1728                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1729                 E1000_WRITE_FLUSH(hw);
1730
1731                 return 0;
1732         }
1733
1734         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1735         return -EIO;
1736 }
1737
1738 static int
1739 eth_em_rar_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1740                 uint32_t index, __rte_unused uint32_t pool)
1741 {
1742         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1743
1744         return e1000_rar_set(hw, mac_addr->addr_bytes, index);
1745 }
1746
1747 static void
1748 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1749 {
1750         uint8_t addr[RTE_ETHER_ADDR_LEN];
1751         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1752
1753         memset(addr, 0, sizeof(addr));
1754
1755         e1000_rar_set(hw, addr, index);
1756 }
1757
1758 static int
1759 eth_em_default_mac_addr_set(struct rte_eth_dev *dev,
1760                             struct rte_ether_addr *addr)
1761 {
1762         eth_em_rar_clear(dev, 0);
1763
1764         return eth_em_rar_set(dev, (void *)addr, 0, 0);
1765 }
1766
1767 static int
1768 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1769 {
1770         struct rte_eth_dev_info dev_info;
1771         struct e1000_hw *hw;
1772         uint32_t frame_size;
1773         uint32_t rctl;
1774
1775         eth_em_infos_get(dev, &dev_info);
1776         frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
1777                 VLAN_TAG_SIZE;
1778
1779         /* check that mtu is within the allowed range */
1780         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
1781                 return -EINVAL;
1782
1783         /* refuse mtu that requires the support of scattered packets when this
1784          * feature has not been enabled before. */
1785         if (!dev->data->scattered_rx &&
1786             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1787                 return -EINVAL;
1788
1789         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1790         rctl = E1000_READ_REG(hw, E1000_RCTL);
1791
1792         /* switch to jumbo mode if needed */
1793         if (frame_size > RTE_ETHER_MAX_LEN) {
1794                 dev->data->dev_conf.rxmode.offloads |=
1795                         DEV_RX_OFFLOAD_JUMBO_FRAME;
1796                 rctl |= E1000_RCTL_LPE;
1797         } else {
1798                 dev->data->dev_conf.rxmode.offloads &=
1799                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1800                 rctl &= ~E1000_RCTL_LPE;
1801         }
1802         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1803
1804         /* update max frame size */
1805         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1806         return 0;
1807 }
1808
1809 static int
1810 eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
1811                         struct rte_ether_addr *mc_addr_set,
1812                         uint32_t nb_mc_addr)
1813 {
1814         struct e1000_hw *hw;
1815
1816         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1817         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
1818         return 0;
1819 }
1820
1821 RTE_PMD_REGISTER_PCI(net_e1000_em, rte_em_pmd);
1822 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_em, pci_id_em_map);
1823 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_em, "* igb_uio | uio_pci_generic | vfio-pci");
1824
1825 /* see e1000_logs.c */
1826 RTE_INIT(igb_init_log)
1827 {
1828         e1000_igb_init_log();
1829 }